1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/clk.h> 27 #include <linux/console.h> 28 #include <linux/ctype.h> 29 #include <linux/cpufreq.h> 30 #include <linux/delay.h> 31 #include <linux/dmaengine.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/err.h> 34 #include <linux/errno.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/ioport.h> 38 #include <linux/major.h> 39 #include <linux/module.h> 40 #include <linux/mm.h> 41 #include <linux/notifier.h> 42 #include <linux/of.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/scatterlist.h> 46 #include <linux/serial.h> 47 #include <linux/serial_sci.h> 48 #include <linux/sh_dma.h> 49 #include <linux/slab.h> 50 #include <linux/string.h> 51 #include <linux/sysrq.h> 52 #include <linux/timer.h> 53 #include <linux/tty.h> 54 #include <linux/tty_flip.h> 55 56 #ifdef CONFIG_SUPERH 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 struct sci_port { 80 struct uart_port port; 81 82 /* Platform configuration */ 83 struct plat_sci_port *cfg; 84 unsigned int overrun_reg; 85 unsigned int overrun_mask; 86 unsigned int error_mask; 87 unsigned int sampling_rate; 88 resource_size_t reg_size; 89 90 /* Break timer */ 91 struct timer_list break_timer; 92 int break_flag; 93 94 /* Interface clock */ 95 struct clk *iclk; 96 /* Function clock */ 97 struct clk *fclk; 98 99 int irqs[SCIx_NR_IRQS]; 100 char *irqstr[SCIx_NR_IRQS]; 101 102 struct dma_chan *chan_tx; 103 struct dma_chan *chan_rx; 104 105 #ifdef CONFIG_SERIAL_SH_SCI_DMA 106 struct dma_async_tx_descriptor *desc_tx; 107 struct dma_async_tx_descriptor *desc_rx[2]; 108 dma_cookie_t cookie_tx; 109 dma_cookie_t cookie_rx[2]; 110 dma_cookie_t active_rx; 111 struct scatterlist sg_tx; 112 unsigned int sg_len_tx; 113 struct scatterlist sg_rx[2]; 114 size_t buf_len_rx; 115 struct sh_dmae_slave param_tx; 116 struct sh_dmae_slave param_rx; 117 struct work_struct work_tx; 118 struct work_struct work_rx; 119 struct timer_list rx_timer; 120 unsigned int rx_timeout; 121 #endif 122 123 struct notifier_block freq_transition; 124 }; 125 126 /* Function prototypes */ 127 static void sci_start_tx(struct uart_port *port); 128 static void sci_stop_tx(struct uart_port *port); 129 static void sci_start_rx(struct uart_port *port); 130 131 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 132 133 static struct sci_port sci_ports[SCI_NPORTS]; 134 static struct uart_driver sci_uart_driver; 135 136 static inline struct sci_port * 137 to_sci_port(struct uart_port *uart) 138 { 139 return container_of(uart, struct sci_port, port); 140 } 141 142 struct plat_sci_reg { 143 u8 offset, size; 144 }; 145 146 /* Helper for invalidating specific entries of an inherited map. */ 147 #define sci_reg_invalid { .offset = 0, .size = 0 } 148 149 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 150 [SCIx_PROBE_REGTYPE] = { 151 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 152 }, 153 154 /* 155 * Common SCI definitions, dependent on the port's regshift 156 * value. 157 */ 158 [SCIx_SCI_REGTYPE] = { 159 [SCSMR] = { 0x00, 8 }, 160 [SCBRR] = { 0x01, 8 }, 161 [SCSCR] = { 0x02, 8 }, 162 [SCxTDR] = { 0x03, 8 }, 163 [SCxSR] = { 0x04, 8 }, 164 [SCxRDR] = { 0x05, 8 }, 165 [SCFCR] = sci_reg_invalid, 166 [SCFDR] = sci_reg_invalid, 167 [SCTFDR] = sci_reg_invalid, 168 [SCRFDR] = sci_reg_invalid, 169 [SCSPTR] = sci_reg_invalid, 170 [SCLSR] = sci_reg_invalid, 171 [HSSRR] = sci_reg_invalid, 172 [SCPCR] = sci_reg_invalid, 173 [SCPDR] = sci_reg_invalid, 174 }, 175 176 /* 177 * Common definitions for legacy IrDA ports, dependent on 178 * regshift value. 179 */ 180 [SCIx_IRDA_REGTYPE] = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 [SCFCR] = { 0x06, 8 }, 188 [SCFDR] = { 0x07, 16 }, 189 [SCTFDR] = sci_reg_invalid, 190 [SCRFDR] = sci_reg_invalid, 191 [SCSPTR] = sci_reg_invalid, 192 [SCLSR] = sci_reg_invalid, 193 [HSSRR] = sci_reg_invalid, 194 [SCPCR] = sci_reg_invalid, 195 [SCPDR] = sci_reg_invalid, 196 }, 197 198 /* 199 * Common SCIFA definitions. 200 */ 201 [SCIx_SCIFA_REGTYPE] = { 202 [SCSMR] = { 0x00, 16 }, 203 [SCBRR] = { 0x04, 8 }, 204 [SCSCR] = { 0x08, 16 }, 205 [SCxTDR] = { 0x20, 8 }, 206 [SCxSR] = { 0x14, 16 }, 207 [SCxRDR] = { 0x24, 8 }, 208 [SCFCR] = { 0x18, 16 }, 209 [SCFDR] = { 0x1c, 16 }, 210 [SCTFDR] = sci_reg_invalid, 211 [SCRFDR] = sci_reg_invalid, 212 [SCSPTR] = sci_reg_invalid, 213 [SCLSR] = sci_reg_invalid, 214 [HSSRR] = sci_reg_invalid, 215 [SCPCR] = { 0x30, 16 }, 216 [SCPDR] = { 0x34, 16 }, 217 }, 218 219 /* 220 * Common SCIFB definitions. 221 */ 222 [SCIx_SCIFB_REGTYPE] = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x40, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x60, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = sci_reg_invalid, 231 [SCTFDR] = { 0x38, 16 }, 232 [SCRFDR] = { 0x3c, 16 }, 233 [SCSPTR] = sci_reg_invalid, 234 [SCLSR] = sci_reg_invalid, 235 [HSSRR] = sci_reg_invalid, 236 [SCPCR] = { 0x30, 16 }, 237 [SCPDR] = { 0x34, 16 }, 238 }, 239 240 /* 241 * Common SH-2(A) SCIF definitions for ports with FIFO data 242 * count registers. 243 */ 244 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 245 [SCSMR] = { 0x00, 16 }, 246 [SCBRR] = { 0x04, 8 }, 247 [SCSCR] = { 0x08, 16 }, 248 [SCxTDR] = { 0x0c, 8 }, 249 [SCxSR] = { 0x10, 16 }, 250 [SCxRDR] = { 0x14, 8 }, 251 [SCFCR] = { 0x18, 16 }, 252 [SCFDR] = { 0x1c, 16 }, 253 [SCTFDR] = sci_reg_invalid, 254 [SCRFDR] = sci_reg_invalid, 255 [SCSPTR] = { 0x20, 16 }, 256 [SCLSR] = { 0x24, 16 }, 257 [HSSRR] = sci_reg_invalid, 258 [SCPCR] = sci_reg_invalid, 259 [SCPDR] = sci_reg_invalid, 260 }, 261 262 /* 263 * Common SH-3 SCIF definitions. 264 */ 265 [SCIx_SH3_SCIF_REGTYPE] = { 266 [SCSMR] = { 0x00, 8 }, 267 [SCBRR] = { 0x02, 8 }, 268 [SCSCR] = { 0x04, 8 }, 269 [SCxTDR] = { 0x06, 8 }, 270 [SCxSR] = { 0x08, 16 }, 271 [SCxRDR] = { 0x0a, 8 }, 272 [SCFCR] = { 0x0c, 8 }, 273 [SCFDR] = { 0x0e, 16 }, 274 [SCTFDR] = sci_reg_invalid, 275 [SCRFDR] = sci_reg_invalid, 276 [SCSPTR] = sci_reg_invalid, 277 [SCLSR] = sci_reg_invalid, 278 [HSSRR] = sci_reg_invalid, 279 [SCPCR] = sci_reg_invalid, 280 [SCPDR] = sci_reg_invalid, 281 }, 282 283 /* 284 * Common SH-4(A) SCIF(B) definitions. 285 */ 286 [SCIx_SH4_SCIF_REGTYPE] = { 287 [SCSMR] = { 0x00, 16 }, 288 [SCBRR] = { 0x04, 8 }, 289 [SCSCR] = { 0x08, 16 }, 290 [SCxTDR] = { 0x0c, 8 }, 291 [SCxSR] = { 0x10, 16 }, 292 [SCxRDR] = { 0x14, 8 }, 293 [SCFCR] = { 0x18, 16 }, 294 [SCFDR] = { 0x1c, 16 }, 295 [SCTFDR] = sci_reg_invalid, 296 [SCRFDR] = sci_reg_invalid, 297 [SCSPTR] = { 0x20, 16 }, 298 [SCLSR] = { 0x24, 16 }, 299 [HSSRR] = sci_reg_invalid, 300 [SCPCR] = sci_reg_invalid, 301 [SCPDR] = sci_reg_invalid, 302 }, 303 304 /* 305 * Common HSCIF definitions. 306 */ 307 [SCIx_HSCIF_REGTYPE] = { 308 [SCSMR] = { 0x00, 16 }, 309 [SCBRR] = { 0x04, 8 }, 310 [SCSCR] = { 0x08, 16 }, 311 [SCxTDR] = { 0x0c, 8 }, 312 [SCxSR] = { 0x10, 16 }, 313 [SCxRDR] = { 0x14, 8 }, 314 [SCFCR] = { 0x18, 16 }, 315 [SCFDR] = { 0x1c, 16 }, 316 [SCTFDR] = sci_reg_invalid, 317 [SCRFDR] = sci_reg_invalid, 318 [SCSPTR] = { 0x20, 16 }, 319 [SCLSR] = { 0x24, 16 }, 320 [HSSRR] = { 0x40, 16 }, 321 [SCPCR] = sci_reg_invalid, 322 [SCPDR] = sci_reg_invalid, 323 }, 324 325 /* 326 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 327 * register. 328 */ 329 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 330 [SCSMR] = { 0x00, 16 }, 331 [SCBRR] = { 0x04, 8 }, 332 [SCSCR] = { 0x08, 16 }, 333 [SCxTDR] = { 0x0c, 8 }, 334 [SCxSR] = { 0x10, 16 }, 335 [SCxRDR] = { 0x14, 8 }, 336 [SCFCR] = { 0x18, 16 }, 337 [SCFDR] = { 0x1c, 16 }, 338 [SCTFDR] = sci_reg_invalid, 339 [SCRFDR] = sci_reg_invalid, 340 [SCSPTR] = sci_reg_invalid, 341 [SCLSR] = { 0x24, 16 }, 342 [HSSRR] = sci_reg_invalid, 343 [SCPCR] = sci_reg_invalid, 344 [SCPDR] = sci_reg_invalid, 345 }, 346 347 /* 348 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 349 * count registers. 350 */ 351 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 352 [SCSMR] = { 0x00, 16 }, 353 [SCBRR] = { 0x04, 8 }, 354 [SCSCR] = { 0x08, 16 }, 355 [SCxTDR] = { 0x0c, 8 }, 356 [SCxSR] = { 0x10, 16 }, 357 [SCxRDR] = { 0x14, 8 }, 358 [SCFCR] = { 0x18, 16 }, 359 [SCFDR] = { 0x1c, 16 }, 360 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 361 [SCRFDR] = { 0x20, 16 }, 362 [SCSPTR] = { 0x24, 16 }, 363 [SCLSR] = { 0x28, 16 }, 364 [HSSRR] = sci_reg_invalid, 365 [SCPCR] = sci_reg_invalid, 366 [SCPDR] = sci_reg_invalid, 367 }, 368 369 /* 370 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 371 * registers. 372 */ 373 [SCIx_SH7705_SCIF_REGTYPE] = { 374 [SCSMR] = { 0x00, 16 }, 375 [SCBRR] = { 0x04, 8 }, 376 [SCSCR] = { 0x08, 16 }, 377 [SCxTDR] = { 0x20, 8 }, 378 [SCxSR] = { 0x14, 16 }, 379 [SCxRDR] = { 0x24, 8 }, 380 [SCFCR] = { 0x18, 16 }, 381 [SCFDR] = { 0x1c, 16 }, 382 [SCTFDR] = sci_reg_invalid, 383 [SCRFDR] = sci_reg_invalid, 384 [SCSPTR] = sci_reg_invalid, 385 [SCLSR] = sci_reg_invalid, 386 [HSSRR] = sci_reg_invalid, 387 [SCPCR] = sci_reg_invalid, 388 [SCPDR] = sci_reg_invalid, 389 }, 390 }; 391 392 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 393 394 /* 395 * The "offset" here is rather misleading, in that it refers to an enum 396 * value relative to the port mapping rather than the fixed offset 397 * itself, which needs to be manually retrieved from the platform's 398 * register map for the given port. 399 */ 400 static unsigned int sci_serial_in(struct uart_port *p, int offset) 401 { 402 struct plat_sci_reg *reg = sci_getreg(p, offset); 403 404 if (reg->size == 8) 405 return ioread8(p->membase + (reg->offset << p->regshift)); 406 else if (reg->size == 16) 407 return ioread16(p->membase + (reg->offset << p->regshift)); 408 else 409 WARN(1, "Invalid register access\n"); 410 411 return 0; 412 } 413 414 static void sci_serial_out(struct uart_port *p, int offset, int value) 415 { 416 struct plat_sci_reg *reg = sci_getreg(p, offset); 417 418 if (reg->size == 8) 419 iowrite8(value, p->membase + (reg->offset << p->regshift)); 420 else if (reg->size == 16) 421 iowrite16(value, p->membase + (reg->offset << p->regshift)); 422 else 423 WARN(1, "Invalid register access\n"); 424 } 425 426 static int sci_probe_regmap(struct plat_sci_port *cfg) 427 { 428 switch (cfg->type) { 429 case PORT_SCI: 430 cfg->regtype = SCIx_SCI_REGTYPE; 431 break; 432 case PORT_IRDA: 433 cfg->regtype = SCIx_IRDA_REGTYPE; 434 break; 435 case PORT_SCIFA: 436 cfg->regtype = SCIx_SCIFA_REGTYPE; 437 break; 438 case PORT_SCIFB: 439 cfg->regtype = SCIx_SCIFB_REGTYPE; 440 break; 441 case PORT_SCIF: 442 /* 443 * The SH-4 is a bit of a misnomer here, although that's 444 * where this particular port layout originated. This 445 * configuration (or some slight variation thereof) 446 * remains the dominant model for all SCIFs. 447 */ 448 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 449 break; 450 case PORT_HSCIF: 451 cfg->regtype = SCIx_HSCIF_REGTYPE; 452 break; 453 default: 454 pr_err("Can't probe register map for given port\n"); 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static void sci_port_enable(struct sci_port *sci_port) 462 { 463 if (!sci_port->port.dev) 464 return; 465 466 pm_runtime_get_sync(sci_port->port.dev); 467 468 clk_prepare_enable(sci_port->iclk); 469 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 470 clk_prepare_enable(sci_port->fclk); 471 } 472 473 static void sci_port_disable(struct sci_port *sci_port) 474 { 475 if (!sci_port->port.dev) 476 return; 477 478 /* Cancel the break timer to ensure that the timer handler will not try 479 * to access the hardware with clocks and power disabled. Reset the 480 * break flag to make the break debouncing state machine ready for the 481 * next break. 482 */ 483 del_timer_sync(&sci_port->break_timer); 484 sci_port->break_flag = 0; 485 486 clk_disable_unprepare(sci_port->fclk); 487 clk_disable_unprepare(sci_port->iclk); 488 489 pm_runtime_put_sync(sci_port->port.dev); 490 } 491 492 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 493 494 #ifdef CONFIG_CONSOLE_POLL 495 static int sci_poll_get_char(struct uart_port *port) 496 { 497 unsigned short status; 498 int c; 499 500 do { 501 status = serial_port_in(port, SCxSR); 502 if (status & SCxSR_ERRORS(port)) { 503 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 504 continue; 505 } 506 break; 507 } while (1); 508 509 if (!(status & SCxSR_RDxF(port))) 510 return NO_POLL_CHAR; 511 512 c = serial_port_in(port, SCxRDR); 513 514 /* Dummy read */ 515 serial_port_in(port, SCxSR); 516 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 517 518 return c; 519 } 520 #endif 521 522 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 523 { 524 unsigned short status; 525 526 do { 527 status = serial_port_in(port, SCxSR); 528 } while (!(status & SCxSR_TDxE(port))); 529 530 serial_port_out(port, SCxTDR, c); 531 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 532 } 533 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 534 535 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 536 { 537 struct sci_port *s = to_sci_port(port); 538 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 539 540 /* 541 * Use port-specific handler if provided. 542 */ 543 if (s->cfg->ops && s->cfg->ops->init_pins) { 544 s->cfg->ops->init_pins(port, cflag); 545 return; 546 } 547 548 /* 549 * For the generic path SCSPTR is necessary. Bail out if that's 550 * unavailable, too. 551 */ 552 if (!reg->size) 553 return; 554 555 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && 556 ((!(cflag & CRTSCTS)))) { 557 unsigned short status; 558 559 status = serial_port_in(port, SCSPTR); 560 status &= ~SCSPTR_CTSIO; 561 status |= SCSPTR_RTSIO; 562 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ 563 } 564 } 565 566 static int sci_txfill(struct uart_port *port) 567 { 568 struct plat_sci_reg *reg; 569 570 reg = sci_getreg(port, SCTFDR); 571 if (reg->size) 572 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); 573 574 reg = sci_getreg(port, SCFDR); 575 if (reg->size) 576 return serial_port_in(port, SCFDR) >> 8; 577 578 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 579 } 580 581 static int sci_txroom(struct uart_port *port) 582 { 583 return port->fifosize - sci_txfill(port); 584 } 585 586 static int sci_rxfill(struct uart_port *port) 587 { 588 struct plat_sci_reg *reg; 589 590 reg = sci_getreg(port, SCRFDR); 591 if (reg->size) 592 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); 593 594 reg = sci_getreg(port, SCFDR); 595 if (reg->size) 596 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); 597 598 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 599 } 600 601 /* 602 * SCI helper for checking the state of the muxed port/RXD pins. 603 */ 604 static inline int sci_rxd_in(struct uart_port *port) 605 { 606 struct sci_port *s = to_sci_port(port); 607 608 if (s->cfg->port_reg <= 0) 609 return 1; 610 611 /* Cast for ARM damage */ 612 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); 613 } 614 615 /* ********************************************************************** * 616 * the interrupt related routines * 617 * ********************************************************************** */ 618 619 static void sci_transmit_chars(struct uart_port *port) 620 { 621 struct circ_buf *xmit = &port->state->xmit; 622 unsigned int stopped = uart_tx_stopped(port); 623 unsigned short status; 624 unsigned short ctrl; 625 int count; 626 627 status = serial_port_in(port, SCxSR); 628 if (!(status & SCxSR_TDxE(port))) { 629 ctrl = serial_port_in(port, SCSCR); 630 if (uart_circ_empty(xmit)) 631 ctrl &= ~SCSCR_TIE; 632 else 633 ctrl |= SCSCR_TIE; 634 serial_port_out(port, SCSCR, ctrl); 635 return; 636 } 637 638 count = sci_txroom(port); 639 640 do { 641 unsigned char c; 642 643 if (port->x_char) { 644 c = port->x_char; 645 port->x_char = 0; 646 } else if (!uart_circ_empty(xmit) && !stopped) { 647 c = xmit->buf[xmit->tail]; 648 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 649 } else { 650 break; 651 } 652 653 serial_port_out(port, SCxTDR, c); 654 655 port->icount.tx++; 656 } while (--count > 0); 657 658 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 659 660 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 661 uart_write_wakeup(port); 662 if (uart_circ_empty(xmit)) { 663 sci_stop_tx(port); 664 } else { 665 ctrl = serial_port_in(port, SCSCR); 666 667 if (port->type != PORT_SCI) { 668 serial_port_in(port, SCxSR); /* Dummy read */ 669 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 670 } 671 672 ctrl |= SCSCR_TIE; 673 serial_port_out(port, SCSCR, ctrl); 674 } 675 } 676 677 /* On SH3, SCIF may read end-of-break as a space->mark char */ 678 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 679 680 static void sci_receive_chars(struct uart_port *port) 681 { 682 struct sci_port *sci_port = to_sci_port(port); 683 struct tty_port *tport = &port->state->port; 684 int i, count, copied = 0; 685 unsigned short status; 686 unsigned char flag; 687 688 status = serial_port_in(port, SCxSR); 689 if (!(status & SCxSR_RDxF(port))) 690 return; 691 692 while (1) { 693 /* Don't copy more bytes than there is room for in the buffer */ 694 count = tty_buffer_request_room(tport, sci_rxfill(port)); 695 696 /* If for any reason we can't copy more data, we're done! */ 697 if (count == 0) 698 break; 699 700 if (port->type == PORT_SCI) { 701 char c = serial_port_in(port, SCxRDR); 702 if (uart_handle_sysrq_char(port, c) || 703 sci_port->break_flag) 704 count = 0; 705 else 706 tty_insert_flip_char(tport, c, TTY_NORMAL); 707 } else { 708 for (i = 0; i < count; i++) { 709 char c = serial_port_in(port, SCxRDR); 710 711 status = serial_port_in(port, SCxSR); 712 #if defined(CONFIG_CPU_SH3) 713 /* Skip "chars" during break */ 714 if (sci_port->break_flag) { 715 if ((c == 0) && 716 (status & SCxSR_FER(port))) { 717 count--; i--; 718 continue; 719 } 720 721 /* Nonzero => end-of-break */ 722 dev_dbg(port->dev, "debounce<%02x>\n", c); 723 sci_port->break_flag = 0; 724 725 if (STEPFN(c)) { 726 count--; i--; 727 continue; 728 } 729 } 730 #endif /* CONFIG_CPU_SH3 */ 731 if (uart_handle_sysrq_char(port, c)) { 732 count--; i--; 733 continue; 734 } 735 736 /* Store data and status */ 737 if (status & SCxSR_FER(port)) { 738 flag = TTY_FRAME; 739 port->icount.frame++; 740 dev_notice(port->dev, "frame error\n"); 741 } else if (status & SCxSR_PER(port)) { 742 flag = TTY_PARITY; 743 port->icount.parity++; 744 dev_notice(port->dev, "parity error\n"); 745 } else 746 flag = TTY_NORMAL; 747 748 tty_insert_flip_char(tport, c, flag); 749 } 750 } 751 752 serial_port_in(port, SCxSR); /* dummy read */ 753 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 754 755 copied += count; 756 port->icount.rx += count; 757 } 758 759 if (copied) { 760 /* Tell the rest of the system the news. New characters! */ 761 tty_flip_buffer_push(tport); 762 } else { 763 serial_port_in(port, SCxSR); /* dummy read */ 764 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 765 } 766 } 767 768 #define SCI_BREAK_JIFFIES (HZ/20) 769 770 /* 771 * The sci generates interrupts during the break, 772 * 1 per millisecond or so during the break period, for 9600 baud. 773 * So dont bother disabling interrupts. 774 * But dont want more than 1 break event. 775 * Use a kernel timer to periodically poll the rx line until 776 * the break is finished. 777 */ 778 static inline void sci_schedule_break_timer(struct sci_port *port) 779 { 780 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 781 } 782 783 /* Ensure that two consecutive samples find the break over. */ 784 static void sci_break_timer(unsigned long data) 785 { 786 struct sci_port *port = (struct sci_port *)data; 787 788 if (sci_rxd_in(&port->port) == 0) { 789 port->break_flag = 1; 790 sci_schedule_break_timer(port); 791 } else if (port->break_flag == 1) { 792 /* break is over. */ 793 port->break_flag = 2; 794 sci_schedule_break_timer(port); 795 } else 796 port->break_flag = 0; 797 } 798 799 static int sci_handle_errors(struct uart_port *port) 800 { 801 int copied = 0; 802 unsigned short status = serial_port_in(port, SCxSR); 803 struct tty_port *tport = &port->state->port; 804 struct sci_port *s = to_sci_port(port); 805 806 /* Handle overruns */ 807 if (status & s->overrun_mask) { 808 port->icount.overrun++; 809 810 /* overrun error */ 811 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 812 copied++; 813 814 dev_notice(port->dev, "overrun error\n"); 815 } 816 817 if (status & SCxSR_FER(port)) { 818 if (sci_rxd_in(port) == 0) { 819 /* Notify of BREAK */ 820 struct sci_port *sci_port = to_sci_port(port); 821 822 if (!sci_port->break_flag) { 823 port->icount.brk++; 824 825 sci_port->break_flag = 1; 826 sci_schedule_break_timer(sci_port); 827 828 /* Do sysrq handling. */ 829 if (uart_handle_break(port)) 830 return 0; 831 832 dev_dbg(port->dev, "BREAK detected\n"); 833 834 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 835 copied++; 836 } 837 838 } else { 839 /* frame error */ 840 port->icount.frame++; 841 842 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 843 copied++; 844 845 dev_notice(port->dev, "frame error\n"); 846 } 847 } 848 849 if (status & SCxSR_PER(port)) { 850 /* parity error */ 851 port->icount.parity++; 852 853 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 854 copied++; 855 856 dev_notice(port->dev, "parity error\n"); 857 } 858 859 if (copied) 860 tty_flip_buffer_push(tport); 861 862 return copied; 863 } 864 865 static int sci_handle_fifo_overrun(struct uart_port *port) 866 { 867 struct tty_port *tport = &port->state->port; 868 struct sci_port *s = to_sci_port(port); 869 struct plat_sci_reg *reg; 870 int copied = 0; 871 u16 status; 872 873 reg = sci_getreg(port, s->overrun_reg); 874 if (!reg->size) 875 return 0; 876 877 status = serial_port_in(port, s->overrun_reg); 878 if (status & s->overrun_mask) { 879 status &= ~s->overrun_mask; 880 serial_port_out(port, s->overrun_reg, status); 881 882 port->icount.overrun++; 883 884 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 885 tty_flip_buffer_push(tport); 886 887 dev_dbg(port->dev, "overrun error\n"); 888 copied++; 889 } 890 891 return copied; 892 } 893 894 static int sci_handle_breaks(struct uart_port *port) 895 { 896 int copied = 0; 897 unsigned short status = serial_port_in(port, SCxSR); 898 struct tty_port *tport = &port->state->port; 899 struct sci_port *s = to_sci_port(port); 900 901 if (uart_handle_break(port)) 902 return 0; 903 904 if (!s->break_flag && status & SCxSR_BRK(port)) { 905 #if defined(CONFIG_CPU_SH3) 906 /* Debounce break */ 907 s->break_flag = 1; 908 #endif 909 910 port->icount.brk++; 911 912 /* Notify of BREAK */ 913 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 914 copied++; 915 916 dev_dbg(port->dev, "BREAK detected\n"); 917 } 918 919 if (copied) 920 tty_flip_buffer_push(tport); 921 922 copied += sci_handle_fifo_overrun(port); 923 924 return copied; 925 } 926 927 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 928 { 929 #ifdef CONFIG_SERIAL_SH_SCI_DMA 930 struct uart_port *port = ptr; 931 struct sci_port *s = to_sci_port(port); 932 933 if (s->chan_rx) { 934 u16 scr = serial_port_in(port, SCSCR); 935 u16 ssr = serial_port_in(port, SCxSR); 936 937 /* Disable future Rx interrupts */ 938 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 939 disable_irq_nosync(irq); 940 scr |= SCSCR_RDRQE; 941 } else { 942 scr &= ~SCSCR_RIE; 943 } 944 serial_port_out(port, SCSCR, scr); 945 /* Clear current interrupt */ 946 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 947 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 948 jiffies, s->rx_timeout); 949 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 950 951 return IRQ_HANDLED; 952 } 953 #endif 954 955 /* I think sci_receive_chars has to be called irrespective 956 * of whether the I_IXOFF is set, otherwise, how is the interrupt 957 * to be disabled? 958 */ 959 sci_receive_chars(ptr); 960 961 return IRQ_HANDLED; 962 } 963 964 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 965 { 966 struct uart_port *port = ptr; 967 unsigned long flags; 968 969 spin_lock_irqsave(&port->lock, flags); 970 sci_transmit_chars(port); 971 spin_unlock_irqrestore(&port->lock, flags); 972 973 return IRQ_HANDLED; 974 } 975 976 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 977 { 978 struct uart_port *port = ptr; 979 980 /* Handle errors */ 981 if (port->type == PORT_SCI) { 982 if (sci_handle_errors(port)) { 983 /* discard character in rx buffer */ 984 serial_port_in(port, SCxSR); 985 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 986 } 987 } else { 988 sci_handle_fifo_overrun(port); 989 sci_rx_interrupt(irq, ptr); 990 } 991 992 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 993 994 /* Kick the transmission */ 995 sci_tx_interrupt(irq, ptr); 996 997 return IRQ_HANDLED; 998 } 999 1000 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1001 { 1002 struct uart_port *port = ptr; 1003 1004 /* Handle BREAKs */ 1005 sci_handle_breaks(port); 1006 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 1007 1008 return IRQ_HANDLED; 1009 } 1010 1011 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 1012 { 1013 /* 1014 * Not all ports (such as SCIFA) will support REIE. Rather than 1015 * special-casing the port type, we check the port initialization 1016 * IRQ enable mask to see whether the IRQ is desired at all. If 1017 * it's unset, it's logically inferred that there's no point in 1018 * testing for it. 1019 */ 1020 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 1021 } 1022 1023 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1024 { 1025 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1026 struct uart_port *port = ptr; 1027 struct sci_port *s = to_sci_port(port); 1028 irqreturn_t ret = IRQ_NONE; 1029 1030 ssr_status = serial_port_in(port, SCxSR); 1031 scr_status = serial_port_in(port, SCSCR); 1032 if (s->overrun_reg == SCxSR) 1033 orer_status = ssr_status; 1034 else { 1035 if (sci_getreg(port, s->overrun_reg)->size) 1036 orer_status = serial_port_in(port, s->overrun_reg); 1037 } 1038 1039 err_enabled = scr_status & port_rx_irq_mask(port); 1040 1041 /* Tx Interrupt */ 1042 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1043 !s->chan_tx) 1044 ret = sci_tx_interrupt(irq, ptr); 1045 1046 /* 1047 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1048 * DR flags 1049 */ 1050 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1051 (scr_status & SCSCR_RIE)) { 1052 if (port->type == PORT_SCIF || port->type == PORT_HSCIF) 1053 sci_handle_fifo_overrun(port); 1054 ret = sci_rx_interrupt(irq, ptr); 1055 } 1056 1057 /* Error Interrupt */ 1058 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1059 ret = sci_er_interrupt(irq, ptr); 1060 1061 /* Break Interrupt */ 1062 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1063 ret = sci_br_interrupt(irq, ptr); 1064 1065 /* Overrun Interrupt */ 1066 if (orer_status & s->overrun_mask) 1067 sci_handle_fifo_overrun(port); 1068 1069 return ret; 1070 } 1071 1072 /* 1073 * Here we define a transition notifier so that we can update all of our 1074 * ports' baud rate when the peripheral clock changes. 1075 */ 1076 static int sci_notifier(struct notifier_block *self, 1077 unsigned long phase, void *p) 1078 { 1079 struct sci_port *sci_port; 1080 unsigned long flags; 1081 1082 sci_port = container_of(self, struct sci_port, freq_transition); 1083 1084 if (phase == CPUFREQ_POSTCHANGE) { 1085 struct uart_port *port = &sci_port->port; 1086 1087 spin_lock_irqsave(&port->lock, flags); 1088 port->uartclk = clk_get_rate(sci_port->iclk); 1089 spin_unlock_irqrestore(&port->lock, flags); 1090 } 1091 1092 return NOTIFY_OK; 1093 } 1094 1095 static struct sci_irq_desc { 1096 const char *desc; 1097 irq_handler_t handler; 1098 } sci_irq_desc[] = { 1099 /* 1100 * Split out handlers, the default case. 1101 */ 1102 [SCIx_ERI_IRQ] = { 1103 .desc = "rx err", 1104 .handler = sci_er_interrupt, 1105 }, 1106 1107 [SCIx_RXI_IRQ] = { 1108 .desc = "rx full", 1109 .handler = sci_rx_interrupt, 1110 }, 1111 1112 [SCIx_TXI_IRQ] = { 1113 .desc = "tx empty", 1114 .handler = sci_tx_interrupt, 1115 }, 1116 1117 [SCIx_BRI_IRQ] = { 1118 .desc = "break", 1119 .handler = sci_br_interrupt, 1120 }, 1121 1122 /* 1123 * Special muxed handler. 1124 */ 1125 [SCIx_MUX_IRQ] = { 1126 .desc = "mux", 1127 .handler = sci_mpxed_interrupt, 1128 }, 1129 }; 1130 1131 static int sci_request_irq(struct sci_port *port) 1132 { 1133 struct uart_port *up = &port->port; 1134 int i, j, ret = 0; 1135 1136 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1137 struct sci_irq_desc *desc; 1138 int irq; 1139 1140 if (SCIx_IRQ_IS_MUXED(port)) { 1141 i = SCIx_MUX_IRQ; 1142 irq = up->irq; 1143 } else { 1144 irq = port->irqs[i]; 1145 1146 /* 1147 * Certain port types won't support all of the 1148 * available interrupt sources. 1149 */ 1150 if (unlikely(irq < 0)) 1151 continue; 1152 } 1153 1154 desc = sci_irq_desc + i; 1155 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1156 dev_name(up->dev), desc->desc); 1157 if (!port->irqstr[j]) { 1158 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1159 desc->desc); 1160 goto out_nomem; 1161 } 1162 1163 ret = request_irq(irq, desc->handler, up->irqflags, 1164 port->irqstr[j], port); 1165 if (unlikely(ret)) { 1166 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1167 goto out_noirq; 1168 } 1169 } 1170 1171 return 0; 1172 1173 out_noirq: 1174 while (--i >= 0) 1175 free_irq(port->irqs[i], port); 1176 1177 out_nomem: 1178 while (--j >= 0) 1179 kfree(port->irqstr[j]); 1180 1181 return ret; 1182 } 1183 1184 static void sci_free_irq(struct sci_port *port) 1185 { 1186 int i; 1187 1188 /* 1189 * Intentionally in reverse order so we iterate over the muxed 1190 * IRQ first. 1191 */ 1192 for (i = 0; i < SCIx_NR_IRQS; i++) { 1193 int irq = port->irqs[i]; 1194 1195 /* 1196 * Certain port types won't support all of the available 1197 * interrupt sources. 1198 */ 1199 if (unlikely(irq < 0)) 1200 continue; 1201 1202 free_irq(port->irqs[i], port); 1203 kfree(port->irqstr[i]); 1204 1205 if (SCIx_IRQ_IS_MUXED(port)) { 1206 /* If there's only one IRQ, we're done. */ 1207 return; 1208 } 1209 } 1210 } 1211 1212 static unsigned int sci_tx_empty(struct uart_port *port) 1213 { 1214 unsigned short status = serial_port_in(port, SCxSR); 1215 unsigned short in_tx_fifo = sci_txfill(port); 1216 1217 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1218 } 1219 1220 /* 1221 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1222 * CTS/RTS is supported in hardware by at least one port and controlled 1223 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1224 * handled via the ->init_pins() op, which is a bit of a one-way street, 1225 * lacking any ability to defer pin control -- this will later be 1226 * converted over to the GPIO framework). 1227 * 1228 * Other modes (such as loopback) are supported generically on certain 1229 * port types, but not others. For these it's sufficient to test for the 1230 * existence of the support register and simply ignore the port type. 1231 */ 1232 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1233 { 1234 if (mctrl & TIOCM_LOOP) { 1235 struct plat_sci_reg *reg; 1236 1237 /* 1238 * Standard loopback mode for SCFCR ports. 1239 */ 1240 reg = sci_getreg(port, SCFCR); 1241 if (reg->size) 1242 serial_port_out(port, SCFCR, 1243 serial_port_in(port, SCFCR) | 1244 SCFCR_LOOP); 1245 } 1246 } 1247 1248 static unsigned int sci_get_mctrl(struct uart_port *port) 1249 { 1250 /* 1251 * CTS/RTS is handled in hardware when supported, while nothing 1252 * else is wired up. Keep it simple and simply assert DSR/CAR. 1253 */ 1254 return TIOCM_DSR | TIOCM_CAR; 1255 } 1256 1257 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1258 static void sci_dma_tx_complete(void *arg) 1259 { 1260 struct sci_port *s = arg; 1261 struct uart_port *port = &s->port; 1262 struct circ_buf *xmit = &port->state->xmit; 1263 unsigned long flags; 1264 1265 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1266 1267 spin_lock_irqsave(&port->lock, flags); 1268 1269 xmit->tail += sg_dma_len(&s->sg_tx); 1270 xmit->tail &= UART_XMIT_SIZE - 1; 1271 1272 port->icount.tx += sg_dma_len(&s->sg_tx); 1273 1274 async_tx_ack(s->desc_tx); 1275 s->desc_tx = NULL; 1276 1277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1278 uart_write_wakeup(port); 1279 1280 if (!uart_circ_empty(xmit)) { 1281 s->cookie_tx = 0; 1282 schedule_work(&s->work_tx); 1283 } else { 1284 s->cookie_tx = -EINVAL; 1285 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1286 u16 ctrl = serial_port_in(port, SCSCR); 1287 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1288 } 1289 } 1290 1291 spin_unlock_irqrestore(&port->lock, flags); 1292 } 1293 1294 /* Locking: called with port lock held */ 1295 static int sci_dma_rx_push(struct sci_port *s, size_t count) 1296 { 1297 struct uart_port *port = &s->port; 1298 struct tty_port *tport = &port->state->port; 1299 int i, active, room; 1300 1301 room = tty_buffer_request_room(tport, count); 1302 1303 if (s->active_rx == s->cookie_rx[0]) { 1304 active = 0; 1305 } else if (s->active_rx == s->cookie_rx[1]) { 1306 active = 1; 1307 } else { 1308 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1309 return 0; 1310 } 1311 1312 if (room < count) 1313 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", 1314 count - room); 1315 if (!room) 1316 return room; 1317 1318 for (i = 0; i < room; i++) 1319 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1320 TTY_NORMAL); 1321 1322 port->icount.rx += room; 1323 1324 return room; 1325 } 1326 1327 static void sci_dma_rx_complete(void *arg) 1328 { 1329 struct sci_port *s = arg; 1330 struct uart_port *port = &s->port; 1331 unsigned long flags; 1332 int count; 1333 1334 dev_dbg(port->dev, "%s(%d) active #%d\n", 1335 __func__, port->line, s->active_rx); 1336 1337 spin_lock_irqsave(&port->lock, flags); 1338 1339 count = sci_dma_rx_push(s, s->buf_len_rx); 1340 1341 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1342 1343 spin_unlock_irqrestore(&port->lock, flags); 1344 1345 if (count) 1346 tty_flip_buffer_push(&port->state->port); 1347 1348 schedule_work(&s->work_rx); 1349 } 1350 1351 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1352 { 1353 struct dma_chan *chan = s->chan_rx; 1354 struct uart_port *port = &s->port; 1355 1356 s->chan_rx = NULL; 1357 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1358 dma_release_channel(chan); 1359 if (sg_dma_address(&s->sg_rx[0])) 1360 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1361 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1362 if (enable_pio) 1363 sci_start_rx(port); 1364 } 1365 1366 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1367 { 1368 struct dma_chan *chan = s->chan_tx; 1369 struct uart_port *port = &s->port; 1370 1371 s->chan_tx = NULL; 1372 s->cookie_tx = -EINVAL; 1373 dma_release_channel(chan); 1374 if (enable_pio) 1375 sci_start_tx(port); 1376 } 1377 1378 static void sci_submit_rx(struct sci_port *s) 1379 { 1380 struct dma_chan *chan = s->chan_rx; 1381 int i; 1382 1383 for (i = 0; i < 2; i++) { 1384 struct scatterlist *sg = &s->sg_rx[i]; 1385 struct dma_async_tx_descriptor *desc; 1386 1387 desc = dmaengine_prep_slave_sg(chan, 1388 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1389 1390 if (desc) { 1391 s->desc_rx[i] = desc; 1392 desc->callback = sci_dma_rx_complete; 1393 desc->callback_param = s; 1394 s->cookie_rx[i] = desc->tx_submit(desc); 1395 } 1396 1397 if (!desc || s->cookie_rx[i] < 0) { 1398 if (i) { 1399 async_tx_ack(s->desc_rx[0]); 1400 s->cookie_rx[0] = -EINVAL; 1401 } 1402 if (desc) { 1403 async_tx_ack(desc); 1404 s->cookie_rx[i] = -EINVAL; 1405 } 1406 dev_warn(s->port.dev, 1407 "failed to re-start DMA, using PIO\n"); 1408 sci_rx_dma_release(s, true); 1409 return; 1410 } 1411 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", 1412 __func__, s->cookie_rx[i], i); 1413 } 1414 1415 s->active_rx = s->cookie_rx[0]; 1416 1417 dma_async_issue_pending(chan); 1418 } 1419 1420 static void work_fn_rx(struct work_struct *work) 1421 { 1422 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1423 struct uart_port *port = &s->port; 1424 struct dma_async_tx_descriptor *desc; 1425 int new; 1426 1427 if (s->active_rx == s->cookie_rx[0]) { 1428 new = 0; 1429 } else if (s->active_rx == s->cookie_rx[1]) { 1430 new = 1; 1431 } else { 1432 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1433 return; 1434 } 1435 desc = s->desc_rx[new]; 1436 1437 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1438 DMA_COMPLETE) { 1439 /* Handle incomplete DMA receive */ 1440 struct dma_chan *chan = s->chan_rx; 1441 struct shdma_desc *sh_desc = container_of(desc, 1442 struct shdma_desc, async_tx); 1443 unsigned long flags; 1444 int count; 1445 1446 dmaengine_terminate_all(chan); 1447 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n", 1448 sh_desc->partial, sh_desc->cookie); 1449 1450 spin_lock_irqsave(&port->lock, flags); 1451 count = sci_dma_rx_push(s, sh_desc->partial); 1452 spin_unlock_irqrestore(&port->lock, flags); 1453 1454 if (count) 1455 tty_flip_buffer_push(&port->state->port); 1456 1457 sci_submit_rx(s); 1458 1459 return; 1460 } 1461 1462 s->cookie_rx[new] = desc->tx_submit(desc); 1463 if (s->cookie_rx[new] < 0) { 1464 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1465 sci_rx_dma_release(s, true); 1466 return; 1467 } 1468 1469 s->active_rx = s->cookie_rx[!new]; 1470 1471 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", 1472 __func__, s->cookie_rx[new], new, s->active_rx); 1473 } 1474 1475 static void work_fn_tx(struct work_struct *work) 1476 { 1477 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1478 struct dma_async_tx_descriptor *desc; 1479 struct dma_chan *chan = s->chan_tx; 1480 struct uart_port *port = &s->port; 1481 struct circ_buf *xmit = &port->state->xmit; 1482 struct scatterlist *sg = &s->sg_tx; 1483 1484 /* 1485 * DMA is idle now. 1486 * Port xmit buffer is already mapped, and it is one page... Just adjust 1487 * offsets and lengths. Since it is a circular buffer, we have to 1488 * transmit till the end, and then the rest. Take the port lock to get a 1489 * consistent xmit buffer state. 1490 */ 1491 spin_lock_irq(&port->lock); 1492 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1493 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1494 sg->offset; 1495 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1496 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1497 spin_unlock_irq(&port->lock); 1498 1499 BUG_ON(!sg_dma_len(sg)); 1500 1501 desc = dmaengine_prep_slave_sg(chan, 1502 sg, s->sg_len_tx, DMA_MEM_TO_DEV, 1503 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1504 if (!desc) { 1505 /* switch to PIO */ 1506 sci_tx_dma_release(s, true); 1507 return; 1508 } 1509 1510 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1511 1512 spin_lock_irq(&port->lock); 1513 s->desc_tx = desc; 1514 desc->callback = sci_dma_tx_complete; 1515 desc->callback_param = s; 1516 spin_unlock_irq(&port->lock); 1517 s->cookie_tx = desc->tx_submit(desc); 1518 if (s->cookie_tx < 0) { 1519 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1520 /* switch to PIO */ 1521 sci_tx_dma_release(s, true); 1522 return; 1523 } 1524 1525 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1526 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1527 1528 dma_async_issue_pending(chan); 1529 } 1530 #endif 1531 1532 static void sci_start_tx(struct uart_port *port) 1533 { 1534 struct sci_port *s = to_sci_port(port); 1535 unsigned short ctrl; 1536 1537 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1538 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1539 u16 new, scr = serial_port_in(port, SCSCR); 1540 if (s->chan_tx) 1541 new = scr | SCSCR_TDRQE; 1542 else 1543 new = scr & ~SCSCR_TDRQE; 1544 if (new != scr) 1545 serial_port_out(port, SCSCR, new); 1546 } 1547 1548 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1549 s->cookie_tx < 0) { 1550 s->cookie_tx = 0; 1551 schedule_work(&s->work_tx); 1552 } 1553 #endif 1554 1555 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1556 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1557 ctrl = serial_port_in(port, SCSCR); 1558 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 1559 } 1560 } 1561 1562 static void sci_stop_tx(struct uart_port *port) 1563 { 1564 unsigned short ctrl; 1565 1566 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1567 ctrl = serial_port_in(port, SCSCR); 1568 1569 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1570 ctrl &= ~SCSCR_TDRQE; 1571 1572 ctrl &= ~SCSCR_TIE; 1573 1574 serial_port_out(port, SCSCR, ctrl); 1575 } 1576 1577 static void sci_start_rx(struct uart_port *port) 1578 { 1579 unsigned short ctrl; 1580 1581 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 1582 1583 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1584 ctrl &= ~SCSCR_RDRQE; 1585 1586 serial_port_out(port, SCSCR, ctrl); 1587 } 1588 1589 static void sci_stop_rx(struct uart_port *port) 1590 { 1591 unsigned short ctrl; 1592 1593 ctrl = serial_port_in(port, SCSCR); 1594 1595 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1596 ctrl &= ~SCSCR_RDRQE; 1597 1598 ctrl &= ~port_rx_irq_mask(port); 1599 1600 serial_port_out(port, SCSCR, ctrl); 1601 } 1602 1603 static void sci_break_ctl(struct uart_port *port, int break_state) 1604 { 1605 struct sci_port *s = to_sci_port(port); 1606 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 1607 unsigned short scscr, scsptr; 1608 1609 /* check wheter the port has SCSPTR */ 1610 if (!reg->size) { 1611 /* 1612 * Not supported by hardware. Most parts couple break and rx 1613 * interrupts together, with break detection always enabled. 1614 */ 1615 return; 1616 } 1617 1618 scsptr = serial_port_in(port, SCSPTR); 1619 scscr = serial_port_in(port, SCSCR); 1620 1621 if (break_state == -1) { 1622 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1623 scscr &= ~SCSCR_TE; 1624 } else { 1625 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1626 scscr |= SCSCR_TE; 1627 } 1628 1629 serial_port_out(port, SCSPTR, scsptr); 1630 serial_port_out(port, SCSCR, scscr); 1631 } 1632 1633 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1634 static bool filter(struct dma_chan *chan, void *slave) 1635 { 1636 struct sh_dmae_slave *param = slave; 1637 1638 dev_dbg(chan->device->dev, "%s: slave ID %d\n", 1639 __func__, param->shdma_slave.slave_id); 1640 1641 chan->private = ¶m->shdma_slave; 1642 return true; 1643 } 1644 1645 static void rx_timer_fn(unsigned long arg) 1646 { 1647 struct sci_port *s = (struct sci_port *)arg; 1648 struct uart_port *port = &s->port; 1649 u16 scr = serial_port_in(port, SCSCR); 1650 1651 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1652 scr &= ~SCSCR_RDRQE; 1653 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1654 } 1655 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1656 dev_dbg(port->dev, "DMA Rx timed out\n"); 1657 schedule_work(&s->work_rx); 1658 } 1659 1660 static void sci_request_dma(struct uart_port *port) 1661 { 1662 struct sci_port *s = to_sci_port(port); 1663 struct sh_dmae_slave *param; 1664 struct dma_chan *chan; 1665 dma_cap_mask_t mask; 1666 int nent; 1667 1668 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1669 1670 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1671 return; 1672 1673 dma_cap_zero(mask); 1674 dma_cap_set(DMA_SLAVE, mask); 1675 1676 param = &s->param_tx; 1677 1678 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1679 param->shdma_slave.slave_id = s->cfg->dma_slave_tx; 1680 1681 s->cookie_tx = -EINVAL; 1682 chan = dma_request_channel(mask, filter, param); 1683 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1684 if (chan) { 1685 s->chan_tx = chan; 1686 sg_init_table(&s->sg_tx, 1); 1687 /* UART circular tx buffer is an aligned page. */ 1688 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK); 1689 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1690 UART_XMIT_SIZE, 1691 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK); 1692 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1693 if (!nent) 1694 sci_tx_dma_release(s, false); 1695 else 1696 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", 1697 __func__, 1698 sg_dma_len(&s->sg_tx), port->state->xmit.buf, 1699 &sg_dma_address(&s->sg_tx)); 1700 1701 s->sg_len_tx = nent; 1702 1703 INIT_WORK(&s->work_tx, work_fn_tx); 1704 } 1705 1706 param = &s->param_rx; 1707 1708 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1709 param->shdma_slave.slave_id = s->cfg->dma_slave_rx; 1710 1711 chan = dma_request_channel(mask, filter, param); 1712 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1713 if (chan) { 1714 dma_addr_t dma[2]; 1715 void *buf[2]; 1716 int i; 1717 1718 s->chan_rx = chan; 1719 1720 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1721 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1722 &dma[0], GFP_KERNEL); 1723 1724 if (!buf[0]) { 1725 dev_warn(port->dev, 1726 "failed to allocate dma buffer, using PIO\n"); 1727 sci_rx_dma_release(s, true); 1728 return; 1729 } 1730 1731 buf[1] = buf[0] + s->buf_len_rx; 1732 dma[1] = dma[0] + s->buf_len_rx; 1733 1734 for (i = 0; i < 2; i++) { 1735 struct scatterlist *sg = &s->sg_rx[i]; 1736 1737 sg_init_table(sg, 1); 1738 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1739 (uintptr_t)buf[i] & ~PAGE_MASK); 1740 sg_dma_address(sg) = dma[i]; 1741 } 1742 1743 INIT_WORK(&s->work_rx, work_fn_rx); 1744 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1745 1746 sci_submit_rx(s); 1747 } 1748 } 1749 1750 static void sci_free_dma(struct uart_port *port) 1751 { 1752 struct sci_port *s = to_sci_port(port); 1753 1754 if (s->chan_tx) 1755 sci_tx_dma_release(s, false); 1756 if (s->chan_rx) 1757 sci_rx_dma_release(s, false); 1758 } 1759 #else 1760 static inline void sci_request_dma(struct uart_port *port) 1761 { 1762 } 1763 1764 static inline void sci_free_dma(struct uart_port *port) 1765 { 1766 } 1767 #endif 1768 1769 static int sci_startup(struct uart_port *port) 1770 { 1771 struct sci_port *s = to_sci_port(port); 1772 unsigned long flags; 1773 int ret; 1774 1775 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1776 1777 ret = sci_request_irq(s); 1778 if (unlikely(ret < 0)) 1779 return ret; 1780 1781 sci_request_dma(port); 1782 1783 spin_lock_irqsave(&port->lock, flags); 1784 sci_start_tx(port); 1785 sci_start_rx(port); 1786 spin_unlock_irqrestore(&port->lock, flags); 1787 1788 return 0; 1789 } 1790 1791 static void sci_shutdown(struct uart_port *port) 1792 { 1793 struct sci_port *s = to_sci_port(port); 1794 unsigned long flags; 1795 1796 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1797 1798 spin_lock_irqsave(&port->lock, flags); 1799 sci_stop_rx(port); 1800 sci_stop_tx(port); 1801 spin_unlock_irqrestore(&port->lock, flags); 1802 1803 sci_free_dma(port); 1804 sci_free_irq(s); 1805 } 1806 1807 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 1808 unsigned long freq) 1809 { 1810 if (s->sampling_rate) 1811 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; 1812 1813 /* Warn, but use a safe default */ 1814 WARN_ON(1); 1815 1816 return ((freq + 16 * bps) / (32 * bps) - 1); 1817 } 1818 1819 /* calculate frame length from SMR */ 1820 static int sci_baud_calc_frame_len(unsigned int smr_val) 1821 { 1822 int len = 10; 1823 1824 if (smr_val & SCSMR_CHR) 1825 len--; 1826 if (smr_val & SCSMR_PE) 1827 len++; 1828 if (smr_val & SCSMR_STOP) 1829 len++; 1830 1831 return len; 1832 } 1833 1834 1835 /* calculate sample rate, BRR, and clock select for HSCIF */ 1836 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, 1837 int *brr, unsigned int *srr, 1838 unsigned int *cks, int frame_len) 1839 { 1840 int sr, c, br, err, recv_margin; 1841 int min_err = 1000; /* 100% */ 1842 int recv_max_margin = 0; 1843 1844 /* Find the combination of sample rate and clock select with the 1845 smallest deviation from the desired baud rate. */ 1846 for (sr = 8; sr <= 32; sr++) { 1847 for (c = 0; c <= 3; c++) { 1848 /* integerized formulas from HSCIF documentation */ 1849 br = DIV_ROUND_CLOSEST(freq, (sr * 1850 (1 << (2 * c + 1)) * bps)) - 1; 1851 br = clamp(br, 0, 255); 1852 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr * 1853 (1 << (2 * c + 1)) / 1000)) - 1854 1000; 1855 /* Calc recv margin 1856 * M: Receive margin (%) 1857 * N: Ratio of bit rate to clock (N = sampling rate) 1858 * D: Clock duty (D = 0 to 1.0) 1859 * L: Frame length (L = 9 to 12) 1860 * F: Absolute value of clock frequency deviation 1861 * 1862 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 1863 * (|D - 0.5| / N * (1 + F))| 1864 * NOTE: Usually, treat D for 0.5, F is 0 by this 1865 * calculation. 1866 */ 1867 recv_margin = abs((500 - 1868 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10); 1869 if (abs(min_err) > abs(err)) { 1870 min_err = err; 1871 recv_max_margin = recv_margin; 1872 } else if ((min_err == err) && 1873 (recv_margin > recv_max_margin)) 1874 recv_max_margin = recv_margin; 1875 else 1876 continue; 1877 1878 *brr = br; 1879 *srr = sr - 1; 1880 *cks = c; 1881 } 1882 } 1883 1884 if (min_err == 1000) { 1885 WARN_ON(1); 1886 /* use defaults */ 1887 *brr = 255; 1888 *srr = 15; 1889 *cks = 0; 1890 } 1891 } 1892 1893 static void sci_reset(struct uart_port *port) 1894 { 1895 struct plat_sci_reg *reg; 1896 unsigned int status; 1897 1898 do { 1899 status = serial_port_in(port, SCxSR); 1900 } while (!(status & SCxSR_TEND(port))); 1901 1902 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1903 1904 reg = sci_getreg(port, SCFCR); 1905 if (reg->size) 1906 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1907 } 1908 1909 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1910 struct ktermios *old) 1911 { 1912 struct sci_port *s = to_sci_port(port); 1913 struct plat_sci_reg *reg; 1914 unsigned int baud, smr_val = 0, max_baud, cks = 0; 1915 int t = -1; 1916 unsigned int srr = 15; 1917 1918 if ((termios->c_cflag & CSIZE) == CS7) 1919 smr_val |= SCSMR_CHR; 1920 if (termios->c_cflag & PARENB) 1921 smr_val |= SCSMR_PE; 1922 if (termios->c_cflag & PARODD) 1923 smr_val |= SCSMR_PE | SCSMR_ODD; 1924 if (termios->c_cflag & CSTOPB) 1925 smr_val |= SCSMR_STOP; 1926 1927 /* 1928 * earlyprintk comes here early on with port->uartclk set to zero. 1929 * the clock framework is not up and running at this point so here 1930 * we assume that 115200 is the maximum baud rate. please note that 1931 * the baud rate is not programmed during earlyprintk - it is assumed 1932 * that the previous boot loader has enabled required clocks and 1933 * setup the baud rate generator hardware for us already. 1934 */ 1935 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1936 1937 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1938 if (likely(baud && port->uartclk)) { 1939 if (s->cfg->type == PORT_HSCIF) { 1940 int frame_len = sci_baud_calc_frame_len(smr_val); 1941 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, 1942 &cks, frame_len); 1943 } else { 1944 t = sci_scbrr_calc(s, baud, port->uartclk); 1945 for (cks = 0; t >= 256 && cks <= 3; cks++) 1946 t >>= 2; 1947 } 1948 } 1949 1950 sci_port_enable(s); 1951 1952 sci_reset(port); 1953 1954 smr_val |= serial_port_in(port, SCSMR) & 3; 1955 1956 uart_update_timeout(port, termios->c_cflag, baud); 1957 1958 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", 1959 __func__, smr_val, cks, t, s->cfg->scscr); 1960 1961 if (t >= 0) { 1962 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks); 1963 serial_port_out(port, SCBRR, t); 1964 reg = sci_getreg(port, HSSRR); 1965 if (reg->size) 1966 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 1967 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1968 } else 1969 serial_port_out(port, SCSMR, smr_val); 1970 1971 sci_init_pins(port, termios->c_cflag); 1972 1973 reg = sci_getreg(port, SCFCR); 1974 if (reg->size) { 1975 unsigned short ctrl = serial_port_in(port, SCFCR); 1976 1977 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { 1978 if (termios->c_cflag & CRTSCTS) 1979 ctrl |= SCFCR_MCE; 1980 else 1981 ctrl &= ~SCFCR_MCE; 1982 } 1983 1984 /* 1985 * As we've done a sci_reset() above, ensure we don't 1986 * interfere with the FIFOs while toggling MCE. As the 1987 * reset values could still be set, simply mask them out. 1988 */ 1989 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 1990 1991 serial_port_out(port, SCFCR, ctrl); 1992 } 1993 1994 serial_port_out(port, SCSCR, s->cfg->scscr); 1995 1996 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1997 /* 1998 * Calculate delay for 2 DMA buffers (4 FIFO). 1999 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10 2000 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 2001 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 2002 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO 2003 * sizes), but when performing a faster transfer, value obtained by 2004 * this formula is may not enough. Therefore, if value is smaller than 2005 * 20msec, this sets 20msec as timeout of DMA. 2006 */ 2007 if (s->chan_rx) { 2008 unsigned int bits; 2009 2010 /* byte size and parity */ 2011 switch (termios->c_cflag & CSIZE) { 2012 case CS5: 2013 bits = 7; 2014 break; 2015 case CS6: 2016 bits = 8; 2017 break; 2018 case CS7: 2019 bits = 9; 2020 break; 2021 default: 2022 bits = 10; 2023 break; 2024 } 2025 2026 if (termios->c_cflag & CSTOPB) 2027 bits++; 2028 if (termios->c_cflag & PARENB) 2029 bits++; 2030 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) / 2031 (baud / 10), 10); 2032 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", 2033 s->rx_timeout * 1000 / HZ, port->timeout); 2034 if (s->rx_timeout < msecs_to_jiffies(20)) 2035 s->rx_timeout = msecs_to_jiffies(20); 2036 } 2037 #endif 2038 2039 if ((termios->c_cflag & CREAD) != 0) 2040 sci_start_rx(port); 2041 2042 sci_port_disable(s); 2043 } 2044 2045 static void sci_pm(struct uart_port *port, unsigned int state, 2046 unsigned int oldstate) 2047 { 2048 struct sci_port *sci_port = to_sci_port(port); 2049 2050 switch (state) { 2051 case UART_PM_STATE_OFF: 2052 sci_port_disable(sci_port); 2053 break; 2054 default: 2055 sci_port_enable(sci_port); 2056 break; 2057 } 2058 } 2059 2060 static const char *sci_type(struct uart_port *port) 2061 { 2062 switch (port->type) { 2063 case PORT_IRDA: 2064 return "irda"; 2065 case PORT_SCI: 2066 return "sci"; 2067 case PORT_SCIF: 2068 return "scif"; 2069 case PORT_SCIFA: 2070 return "scifa"; 2071 case PORT_SCIFB: 2072 return "scifb"; 2073 case PORT_HSCIF: 2074 return "hscif"; 2075 } 2076 2077 return NULL; 2078 } 2079 2080 static int sci_remap_port(struct uart_port *port) 2081 { 2082 struct sci_port *sport = to_sci_port(port); 2083 2084 /* 2085 * Nothing to do if there's already an established membase. 2086 */ 2087 if (port->membase) 2088 return 0; 2089 2090 if (port->flags & UPF_IOREMAP) { 2091 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2092 if (unlikely(!port->membase)) { 2093 dev_err(port->dev, "can't remap port#%d\n", port->line); 2094 return -ENXIO; 2095 } 2096 } else { 2097 /* 2098 * For the simple (and majority of) cases where we don't 2099 * need to do any remapping, just cast the cookie 2100 * directly. 2101 */ 2102 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2103 } 2104 2105 return 0; 2106 } 2107 2108 static void sci_release_port(struct uart_port *port) 2109 { 2110 struct sci_port *sport = to_sci_port(port); 2111 2112 if (port->flags & UPF_IOREMAP) { 2113 iounmap(port->membase); 2114 port->membase = NULL; 2115 } 2116 2117 release_mem_region(port->mapbase, sport->reg_size); 2118 } 2119 2120 static int sci_request_port(struct uart_port *port) 2121 { 2122 struct resource *res; 2123 struct sci_port *sport = to_sci_port(port); 2124 int ret; 2125 2126 res = request_mem_region(port->mapbase, sport->reg_size, 2127 dev_name(port->dev)); 2128 if (unlikely(res == NULL)) { 2129 dev_err(port->dev, "request_mem_region failed."); 2130 return -EBUSY; 2131 } 2132 2133 ret = sci_remap_port(port); 2134 if (unlikely(ret != 0)) { 2135 release_resource(res); 2136 return ret; 2137 } 2138 2139 return 0; 2140 } 2141 2142 static void sci_config_port(struct uart_port *port, int flags) 2143 { 2144 if (flags & UART_CONFIG_TYPE) { 2145 struct sci_port *sport = to_sci_port(port); 2146 2147 port->type = sport->cfg->type; 2148 sci_request_port(port); 2149 } 2150 } 2151 2152 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2153 { 2154 if (ser->baud_base < 2400) 2155 /* No paper tape reader for Mitch.. */ 2156 return -EINVAL; 2157 2158 return 0; 2159 } 2160 2161 static struct uart_ops sci_uart_ops = { 2162 .tx_empty = sci_tx_empty, 2163 .set_mctrl = sci_set_mctrl, 2164 .get_mctrl = sci_get_mctrl, 2165 .start_tx = sci_start_tx, 2166 .stop_tx = sci_stop_tx, 2167 .stop_rx = sci_stop_rx, 2168 .break_ctl = sci_break_ctl, 2169 .startup = sci_startup, 2170 .shutdown = sci_shutdown, 2171 .set_termios = sci_set_termios, 2172 .pm = sci_pm, 2173 .type = sci_type, 2174 .release_port = sci_release_port, 2175 .request_port = sci_request_port, 2176 .config_port = sci_config_port, 2177 .verify_port = sci_verify_port, 2178 #ifdef CONFIG_CONSOLE_POLL 2179 .poll_get_char = sci_poll_get_char, 2180 .poll_put_char = sci_poll_put_char, 2181 #endif 2182 }; 2183 2184 static int sci_init_single(struct platform_device *dev, 2185 struct sci_port *sci_port, unsigned int index, 2186 struct plat_sci_port *p, bool early) 2187 { 2188 struct uart_port *port = &sci_port->port; 2189 const struct resource *res; 2190 unsigned int sampling_rate; 2191 unsigned int i; 2192 int ret; 2193 2194 sci_port->cfg = p; 2195 2196 port->ops = &sci_uart_ops; 2197 port->iotype = UPIO_MEM; 2198 port->line = index; 2199 2200 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2201 if (res == NULL) 2202 return -ENOMEM; 2203 2204 port->mapbase = res->start; 2205 sci_port->reg_size = resource_size(res); 2206 2207 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2208 sci_port->irqs[i] = platform_get_irq(dev, i); 2209 2210 /* The SCI generates several interrupts. They can be muxed together or 2211 * connected to different interrupt lines. In the muxed case only one 2212 * interrupt resource is specified. In the non-muxed case three or four 2213 * interrupt resources are specified, as the BRI interrupt is optional. 2214 */ 2215 if (sci_port->irqs[0] < 0) 2216 return -ENXIO; 2217 2218 if (sci_port->irqs[1] < 0) { 2219 sci_port->irqs[1] = sci_port->irqs[0]; 2220 sci_port->irqs[2] = sci_port->irqs[0]; 2221 sci_port->irqs[3] = sci_port->irqs[0]; 2222 } 2223 2224 if (p->regtype == SCIx_PROBE_REGTYPE) { 2225 ret = sci_probe_regmap(p); 2226 if (unlikely(ret)) 2227 return ret; 2228 } 2229 2230 switch (p->type) { 2231 case PORT_SCIFB: 2232 port->fifosize = 256; 2233 sci_port->overrun_reg = SCxSR; 2234 sci_port->overrun_mask = SCIFA_ORER; 2235 sampling_rate = 16; 2236 break; 2237 case PORT_HSCIF: 2238 port->fifosize = 128; 2239 sampling_rate = 0; 2240 sci_port->overrun_reg = SCLSR; 2241 sci_port->overrun_mask = SCLSR_ORER; 2242 break; 2243 case PORT_SCIFA: 2244 port->fifosize = 64; 2245 sci_port->overrun_reg = SCxSR; 2246 sci_port->overrun_mask = SCIFA_ORER; 2247 sampling_rate = 16; 2248 break; 2249 case PORT_SCIF: 2250 port->fifosize = 16; 2251 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { 2252 sci_port->overrun_reg = SCxSR; 2253 sci_port->overrun_mask = SCIFA_ORER; 2254 sampling_rate = 16; 2255 } else { 2256 sci_port->overrun_reg = SCLSR; 2257 sci_port->overrun_mask = SCLSR_ORER; 2258 sampling_rate = 32; 2259 } 2260 break; 2261 default: 2262 port->fifosize = 1; 2263 sci_port->overrun_reg = SCxSR; 2264 sci_port->overrun_mask = SCI_ORER; 2265 sampling_rate = 32; 2266 break; 2267 } 2268 2269 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2270 * match the SoC datasheet, this should be investigated. Let platform 2271 * data override the sampling rate for now. 2272 */ 2273 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate 2274 : sampling_rate; 2275 2276 if (!early) { 2277 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2278 if (IS_ERR(sci_port->iclk)) { 2279 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 2280 if (IS_ERR(sci_port->iclk)) { 2281 dev_err(&dev->dev, "can't get iclk\n"); 2282 return PTR_ERR(sci_port->iclk); 2283 } 2284 } 2285 2286 /* 2287 * The function clock is optional, ignore it if we can't 2288 * find it. 2289 */ 2290 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 2291 if (IS_ERR(sci_port->fclk)) 2292 sci_port->fclk = NULL; 2293 2294 port->dev = &dev->dev; 2295 2296 pm_runtime_enable(&dev->dev); 2297 } 2298 2299 sci_port->break_timer.data = (unsigned long)sci_port; 2300 sci_port->break_timer.function = sci_break_timer; 2301 init_timer(&sci_port->break_timer); 2302 2303 /* 2304 * Establish some sensible defaults for the error detection. 2305 */ 2306 sci_port->error_mask = (p->type == PORT_SCI) ? 2307 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 2308 2309 /* 2310 * Make the error mask inclusive of overrun detection, if 2311 * supported. 2312 */ 2313 if (sci_port->overrun_reg == SCxSR) 2314 sci_port->error_mask |= sci_port->overrun_mask; 2315 2316 port->type = p->type; 2317 port->flags = UPF_FIXED_PORT | p->flags; 2318 port->regshift = p->regshift; 2319 2320 /* 2321 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2322 * for the multi-IRQ ports, which is where we are primarily 2323 * concerned with the shutdown path synchronization. 2324 * 2325 * For the muxed case there's nothing more to do. 2326 */ 2327 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2328 port->irqflags = 0; 2329 2330 port->serial_in = sci_serial_in; 2331 port->serial_out = sci_serial_out; 2332 2333 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 2334 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 2335 p->dma_slave_tx, p->dma_slave_rx); 2336 2337 return 0; 2338 } 2339 2340 static void sci_cleanup_single(struct sci_port *port) 2341 { 2342 clk_put(port->iclk); 2343 clk_put(port->fclk); 2344 2345 pm_runtime_disable(port->port.dev); 2346 } 2347 2348 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2349 static void serial_console_putchar(struct uart_port *port, int ch) 2350 { 2351 sci_poll_put_char(port, ch); 2352 } 2353 2354 /* 2355 * Print a string to the serial port trying not to disturb 2356 * any possible real use of the port... 2357 */ 2358 static void serial_console_write(struct console *co, const char *s, 2359 unsigned count) 2360 { 2361 struct sci_port *sci_port = &sci_ports[co->index]; 2362 struct uart_port *port = &sci_port->port; 2363 unsigned short bits, ctrl; 2364 unsigned long flags; 2365 int locked = 1; 2366 2367 local_irq_save(flags); 2368 if (port->sysrq) 2369 locked = 0; 2370 else if (oops_in_progress) 2371 locked = spin_trylock(&port->lock); 2372 else 2373 spin_lock(&port->lock); 2374 2375 /* first save the SCSCR then disable the interrupts */ 2376 ctrl = serial_port_in(port, SCSCR); 2377 serial_port_out(port, SCSCR, sci_port->cfg->scscr); 2378 2379 uart_console_write(port, s, count, serial_console_putchar); 2380 2381 /* wait until fifo is empty and last bit has been transmitted */ 2382 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2383 while ((serial_port_in(port, SCxSR) & bits) != bits) 2384 cpu_relax(); 2385 2386 /* restore the SCSCR */ 2387 serial_port_out(port, SCSCR, ctrl); 2388 2389 if (locked) 2390 spin_unlock(&port->lock); 2391 local_irq_restore(flags); 2392 } 2393 2394 static int serial_console_setup(struct console *co, char *options) 2395 { 2396 struct sci_port *sci_port; 2397 struct uart_port *port; 2398 int baud = 115200; 2399 int bits = 8; 2400 int parity = 'n'; 2401 int flow = 'n'; 2402 int ret; 2403 2404 /* 2405 * Refuse to handle any bogus ports. 2406 */ 2407 if (co->index < 0 || co->index >= SCI_NPORTS) 2408 return -ENODEV; 2409 2410 sci_port = &sci_ports[co->index]; 2411 port = &sci_port->port; 2412 2413 /* 2414 * Refuse to handle uninitialized ports. 2415 */ 2416 if (!port->ops) 2417 return -ENODEV; 2418 2419 ret = sci_remap_port(port); 2420 if (unlikely(ret != 0)) 2421 return ret; 2422 2423 if (options) 2424 uart_parse_options(options, &baud, &parity, &bits, &flow); 2425 2426 return uart_set_options(port, co, baud, parity, bits, flow); 2427 } 2428 2429 static struct console serial_console = { 2430 .name = "ttySC", 2431 .device = uart_console_device, 2432 .write = serial_console_write, 2433 .setup = serial_console_setup, 2434 .flags = CON_PRINTBUFFER, 2435 .index = -1, 2436 .data = &sci_uart_driver, 2437 }; 2438 2439 static struct console early_serial_console = { 2440 .name = "early_ttySC", 2441 .write = serial_console_write, 2442 .flags = CON_PRINTBUFFER, 2443 .index = -1, 2444 }; 2445 2446 static char early_serial_buf[32]; 2447 2448 static int sci_probe_earlyprintk(struct platform_device *pdev) 2449 { 2450 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2451 2452 if (early_serial_console.data) 2453 return -EEXIST; 2454 2455 early_serial_console.index = pdev->id; 2456 2457 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 2458 2459 serial_console_setup(&early_serial_console, early_serial_buf); 2460 2461 if (!strstr(early_serial_buf, "keep")) 2462 early_serial_console.flags |= CON_BOOT; 2463 2464 register_console(&early_serial_console); 2465 return 0; 2466 } 2467 2468 #define SCI_CONSOLE (&serial_console) 2469 2470 #else 2471 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2472 { 2473 return -EINVAL; 2474 } 2475 2476 #define SCI_CONSOLE NULL 2477 2478 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2479 2480 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 2481 2482 static struct uart_driver sci_uart_driver = { 2483 .owner = THIS_MODULE, 2484 .driver_name = "sci", 2485 .dev_name = "ttySC", 2486 .major = SCI_MAJOR, 2487 .minor = SCI_MINOR_START, 2488 .nr = SCI_NPORTS, 2489 .cons = SCI_CONSOLE, 2490 }; 2491 2492 static int sci_remove(struct platform_device *dev) 2493 { 2494 struct sci_port *port = platform_get_drvdata(dev); 2495 2496 cpufreq_unregister_notifier(&port->freq_transition, 2497 CPUFREQ_TRANSITION_NOTIFIER); 2498 2499 uart_remove_one_port(&sci_uart_driver, &port->port); 2500 2501 sci_cleanup_single(port); 2502 2503 return 0; 2504 } 2505 2506 struct sci_port_info { 2507 unsigned int type; 2508 unsigned int regtype; 2509 }; 2510 2511 static const struct of_device_id of_sci_match[] = { 2512 { 2513 .compatible = "renesas,scif", 2514 .data = &(const struct sci_port_info) { 2515 .type = PORT_SCIF, 2516 .regtype = SCIx_SH4_SCIF_REGTYPE, 2517 }, 2518 }, { 2519 .compatible = "renesas,scifa", 2520 .data = &(const struct sci_port_info) { 2521 .type = PORT_SCIFA, 2522 .regtype = SCIx_SCIFA_REGTYPE, 2523 }, 2524 }, { 2525 .compatible = "renesas,scifb", 2526 .data = &(const struct sci_port_info) { 2527 .type = PORT_SCIFB, 2528 .regtype = SCIx_SCIFB_REGTYPE, 2529 }, 2530 }, { 2531 .compatible = "renesas,hscif", 2532 .data = &(const struct sci_port_info) { 2533 .type = PORT_HSCIF, 2534 .regtype = SCIx_HSCIF_REGTYPE, 2535 }, 2536 }, { 2537 .compatible = "renesas,sci", 2538 .data = &(const struct sci_port_info) { 2539 .type = PORT_SCI, 2540 .regtype = SCIx_SCI_REGTYPE, 2541 }, 2542 }, { 2543 /* Terminator */ 2544 }, 2545 }; 2546 MODULE_DEVICE_TABLE(of, of_sci_match); 2547 2548 static struct plat_sci_port * 2549 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) 2550 { 2551 struct device_node *np = pdev->dev.of_node; 2552 const struct of_device_id *match; 2553 const struct sci_port_info *info; 2554 struct plat_sci_port *p; 2555 int id; 2556 2557 if (!IS_ENABLED(CONFIG_OF) || !np) 2558 return NULL; 2559 2560 match = of_match_node(of_sci_match, pdev->dev.of_node); 2561 if (!match) 2562 return NULL; 2563 2564 info = match->data; 2565 2566 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 2567 if (!p) { 2568 dev_err(&pdev->dev, "failed to allocate DT config data\n"); 2569 return NULL; 2570 } 2571 2572 /* Get the line number for the aliases node. */ 2573 id = of_alias_get_id(np, "serial"); 2574 if (id < 0) { 2575 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 2576 return NULL; 2577 } 2578 2579 *dev_id = id; 2580 2581 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; 2582 p->type = info->type; 2583 p->regtype = info->regtype; 2584 p->scscr = SCSCR_RE | SCSCR_TE; 2585 2586 return p; 2587 } 2588 2589 static int sci_probe_single(struct platform_device *dev, 2590 unsigned int index, 2591 struct plat_sci_port *p, 2592 struct sci_port *sciport) 2593 { 2594 int ret; 2595 2596 /* Sanity check */ 2597 if (unlikely(index >= SCI_NPORTS)) { 2598 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 2599 index+1, SCI_NPORTS); 2600 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2601 return -EINVAL; 2602 } 2603 2604 ret = sci_init_single(dev, sciport, index, p, false); 2605 if (ret) 2606 return ret; 2607 2608 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 2609 if (ret) { 2610 sci_cleanup_single(sciport); 2611 return ret; 2612 } 2613 2614 return 0; 2615 } 2616 2617 static int sci_probe(struct platform_device *dev) 2618 { 2619 struct plat_sci_port *p; 2620 struct sci_port *sp; 2621 unsigned int dev_id; 2622 int ret; 2623 2624 /* 2625 * If we've come here via earlyprintk initialization, head off to 2626 * the special early probe. We don't have sufficient device state 2627 * to make it beyond this yet. 2628 */ 2629 if (is_early_platform_device(dev)) 2630 return sci_probe_earlyprintk(dev); 2631 2632 if (dev->dev.of_node) { 2633 p = sci_parse_dt(dev, &dev_id); 2634 if (p == NULL) 2635 return -EINVAL; 2636 } else { 2637 p = dev->dev.platform_data; 2638 if (p == NULL) { 2639 dev_err(&dev->dev, "no platform data supplied\n"); 2640 return -EINVAL; 2641 } 2642 2643 dev_id = dev->id; 2644 } 2645 2646 sp = &sci_ports[dev_id]; 2647 platform_set_drvdata(dev, sp); 2648 2649 ret = sci_probe_single(dev, dev_id, p, sp); 2650 if (ret) 2651 return ret; 2652 2653 sp->freq_transition.notifier_call = sci_notifier; 2654 2655 ret = cpufreq_register_notifier(&sp->freq_transition, 2656 CPUFREQ_TRANSITION_NOTIFIER); 2657 if (unlikely(ret < 0)) { 2658 uart_remove_one_port(&sci_uart_driver, &sp->port); 2659 sci_cleanup_single(sp); 2660 return ret; 2661 } 2662 2663 #ifdef CONFIG_SH_STANDARD_BIOS 2664 sh_bios_gdb_detach(); 2665 #endif 2666 2667 return 0; 2668 } 2669 2670 static __maybe_unused int sci_suspend(struct device *dev) 2671 { 2672 struct sci_port *sport = dev_get_drvdata(dev); 2673 2674 if (sport) 2675 uart_suspend_port(&sci_uart_driver, &sport->port); 2676 2677 return 0; 2678 } 2679 2680 static __maybe_unused int sci_resume(struct device *dev) 2681 { 2682 struct sci_port *sport = dev_get_drvdata(dev); 2683 2684 if (sport) 2685 uart_resume_port(&sci_uart_driver, &sport->port); 2686 2687 return 0; 2688 } 2689 2690 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 2691 2692 static struct platform_driver sci_driver = { 2693 .probe = sci_probe, 2694 .remove = sci_remove, 2695 .driver = { 2696 .name = "sh-sci", 2697 .pm = &sci_dev_pm_ops, 2698 .of_match_table = of_match_ptr(of_sci_match), 2699 }, 2700 }; 2701 2702 static int __init sci_init(void) 2703 { 2704 int ret; 2705 2706 pr_info("%s\n", banner); 2707 2708 ret = uart_register_driver(&sci_uart_driver); 2709 if (likely(ret == 0)) { 2710 ret = platform_driver_register(&sci_driver); 2711 if (unlikely(ret)) 2712 uart_unregister_driver(&sci_uart_driver); 2713 } 2714 2715 return ret; 2716 } 2717 2718 static void __exit sci_exit(void) 2719 { 2720 platform_driver_unregister(&sci_driver); 2721 uart_unregister_driver(&sci_uart_driver); 2722 } 2723 2724 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2725 early_platform_init_buffer("earlyprintk", &sci_driver, 2726 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2727 #endif 2728 module_init(sci_init); 2729 module_exit(sci_exit); 2730 2731 MODULE_LICENSE("GPL"); 2732 MODULE_ALIAS("platform:sh-sci"); 2733 MODULE_AUTHOR("Paul Mundt"); 2734 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 2735