1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "serial_mctrl_gpio.h" 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_DRI_IRQ, 69 SCIx_TEI_IRQ, 70 SCIx_NR_IRQS, 71 72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 73 }; 74 75 #define SCIx_IRQ_IS_MUXED(port) \ 76 ((port)->irqs[SCIx_ERI_IRQ] == \ 77 (port)->irqs[SCIx_RXI_IRQ]) || \ 78 ((port)->irqs[SCIx_ERI_IRQ] && \ 79 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 80 81 enum SCI_CLKS { 82 SCI_FCK, /* Functional Clock */ 83 SCI_SCK, /* Optional External Clock */ 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 86 SCI_NUM_CLKS 87 }; 88 89 /* Bit x set means sampling rate x + 1 is supported */ 90 #define SCI_SR(x) BIT((x) - 1) 91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 92 93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 95 SCI_SR(19) | SCI_SR(27) 96 97 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 98 #define max_sr(_port) fls((_port)->sampling_rate_mask) 99 100 /* Iterate over all supported sampling rates, from high to low */ 101 #define for_each_sr(_sr, _port) \ 102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 103 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 104 105 struct plat_sci_reg { 106 u8 offset, size; 107 }; 108 109 struct sci_port_params { 110 const struct plat_sci_reg regs[SCIx_NR_REGS]; 111 unsigned int fifosize; 112 unsigned int overrun_reg; 113 unsigned int overrun_mask; 114 unsigned int sampling_rate_mask; 115 unsigned int error_mask; 116 unsigned int error_clear; 117 }; 118 119 struct sci_port { 120 struct uart_port port; 121 122 /* Platform configuration */ 123 const struct sci_port_params *params; 124 const struct plat_sci_port *cfg; 125 unsigned int sampling_rate_mask; 126 resource_size_t reg_size; 127 struct mctrl_gpios *gpios; 128 129 /* Clocks */ 130 struct clk *clks[SCI_NUM_CLKS]; 131 unsigned long clk_rates[SCI_NUM_CLKS]; 132 133 int irqs[SCIx_NR_IRQS]; 134 char *irqstr[SCIx_NR_IRQS]; 135 136 struct dma_chan *chan_tx; 137 struct dma_chan *chan_rx; 138 139 #ifdef CONFIG_SERIAL_SH_SCI_DMA 140 struct dma_chan *chan_tx_saved; 141 struct dma_chan *chan_rx_saved; 142 dma_cookie_t cookie_tx; 143 dma_cookie_t cookie_rx[2]; 144 dma_cookie_t active_rx; 145 dma_addr_t tx_dma_addr; 146 unsigned int tx_dma_len; 147 struct scatterlist sg_rx[2]; 148 void *rx_buf[2]; 149 size_t buf_len_rx; 150 struct work_struct work_tx; 151 struct hrtimer rx_timer; 152 unsigned int rx_timeout; /* microseconds */ 153 #endif 154 unsigned int rx_frame; 155 int rx_trigger; 156 struct timer_list rx_fifo_timer; 157 int rx_fifo_timeout; 158 u16 hscif_tot; 159 160 bool has_rtscts; 161 bool autorts; 162 }; 163 164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 165 166 static struct sci_port sci_ports[SCI_NPORTS]; 167 static unsigned long sci_ports_in_use; 168 static struct uart_driver sci_uart_driver; 169 170 static inline struct sci_port * 171 to_sci_port(struct uart_port *uart) 172 { 173 return container_of(uart, struct sci_port, port); 174 } 175 176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 177 /* 178 * Common SCI definitions, dependent on the port's regshift 179 * value. 180 */ 181 [SCIx_SCI_REGTYPE] = { 182 .regs = { 183 [SCSMR] = { 0x00, 8 }, 184 [SCBRR] = { 0x01, 8 }, 185 [SCSCR] = { 0x02, 8 }, 186 [SCxTDR] = { 0x03, 8 }, 187 [SCxSR] = { 0x04, 8 }, 188 [SCxRDR] = { 0x05, 8 }, 189 }, 190 .fifosize = 1, 191 .overrun_reg = SCxSR, 192 .overrun_mask = SCI_ORER, 193 .sampling_rate_mask = SCI_SR(32), 194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 196 }, 197 198 /* 199 * Common definitions for legacy IrDA ports. 200 */ 201 [SCIx_IRDA_REGTYPE] = { 202 .regs = { 203 [SCSMR] = { 0x00, 8 }, 204 [SCBRR] = { 0x02, 8 }, 205 [SCSCR] = { 0x04, 8 }, 206 [SCxTDR] = { 0x06, 8 }, 207 [SCxSR] = { 0x08, 16 }, 208 [SCxRDR] = { 0x0a, 8 }, 209 [SCFCR] = { 0x0c, 8 }, 210 [SCFDR] = { 0x0e, 16 }, 211 }, 212 .fifosize = 1, 213 .overrun_reg = SCxSR, 214 .overrun_mask = SCI_ORER, 215 .sampling_rate_mask = SCI_SR(32), 216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 218 }, 219 220 /* 221 * Common SCIFA definitions. 222 */ 223 [SCIx_SCIFA_REGTYPE] = { 224 .regs = { 225 [SCSMR] = { 0x00, 16 }, 226 [SCBRR] = { 0x04, 8 }, 227 [SCSCR] = { 0x08, 16 }, 228 [SCxTDR] = { 0x20, 8 }, 229 [SCxSR] = { 0x14, 16 }, 230 [SCxRDR] = { 0x24, 8 }, 231 [SCFCR] = { 0x18, 16 }, 232 [SCFDR] = { 0x1c, 16 }, 233 [SCPCR] = { 0x30, 16 }, 234 [SCPDR] = { 0x34, 16 }, 235 }, 236 .fifosize = 64, 237 .overrun_reg = SCxSR, 238 .overrun_mask = SCIFA_ORER, 239 .sampling_rate_mask = SCI_SR_SCIFAB, 240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 242 }, 243 244 /* 245 * Common SCIFB definitions. 246 */ 247 [SCIx_SCIFB_REGTYPE] = { 248 .regs = { 249 [SCSMR] = { 0x00, 16 }, 250 [SCBRR] = { 0x04, 8 }, 251 [SCSCR] = { 0x08, 16 }, 252 [SCxTDR] = { 0x40, 8 }, 253 [SCxSR] = { 0x14, 16 }, 254 [SCxRDR] = { 0x60, 8 }, 255 [SCFCR] = { 0x18, 16 }, 256 [SCTFDR] = { 0x38, 16 }, 257 [SCRFDR] = { 0x3c, 16 }, 258 [SCPCR] = { 0x30, 16 }, 259 [SCPDR] = { 0x34, 16 }, 260 }, 261 .fifosize = 256, 262 .overrun_reg = SCxSR, 263 .overrun_mask = SCIFA_ORER, 264 .sampling_rate_mask = SCI_SR_SCIFAB, 265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 267 }, 268 269 /* 270 * Common SH-2(A) SCIF definitions for ports with FIFO data 271 * count registers. 272 */ 273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 274 .regs = { 275 [SCSMR] = { 0x00, 16 }, 276 [SCBRR] = { 0x04, 8 }, 277 [SCSCR] = { 0x08, 16 }, 278 [SCxTDR] = { 0x0c, 8 }, 279 [SCxSR] = { 0x10, 16 }, 280 [SCxRDR] = { 0x14, 8 }, 281 [SCFCR] = { 0x18, 16 }, 282 [SCFDR] = { 0x1c, 16 }, 283 [SCSPTR] = { 0x20, 16 }, 284 [SCLSR] = { 0x24, 16 }, 285 }, 286 .fifosize = 16, 287 .overrun_reg = SCLSR, 288 .overrun_mask = SCLSR_ORER, 289 .sampling_rate_mask = SCI_SR(32), 290 .error_mask = SCIF_DEFAULT_ERROR_MASK, 291 .error_clear = SCIF_ERROR_CLEAR, 292 }, 293 294 /* 295 * The "SCIFA" that is in RZ/T and RZ/A2. 296 * It looks like a normal SCIF with FIFO data, but with a 297 * compressed address space. Also, the break out of interrupts 298 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 299 */ 300 [SCIx_RZ_SCIFA_REGTYPE] = { 301 .regs = { 302 [SCSMR] = { 0x00, 16 }, 303 [SCBRR] = { 0x02, 8 }, 304 [SCSCR] = { 0x04, 16 }, 305 [SCxTDR] = { 0x06, 8 }, 306 [SCxSR] = { 0x08, 16 }, 307 [SCxRDR] = { 0x0A, 8 }, 308 [SCFCR] = { 0x0C, 16 }, 309 [SCFDR] = { 0x0E, 16 }, 310 [SCSPTR] = { 0x10, 16 }, 311 [SCLSR] = { 0x12, 16 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ 506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 s->cookie_tx = 0; 592 schedule_work(&s->work_tx); 593 } 594 #endif 595 596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 598 ctrl = serial_port_in(port, SCSCR); 599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 600 } 601 } 602 603 static void sci_stop_tx(struct uart_port *port) 604 { 605 unsigned short ctrl; 606 607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 608 ctrl = serial_port_in(port, SCSCR); 609 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 611 ctrl &= ~SCSCR_TDRQE; 612 613 ctrl &= ~SCSCR_TIE; 614 615 serial_port_out(port, SCSCR, ctrl); 616 } 617 618 static void sci_start_rx(struct uart_port *port) 619 { 620 unsigned short ctrl; 621 622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 623 624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 625 ctrl &= ~SCSCR_RDRQE; 626 627 serial_port_out(port, SCSCR, ctrl); 628 } 629 630 static void sci_stop_rx(struct uart_port *port) 631 { 632 unsigned short ctrl; 633 634 ctrl = serial_port_in(port, SCSCR); 635 636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 637 ctrl &= ~SCSCR_RDRQE; 638 639 ctrl &= ~port_rx_irq_mask(port); 640 641 serial_port_out(port, SCSCR, ctrl); 642 } 643 644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 645 { 646 if (port->type == PORT_SCI) { 647 /* Just store the mask */ 648 serial_port_out(port, SCxSR, mask); 649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 651 /* Only clear the status bits we want to clear */ 652 serial_port_out(port, SCxSR, 653 serial_port_in(port, SCxSR) & mask); 654 } else { 655 /* Store the mask, clear parity/framing errors */ 656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 657 } 658 } 659 660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 662 663 #ifdef CONFIG_CONSOLE_POLL 664 static int sci_poll_get_char(struct uart_port *port) 665 { 666 unsigned short status; 667 int c; 668 669 do { 670 status = serial_port_in(port, SCxSR); 671 if (status & SCxSR_ERRORS(port)) { 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 673 continue; 674 } 675 break; 676 } while (1); 677 678 if (!(status & SCxSR_RDxF(port))) 679 return NO_POLL_CHAR; 680 681 c = serial_port_in(port, SCxRDR); 682 683 /* Dummy read */ 684 serial_port_in(port, SCxSR); 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 686 687 return c; 688 } 689 #endif 690 691 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 692 { 693 unsigned short status; 694 695 do { 696 status = serial_port_in(port, SCxSR); 697 } while (!(status & SCxSR_TDxE(port))); 698 699 serial_port_out(port, SCxTDR, c); 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 701 } 702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 703 CONFIG_SERIAL_SH_SCI_EARLYCON */ 704 705 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 706 { 707 struct sci_port *s = to_sci_port(port); 708 709 /* 710 * Use port-specific handler if provided. 711 */ 712 if (s->cfg->ops && s->cfg->ops->init_pins) { 713 s->cfg->ops->init_pins(port, cflag); 714 return; 715 } 716 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 718 u16 data = serial_port_in(port, SCPDR); 719 u16 ctrl = serial_port_in(port, SCPCR); 720 721 /* Enable RXD and TXD pin functions */ 722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 723 if (to_sci_port(port)->has_rtscts) { 724 /* RTS# is output, active low, unless autorts */ 725 if (!(port->mctrl & TIOCM_RTS)) { 726 ctrl |= SCPCR_RTSC; 727 data |= SCPDR_RTSD; 728 } else if (!s->autorts) { 729 ctrl |= SCPCR_RTSC; 730 data &= ~SCPDR_RTSD; 731 } else { 732 /* Enable RTS# pin function */ 733 ctrl &= ~SCPCR_RTSC; 734 } 735 /* Enable CTS# pin function */ 736 ctrl &= ~SCPCR_CTSC; 737 } 738 serial_port_out(port, SCPDR, data); 739 serial_port_out(port, SCPCR, ctrl); 740 } else if (sci_getreg(port, SCSPTR)->size) { 741 u16 status = serial_port_in(port, SCSPTR); 742 743 /* RTS# is always output; and active low, unless autorts */ 744 status |= SCSPTR_RTSIO; 745 if (!(port->mctrl & TIOCM_RTS)) 746 status |= SCSPTR_RTSDT; 747 else if (!s->autorts) 748 status &= ~SCSPTR_RTSDT; 749 /* CTS# and SCK are inputs */ 750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 751 serial_port_out(port, SCSPTR, status); 752 } 753 } 754 755 static int sci_txfill(struct uart_port *port) 756 { 757 struct sci_port *s = to_sci_port(port); 758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 759 const struct plat_sci_reg *reg; 760 761 reg = sci_getreg(port, SCTFDR); 762 if (reg->size) 763 return serial_port_in(port, SCTFDR) & fifo_mask; 764 765 reg = sci_getreg(port, SCFDR); 766 if (reg->size) 767 return serial_port_in(port, SCFDR) >> 8; 768 769 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 770 } 771 772 static int sci_txroom(struct uart_port *port) 773 { 774 return port->fifosize - sci_txfill(port); 775 } 776 777 static int sci_rxfill(struct uart_port *port) 778 { 779 struct sci_port *s = to_sci_port(port); 780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 781 const struct plat_sci_reg *reg; 782 783 reg = sci_getreg(port, SCRFDR); 784 if (reg->size) 785 return serial_port_in(port, SCRFDR) & fifo_mask; 786 787 reg = sci_getreg(port, SCFDR); 788 if (reg->size) 789 return serial_port_in(port, SCFDR) & fifo_mask; 790 791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 792 } 793 794 /* ********************************************************************** * 795 * the interrupt related routines * 796 * ********************************************************************** */ 797 798 static void sci_transmit_chars(struct uart_port *port) 799 { 800 struct circ_buf *xmit = &port->state->xmit; 801 unsigned int stopped = uart_tx_stopped(port); 802 unsigned short status; 803 unsigned short ctrl; 804 int count; 805 806 status = serial_port_in(port, SCxSR); 807 if (!(status & SCxSR_TDxE(port))) { 808 ctrl = serial_port_in(port, SCSCR); 809 if (uart_circ_empty(xmit)) 810 ctrl &= ~SCSCR_TIE; 811 else 812 ctrl |= SCSCR_TIE; 813 serial_port_out(port, SCSCR, ctrl); 814 return; 815 } 816 817 count = sci_txroom(port); 818 819 do { 820 unsigned char c; 821 822 if (port->x_char) { 823 c = port->x_char; 824 port->x_char = 0; 825 } else if (!uart_circ_empty(xmit) && !stopped) { 826 c = xmit->buf[xmit->tail]; 827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 828 } else { 829 break; 830 } 831 832 serial_port_out(port, SCxTDR, c); 833 834 port->icount.tx++; 835 } while (--count > 0); 836 837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 838 839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 840 uart_write_wakeup(port); 841 if (uart_circ_empty(xmit)) { 842 sci_stop_tx(port); 843 } else { 844 ctrl = serial_port_in(port, SCSCR); 845 846 if (port->type != PORT_SCI) { 847 serial_port_in(port, SCxSR); /* Dummy read */ 848 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 849 } 850 851 ctrl |= SCSCR_TIE; 852 serial_port_out(port, SCSCR, ctrl); 853 } 854 } 855 856 /* On SH3, SCIF may read end-of-break as a space->mark char */ 857 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 858 859 static void sci_receive_chars(struct uart_port *port) 860 { 861 struct tty_port *tport = &port->state->port; 862 int i, count, copied = 0; 863 unsigned short status; 864 unsigned char flag; 865 866 status = serial_port_in(port, SCxSR); 867 if (!(status & SCxSR_RDxF(port))) 868 return; 869 870 while (1) { 871 /* Don't copy more bytes than there is room for in the buffer */ 872 count = tty_buffer_request_room(tport, sci_rxfill(port)); 873 874 /* If for any reason we can't copy more data, we're done! */ 875 if (count == 0) 876 break; 877 878 if (port->type == PORT_SCI) { 879 char c = serial_port_in(port, SCxRDR); 880 if (uart_handle_sysrq_char(port, c)) 881 count = 0; 882 else 883 tty_insert_flip_char(tport, c, TTY_NORMAL); 884 } else { 885 for (i = 0; i < count; i++) { 886 char c = serial_port_in(port, SCxRDR); 887 888 status = serial_port_in(port, SCxSR); 889 if (uart_handle_sysrq_char(port, c)) { 890 count--; i--; 891 continue; 892 } 893 894 /* Store data and status */ 895 if (status & SCxSR_FER(port)) { 896 flag = TTY_FRAME; 897 port->icount.frame++; 898 dev_notice(port->dev, "frame error\n"); 899 } else if (status & SCxSR_PER(port)) { 900 flag = TTY_PARITY; 901 port->icount.parity++; 902 dev_notice(port->dev, "parity error\n"); 903 } else 904 flag = TTY_NORMAL; 905 906 tty_insert_flip_char(tport, c, flag); 907 } 908 } 909 910 serial_port_in(port, SCxSR); /* dummy read */ 911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 912 913 copied += count; 914 port->icount.rx += count; 915 } 916 917 if (copied) { 918 /* Tell the rest of the system the news. New characters! */ 919 tty_flip_buffer_push(tport); 920 } else { 921 /* TTY buffers full; read from RX reg to prevent lockup */ 922 serial_port_in(port, SCxRDR); 923 serial_port_in(port, SCxSR); /* dummy read */ 924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 925 } 926 } 927 928 static int sci_handle_errors(struct uart_port *port) 929 { 930 int copied = 0; 931 unsigned short status = serial_port_in(port, SCxSR); 932 struct tty_port *tport = &port->state->port; 933 struct sci_port *s = to_sci_port(port); 934 935 /* Handle overruns */ 936 if (status & s->params->overrun_mask) { 937 port->icount.overrun++; 938 939 /* overrun error */ 940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 941 copied++; 942 943 dev_notice(port->dev, "overrun error\n"); 944 } 945 946 if (status & SCxSR_FER(port)) { 947 /* frame error */ 948 port->icount.frame++; 949 950 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 951 copied++; 952 953 dev_notice(port->dev, "frame error\n"); 954 } 955 956 if (status & SCxSR_PER(port)) { 957 /* parity error */ 958 port->icount.parity++; 959 960 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 961 copied++; 962 963 dev_notice(port->dev, "parity error\n"); 964 } 965 966 if (copied) 967 tty_flip_buffer_push(tport); 968 969 return copied; 970 } 971 972 static int sci_handle_fifo_overrun(struct uart_port *port) 973 { 974 struct tty_port *tport = &port->state->port; 975 struct sci_port *s = to_sci_port(port); 976 const struct plat_sci_reg *reg; 977 int copied = 0; 978 u16 status; 979 980 reg = sci_getreg(port, s->params->overrun_reg); 981 if (!reg->size) 982 return 0; 983 984 status = serial_port_in(port, s->params->overrun_reg); 985 if (status & s->params->overrun_mask) { 986 status &= ~s->params->overrun_mask; 987 serial_port_out(port, s->params->overrun_reg, status); 988 989 port->icount.overrun++; 990 991 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 992 tty_flip_buffer_push(tport); 993 994 dev_dbg(port->dev, "overrun error\n"); 995 copied++; 996 } 997 998 return copied; 999 } 1000 1001 static int sci_handle_breaks(struct uart_port *port) 1002 { 1003 int copied = 0; 1004 unsigned short status = serial_port_in(port, SCxSR); 1005 struct tty_port *tport = &port->state->port; 1006 1007 if (uart_handle_break(port)) 1008 return 0; 1009 1010 if (status & SCxSR_BRK(port)) { 1011 port->icount.brk++; 1012 1013 /* Notify of BREAK */ 1014 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1015 copied++; 1016 1017 dev_dbg(port->dev, "BREAK detected\n"); 1018 } 1019 1020 if (copied) 1021 tty_flip_buffer_push(tport); 1022 1023 copied += sci_handle_fifo_overrun(port); 1024 1025 return copied; 1026 } 1027 1028 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1029 { 1030 unsigned int bits; 1031 1032 if (rx_trig < 1) 1033 rx_trig = 1; 1034 if (rx_trig >= port->fifosize) 1035 rx_trig = port->fifosize; 1036 1037 /* HSCIF can be set to an arbitrary level. */ 1038 if (sci_getreg(port, HSRTRGR)->size) { 1039 serial_port_out(port, HSRTRGR, rx_trig); 1040 return rx_trig; 1041 } 1042 1043 switch (port->type) { 1044 case PORT_SCIF: 1045 if (rx_trig < 4) { 1046 bits = 0; 1047 rx_trig = 1; 1048 } else if (rx_trig < 8) { 1049 bits = SCFCR_RTRG0; 1050 rx_trig = 4; 1051 } else if (rx_trig < 14) { 1052 bits = SCFCR_RTRG1; 1053 rx_trig = 8; 1054 } else { 1055 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1056 rx_trig = 14; 1057 } 1058 break; 1059 case PORT_SCIFA: 1060 case PORT_SCIFB: 1061 if (rx_trig < 16) { 1062 bits = 0; 1063 rx_trig = 1; 1064 } else if (rx_trig < 32) { 1065 bits = SCFCR_RTRG0; 1066 rx_trig = 16; 1067 } else if (rx_trig < 48) { 1068 bits = SCFCR_RTRG1; 1069 rx_trig = 32; 1070 } else { 1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1072 rx_trig = 48; 1073 } 1074 break; 1075 default: 1076 WARN(1, "unknown FIFO configuration"); 1077 return 1; 1078 } 1079 1080 serial_port_out(port, SCFCR, 1081 (serial_port_in(port, SCFCR) & 1082 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1083 1084 return rx_trig; 1085 } 1086 1087 static int scif_rtrg_enabled(struct uart_port *port) 1088 { 1089 if (sci_getreg(port, HSRTRGR)->size) 1090 return serial_port_in(port, HSRTRGR) != 0; 1091 else 1092 return (serial_port_in(port, SCFCR) & 1093 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1094 } 1095 1096 static void rx_fifo_timer_fn(struct timer_list *t) 1097 { 1098 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1099 struct uart_port *port = &s->port; 1100 1101 dev_dbg(port->dev, "Rx timed out\n"); 1102 scif_set_rtrg(port, 1); 1103 } 1104 1105 static ssize_t rx_trigger_show(struct device *dev, 1106 struct device_attribute *attr, 1107 char *buf) 1108 { 1109 struct uart_port *port = dev_get_drvdata(dev); 1110 struct sci_port *sci = to_sci_port(port); 1111 1112 return sprintf(buf, "%d\n", sci->rx_trigger); 1113 } 1114 1115 static ssize_t rx_trigger_store(struct device *dev, 1116 struct device_attribute *attr, 1117 const char *buf, 1118 size_t count) 1119 { 1120 struct uart_port *port = dev_get_drvdata(dev); 1121 struct sci_port *sci = to_sci_port(port); 1122 int ret; 1123 long r; 1124 1125 ret = kstrtol(buf, 0, &r); 1126 if (ret) 1127 return ret; 1128 1129 sci->rx_trigger = scif_set_rtrg(port, r); 1130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1131 scif_set_rtrg(port, 1); 1132 1133 return count; 1134 } 1135 1136 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1137 1138 static ssize_t rx_fifo_timeout_show(struct device *dev, 1139 struct device_attribute *attr, 1140 char *buf) 1141 { 1142 struct uart_port *port = dev_get_drvdata(dev); 1143 struct sci_port *sci = to_sci_port(port); 1144 int v; 1145 1146 if (port->type == PORT_HSCIF) 1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1148 else 1149 v = sci->rx_fifo_timeout; 1150 1151 return sprintf(buf, "%d\n", v); 1152 } 1153 1154 static ssize_t rx_fifo_timeout_store(struct device *dev, 1155 struct device_attribute *attr, 1156 const char *buf, 1157 size_t count) 1158 { 1159 struct uart_port *port = dev_get_drvdata(dev); 1160 struct sci_port *sci = to_sci_port(port); 1161 int ret; 1162 long r; 1163 1164 ret = kstrtol(buf, 0, &r); 1165 if (ret) 1166 return ret; 1167 1168 if (port->type == PORT_HSCIF) { 1169 if (r < 0 || r > 3) 1170 return -EINVAL; 1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1172 } else { 1173 sci->rx_fifo_timeout = r; 1174 scif_set_rtrg(port, 1); 1175 if (r > 0) 1176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1177 } 1178 1179 return count; 1180 } 1181 1182 static DEVICE_ATTR_RW(rx_fifo_timeout); 1183 1184 1185 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1186 static void sci_dma_tx_complete(void *arg) 1187 { 1188 struct sci_port *s = arg; 1189 struct uart_port *port = &s->port; 1190 struct circ_buf *xmit = &port->state->xmit; 1191 unsigned long flags; 1192 1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1194 1195 spin_lock_irqsave(&port->lock, flags); 1196 1197 xmit->tail += s->tx_dma_len; 1198 xmit->tail &= UART_XMIT_SIZE - 1; 1199 1200 port->icount.tx += s->tx_dma_len; 1201 1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1203 uart_write_wakeup(port); 1204 1205 if (!uart_circ_empty(xmit)) { 1206 s->cookie_tx = 0; 1207 schedule_work(&s->work_tx); 1208 } else { 1209 s->cookie_tx = -EINVAL; 1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1211 u16 ctrl = serial_port_in(port, SCSCR); 1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1213 } 1214 } 1215 1216 spin_unlock_irqrestore(&port->lock, flags); 1217 } 1218 1219 /* Locking: called with port lock held */ 1220 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1221 { 1222 struct uart_port *port = &s->port; 1223 struct tty_port *tport = &port->state->port; 1224 int copied; 1225 1226 copied = tty_insert_flip_string(tport, buf, count); 1227 if (copied < count) 1228 port->icount.buf_overrun++; 1229 1230 port->icount.rx += copied; 1231 1232 return copied; 1233 } 1234 1235 static int sci_dma_rx_find_active(struct sci_port *s) 1236 { 1237 unsigned int i; 1238 1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1240 if (s->active_rx == s->cookie_rx[i]) 1241 return i; 1242 1243 return -1; 1244 } 1245 1246 static void sci_rx_dma_release(struct sci_port *s) 1247 { 1248 struct dma_chan *chan = s->chan_rx_saved; 1249 1250 s->chan_rx_saved = s->chan_rx = NULL; 1251 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1252 dmaengine_terminate_sync(chan); 1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1254 sg_dma_address(&s->sg_rx[0])); 1255 dma_release_channel(chan); 1256 } 1257 1258 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1259 { 1260 long sec = usec / 1000000; 1261 long nsec = (usec % 1000000) * 1000; 1262 ktime_t t = ktime_set(sec, nsec); 1263 1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1265 } 1266 1267 static void sci_dma_rx_complete(void *arg) 1268 { 1269 struct sci_port *s = arg; 1270 struct dma_chan *chan = s->chan_rx; 1271 struct uart_port *port = &s->port; 1272 struct dma_async_tx_descriptor *desc; 1273 unsigned long flags; 1274 int active, count = 0; 1275 1276 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1277 s->active_rx); 1278 1279 spin_lock_irqsave(&port->lock, flags); 1280 1281 active = sci_dma_rx_find_active(s); 1282 if (active >= 0) 1283 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1284 1285 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1286 1287 if (count) 1288 tty_flip_buffer_push(&port->state->port); 1289 1290 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1291 DMA_DEV_TO_MEM, 1292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1293 if (!desc) 1294 goto fail; 1295 1296 desc->callback = sci_dma_rx_complete; 1297 desc->callback_param = s; 1298 s->cookie_rx[active] = dmaengine_submit(desc); 1299 if (dma_submit_error(s->cookie_rx[active])) 1300 goto fail; 1301 1302 s->active_rx = s->cookie_rx[!active]; 1303 1304 dma_async_issue_pending(chan); 1305 1306 spin_unlock_irqrestore(&port->lock, flags); 1307 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1308 __func__, s->cookie_rx[active], active, s->active_rx); 1309 return; 1310 1311 fail: 1312 spin_unlock_irqrestore(&port->lock, flags); 1313 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1314 /* Switch to PIO */ 1315 spin_lock_irqsave(&port->lock, flags); 1316 s->chan_rx = NULL; 1317 sci_start_rx(port); 1318 spin_unlock_irqrestore(&port->lock, flags); 1319 } 1320 1321 static void sci_tx_dma_release(struct sci_port *s) 1322 { 1323 struct dma_chan *chan = s->chan_tx_saved; 1324 1325 cancel_work_sync(&s->work_tx); 1326 s->chan_tx_saved = s->chan_tx = NULL; 1327 s->cookie_tx = -EINVAL; 1328 dmaengine_terminate_sync(chan); 1329 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1330 DMA_TO_DEVICE); 1331 dma_release_channel(chan); 1332 } 1333 1334 static int sci_submit_rx(struct sci_port *s, bool port_lock_held) 1335 { 1336 struct dma_chan *chan = s->chan_rx; 1337 struct uart_port *port = &s->port; 1338 unsigned long flags; 1339 int i; 1340 1341 for (i = 0; i < 2; i++) { 1342 struct scatterlist *sg = &s->sg_rx[i]; 1343 struct dma_async_tx_descriptor *desc; 1344 1345 desc = dmaengine_prep_slave_sg(chan, 1346 sg, 1, DMA_DEV_TO_MEM, 1347 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1348 if (!desc) 1349 goto fail; 1350 1351 desc->callback = sci_dma_rx_complete; 1352 desc->callback_param = s; 1353 s->cookie_rx[i] = dmaengine_submit(desc); 1354 if (dma_submit_error(s->cookie_rx[i])) 1355 goto fail; 1356 1357 } 1358 1359 s->active_rx = s->cookie_rx[0]; 1360 1361 dma_async_issue_pending(chan); 1362 return 0; 1363 1364 fail: 1365 /* Switch to PIO */ 1366 if (!port_lock_held) 1367 spin_lock_irqsave(&port->lock, flags); 1368 if (i) 1369 dmaengine_terminate_async(chan); 1370 for (i = 0; i < 2; i++) 1371 s->cookie_rx[i] = -EINVAL; 1372 s->active_rx = 0; 1373 s->chan_rx = NULL; 1374 sci_start_rx(port); 1375 if (!port_lock_held) 1376 spin_unlock_irqrestore(&port->lock, flags); 1377 return -EAGAIN; 1378 } 1379 1380 static void work_fn_tx(struct work_struct *work) 1381 { 1382 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1383 struct dma_async_tx_descriptor *desc; 1384 struct dma_chan *chan = s->chan_tx; 1385 struct uart_port *port = &s->port; 1386 struct circ_buf *xmit = &port->state->xmit; 1387 unsigned long flags; 1388 dma_addr_t buf; 1389 1390 /* 1391 * DMA is idle now. 1392 * Port xmit buffer is already mapped, and it is one page... Just adjust 1393 * offsets and lengths. Since it is a circular buffer, we have to 1394 * transmit till the end, and then the rest. Take the port lock to get a 1395 * consistent xmit buffer state. 1396 */ 1397 spin_lock_irq(&port->lock); 1398 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1399 s->tx_dma_len = min_t(unsigned int, 1400 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1401 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1402 spin_unlock_irq(&port->lock); 1403 1404 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1405 DMA_MEM_TO_DEV, 1406 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1407 if (!desc) { 1408 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1409 goto switch_to_pio; 1410 } 1411 1412 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1413 DMA_TO_DEVICE); 1414 1415 spin_lock_irq(&port->lock); 1416 desc->callback = sci_dma_tx_complete; 1417 desc->callback_param = s; 1418 spin_unlock_irq(&port->lock); 1419 s->cookie_tx = dmaengine_submit(desc); 1420 if (dma_submit_error(s->cookie_tx)) { 1421 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1422 goto switch_to_pio; 1423 } 1424 1425 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1426 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1427 1428 dma_async_issue_pending(chan); 1429 return; 1430 1431 switch_to_pio: 1432 spin_lock_irqsave(&port->lock, flags); 1433 s->chan_tx = NULL; 1434 sci_start_tx(port); 1435 spin_unlock_irqrestore(&port->lock, flags); 1436 return; 1437 } 1438 1439 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t) 1440 { 1441 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1442 struct dma_chan *chan = s->chan_rx; 1443 struct uart_port *port = &s->port; 1444 struct dma_tx_state state; 1445 enum dma_status status; 1446 unsigned long flags; 1447 unsigned int read; 1448 int active, count; 1449 u16 scr; 1450 1451 dev_dbg(port->dev, "DMA Rx timed out\n"); 1452 1453 spin_lock_irqsave(&port->lock, flags); 1454 1455 active = sci_dma_rx_find_active(s); 1456 if (active < 0) { 1457 spin_unlock_irqrestore(&port->lock, flags); 1458 return HRTIMER_NORESTART; 1459 } 1460 1461 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1462 if (status == DMA_COMPLETE) { 1463 spin_unlock_irqrestore(&port->lock, flags); 1464 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1465 s->active_rx, active); 1466 1467 /* Let packet complete handler take care of the packet */ 1468 return HRTIMER_NORESTART; 1469 } 1470 1471 dmaengine_pause(chan); 1472 1473 /* 1474 * sometimes DMA transfer doesn't stop even if it is stopped and 1475 * data keeps on coming until transaction is complete so check 1476 * for DMA_COMPLETE again 1477 * Let packet complete handler take care of the packet 1478 */ 1479 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1480 if (status == DMA_COMPLETE) { 1481 spin_unlock_irqrestore(&port->lock, flags); 1482 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1483 return HRTIMER_NORESTART; 1484 } 1485 1486 /* Handle incomplete DMA receive */ 1487 dmaengine_terminate_async(s->chan_rx); 1488 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1489 1490 if (read) { 1491 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1492 if (count) 1493 tty_flip_buffer_push(&port->state->port); 1494 } 1495 1496 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1497 sci_submit_rx(s, true); 1498 1499 /* Direct new serial port interrupts back to CPU */ 1500 scr = serial_port_in(port, SCSCR); 1501 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1502 scr &= ~SCSCR_RDRQE; 1503 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1504 } 1505 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1506 1507 spin_unlock_irqrestore(&port->lock, flags); 1508 1509 return HRTIMER_NORESTART; 1510 } 1511 1512 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1513 enum dma_transfer_direction dir) 1514 { 1515 struct dma_chan *chan; 1516 struct dma_slave_config cfg; 1517 int ret; 1518 1519 chan = dma_request_slave_channel(port->dev, 1520 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1521 if (!chan) { 1522 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1523 return NULL; 1524 } 1525 1526 memset(&cfg, 0, sizeof(cfg)); 1527 cfg.direction = dir; 1528 if (dir == DMA_MEM_TO_DEV) { 1529 cfg.dst_addr = port->mapbase + 1530 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1531 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1532 } else { 1533 cfg.src_addr = port->mapbase + 1534 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1535 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1536 } 1537 1538 ret = dmaengine_slave_config(chan, &cfg); 1539 if (ret) { 1540 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1541 dma_release_channel(chan); 1542 return NULL; 1543 } 1544 1545 return chan; 1546 } 1547 1548 static void sci_request_dma(struct uart_port *port) 1549 { 1550 struct sci_port *s = to_sci_port(port); 1551 struct dma_chan *chan; 1552 1553 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1554 1555 if (!port->dev->of_node) 1556 return; 1557 1558 s->cookie_tx = -EINVAL; 1559 1560 /* 1561 * Don't request a dma channel if no channel was specified 1562 * in the device tree. 1563 */ 1564 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1565 return; 1566 1567 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1568 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1569 if (chan) { 1570 /* UART circular tx buffer is an aligned page. */ 1571 s->tx_dma_addr = dma_map_single(chan->device->dev, 1572 port->state->xmit.buf, 1573 UART_XMIT_SIZE, 1574 DMA_TO_DEVICE); 1575 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1576 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1577 dma_release_channel(chan); 1578 } else { 1579 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1580 __func__, UART_XMIT_SIZE, 1581 port->state->xmit.buf, &s->tx_dma_addr); 1582 1583 INIT_WORK(&s->work_tx, work_fn_tx); 1584 s->chan_tx_saved = s->chan_tx = chan; 1585 } 1586 } 1587 1588 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1589 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1590 if (chan) { 1591 unsigned int i; 1592 dma_addr_t dma; 1593 void *buf; 1594 1595 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1596 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1597 &dma, GFP_KERNEL); 1598 if (!buf) { 1599 dev_warn(port->dev, 1600 "Failed to allocate Rx dma buffer, using PIO\n"); 1601 dma_release_channel(chan); 1602 return; 1603 } 1604 1605 for (i = 0; i < 2; i++) { 1606 struct scatterlist *sg = &s->sg_rx[i]; 1607 1608 sg_init_table(sg, 1); 1609 s->rx_buf[i] = buf; 1610 sg_dma_address(sg) = dma; 1611 sg_dma_len(sg) = s->buf_len_rx; 1612 1613 buf += s->buf_len_rx; 1614 dma += s->buf_len_rx; 1615 } 1616 1617 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1618 s->rx_timer.function = rx_timer_fn; 1619 1620 s->chan_rx_saved = s->chan_rx = chan; 1621 1622 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1623 sci_submit_rx(s, false); 1624 } 1625 } 1626 1627 static void sci_free_dma(struct uart_port *port) 1628 { 1629 struct sci_port *s = to_sci_port(port); 1630 1631 if (s->chan_tx_saved) 1632 sci_tx_dma_release(s); 1633 if (s->chan_rx_saved) 1634 sci_rx_dma_release(s); 1635 } 1636 1637 static void sci_flush_buffer(struct uart_port *port) 1638 { 1639 /* 1640 * In uart_flush_buffer(), the xmit circular buffer has just been 1641 * cleared, so we have to reset tx_dma_len accordingly. 1642 */ 1643 to_sci_port(port)->tx_dma_len = 0; 1644 } 1645 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1646 static inline void sci_request_dma(struct uart_port *port) 1647 { 1648 } 1649 1650 static inline void sci_free_dma(struct uart_port *port) 1651 { 1652 } 1653 1654 #define sci_flush_buffer NULL 1655 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1656 1657 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1658 { 1659 struct uart_port *port = ptr; 1660 struct sci_port *s = to_sci_port(port); 1661 1662 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1663 if (s->chan_rx) { 1664 u16 scr = serial_port_in(port, SCSCR); 1665 u16 ssr = serial_port_in(port, SCxSR); 1666 1667 /* Disable future Rx interrupts */ 1668 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1669 disable_irq_nosync(irq); 1670 scr |= SCSCR_RDRQE; 1671 } else { 1672 if (sci_submit_rx(s, false) < 0) 1673 goto handle_pio; 1674 1675 scr &= ~SCSCR_RIE; 1676 } 1677 serial_port_out(port, SCSCR, scr); 1678 /* Clear current interrupt */ 1679 serial_port_out(port, SCxSR, 1680 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1681 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1682 jiffies, s->rx_timeout); 1683 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1684 1685 return IRQ_HANDLED; 1686 } 1687 1688 handle_pio: 1689 #endif 1690 1691 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1692 if (!scif_rtrg_enabled(port)) 1693 scif_set_rtrg(port, s->rx_trigger); 1694 1695 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1696 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1697 } 1698 1699 /* I think sci_receive_chars has to be called irrespective 1700 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1701 * to be disabled? 1702 */ 1703 sci_receive_chars(port); 1704 1705 return IRQ_HANDLED; 1706 } 1707 1708 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1709 { 1710 struct uart_port *port = ptr; 1711 unsigned long flags; 1712 1713 spin_lock_irqsave(&port->lock, flags); 1714 sci_transmit_chars(port); 1715 spin_unlock_irqrestore(&port->lock, flags); 1716 1717 return IRQ_HANDLED; 1718 } 1719 1720 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1721 { 1722 struct uart_port *port = ptr; 1723 1724 /* Handle BREAKs */ 1725 sci_handle_breaks(port); 1726 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1727 1728 return IRQ_HANDLED; 1729 } 1730 1731 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1732 { 1733 struct uart_port *port = ptr; 1734 struct sci_port *s = to_sci_port(port); 1735 1736 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1737 /* Break and Error interrupts are muxed */ 1738 unsigned short ssr_status = serial_port_in(port, SCxSR); 1739 1740 /* Break Interrupt */ 1741 if (ssr_status & SCxSR_BRK(port)) 1742 sci_br_interrupt(irq, ptr); 1743 1744 /* Break only? */ 1745 if (!(ssr_status & SCxSR_ERRORS(port))) 1746 return IRQ_HANDLED; 1747 } 1748 1749 /* Handle errors */ 1750 if (port->type == PORT_SCI) { 1751 if (sci_handle_errors(port)) { 1752 /* discard character in rx buffer */ 1753 serial_port_in(port, SCxSR); 1754 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1755 } 1756 } else { 1757 sci_handle_fifo_overrun(port); 1758 if (!s->chan_rx) 1759 sci_receive_chars(port); 1760 } 1761 1762 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1763 1764 /* Kick the transmission */ 1765 if (!s->chan_tx) 1766 sci_tx_interrupt(irq, ptr); 1767 1768 return IRQ_HANDLED; 1769 } 1770 1771 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1772 { 1773 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1774 struct uart_port *port = ptr; 1775 struct sci_port *s = to_sci_port(port); 1776 irqreturn_t ret = IRQ_NONE; 1777 1778 ssr_status = serial_port_in(port, SCxSR); 1779 scr_status = serial_port_in(port, SCSCR); 1780 if (s->params->overrun_reg == SCxSR) 1781 orer_status = ssr_status; 1782 else if (sci_getreg(port, s->params->overrun_reg)->size) 1783 orer_status = serial_port_in(port, s->params->overrun_reg); 1784 1785 err_enabled = scr_status & port_rx_irq_mask(port); 1786 1787 /* Tx Interrupt */ 1788 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1789 !s->chan_tx) 1790 ret = sci_tx_interrupt(irq, ptr); 1791 1792 /* 1793 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1794 * DR flags 1795 */ 1796 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1797 (scr_status & SCSCR_RIE)) 1798 ret = sci_rx_interrupt(irq, ptr); 1799 1800 /* Error Interrupt */ 1801 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1802 ret = sci_er_interrupt(irq, ptr); 1803 1804 /* Break Interrupt */ 1805 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1806 ret = sci_br_interrupt(irq, ptr); 1807 1808 /* Overrun Interrupt */ 1809 if (orer_status & s->params->overrun_mask) { 1810 sci_handle_fifo_overrun(port); 1811 ret = IRQ_HANDLED; 1812 } 1813 1814 return ret; 1815 } 1816 1817 static const struct sci_irq_desc { 1818 const char *desc; 1819 irq_handler_t handler; 1820 } sci_irq_desc[] = { 1821 /* 1822 * Split out handlers, the default case. 1823 */ 1824 [SCIx_ERI_IRQ] = { 1825 .desc = "rx err", 1826 .handler = sci_er_interrupt, 1827 }, 1828 1829 [SCIx_RXI_IRQ] = { 1830 .desc = "rx full", 1831 .handler = sci_rx_interrupt, 1832 }, 1833 1834 [SCIx_TXI_IRQ] = { 1835 .desc = "tx empty", 1836 .handler = sci_tx_interrupt, 1837 }, 1838 1839 [SCIx_BRI_IRQ] = { 1840 .desc = "break", 1841 .handler = sci_br_interrupt, 1842 }, 1843 1844 [SCIx_DRI_IRQ] = { 1845 .desc = "rx ready", 1846 .handler = sci_rx_interrupt, 1847 }, 1848 1849 [SCIx_TEI_IRQ] = { 1850 .desc = "tx end", 1851 .handler = sci_tx_interrupt, 1852 }, 1853 1854 /* 1855 * Special muxed handler. 1856 */ 1857 [SCIx_MUX_IRQ] = { 1858 .desc = "mux", 1859 .handler = sci_mpxed_interrupt, 1860 }, 1861 }; 1862 1863 static int sci_request_irq(struct sci_port *port) 1864 { 1865 struct uart_port *up = &port->port; 1866 int i, j, w, ret = 0; 1867 1868 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1869 const struct sci_irq_desc *desc; 1870 int irq; 1871 1872 /* Check if already registered (muxed) */ 1873 for (w = 0; w < i; w++) 1874 if (port->irqs[w] == port->irqs[i]) 1875 w = i + 1; 1876 if (w > i) 1877 continue; 1878 1879 if (SCIx_IRQ_IS_MUXED(port)) { 1880 i = SCIx_MUX_IRQ; 1881 irq = up->irq; 1882 } else { 1883 irq = port->irqs[i]; 1884 1885 /* 1886 * Certain port types won't support all of the 1887 * available interrupt sources. 1888 */ 1889 if (unlikely(irq < 0)) 1890 continue; 1891 } 1892 1893 desc = sci_irq_desc + i; 1894 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1895 dev_name(up->dev), desc->desc); 1896 if (!port->irqstr[j]) { 1897 ret = -ENOMEM; 1898 goto out_nomem; 1899 } 1900 1901 ret = request_irq(irq, desc->handler, up->irqflags, 1902 port->irqstr[j], port); 1903 if (unlikely(ret)) { 1904 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1905 goto out_noirq; 1906 } 1907 } 1908 1909 return 0; 1910 1911 out_noirq: 1912 while (--i >= 0) 1913 free_irq(port->irqs[i], port); 1914 1915 out_nomem: 1916 while (--j >= 0) 1917 kfree(port->irqstr[j]); 1918 1919 return ret; 1920 } 1921 1922 static void sci_free_irq(struct sci_port *port) 1923 { 1924 int i; 1925 1926 /* 1927 * Intentionally in reverse order so we iterate over the muxed 1928 * IRQ first. 1929 */ 1930 for (i = 0; i < SCIx_NR_IRQS; i++) { 1931 int irq = port->irqs[i]; 1932 1933 /* 1934 * Certain port types won't support all of the available 1935 * interrupt sources. 1936 */ 1937 if (unlikely(irq < 0)) 1938 continue; 1939 1940 free_irq(port->irqs[i], port); 1941 kfree(port->irqstr[i]); 1942 1943 if (SCIx_IRQ_IS_MUXED(port)) { 1944 /* If there's only one IRQ, we're done. */ 1945 return; 1946 } 1947 } 1948 } 1949 1950 static unsigned int sci_tx_empty(struct uart_port *port) 1951 { 1952 unsigned short status = serial_port_in(port, SCxSR); 1953 unsigned short in_tx_fifo = sci_txfill(port); 1954 1955 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1956 } 1957 1958 static void sci_set_rts(struct uart_port *port, bool state) 1959 { 1960 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1961 u16 data = serial_port_in(port, SCPDR); 1962 1963 /* Active low */ 1964 if (state) 1965 data &= ~SCPDR_RTSD; 1966 else 1967 data |= SCPDR_RTSD; 1968 serial_port_out(port, SCPDR, data); 1969 1970 /* RTS# is output */ 1971 serial_port_out(port, SCPCR, 1972 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1973 } else if (sci_getreg(port, SCSPTR)->size) { 1974 u16 ctrl = serial_port_in(port, SCSPTR); 1975 1976 /* Active low */ 1977 if (state) 1978 ctrl &= ~SCSPTR_RTSDT; 1979 else 1980 ctrl |= SCSPTR_RTSDT; 1981 serial_port_out(port, SCSPTR, ctrl); 1982 } 1983 } 1984 1985 static bool sci_get_cts(struct uart_port *port) 1986 { 1987 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1988 /* Active low */ 1989 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 1990 } else if (sci_getreg(port, SCSPTR)->size) { 1991 /* Active low */ 1992 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 1993 } 1994 1995 return true; 1996 } 1997 1998 /* 1999 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2000 * CTS/RTS is supported in hardware by at least one port and controlled 2001 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2002 * handled via the ->init_pins() op, which is a bit of a one-way street, 2003 * lacking any ability to defer pin control -- this will later be 2004 * converted over to the GPIO framework). 2005 * 2006 * Other modes (such as loopback) are supported generically on certain 2007 * port types, but not others. For these it's sufficient to test for the 2008 * existence of the support register and simply ignore the port type. 2009 */ 2010 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2011 { 2012 struct sci_port *s = to_sci_port(port); 2013 2014 if (mctrl & TIOCM_LOOP) { 2015 const struct plat_sci_reg *reg; 2016 2017 /* 2018 * Standard loopback mode for SCFCR ports. 2019 */ 2020 reg = sci_getreg(port, SCFCR); 2021 if (reg->size) 2022 serial_port_out(port, SCFCR, 2023 serial_port_in(port, SCFCR) | 2024 SCFCR_LOOP); 2025 } 2026 2027 mctrl_gpio_set(s->gpios, mctrl); 2028 2029 if (!s->has_rtscts) 2030 return; 2031 2032 if (!(mctrl & TIOCM_RTS)) { 2033 /* Disable Auto RTS */ 2034 serial_port_out(port, SCFCR, 2035 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2036 2037 /* Clear RTS */ 2038 sci_set_rts(port, 0); 2039 } else if (s->autorts) { 2040 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2041 /* Enable RTS# pin function */ 2042 serial_port_out(port, SCPCR, 2043 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2044 } 2045 2046 /* Enable Auto RTS */ 2047 serial_port_out(port, SCFCR, 2048 serial_port_in(port, SCFCR) | SCFCR_MCE); 2049 } else { 2050 /* Set RTS */ 2051 sci_set_rts(port, 1); 2052 } 2053 } 2054 2055 static unsigned int sci_get_mctrl(struct uart_port *port) 2056 { 2057 struct sci_port *s = to_sci_port(port); 2058 struct mctrl_gpios *gpios = s->gpios; 2059 unsigned int mctrl = 0; 2060 2061 mctrl_gpio_get(gpios, &mctrl); 2062 2063 /* 2064 * CTS/RTS is handled in hardware when supported, while nothing 2065 * else is wired up. 2066 */ 2067 if (s->autorts) { 2068 if (sci_get_cts(port)) 2069 mctrl |= TIOCM_CTS; 2070 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 2071 mctrl |= TIOCM_CTS; 2072 } 2073 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 2074 mctrl |= TIOCM_DSR; 2075 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 2076 mctrl |= TIOCM_CAR; 2077 2078 return mctrl; 2079 } 2080 2081 static void sci_enable_ms(struct uart_port *port) 2082 { 2083 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2084 } 2085 2086 static void sci_break_ctl(struct uart_port *port, int break_state) 2087 { 2088 unsigned short scscr, scsptr; 2089 unsigned long flags; 2090 2091 /* check wheter the port has SCSPTR */ 2092 if (!sci_getreg(port, SCSPTR)->size) { 2093 /* 2094 * Not supported by hardware. Most parts couple break and rx 2095 * interrupts together, with break detection always enabled. 2096 */ 2097 return; 2098 } 2099 2100 spin_lock_irqsave(&port->lock, flags); 2101 scsptr = serial_port_in(port, SCSPTR); 2102 scscr = serial_port_in(port, SCSCR); 2103 2104 if (break_state == -1) { 2105 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2106 scscr &= ~SCSCR_TE; 2107 } else { 2108 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2109 scscr |= SCSCR_TE; 2110 } 2111 2112 serial_port_out(port, SCSPTR, scsptr); 2113 serial_port_out(port, SCSCR, scscr); 2114 spin_unlock_irqrestore(&port->lock, flags); 2115 } 2116 2117 static int sci_startup(struct uart_port *port) 2118 { 2119 struct sci_port *s = to_sci_port(port); 2120 int ret; 2121 2122 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2123 2124 sci_request_dma(port); 2125 2126 ret = sci_request_irq(s); 2127 if (unlikely(ret < 0)) { 2128 sci_free_dma(port); 2129 return ret; 2130 } 2131 2132 return 0; 2133 } 2134 2135 static void sci_shutdown(struct uart_port *port) 2136 { 2137 struct sci_port *s = to_sci_port(port); 2138 unsigned long flags; 2139 u16 scr; 2140 2141 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2142 2143 s->autorts = false; 2144 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2145 2146 spin_lock_irqsave(&port->lock, flags); 2147 sci_stop_rx(port); 2148 sci_stop_tx(port); 2149 /* 2150 * Stop RX and TX, disable related interrupts, keep clock source 2151 * and HSCIF TOT bits 2152 */ 2153 scr = serial_port_in(port, SCSCR); 2154 serial_port_out(port, SCSCR, scr & 2155 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2156 spin_unlock_irqrestore(&port->lock, flags); 2157 2158 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2159 if (s->chan_rx_saved) { 2160 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2161 port->line); 2162 hrtimer_cancel(&s->rx_timer); 2163 } 2164 #endif 2165 2166 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2167 del_timer_sync(&s->rx_fifo_timer); 2168 sci_free_irq(s); 2169 sci_free_dma(port); 2170 } 2171 2172 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2173 unsigned int *srr) 2174 { 2175 unsigned long freq = s->clk_rates[SCI_SCK]; 2176 int err, min_err = INT_MAX; 2177 unsigned int sr; 2178 2179 if (s->port.type != PORT_HSCIF) 2180 freq *= 2; 2181 2182 for_each_sr(sr, s) { 2183 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2184 if (abs(err) >= abs(min_err)) 2185 continue; 2186 2187 min_err = err; 2188 *srr = sr - 1; 2189 2190 if (!err) 2191 break; 2192 } 2193 2194 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2195 *srr + 1); 2196 return min_err; 2197 } 2198 2199 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2200 unsigned long freq, unsigned int *dlr, 2201 unsigned int *srr) 2202 { 2203 int err, min_err = INT_MAX; 2204 unsigned int sr, dl; 2205 2206 if (s->port.type != PORT_HSCIF) 2207 freq *= 2; 2208 2209 for_each_sr(sr, s) { 2210 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2211 dl = clamp(dl, 1U, 65535U); 2212 2213 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2214 if (abs(err) >= abs(min_err)) 2215 continue; 2216 2217 min_err = err; 2218 *dlr = dl; 2219 *srr = sr - 1; 2220 2221 if (!err) 2222 break; 2223 } 2224 2225 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2226 min_err, *dlr, *srr + 1); 2227 return min_err; 2228 } 2229 2230 /* calculate sample rate, BRR, and clock select */ 2231 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2232 unsigned int *brr, unsigned int *srr, 2233 unsigned int *cks) 2234 { 2235 unsigned long freq = s->clk_rates[SCI_FCK]; 2236 unsigned int sr, br, prediv, scrate, c; 2237 int err, min_err = INT_MAX; 2238 2239 if (s->port.type != PORT_HSCIF) 2240 freq *= 2; 2241 2242 /* 2243 * Find the combination of sample rate and clock select with the 2244 * smallest deviation from the desired baud rate. 2245 * Prefer high sample rates to maximise the receive margin. 2246 * 2247 * M: Receive margin (%) 2248 * N: Ratio of bit rate to clock (N = sampling rate) 2249 * D: Clock duty (D = 0 to 1.0) 2250 * L: Frame length (L = 9 to 12) 2251 * F: Absolute value of clock frequency deviation 2252 * 2253 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2254 * (|D - 0.5| / N * (1 + F))| 2255 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2256 */ 2257 for_each_sr(sr, s) { 2258 for (c = 0; c <= 3; c++) { 2259 /* integerized formulas from HSCIF documentation */ 2260 prediv = sr * (1 << (2 * c + 1)); 2261 2262 /* 2263 * We need to calculate: 2264 * 2265 * br = freq / (prediv * bps) clamped to [1..256] 2266 * err = freq / (br * prediv) - bps 2267 * 2268 * Watch out for overflow when calculating the desired 2269 * sampling clock rate! 2270 */ 2271 if (bps > UINT_MAX / prediv) 2272 break; 2273 2274 scrate = prediv * bps; 2275 br = DIV_ROUND_CLOSEST(freq, scrate); 2276 br = clamp(br, 1U, 256U); 2277 2278 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2279 if (abs(err) >= abs(min_err)) 2280 continue; 2281 2282 min_err = err; 2283 *brr = br - 1; 2284 *srr = sr - 1; 2285 *cks = c; 2286 2287 if (!err) 2288 goto found; 2289 } 2290 } 2291 2292 found: 2293 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2294 min_err, *brr, *srr + 1, *cks); 2295 return min_err; 2296 } 2297 2298 static void sci_reset(struct uart_port *port) 2299 { 2300 const struct plat_sci_reg *reg; 2301 unsigned int status; 2302 struct sci_port *s = to_sci_port(port); 2303 2304 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2305 2306 reg = sci_getreg(port, SCFCR); 2307 if (reg->size) 2308 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2309 2310 sci_clear_SCxSR(port, 2311 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2312 SCxSR_BREAK_CLEAR(port)); 2313 if (sci_getreg(port, SCLSR)->size) { 2314 status = serial_port_in(port, SCLSR); 2315 status &= ~(SCLSR_TO | SCLSR_ORER); 2316 serial_port_out(port, SCLSR, status); 2317 } 2318 2319 if (s->rx_trigger > 1) { 2320 if (s->rx_fifo_timeout) { 2321 scif_set_rtrg(port, 1); 2322 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2323 } else { 2324 if (port->type == PORT_SCIFA || 2325 port->type == PORT_SCIFB) 2326 scif_set_rtrg(port, 1); 2327 else 2328 scif_set_rtrg(port, s->rx_trigger); 2329 } 2330 } 2331 } 2332 2333 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2334 struct ktermios *old) 2335 { 2336 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2337 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2338 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2339 struct sci_port *s = to_sci_port(port); 2340 const struct plat_sci_reg *reg; 2341 int min_err = INT_MAX, err; 2342 unsigned long max_freq = 0; 2343 int best_clk = -1; 2344 unsigned long flags; 2345 2346 if ((termios->c_cflag & CSIZE) == CS7) 2347 smr_val |= SCSMR_CHR; 2348 if (termios->c_cflag & PARENB) 2349 smr_val |= SCSMR_PE; 2350 if (termios->c_cflag & PARODD) 2351 smr_val |= SCSMR_PE | SCSMR_ODD; 2352 if (termios->c_cflag & CSTOPB) 2353 smr_val |= SCSMR_STOP; 2354 2355 /* 2356 * earlyprintk comes here early on with port->uartclk set to zero. 2357 * the clock framework is not up and running at this point so here 2358 * we assume that 115200 is the maximum baud rate. please note that 2359 * the baud rate is not programmed during earlyprintk - it is assumed 2360 * that the previous boot loader has enabled required clocks and 2361 * setup the baud rate generator hardware for us already. 2362 */ 2363 if (!port->uartclk) { 2364 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2365 goto done; 2366 } 2367 2368 for (i = 0; i < SCI_NUM_CLKS; i++) 2369 max_freq = max(max_freq, s->clk_rates[i]); 2370 2371 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2372 if (!baud) 2373 goto done; 2374 2375 /* 2376 * There can be multiple sources for the sampling clock. Find the one 2377 * that gives us the smallest deviation from the desired baud rate. 2378 */ 2379 2380 /* Optional Undivided External Clock */ 2381 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2382 port->type != PORT_SCIFB) { 2383 err = sci_sck_calc(s, baud, &srr1); 2384 if (abs(err) < abs(min_err)) { 2385 best_clk = SCI_SCK; 2386 scr_val = SCSCR_CKE1; 2387 sccks = SCCKS_CKS; 2388 min_err = err; 2389 srr = srr1; 2390 if (!err) 2391 goto done; 2392 } 2393 } 2394 2395 /* Optional BRG Frequency Divided External Clock */ 2396 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2397 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2398 &srr1); 2399 if (abs(err) < abs(min_err)) { 2400 best_clk = SCI_SCIF_CLK; 2401 scr_val = SCSCR_CKE1; 2402 sccks = 0; 2403 min_err = err; 2404 dl = dl1; 2405 srr = srr1; 2406 if (!err) 2407 goto done; 2408 } 2409 } 2410 2411 /* Optional BRG Frequency Divided Internal Clock */ 2412 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2413 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2414 &srr1); 2415 if (abs(err) < abs(min_err)) { 2416 best_clk = SCI_BRG_INT; 2417 scr_val = SCSCR_CKE1; 2418 sccks = SCCKS_XIN; 2419 min_err = err; 2420 dl = dl1; 2421 srr = srr1; 2422 if (!min_err) 2423 goto done; 2424 } 2425 } 2426 2427 /* Divided Functional Clock using standard Bit Rate Register */ 2428 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2429 if (abs(err) < abs(min_err)) { 2430 best_clk = SCI_FCK; 2431 scr_val = 0; 2432 min_err = err; 2433 brr = brr1; 2434 srr = srr1; 2435 cks = cks1; 2436 } 2437 2438 done: 2439 if (best_clk >= 0) 2440 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2441 s->clks[best_clk], baud, min_err); 2442 2443 sci_port_enable(s); 2444 2445 /* 2446 * Program the optional External Baud Rate Generator (BRG) first. 2447 * It controls the mux to select (H)SCK or frequency divided clock. 2448 */ 2449 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2450 serial_port_out(port, SCDL, dl); 2451 serial_port_out(port, SCCKS, sccks); 2452 } 2453 2454 spin_lock_irqsave(&port->lock, flags); 2455 2456 sci_reset(port); 2457 2458 uart_update_timeout(port, termios->c_cflag, baud); 2459 2460 /* byte size and parity */ 2461 switch (termios->c_cflag & CSIZE) { 2462 case CS5: 2463 bits = 7; 2464 break; 2465 case CS6: 2466 bits = 8; 2467 break; 2468 case CS7: 2469 bits = 9; 2470 break; 2471 default: 2472 bits = 10; 2473 break; 2474 } 2475 2476 if (termios->c_cflag & CSTOPB) 2477 bits++; 2478 if (termios->c_cflag & PARENB) 2479 bits++; 2480 2481 if (best_clk >= 0) { 2482 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2483 switch (srr + 1) { 2484 case 5: smr_val |= SCSMR_SRC_5; break; 2485 case 7: smr_val |= SCSMR_SRC_7; break; 2486 case 11: smr_val |= SCSMR_SRC_11; break; 2487 case 13: smr_val |= SCSMR_SRC_13; break; 2488 case 16: smr_val |= SCSMR_SRC_16; break; 2489 case 17: smr_val |= SCSMR_SRC_17; break; 2490 case 19: smr_val |= SCSMR_SRC_19; break; 2491 case 27: smr_val |= SCSMR_SRC_27; break; 2492 } 2493 smr_val |= cks; 2494 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2495 serial_port_out(port, SCSMR, smr_val); 2496 serial_port_out(port, SCBRR, brr); 2497 if (sci_getreg(port, HSSRR)->size) { 2498 unsigned int hssrr = srr | HSCIF_SRE; 2499 /* Calculate deviation from intended rate at the 2500 * center of the last stop bit in sampling clocks. 2501 */ 2502 int last_stop = bits * 2 - 1; 2503 int deviation = min_err * srr * last_stop / 2 / baud; 2504 2505 if (abs(deviation) >= 2) { 2506 /* At least two sampling clocks off at the 2507 * last stop bit; we can increase the error 2508 * margin by shifting the sampling point. 2509 */ 2510 int shift = min(-8, max(7, deviation / 2)); 2511 2512 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2513 HSCIF_SRHP_MASK; 2514 hssrr |= HSCIF_SRDE; 2515 } 2516 serial_port_out(port, HSSRR, hssrr); 2517 } 2518 2519 /* Wait one bit interval */ 2520 udelay((1000000 + (baud - 1)) / baud); 2521 } else { 2522 /* Don't touch the bit rate configuration */ 2523 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2524 smr_val |= serial_port_in(port, SCSMR) & 2525 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2526 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2527 serial_port_out(port, SCSMR, smr_val); 2528 } 2529 2530 sci_init_pins(port, termios->c_cflag); 2531 2532 port->status &= ~UPSTAT_AUTOCTS; 2533 s->autorts = false; 2534 reg = sci_getreg(port, SCFCR); 2535 if (reg->size) { 2536 unsigned short ctrl = serial_port_in(port, SCFCR); 2537 2538 if ((port->flags & UPF_HARD_FLOW) && 2539 (termios->c_cflag & CRTSCTS)) { 2540 /* There is no CTS interrupt to restart the hardware */ 2541 port->status |= UPSTAT_AUTOCTS; 2542 /* MCE is enabled when RTS is raised */ 2543 s->autorts = true; 2544 } 2545 2546 /* 2547 * As we've done a sci_reset() above, ensure we don't 2548 * interfere with the FIFOs while toggling MCE. As the 2549 * reset values could still be set, simply mask them out. 2550 */ 2551 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2552 2553 serial_port_out(port, SCFCR, ctrl); 2554 } 2555 if (port->flags & UPF_HARD_FLOW) { 2556 /* Refresh (Auto) RTS */ 2557 sci_set_mctrl(port, port->mctrl); 2558 } 2559 2560 scr_val |= SCSCR_RE | SCSCR_TE | 2561 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2562 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2563 if ((srr + 1 == 5) && 2564 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2565 /* 2566 * In asynchronous mode, when the sampling rate is 1/5, first 2567 * received data may become invalid on some SCIFA and SCIFB. 2568 * To avoid this problem wait more than 1 serial data time (1 2569 * bit time x serial data number) after setting SCSCR.RE = 1. 2570 */ 2571 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2572 } 2573 2574 /* 2575 * Calculate delay for 2 DMA buffers (4 FIFO). 2576 * See serial_core.c::uart_update_timeout(). 2577 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2578 * function calculates 1 jiffie for the data plus 5 jiffies for the 2579 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2580 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2581 * value obtained by this formula is too small. Therefore, if the value 2582 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2583 */ 2584 s->rx_frame = (10000 * bits) / (baud / 100); 2585 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2586 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2587 if (s->rx_timeout < 20) 2588 s->rx_timeout = 20; 2589 #endif 2590 2591 if ((termios->c_cflag & CREAD) != 0) 2592 sci_start_rx(port); 2593 2594 spin_unlock_irqrestore(&port->lock, flags); 2595 2596 sci_port_disable(s); 2597 2598 if (UART_ENABLE_MS(port, termios->c_cflag)) 2599 sci_enable_ms(port); 2600 } 2601 2602 static void sci_pm(struct uart_port *port, unsigned int state, 2603 unsigned int oldstate) 2604 { 2605 struct sci_port *sci_port = to_sci_port(port); 2606 2607 switch (state) { 2608 case UART_PM_STATE_OFF: 2609 sci_port_disable(sci_port); 2610 break; 2611 default: 2612 sci_port_enable(sci_port); 2613 break; 2614 } 2615 } 2616 2617 static const char *sci_type(struct uart_port *port) 2618 { 2619 switch (port->type) { 2620 case PORT_IRDA: 2621 return "irda"; 2622 case PORT_SCI: 2623 return "sci"; 2624 case PORT_SCIF: 2625 return "scif"; 2626 case PORT_SCIFA: 2627 return "scifa"; 2628 case PORT_SCIFB: 2629 return "scifb"; 2630 case PORT_HSCIF: 2631 return "hscif"; 2632 } 2633 2634 return NULL; 2635 } 2636 2637 static int sci_remap_port(struct uart_port *port) 2638 { 2639 struct sci_port *sport = to_sci_port(port); 2640 2641 /* 2642 * Nothing to do if there's already an established membase. 2643 */ 2644 if (port->membase) 2645 return 0; 2646 2647 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2648 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2649 if (unlikely(!port->membase)) { 2650 dev_err(port->dev, "can't remap port#%d\n", port->line); 2651 return -ENXIO; 2652 } 2653 } else { 2654 /* 2655 * For the simple (and majority of) cases where we don't 2656 * need to do any remapping, just cast the cookie 2657 * directly. 2658 */ 2659 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2660 } 2661 2662 return 0; 2663 } 2664 2665 static void sci_release_port(struct uart_port *port) 2666 { 2667 struct sci_port *sport = to_sci_port(port); 2668 2669 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2670 iounmap(port->membase); 2671 port->membase = NULL; 2672 } 2673 2674 release_mem_region(port->mapbase, sport->reg_size); 2675 } 2676 2677 static int sci_request_port(struct uart_port *port) 2678 { 2679 struct resource *res; 2680 struct sci_port *sport = to_sci_port(port); 2681 int ret; 2682 2683 res = request_mem_region(port->mapbase, sport->reg_size, 2684 dev_name(port->dev)); 2685 if (unlikely(res == NULL)) { 2686 dev_err(port->dev, "request_mem_region failed."); 2687 return -EBUSY; 2688 } 2689 2690 ret = sci_remap_port(port); 2691 if (unlikely(ret != 0)) { 2692 release_resource(res); 2693 return ret; 2694 } 2695 2696 return 0; 2697 } 2698 2699 static void sci_config_port(struct uart_port *port, int flags) 2700 { 2701 if (flags & UART_CONFIG_TYPE) { 2702 struct sci_port *sport = to_sci_port(port); 2703 2704 port->type = sport->cfg->type; 2705 sci_request_port(port); 2706 } 2707 } 2708 2709 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2710 { 2711 if (ser->baud_base < 2400) 2712 /* No paper tape reader for Mitch.. */ 2713 return -EINVAL; 2714 2715 return 0; 2716 } 2717 2718 static const struct uart_ops sci_uart_ops = { 2719 .tx_empty = sci_tx_empty, 2720 .set_mctrl = sci_set_mctrl, 2721 .get_mctrl = sci_get_mctrl, 2722 .start_tx = sci_start_tx, 2723 .stop_tx = sci_stop_tx, 2724 .stop_rx = sci_stop_rx, 2725 .enable_ms = sci_enable_ms, 2726 .break_ctl = sci_break_ctl, 2727 .startup = sci_startup, 2728 .shutdown = sci_shutdown, 2729 .flush_buffer = sci_flush_buffer, 2730 .set_termios = sci_set_termios, 2731 .pm = sci_pm, 2732 .type = sci_type, 2733 .release_port = sci_release_port, 2734 .request_port = sci_request_port, 2735 .config_port = sci_config_port, 2736 .verify_port = sci_verify_port, 2737 #ifdef CONFIG_CONSOLE_POLL 2738 .poll_get_char = sci_poll_get_char, 2739 .poll_put_char = sci_poll_put_char, 2740 #endif 2741 }; 2742 2743 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2744 { 2745 const char *clk_names[] = { 2746 [SCI_FCK] = "fck", 2747 [SCI_SCK] = "sck", 2748 [SCI_BRG_INT] = "brg_int", 2749 [SCI_SCIF_CLK] = "scif_clk", 2750 }; 2751 struct clk *clk; 2752 unsigned int i; 2753 2754 if (sci_port->cfg->type == PORT_HSCIF) 2755 clk_names[SCI_SCK] = "hsck"; 2756 2757 for (i = 0; i < SCI_NUM_CLKS; i++) { 2758 clk = devm_clk_get(dev, clk_names[i]); 2759 if (PTR_ERR(clk) == -EPROBE_DEFER) 2760 return -EPROBE_DEFER; 2761 2762 if (IS_ERR(clk) && i == SCI_FCK) { 2763 /* 2764 * "fck" used to be called "sci_ick", and we need to 2765 * maintain DT backward compatibility. 2766 */ 2767 clk = devm_clk_get(dev, "sci_ick"); 2768 if (PTR_ERR(clk) == -EPROBE_DEFER) 2769 return -EPROBE_DEFER; 2770 2771 if (!IS_ERR(clk)) 2772 goto found; 2773 2774 /* 2775 * Not all SH platforms declare a clock lookup entry 2776 * for SCI devices, in which case we need to get the 2777 * global "peripheral_clk" clock. 2778 */ 2779 clk = devm_clk_get(dev, "peripheral_clk"); 2780 if (!IS_ERR(clk)) 2781 goto found; 2782 2783 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2784 PTR_ERR(clk)); 2785 return PTR_ERR(clk); 2786 } 2787 2788 found: 2789 if (IS_ERR(clk)) 2790 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2791 PTR_ERR(clk)); 2792 else 2793 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2794 clk, clk_get_rate(clk)); 2795 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2796 } 2797 return 0; 2798 } 2799 2800 static const struct sci_port_params * 2801 sci_probe_regmap(const struct plat_sci_port *cfg) 2802 { 2803 unsigned int regtype; 2804 2805 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2806 return &sci_port_params[cfg->regtype]; 2807 2808 switch (cfg->type) { 2809 case PORT_SCI: 2810 regtype = SCIx_SCI_REGTYPE; 2811 break; 2812 case PORT_IRDA: 2813 regtype = SCIx_IRDA_REGTYPE; 2814 break; 2815 case PORT_SCIFA: 2816 regtype = SCIx_SCIFA_REGTYPE; 2817 break; 2818 case PORT_SCIFB: 2819 regtype = SCIx_SCIFB_REGTYPE; 2820 break; 2821 case PORT_SCIF: 2822 /* 2823 * The SH-4 is a bit of a misnomer here, although that's 2824 * where this particular port layout originated. This 2825 * configuration (or some slight variation thereof) 2826 * remains the dominant model for all SCIFs. 2827 */ 2828 regtype = SCIx_SH4_SCIF_REGTYPE; 2829 break; 2830 case PORT_HSCIF: 2831 regtype = SCIx_HSCIF_REGTYPE; 2832 break; 2833 default: 2834 pr_err("Can't probe register map for given port\n"); 2835 return NULL; 2836 } 2837 2838 return &sci_port_params[regtype]; 2839 } 2840 2841 static int sci_init_single(struct platform_device *dev, 2842 struct sci_port *sci_port, unsigned int index, 2843 const struct plat_sci_port *p, bool early) 2844 { 2845 struct uart_port *port = &sci_port->port; 2846 const struct resource *res; 2847 unsigned int i; 2848 int ret; 2849 2850 sci_port->cfg = p; 2851 2852 port->ops = &sci_uart_ops; 2853 port->iotype = UPIO_MEM; 2854 port->line = index; 2855 2856 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2857 if (res == NULL) 2858 return -ENOMEM; 2859 2860 port->mapbase = res->start; 2861 sci_port->reg_size = resource_size(res); 2862 2863 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2864 sci_port->irqs[i] = platform_get_irq(dev, i); 2865 2866 /* The SCI generates several interrupts. They can be muxed together or 2867 * connected to different interrupt lines. In the muxed case only one 2868 * interrupt resource is specified as there is only one interrupt ID. 2869 * In the non-muxed case, up to 6 interrupt signals might be generated 2870 * from the SCI, however those signals might have their own individual 2871 * interrupt ID numbers, or muxed together with another interrupt. 2872 */ 2873 if (sci_port->irqs[0] < 0) 2874 return -ENXIO; 2875 2876 if (sci_port->irqs[1] < 0) 2877 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2878 sci_port->irqs[i] = sci_port->irqs[0]; 2879 2880 sci_port->params = sci_probe_regmap(p); 2881 if (unlikely(sci_port->params == NULL)) 2882 return -EINVAL; 2883 2884 switch (p->type) { 2885 case PORT_SCIFB: 2886 sci_port->rx_trigger = 48; 2887 break; 2888 case PORT_HSCIF: 2889 sci_port->rx_trigger = 64; 2890 break; 2891 case PORT_SCIFA: 2892 sci_port->rx_trigger = 32; 2893 break; 2894 case PORT_SCIF: 2895 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2896 /* RX triggering not implemented for this IP */ 2897 sci_port->rx_trigger = 1; 2898 else 2899 sci_port->rx_trigger = 8; 2900 break; 2901 default: 2902 sci_port->rx_trigger = 1; 2903 break; 2904 } 2905 2906 sci_port->rx_fifo_timeout = 0; 2907 sci_port->hscif_tot = 0; 2908 2909 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2910 * match the SoC datasheet, this should be investigated. Let platform 2911 * data override the sampling rate for now. 2912 */ 2913 sci_port->sampling_rate_mask = p->sampling_rate 2914 ? SCI_SR(p->sampling_rate) 2915 : sci_port->params->sampling_rate_mask; 2916 2917 if (!early) { 2918 ret = sci_init_clocks(sci_port, &dev->dev); 2919 if (ret < 0) 2920 return ret; 2921 2922 port->dev = &dev->dev; 2923 2924 pm_runtime_enable(&dev->dev); 2925 } 2926 2927 port->type = p->type; 2928 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2929 port->fifosize = sci_port->params->fifosize; 2930 2931 if (port->type == PORT_SCI) { 2932 if (sci_port->reg_size >= 0x20) 2933 port->regshift = 2; 2934 else 2935 port->regshift = 1; 2936 } 2937 2938 /* 2939 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2940 * for the multi-IRQ ports, which is where we are primarily 2941 * concerned with the shutdown path synchronization. 2942 * 2943 * For the muxed case there's nothing more to do. 2944 */ 2945 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2946 port->irqflags = 0; 2947 2948 port->serial_in = sci_serial_in; 2949 port->serial_out = sci_serial_out; 2950 2951 return 0; 2952 } 2953 2954 static void sci_cleanup_single(struct sci_port *port) 2955 { 2956 pm_runtime_disable(port->port.dev); 2957 } 2958 2959 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2960 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2961 static void serial_console_putchar(struct uart_port *port, int ch) 2962 { 2963 sci_poll_put_char(port, ch); 2964 } 2965 2966 /* 2967 * Print a string to the serial port trying not to disturb 2968 * any possible real use of the port... 2969 */ 2970 static void serial_console_write(struct console *co, const char *s, 2971 unsigned count) 2972 { 2973 struct sci_port *sci_port = &sci_ports[co->index]; 2974 struct uart_port *port = &sci_port->port; 2975 unsigned short bits, ctrl, ctrl_temp; 2976 unsigned long flags; 2977 int locked = 1; 2978 2979 #if defined(SUPPORT_SYSRQ) 2980 if (port->sysrq) 2981 locked = 0; 2982 else 2983 #endif 2984 if (oops_in_progress) 2985 locked = spin_trylock_irqsave(&port->lock, flags); 2986 else 2987 spin_lock_irqsave(&port->lock, flags); 2988 2989 /* first save SCSCR then disable interrupts, keep clock source */ 2990 ctrl = serial_port_in(port, SCSCR); 2991 ctrl_temp = SCSCR_RE | SCSCR_TE | 2992 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2993 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2994 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 2995 2996 uart_console_write(port, s, count, serial_console_putchar); 2997 2998 /* wait until fifo is empty and last bit has been transmitted */ 2999 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3000 while ((serial_port_in(port, SCxSR) & bits) != bits) 3001 cpu_relax(); 3002 3003 /* restore the SCSCR */ 3004 serial_port_out(port, SCSCR, ctrl); 3005 3006 if (locked) 3007 spin_unlock_irqrestore(&port->lock, flags); 3008 } 3009 3010 static int serial_console_setup(struct console *co, char *options) 3011 { 3012 struct sci_port *sci_port; 3013 struct uart_port *port; 3014 int baud = 115200; 3015 int bits = 8; 3016 int parity = 'n'; 3017 int flow = 'n'; 3018 int ret; 3019 3020 /* 3021 * Refuse to handle any bogus ports. 3022 */ 3023 if (co->index < 0 || co->index >= SCI_NPORTS) 3024 return -ENODEV; 3025 3026 sci_port = &sci_ports[co->index]; 3027 port = &sci_port->port; 3028 3029 /* 3030 * Refuse to handle uninitialized ports. 3031 */ 3032 if (!port->ops) 3033 return -ENODEV; 3034 3035 ret = sci_remap_port(port); 3036 if (unlikely(ret != 0)) 3037 return ret; 3038 3039 if (options) 3040 uart_parse_options(options, &baud, &parity, &bits, &flow); 3041 3042 return uart_set_options(port, co, baud, parity, bits, flow); 3043 } 3044 3045 static struct console serial_console = { 3046 .name = "ttySC", 3047 .device = uart_console_device, 3048 .write = serial_console_write, 3049 .setup = serial_console_setup, 3050 .flags = CON_PRINTBUFFER, 3051 .index = -1, 3052 .data = &sci_uart_driver, 3053 }; 3054 3055 static struct console early_serial_console = { 3056 .name = "early_ttySC", 3057 .write = serial_console_write, 3058 .flags = CON_PRINTBUFFER, 3059 .index = -1, 3060 }; 3061 3062 static char early_serial_buf[32]; 3063 3064 static int sci_probe_earlyprintk(struct platform_device *pdev) 3065 { 3066 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3067 3068 if (early_serial_console.data) 3069 return -EEXIST; 3070 3071 early_serial_console.index = pdev->id; 3072 3073 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3074 3075 serial_console_setup(&early_serial_console, early_serial_buf); 3076 3077 if (!strstr(early_serial_buf, "keep")) 3078 early_serial_console.flags |= CON_BOOT; 3079 3080 register_console(&early_serial_console); 3081 return 0; 3082 } 3083 3084 #define SCI_CONSOLE (&serial_console) 3085 3086 #else 3087 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3088 { 3089 return -EINVAL; 3090 } 3091 3092 #define SCI_CONSOLE NULL 3093 3094 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3095 3096 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3097 3098 static DEFINE_MUTEX(sci_uart_registration_lock); 3099 static struct uart_driver sci_uart_driver = { 3100 .owner = THIS_MODULE, 3101 .driver_name = "sci", 3102 .dev_name = "ttySC", 3103 .major = SCI_MAJOR, 3104 .minor = SCI_MINOR_START, 3105 .nr = SCI_NPORTS, 3106 .cons = SCI_CONSOLE, 3107 }; 3108 3109 static int sci_remove(struct platform_device *dev) 3110 { 3111 struct sci_port *port = platform_get_drvdata(dev); 3112 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3113 3114 sci_ports_in_use &= ~BIT(port->port.line); 3115 uart_remove_one_port(&sci_uart_driver, &port->port); 3116 3117 sci_cleanup_single(port); 3118 3119 if (port->port.fifosize > 1) { 3120 sysfs_remove_file(&dev->dev.kobj, 3121 &dev_attr_rx_fifo_trigger.attr); 3122 } 3123 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) { 3124 sysfs_remove_file(&dev->dev.kobj, 3125 &dev_attr_rx_fifo_timeout.attr); 3126 } 3127 3128 return 0; 3129 } 3130 3131 3132 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3133 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3134 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3135 3136 static const struct of_device_id of_sci_match[] = { 3137 /* SoC-specific types */ 3138 { 3139 .compatible = "renesas,scif-r7s72100", 3140 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3141 }, 3142 { 3143 .compatible = "renesas,scif-r7s9210", 3144 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3145 }, 3146 /* Family-specific types */ 3147 { 3148 .compatible = "renesas,rcar-gen1-scif", 3149 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3150 }, { 3151 .compatible = "renesas,rcar-gen2-scif", 3152 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3153 }, { 3154 .compatible = "renesas,rcar-gen3-scif", 3155 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3156 }, 3157 /* Generic types */ 3158 { 3159 .compatible = "renesas,scif", 3160 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3161 }, { 3162 .compatible = "renesas,scifa", 3163 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3164 }, { 3165 .compatible = "renesas,scifb", 3166 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3167 }, { 3168 .compatible = "renesas,hscif", 3169 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3170 }, { 3171 .compatible = "renesas,sci", 3172 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3173 }, { 3174 /* Terminator */ 3175 }, 3176 }; 3177 MODULE_DEVICE_TABLE(of, of_sci_match); 3178 3179 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3180 unsigned int *dev_id) 3181 { 3182 struct device_node *np = pdev->dev.of_node; 3183 struct plat_sci_port *p; 3184 struct sci_port *sp; 3185 const void *data; 3186 int id; 3187 3188 if (!IS_ENABLED(CONFIG_OF) || !np) 3189 return NULL; 3190 3191 data = of_device_get_match_data(&pdev->dev); 3192 3193 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3194 if (!p) 3195 return NULL; 3196 3197 /* Get the line number from the aliases node. */ 3198 id = of_alias_get_id(np, "serial"); 3199 if (id < 0 && ~sci_ports_in_use) 3200 id = ffz(sci_ports_in_use); 3201 if (id < 0) { 3202 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3203 return NULL; 3204 } 3205 if (id >= ARRAY_SIZE(sci_ports)) { 3206 dev_err(&pdev->dev, "serial%d out of range\n", id); 3207 return NULL; 3208 } 3209 3210 sp = &sci_ports[id]; 3211 *dev_id = id; 3212 3213 p->type = SCI_OF_TYPE(data); 3214 p->regtype = SCI_OF_REGTYPE(data); 3215 3216 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3217 3218 return p; 3219 } 3220 3221 static int sci_probe_single(struct platform_device *dev, 3222 unsigned int index, 3223 struct plat_sci_port *p, 3224 struct sci_port *sciport) 3225 { 3226 int ret; 3227 3228 /* Sanity check */ 3229 if (unlikely(index >= SCI_NPORTS)) { 3230 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3231 index+1, SCI_NPORTS); 3232 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3233 return -EINVAL; 3234 } 3235 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3236 if (sci_ports_in_use & BIT(index)) 3237 return -EBUSY; 3238 3239 mutex_lock(&sci_uart_registration_lock); 3240 if (!sci_uart_driver.state) { 3241 ret = uart_register_driver(&sci_uart_driver); 3242 if (ret) { 3243 mutex_unlock(&sci_uart_registration_lock); 3244 return ret; 3245 } 3246 } 3247 mutex_unlock(&sci_uart_registration_lock); 3248 3249 ret = sci_init_single(dev, sciport, index, p, false); 3250 if (ret) 3251 return ret; 3252 3253 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3254 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3255 return PTR_ERR(sciport->gpios); 3256 3257 if (sciport->has_rtscts) { 3258 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3259 UART_GPIO_CTS)) || 3260 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3261 UART_GPIO_RTS))) { 3262 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3263 return -EINVAL; 3264 } 3265 sciport->port.flags |= UPF_HARD_FLOW; 3266 } 3267 3268 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3269 if (ret) { 3270 sci_cleanup_single(sciport); 3271 return ret; 3272 } 3273 3274 return 0; 3275 } 3276 3277 static int sci_probe(struct platform_device *dev) 3278 { 3279 struct plat_sci_port *p; 3280 struct sci_port *sp; 3281 unsigned int dev_id; 3282 int ret; 3283 3284 /* 3285 * If we've come here via earlyprintk initialization, head off to 3286 * the special early probe. We don't have sufficient device state 3287 * to make it beyond this yet. 3288 */ 3289 if (is_early_platform_device(dev)) 3290 return sci_probe_earlyprintk(dev); 3291 3292 if (dev->dev.of_node) { 3293 p = sci_parse_dt(dev, &dev_id); 3294 if (p == NULL) 3295 return -EINVAL; 3296 } else { 3297 p = dev->dev.platform_data; 3298 if (p == NULL) { 3299 dev_err(&dev->dev, "no platform data supplied\n"); 3300 return -EINVAL; 3301 } 3302 3303 dev_id = dev->id; 3304 } 3305 3306 sp = &sci_ports[dev_id]; 3307 platform_set_drvdata(dev, sp); 3308 3309 ret = sci_probe_single(dev, dev_id, p, sp); 3310 if (ret) 3311 return ret; 3312 3313 if (sp->port.fifosize > 1) { 3314 ret = sysfs_create_file(&dev->dev.kobj, 3315 &dev_attr_rx_fifo_trigger.attr); 3316 if (ret) 3317 return ret; 3318 } 3319 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3320 sp->port.type == PORT_HSCIF) { 3321 ret = sysfs_create_file(&dev->dev.kobj, 3322 &dev_attr_rx_fifo_timeout.attr); 3323 if (ret) { 3324 if (sp->port.fifosize > 1) { 3325 sysfs_remove_file(&dev->dev.kobj, 3326 &dev_attr_rx_fifo_trigger.attr); 3327 } 3328 return ret; 3329 } 3330 } 3331 3332 #ifdef CONFIG_SH_STANDARD_BIOS 3333 sh_bios_gdb_detach(); 3334 #endif 3335 3336 sci_ports_in_use |= BIT(dev_id); 3337 return 0; 3338 } 3339 3340 static __maybe_unused int sci_suspend(struct device *dev) 3341 { 3342 struct sci_port *sport = dev_get_drvdata(dev); 3343 3344 if (sport) 3345 uart_suspend_port(&sci_uart_driver, &sport->port); 3346 3347 return 0; 3348 } 3349 3350 static __maybe_unused int sci_resume(struct device *dev) 3351 { 3352 struct sci_port *sport = dev_get_drvdata(dev); 3353 3354 if (sport) 3355 uart_resume_port(&sci_uart_driver, &sport->port); 3356 3357 return 0; 3358 } 3359 3360 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3361 3362 static struct platform_driver sci_driver = { 3363 .probe = sci_probe, 3364 .remove = sci_remove, 3365 .driver = { 3366 .name = "sh-sci", 3367 .pm = &sci_dev_pm_ops, 3368 .of_match_table = of_match_ptr(of_sci_match), 3369 }, 3370 }; 3371 3372 static int __init sci_init(void) 3373 { 3374 pr_info("%s\n", banner); 3375 3376 return platform_driver_register(&sci_driver); 3377 } 3378 3379 static void __exit sci_exit(void) 3380 { 3381 platform_driver_unregister(&sci_driver); 3382 3383 if (sci_uart_driver.state) 3384 uart_unregister_driver(&sci_uart_driver); 3385 } 3386 3387 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3388 early_platform_init_buffer("earlyprintk", &sci_driver, 3389 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3390 #endif 3391 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3392 static struct plat_sci_port port_cfg __initdata; 3393 3394 static int __init early_console_setup(struct earlycon_device *device, 3395 int type) 3396 { 3397 if (!device->port.membase) 3398 return -ENODEV; 3399 3400 device->port.serial_in = sci_serial_in; 3401 device->port.serial_out = sci_serial_out; 3402 device->port.type = type; 3403 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3404 port_cfg.type = type; 3405 sci_ports[0].cfg = &port_cfg; 3406 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3407 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3408 sci_serial_out(&sci_ports[0].port, SCSCR, 3409 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3410 3411 device->con->write = serial_console_write; 3412 return 0; 3413 } 3414 static int __init sci_early_console_setup(struct earlycon_device *device, 3415 const char *opt) 3416 { 3417 return early_console_setup(device, PORT_SCI); 3418 } 3419 static int __init scif_early_console_setup(struct earlycon_device *device, 3420 const char *opt) 3421 { 3422 return early_console_setup(device, PORT_SCIF); 3423 } 3424 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3425 const char *opt) 3426 { 3427 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3428 return early_console_setup(device, PORT_SCIF); 3429 } 3430 static int __init scifa_early_console_setup(struct earlycon_device *device, 3431 const char *opt) 3432 { 3433 return early_console_setup(device, PORT_SCIFA); 3434 } 3435 static int __init scifb_early_console_setup(struct earlycon_device *device, 3436 const char *opt) 3437 { 3438 return early_console_setup(device, PORT_SCIFB); 3439 } 3440 static int __init hscif_early_console_setup(struct earlycon_device *device, 3441 const char *opt) 3442 { 3443 return early_console_setup(device, PORT_HSCIF); 3444 } 3445 3446 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3447 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3448 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3449 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3450 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3451 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3452 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3453 3454 module_init(sci_init); 3455 module_exit(sci_exit); 3456 3457 MODULE_LICENSE("GPL"); 3458 MODULE_ALIAS("platform:sh-sci"); 3459 MODULE_AUTHOR("Paul Mundt"); 3460 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3461