1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/minmax.h> 35 #include <linux/module.h> 36 #include <linux/mm.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/reset.h> 42 #include <linux/scatterlist.h> 43 #include <linux/serial.h> 44 #include <linux/serial_sci.h> 45 #include <linux/sh_dma.h> 46 #include <linux/slab.h> 47 #include <linux/string.h> 48 #include <linux/sysrq.h> 49 #include <linux/timer.h> 50 #include <linux/tty.h> 51 #include <linux/tty_flip.h> 52 53 #ifdef CONFIG_SUPERH 54 #include <asm/sh_bios.h> 55 #include <asm/platform_early.h> 56 #endif 57 58 #include "serial_mctrl_gpio.h" 59 #include "sh-sci.h" 60 61 /* Offsets into the sci_port->irqs array */ 62 enum { 63 SCIx_ERI_IRQ, 64 SCIx_RXI_IRQ, 65 SCIx_TXI_IRQ, 66 SCIx_BRI_IRQ, 67 SCIx_DRI_IRQ, 68 SCIx_TEI_IRQ, 69 SCIx_NR_IRQS, 70 71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 72 }; 73 74 #define SCIx_IRQ_IS_MUXED(port) \ 75 ((port)->irqs[SCIx_ERI_IRQ] == \ 76 (port)->irqs[SCIx_RXI_IRQ]) || \ 77 ((port)->irqs[SCIx_ERI_IRQ] && \ 78 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 79 80 enum SCI_CLKS { 81 SCI_FCK, /* Functional Clock */ 82 SCI_SCK, /* Optional External Clock */ 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 85 SCI_NUM_CLKS 86 }; 87 88 /* Bit x set means sampling rate x + 1 is supported */ 89 #define SCI_SR(x) BIT((x) - 1) 90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 91 92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 94 SCI_SR(19) | SCI_SR(27) 95 96 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 97 #define max_sr(_port) fls((_port)->sampling_rate_mask) 98 99 /* Iterate over all supported sampling rates, from high to low */ 100 #define for_each_sr(_sr, _port) \ 101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 102 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 103 104 struct plat_sci_reg { 105 u8 offset, size; 106 }; 107 108 struct sci_port_params { 109 const struct plat_sci_reg regs[SCIx_NR_REGS]; 110 unsigned int fifosize; 111 unsigned int overrun_reg; 112 unsigned int overrun_mask; 113 unsigned int sampling_rate_mask; 114 unsigned int error_mask; 115 unsigned int error_clear; 116 }; 117 118 struct sci_port { 119 struct uart_port port; 120 121 /* Platform configuration */ 122 const struct sci_port_params *params; 123 const struct plat_sci_port *cfg; 124 unsigned int sampling_rate_mask; 125 resource_size_t reg_size; 126 struct mctrl_gpios *gpios; 127 128 /* Clocks */ 129 struct clk *clks[SCI_NUM_CLKS]; 130 unsigned long clk_rates[SCI_NUM_CLKS]; 131 132 int irqs[SCIx_NR_IRQS]; 133 char *irqstr[SCIx_NR_IRQS]; 134 135 struct dma_chan *chan_tx; 136 struct dma_chan *chan_rx; 137 138 #ifdef CONFIG_SERIAL_SH_SCI_DMA 139 struct dma_chan *chan_tx_saved; 140 struct dma_chan *chan_rx_saved; 141 dma_cookie_t cookie_tx; 142 dma_cookie_t cookie_rx[2]; 143 dma_cookie_t active_rx; 144 dma_addr_t tx_dma_addr; 145 unsigned int tx_dma_len; 146 struct scatterlist sg_rx[2]; 147 void *rx_buf[2]; 148 size_t buf_len_rx; 149 struct work_struct work_tx; 150 struct hrtimer rx_timer; 151 unsigned int rx_timeout; /* microseconds */ 152 #endif 153 unsigned int rx_frame; 154 int rx_trigger; 155 struct timer_list rx_fifo_timer; 156 int rx_fifo_timeout; 157 u16 hscif_tot; 158 159 bool has_rtscts; 160 bool autorts; 161 }; 162 163 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 164 165 static struct sci_port sci_ports[SCI_NPORTS]; 166 static unsigned long sci_ports_in_use; 167 static struct uart_driver sci_uart_driver; 168 169 static inline struct sci_port * 170 to_sci_port(struct uart_port *uart) 171 { 172 return container_of(uart, struct sci_port, port); 173 } 174 175 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 176 /* 177 * Common SCI definitions, dependent on the port's regshift 178 * value. 179 */ 180 [SCIx_SCI_REGTYPE] = { 181 .regs = { 182 [SCSMR] = { 0x00, 8 }, 183 [SCBRR] = { 0x01, 8 }, 184 [SCSCR] = { 0x02, 8 }, 185 [SCxTDR] = { 0x03, 8 }, 186 [SCxSR] = { 0x04, 8 }, 187 [SCxRDR] = { 0x05, 8 }, 188 }, 189 .fifosize = 1, 190 .overrun_reg = SCxSR, 191 .overrun_mask = SCI_ORER, 192 .sampling_rate_mask = SCI_SR(32), 193 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 194 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 195 }, 196 197 /* 198 * Common definitions for legacy IrDA ports. 199 */ 200 [SCIx_IRDA_REGTYPE] = { 201 .regs = { 202 [SCSMR] = { 0x00, 8 }, 203 [SCBRR] = { 0x02, 8 }, 204 [SCSCR] = { 0x04, 8 }, 205 [SCxTDR] = { 0x06, 8 }, 206 [SCxSR] = { 0x08, 16 }, 207 [SCxRDR] = { 0x0a, 8 }, 208 [SCFCR] = { 0x0c, 8 }, 209 [SCFDR] = { 0x0e, 16 }, 210 }, 211 .fifosize = 1, 212 .overrun_reg = SCxSR, 213 .overrun_mask = SCI_ORER, 214 .sampling_rate_mask = SCI_SR(32), 215 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 216 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 217 }, 218 219 /* 220 * Common SCIFA definitions. 221 */ 222 [SCIx_SCIFA_REGTYPE] = { 223 .regs = { 224 [SCSMR] = { 0x00, 16 }, 225 [SCBRR] = { 0x04, 8 }, 226 [SCSCR] = { 0x08, 16 }, 227 [SCxTDR] = { 0x20, 8 }, 228 [SCxSR] = { 0x14, 16 }, 229 [SCxRDR] = { 0x24, 8 }, 230 [SCFCR] = { 0x18, 16 }, 231 [SCFDR] = { 0x1c, 16 }, 232 [SCPCR] = { 0x30, 16 }, 233 [SCPDR] = { 0x34, 16 }, 234 }, 235 .fifosize = 64, 236 .overrun_reg = SCxSR, 237 .overrun_mask = SCIFA_ORER, 238 .sampling_rate_mask = SCI_SR_SCIFAB, 239 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 240 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 241 }, 242 243 /* 244 * Common SCIFB definitions. 245 */ 246 [SCIx_SCIFB_REGTYPE] = { 247 .regs = { 248 [SCSMR] = { 0x00, 16 }, 249 [SCBRR] = { 0x04, 8 }, 250 [SCSCR] = { 0x08, 16 }, 251 [SCxTDR] = { 0x40, 8 }, 252 [SCxSR] = { 0x14, 16 }, 253 [SCxRDR] = { 0x60, 8 }, 254 [SCFCR] = { 0x18, 16 }, 255 [SCTFDR] = { 0x38, 16 }, 256 [SCRFDR] = { 0x3c, 16 }, 257 [SCPCR] = { 0x30, 16 }, 258 [SCPDR] = { 0x34, 16 }, 259 }, 260 .fifosize = 256, 261 .overrun_reg = SCxSR, 262 .overrun_mask = SCIFA_ORER, 263 .sampling_rate_mask = SCI_SR_SCIFAB, 264 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 265 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 266 }, 267 268 /* 269 * Common SH-2(A) SCIF definitions for ports with FIFO data 270 * count registers. 271 */ 272 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 273 .regs = { 274 [SCSMR] = { 0x00, 16 }, 275 [SCBRR] = { 0x04, 8 }, 276 [SCSCR] = { 0x08, 16 }, 277 [SCxTDR] = { 0x0c, 8 }, 278 [SCxSR] = { 0x10, 16 }, 279 [SCxRDR] = { 0x14, 8 }, 280 [SCFCR] = { 0x18, 16 }, 281 [SCFDR] = { 0x1c, 16 }, 282 [SCSPTR] = { 0x20, 16 }, 283 [SCLSR] = { 0x24, 16 }, 284 }, 285 .fifosize = 16, 286 .overrun_reg = SCLSR, 287 .overrun_mask = SCLSR_ORER, 288 .sampling_rate_mask = SCI_SR(32), 289 .error_mask = SCIF_DEFAULT_ERROR_MASK, 290 .error_clear = SCIF_ERROR_CLEAR, 291 }, 292 293 /* 294 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 295 * It looks like a normal SCIF with FIFO data, but with a 296 * compressed address space. Also, the break out of interrupts 297 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 298 */ 299 [SCIx_RZ_SCIFA_REGTYPE] = { 300 .regs = { 301 [SCSMR] = { 0x00, 16 }, 302 [SCBRR] = { 0x02, 8 }, 303 [SCSCR] = { 0x04, 16 }, 304 [SCxTDR] = { 0x06, 8 }, 305 [SCxSR] = { 0x08, 16 }, 306 [SCxRDR] = { 0x0A, 8 }, 307 [SCFCR] = { 0x0C, 16 }, 308 [SCFDR] = { 0x0E, 16 }, 309 [SCSPTR] = { 0x10, 16 }, 310 [SCLSR] = { 0x12, 16 }, 311 [SEMR] = { 0x14, 8 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ 506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 s->cookie_tx = 0; 592 schedule_work(&s->work_tx); 593 } 594 #endif 595 596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 598 ctrl = serial_port_in(port, SCSCR); 599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 600 } 601 } 602 603 static void sci_stop_tx(struct uart_port *port) 604 { 605 unsigned short ctrl; 606 607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 608 ctrl = serial_port_in(port, SCSCR); 609 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 611 ctrl &= ~SCSCR_TDRQE; 612 613 ctrl &= ~SCSCR_TIE; 614 615 serial_port_out(port, SCSCR, ctrl); 616 617 #ifdef CONFIG_SERIAL_SH_SCI_DMA 618 if (to_sci_port(port)->chan_tx && 619 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 620 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 621 to_sci_port(port)->cookie_tx = -EINVAL; 622 } 623 #endif 624 } 625 626 static void sci_start_rx(struct uart_port *port) 627 { 628 unsigned short ctrl; 629 630 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 631 632 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 633 ctrl &= ~SCSCR_RDRQE; 634 635 serial_port_out(port, SCSCR, ctrl); 636 } 637 638 static void sci_stop_rx(struct uart_port *port) 639 { 640 unsigned short ctrl; 641 642 ctrl = serial_port_in(port, SCSCR); 643 644 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 645 ctrl &= ~SCSCR_RDRQE; 646 647 ctrl &= ~port_rx_irq_mask(port); 648 649 serial_port_out(port, SCSCR, ctrl); 650 } 651 652 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 653 { 654 if (port->type == PORT_SCI) { 655 /* Just store the mask */ 656 serial_port_out(port, SCxSR, mask); 657 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 658 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 659 /* Only clear the status bits we want to clear */ 660 serial_port_out(port, SCxSR, 661 serial_port_in(port, SCxSR) & mask); 662 } else { 663 /* Store the mask, clear parity/framing errors */ 664 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 665 } 666 } 667 668 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 669 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 670 671 #ifdef CONFIG_CONSOLE_POLL 672 static int sci_poll_get_char(struct uart_port *port) 673 { 674 unsigned short status; 675 int c; 676 677 do { 678 status = serial_port_in(port, SCxSR); 679 if (status & SCxSR_ERRORS(port)) { 680 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 681 continue; 682 } 683 break; 684 } while (1); 685 686 if (!(status & SCxSR_RDxF(port))) 687 return NO_POLL_CHAR; 688 689 c = serial_port_in(port, SCxRDR); 690 691 /* Dummy read */ 692 serial_port_in(port, SCxSR); 693 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 694 695 return c; 696 } 697 #endif 698 699 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 700 { 701 unsigned short status; 702 703 do { 704 status = serial_port_in(port, SCxSR); 705 } while (!(status & SCxSR_TDxE(port))); 706 707 serial_port_out(port, SCxTDR, c); 708 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 709 } 710 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 711 CONFIG_SERIAL_SH_SCI_EARLYCON */ 712 713 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 714 { 715 struct sci_port *s = to_sci_port(port); 716 717 /* 718 * Use port-specific handler if provided. 719 */ 720 if (s->cfg->ops && s->cfg->ops->init_pins) { 721 s->cfg->ops->init_pins(port, cflag); 722 return; 723 } 724 725 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 726 u16 data = serial_port_in(port, SCPDR); 727 u16 ctrl = serial_port_in(port, SCPCR); 728 729 /* Enable RXD and TXD pin functions */ 730 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 731 if (to_sci_port(port)->has_rtscts) { 732 /* RTS# is output, active low, unless autorts */ 733 if (!(port->mctrl & TIOCM_RTS)) { 734 ctrl |= SCPCR_RTSC; 735 data |= SCPDR_RTSD; 736 } else if (!s->autorts) { 737 ctrl |= SCPCR_RTSC; 738 data &= ~SCPDR_RTSD; 739 } else { 740 /* Enable RTS# pin function */ 741 ctrl &= ~SCPCR_RTSC; 742 } 743 /* Enable CTS# pin function */ 744 ctrl &= ~SCPCR_CTSC; 745 } 746 serial_port_out(port, SCPDR, data); 747 serial_port_out(port, SCPCR, ctrl); 748 } else if (sci_getreg(port, SCSPTR)->size) { 749 u16 status = serial_port_in(port, SCSPTR); 750 751 /* RTS# is always output; and active low, unless autorts */ 752 status |= SCSPTR_RTSIO; 753 if (!(port->mctrl & TIOCM_RTS)) 754 status |= SCSPTR_RTSDT; 755 else if (!s->autorts) 756 status &= ~SCSPTR_RTSDT; 757 /* CTS# and SCK are inputs */ 758 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 759 serial_port_out(port, SCSPTR, status); 760 } 761 } 762 763 static int sci_txfill(struct uart_port *port) 764 { 765 struct sci_port *s = to_sci_port(port); 766 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 767 const struct plat_sci_reg *reg; 768 769 reg = sci_getreg(port, SCTFDR); 770 if (reg->size) 771 return serial_port_in(port, SCTFDR) & fifo_mask; 772 773 reg = sci_getreg(port, SCFDR); 774 if (reg->size) 775 return serial_port_in(port, SCFDR) >> 8; 776 777 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 778 } 779 780 static int sci_txroom(struct uart_port *port) 781 { 782 return port->fifosize - sci_txfill(port); 783 } 784 785 static int sci_rxfill(struct uart_port *port) 786 { 787 struct sci_port *s = to_sci_port(port); 788 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 789 const struct plat_sci_reg *reg; 790 791 reg = sci_getreg(port, SCRFDR); 792 if (reg->size) 793 return serial_port_in(port, SCRFDR) & fifo_mask; 794 795 reg = sci_getreg(port, SCFDR); 796 if (reg->size) 797 return serial_port_in(port, SCFDR) & fifo_mask; 798 799 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 800 } 801 802 /* ********************************************************************** * 803 * the interrupt related routines * 804 * ********************************************************************** */ 805 806 static void sci_transmit_chars(struct uart_port *port) 807 { 808 struct circ_buf *xmit = &port->state->xmit; 809 unsigned int stopped = uart_tx_stopped(port); 810 unsigned short status; 811 unsigned short ctrl; 812 int count; 813 814 status = serial_port_in(port, SCxSR); 815 if (!(status & SCxSR_TDxE(port))) { 816 ctrl = serial_port_in(port, SCSCR); 817 if (uart_circ_empty(xmit)) 818 ctrl &= ~SCSCR_TIE; 819 else 820 ctrl |= SCSCR_TIE; 821 serial_port_out(port, SCSCR, ctrl); 822 return; 823 } 824 825 count = sci_txroom(port); 826 827 do { 828 unsigned char c; 829 830 if (port->x_char) { 831 c = port->x_char; 832 port->x_char = 0; 833 } else if (!uart_circ_empty(xmit) && !stopped) { 834 c = xmit->buf[xmit->tail]; 835 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 836 } else { 837 break; 838 } 839 840 serial_port_out(port, SCxTDR, c); 841 842 port->icount.tx++; 843 } while (--count > 0); 844 845 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 846 847 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 848 uart_write_wakeup(port); 849 if (uart_circ_empty(xmit)) 850 sci_stop_tx(port); 851 852 } 853 854 static void sci_receive_chars(struct uart_port *port) 855 { 856 struct tty_port *tport = &port->state->port; 857 int i, count, copied = 0; 858 unsigned short status; 859 unsigned char flag; 860 861 status = serial_port_in(port, SCxSR); 862 if (!(status & SCxSR_RDxF(port))) 863 return; 864 865 while (1) { 866 /* Don't copy more bytes than there is room for in the buffer */ 867 count = tty_buffer_request_room(tport, sci_rxfill(port)); 868 869 /* If for any reason we can't copy more data, we're done! */ 870 if (count == 0) 871 break; 872 873 if (port->type == PORT_SCI) { 874 char c = serial_port_in(port, SCxRDR); 875 if (uart_handle_sysrq_char(port, c)) 876 count = 0; 877 else 878 tty_insert_flip_char(tport, c, TTY_NORMAL); 879 } else { 880 for (i = 0; i < count; i++) { 881 char c; 882 883 if (port->type == PORT_SCIF || 884 port->type == PORT_HSCIF) { 885 status = serial_port_in(port, SCxSR); 886 c = serial_port_in(port, SCxRDR); 887 } else { 888 c = serial_port_in(port, SCxRDR); 889 status = serial_port_in(port, SCxSR); 890 } 891 if (uart_handle_sysrq_char(port, c)) { 892 count--; i--; 893 continue; 894 } 895 896 /* Store data and status */ 897 if (status & SCxSR_FER(port)) { 898 flag = TTY_FRAME; 899 port->icount.frame++; 900 } else if (status & SCxSR_PER(port)) { 901 flag = TTY_PARITY; 902 port->icount.parity++; 903 } else 904 flag = TTY_NORMAL; 905 906 tty_insert_flip_char(tport, c, flag); 907 } 908 } 909 910 serial_port_in(port, SCxSR); /* dummy read */ 911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 912 913 copied += count; 914 port->icount.rx += count; 915 } 916 917 if (copied) { 918 /* Tell the rest of the system the news. New characters! */ 919 tty_flip_buffer_push(tport); 920 } else { 921 /* TTY buffers full; read from RX reg to prevent lockup */ 922 serial_port_in(port, SCxRDR); 923 serial_port_in(port, SCxSR); /* dummy read */ 924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 925 } 926 } 927 928 static int sci_handle_errors(struct uart_port *port) 929 { 930 int copied = 0; 931 unsigned short status = serial_port_in(port, SCxSR); 932 struct tty_port *tport = &port->state->port; 933 struct sci_port *s = to_sci_port(port); 934 935 /* Handle overruns */ 936 if (status & s->params->overrun_mask) { 937 port->icount.overrun++; 938 939 /* overrun error */ 940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 941 copied++; 942 } 943 944 if (status & SCxSR_FER(port)) { 945 /* frame error */ 946 port->icount.frame++; 947 948 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 949 copied++; 950 } 951 952 if (status & SCxSR_PER(port)) { 953 /* parity error */ 954 port->icount.parity++; 955 956 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 957 copied++; 958 } 959 960 if (copied) 961 tty_flip_buffer_push(tport); 962 963 return copied; 964 } 965 966 static int sci_handle_fifo_overrun(struct uart_port *port) 967 { 968 struct tty_port *tport = &port->state->port; 969 struct sci_port *s = to_sci_port(port); 970 const struct plat_sci_reg *reg; 971 int copied = 0; 972 u16 status; 973 974 reg = sci_getreg(port, s->params->overrun_reg); 975 if (!reg->size) 976 return 0; 977 978 status = serial_port_in(port, s->params->overrun_reg); 979 if (status & s->params->overrun_mask) { 980 status &= ~s->params->overrun_mask; 981 serial_port_out(port, s->params->overrun_reg, status); 982 983 port->icount.overrun++; 984 985 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 986 tty_flip_buffer_push(tport); 987 copied++; 988 } 989 990 return copied; 991 } 992 993 static int sci_handle_breaks(struct uart_port *port) 994 { 995 int copied = 0; 996 unsigned short status = serial_port_in(port, SCxSR); 997 struct tty_port *tport = &port->state->port; 998 999 if (uart_handle_break(port)) 1000 return 0; 1001 1002 if (status & SCxSR_BRK(port)) { 1003 port->icount.brk++; 1004 1005 /* Notify of BREAK */ 1006 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1007 copied++; 1008 } 1009 1010 if (copied) 1011 tty_flip_buffer_push(tport); 1012 1013 copied += sci_handle_fifo_overrun(port); 1014 1015 return copied; 1016 } 1017 1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1019 { 1020 unsigned int bits; 1021 1022 if (rx_trig >= port->fifosize) 1023 rx_trig = port->fifosize - 1; 1024 if (rx_trig < 1) 1025 rx_trig = 1; 1026 1027 /* HSCIF can be set to an arbitrary level. */ 1028 if (sci_getreg(port, HSRTRGR)->size) { 1029 serial_port_out(port, HSRTRGR, rx_trig); 1030 return rx_trig; 1031 } 1032 1033 switch (port->type) { 1034 case PORT_SCIF: 1035 if (rx_trig < 4) { 1036 bits = 0; 1037 rx_trig = 1; 1038 } else if (rx_trig < 8) { 1039 bits = SCFCR_RTRG0; 1040 rx_trig = 4; 1041 } else if (rx_trig < 14) { 1042 bits = SCFCR_RTRG1; 1043 rx_trig = 8; 1044 } else { 1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1046 rx_trig = 14; 1047 } 1048 break; 1049 case PORT_SCIFA: 1050 case PORT_SCIFB: 1051 if (rx_trig < 16) { 1052 bits = 0; 1053 rx_trig = 1; 1054 } else if (rx_trig < 32) { 1055 bits = SCFCR_RTRG0; 1056 rx_trig = 16; 1057 } else if (rx_trig < 48) { 1058 bits = SCFCR_RTRG1; 1059 rx_trig = 32; 1060 } else { 1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1062 rx_trig = 48; 1063 } 1064 break; 1065 default: 1066 WARN(1, "unknown FIFO configuration"); 1067 return 1; 1068 } 1069 1070 serial_port_out(port, SCFCR, 1071 (serial_port_in(port, SCFCR) & 1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1073 1074 return rx_trig; 1075 } 1076 1077 static int scif_rtrg_enabled(struct uart_port *port) 1078 { 1079 if (sci_getreg(port, HSRTRGR)->size) 1080 return serial_port_in(port, HSRTRGR) != 0; 1081 else 1082 return (serial_port_in(port, SCFCR) & 1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1084 } 1085 1086 static void rx_fifo_timer_fn(struct timer_list *t) 1087 { 1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1089 struct uart_port *port = &s->port; 1090 1091 dev_dbg(port->dev, "Rx timed out\n"); 1092 scif_set_rtrg(port, 1); 1093 } 1094 1095 static ssize_t rx_fifo_trigger_show(struct device *dev, 1096 struct device_attribute *attr, char *buf) 1097 { 1098 struct uart_port *port = dev_get_drvdata(dev); 1099 struct sci_port *sci = to_sci_port(port); 1100 1101 return sprintf(buf, "%d\n", sci->rx_trigger); 1102 } 1103 1104 static ssize_t rx_fifo_trigger_store(struct device *dev, 1105 struct device_attribute *attr, 1106 const char *buf, size_t count) 1107 { 1108 struct uart_port *port = dev_get_drvdata(dev); 1109 struct sci_port *sci = to_sci_port(port); 1110 int ret; 1111 long r; 1112 1113 ret = kstrtol(buf, 0, &r); 1114 if (ret) 1115 return ret; 1116 1117 sci->rx_trigger = scif_set_rtrg(port, r); 1118 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1119 scif_set_rtrg(port, 1); 1120 1121 return count; 1122 } 1123 1124 static DEVICE_ATTR_RW(rx_fifo_trigger); 1125 1126 static ssize_t rx_fifo_timeout_show(struct device *dev, 1127 struct device_attribute *attr, 1128 char *buf) 1129 { 1130 struct uart_port *port = dev_get_drvdata(dev); 1131 struct sci_port *sci = to_sci_port(port); 1132 int v; 1133 1134 if (port->type == PORT_HSCIF) 1135 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1136 else 1137 v = sci->rx_fifo_timeout; 1138 1139 return sprintf(buf, "%d\n", v); 1140 } 1141 1142 static ssize_t rx_fifo_timeout_store(struct device *dev, 1143 struct device_attribute *attr, 1144 const char *buf, 1145 size_t count) 1146 { 1147 struct uart_port *port = dev_get_drvdata(dev); 1148 struct sci_port *sci = to_sci_port(port); 1149 int ret; 1150 long r; 1151 1152 ret = kstrtol(buf, 0, &r); 1153 if (ret) 1154 return ret; 1155 1156 if (port->type == PORT_HSCIF) { 1157 if (r < 0 || r > 3) 1158 return -EINVAL; 1159 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1160 } else { 1161 sci->rx_fifo_timeout = r; 1162 scif_set_rtrg(port, 1); 1163 if (r > 0) 1164 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1165 } 1166 1167 return count; 1168 } 1169 1170 static DEVICE_ATTR_RW(rx_fifo_timeout); 1171 1172 1173 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1174 static void sci_dma_tx_complete(void *arg) 1175 { 1176 struct sci_port *s = arg; 1177 struct uart_port *port = &s->port; 1178 struct circ_buf *xmit = &port->state->xmit; 1179 unsigned long flags; 1180 1181 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1182 1183 spin_lock_irqsave(&port->lock, flags); 1184 1185 uart_xmit_advance(port, s->tx_dma_len); 1186 1187 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1188 uart_write_wakeup(port); 1189 1190 if (!uart_circ_empty(xmit)) { 1191 s->cookie_tx = 0; 1192 schedule_work(&s->work_tx); 1193 } else { 1194 s->cookie_tx = -EINVAL; 1195 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1196 u16 ctrl = serial_port_in(port, SCSCR); 1197 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1198 } 1199 } 1200 1201 spin_unlock_irqrestore(&port->lock, flags); 1202 } 1203 1204 /* Locking: called with port lock held */ 1205 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1206 { 1207 struct uart_port *port = &s->port; 1208 struct tty_port *tport = &port->state->port; 1209 int copied; 1210 1211 copied = tty_insert_flip_string(tport, buf, count); 1212 if (copied < count) 1213 port->icount.buf_overrun++; 1214 1215 port->icount.rx += copied; 1216 1217 return copied; 1218 } 1219 1220 static int sci_dma_rx_find_active(struct sci_port *s) 1221 { 1222 unsigned int i; 1223 1224 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1225 if (s->active_rx == s->cookie_rx[i]) 1226 return i; 1227 1228 return -1; 1229 } 1230 1231 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1232 { 1233 unsigned int i; 1234 1235 s->chan_rx = NULL; 1236 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1237 s->cookie_rx[i] = -EINVAL; 1238 s->active_rx = 0; 1239 } 1240 1241 static void sci_dma_rx_release(struct sci_port *s) 1242 { 1243 struct dma_chan *chan = s->chan_rx_saved; 1244 1245 s->chan_rx_saved = NULL; 1246 sci_dma_rx_chan_invalidate(s); 1247 dmaengine_terminate_sync(chan); 1248 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1249 sg_dma_address(&s->sg_rx[0])); 1250 dma_release_channel(chan); 1251 } 1252 1253 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1254 { 1255 long sec = usec / 1000000; 1256 long nsec = (usec % 1000000) * 1000; 1257 ktime_t t = ktime_set(sec, nsec); 1258 1259 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1260 } 1261 1262 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1263 { 1264 struct uart_port *port = &s->port; 1265 u16 scr; 1266 1267 /* Direct new serial port interrupts back to CPU */ 1268 scr = serial_port_in(port, SCSCR); 1269 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1270 scr &= ~SCSCR_RDRQE; 1271 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1272 } 1273 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1274 } 1275 1276 static void sci_dma_rx_complete(void *arg) 1277 { 1278 struct sci_port *s = arg; 1279 struct dma_chan *chan = s->chan_rx; 1280 struct uart_port *port = &s->port; 1281 struct dma_async_tx_descriptor *desc; 1282 unsigned long flags; 1283 int active, count = 0; 1284 1285 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1286 s->active_rx); 1287 1288 spin_lock_irqsave(&port->lock, flags); 1289 1290 active = sci_dma_rx_find_active(s); 1291 if (active >= 0) 1292 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1293 1294 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1295 1296 if (count) 1297 tty_flip_buffer_push(&port->state->port); 1298 1299 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1300 DMA_DEV_TO_MEM, 1301 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1302 if (!desc) 1303 goto fail; 1304 1305 desc->callback = sci_dma_rx_complete; 1306 desc->callback_param = s; 1307 s->cookie_rx[active] = dmaengine_submit(desc); 1308 if (dma_submit_error(s->cookie_rx[active])) 1309 goto fail; 1310 1311 s->active_rx = s->cookie_rx[!active]; 1312 1313 dma_async_issue_pending(chan); 1314 1315 spin_unlock_irqrestore(&port->lock, flags); 1316 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1317 __func__, s->cookie_rx[active], active, s->active_rx); 1318 return; 1319 1320 fail: 1321 spin_unlock_irqrestore(&port->lock, flags); 1322 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1323 /* Switch to PIO */ 1324 spin_lock_irqsave(&port->lock, flags); 1325 dmaengine_terminate_async(chan); 1326 sci_dma_rx_chan_invalidate(s); 1327 sci_dma_rx_reenable_irq(s); 1328 spin_unlock_irqrestore(&port->lock, flags); 1329 } 1330 1331 static void sci_dma_tx_release(struct sci_port *s) 1332 { 1333 struct dma_chan *chan = s->chan_tx_saved; 1334 1335 cancel_work_sync(&s->work_tx); 1336 s->chan_tx_saved = s->chan_tx = NULL; 1337 s->cookie_tx = -EINVAL; 1338 dmaengine_terminate_sync(chan); 1339 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1340 DMA_TO_DEVICE); 1341 dma_release_channel(chan); 1342 } 1343 1344 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1345 { 1346 struct dma_chan *chan = s->chan_rx; 1347 struct uart_port *port = &s->port; 1348 unsigned long flags; 1349 int i; 1350 1351 for (i = 0; i < 2; i++) { 1352 struct scatterlist *sg = &s->sg_rx[i]; 1353 struct dma_async_tx_descriptor *desc; 1354 1355 desc = dmaengine_prep_slave_sg(chan, 1356 sg, 1, DMA_DEV_TO_MEM, 1357 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1358 if (!desc) 1359 goto fail; 1360 1361 desc->callback = sci_dma_rx_complete; 1362 desc->callback_param = s; 1363 s->cookie_rx[i] = dmaengine_submit(desc); 1364 if (dma_submit_error(s->cookie_rx[i])) 1365 goto fail; 1366 1367 } 1368 1369 s->active_rx = s->cookie_rx[0]; 1370 1371 dma_async_issue_pending(chan); 1372 return 0; 1373 1374 fail: 1375 /* Switch to PIO */ 1376 if (!port_lock_held) 1377 spin_lock_irqsave(&port->lock, flags); 1378 if (i) 1379 dmaengine_terminate_async(chan); 1380 sci_dma_rx_chan_invalidate(s); 1381 sci_start_rx(port); 1382 if (!port_lock_held) 1383 spin_unlock_irqrestore(&port->lock, flags); 1384 return -EAGAIN; 1385 } 1386 1387 static void sci_dma_tx_work_fn(struct work_struct *work) 1388 { 1389 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1390 struct dma_async_tx_descriptor *desc; 1391 struct dma_chan *chan = s->chan_tx; 1392 struct uart_port *port = &s->port; 1393 struct circ_buf *xmit = &port->state->xmit; 1394 unsigned long flags; 1395 dma_addr_t buf; 1396 int head, tail; 1397 1398 /* 1399 * DMA is idle now. 1400 * Port xmit buffer is already mapped, and it is one page... Just adjust 1401 * offsets and lengths. Since it is a circular buffer, we have to 1402 * transmit till the end, and then the rest. Take the port lock to get a 1403 * consistent xmit buffer state. 1404 */ 1405 spin_lock_irq(&port->lock); 1406 head = xmit->head; 1407 tail = xmit->tail; 1408 buf = s->tx_dma_addr + tail; 1409 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1410 if (!s->tx_dma_len) { 1411 /* Transmit buffer has been flushed */ 1412 spin_unlock_irq(&port->lock); 1413 return; 1414 } 1415 1416 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1417 DMA_MEM_TO_DEV, 1418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1419 if (!desc) { 1420 spin_unlock_irq(&port->lock); 1421 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1422 goto switch_to_pio; 1423 } 1424 1425 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1426 DMA_TO_DEVICE); 1427 1428 desc->callback = sci_dma_tx_complete; 1429 desc->callback_param = s; 1430 s->cookie_tx = dmaengine_submit(desc); 1431 if (dma_submit_error(s->cookie_tx)) { 1432 spin_unlock_irq(&port->lock); 1433 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1434 goto switch_to_pio; 1435 } 1436 1437 spin_unlock_irq(&port->lock); 1438 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1439 __func__, xmit->buf, tail, head, s->cookie_tx); 1440 1441 dma_async_issue_pending(chan); 1442 return; 1443 1444 switch_to_pio: 1445 spin_lock_irqsave(&port->lock, flags); 1446 s->chan_tx = NULL; 1447 sci_start_tx(port); 1448 spin_unlock_irqrestore(&port->lock, flags); 1449 return; 1450 } 1451 1452 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1453 { 1454 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1455 struct dma_chan *chan = s->chan_rx; 1456 struct uart_port *port = &s->port; 1457 struct dma_tx_state state; 1458 enum dma_status status; 1459 unsigned long flags; 1460 unsigned int read; 1461 int active, count; 1462 1463 dev_dbg(port->dev, "DMA Rx timed out\n"); 1464 1465 spin_lock_irqsave(&port->lock, flags); 1466 1467 active = sci_dma_rx_find_active(s); 1468 if (active < 0) { 1469 spin_unlock_irqrestore(&port->lock, flags); 1470 return HRTIMER_NORESTART; 1471 } 1472 1473 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1474 if (status == DMA_COMPLETE) { 1475 spin_unlock_irqrestore(&port->lock, flags); 1476 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1477 s->active_rx, active); 1478 1479 /* Let packet complete handler take care of the packet */ 1480 return HRTIMER_NORESTART; 1481 } 1482 1483 dmaengine_pause(chan); 1484 1485 /* 1486 * sometimes DMA transfer doesn't stop even if it is stopped and 1487 * data keeps on coming until transaction is complete so check 1488 * for DMA_COMPLETE again 1489 * Let packet complete handler take care of the packet 1490 */ 1491 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1492 if (status == DMA_COMPLETE) { 1493 spin_unlock_irqrestore(&port->lock, flags); 1494 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1495 return HRTIMER_NORESTART; 1496 } 1497 1498 /* Handle incomplete DMA receive */ 1499 dmaengine_terminate_async(s->chan_rx); 1500 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1501 1502 if (read) { 1503 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1504 if (count) 1505 tty_flip_buffer_push(&port->state->port); 1506 } 1507 1508 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1509 sci_dma_rx_submit(s, true); 1510 1511 sci_dma_rx_reenable_irq(s); 1512 1513 spin_unlock_irqrestore(&port->lock, flags); 1514 1515 return HRTIMER_NORESTART; 1516 } 1517 1518 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1519 enum dma_transfer_direction dir) 1520 { 1521 struct dma_chan *chan; 1522 struct dma_slave_config cfg; 1523 int ret; 1524 1525 chan = dma_request_slave_channel(port->dev, 1526 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1527 if (!chan) { 1528 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1529 return NULL; 1530 } 1531 1532 memset(&cfg, 0, sizeof(cfg)); 1533 cfg.direction = dir; 1534 if (dir == DMA_MEM_TO_DEV) { 1535 cfg.dst_addr = port->mapbase + 1536 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1537 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1538 } else { 1539 cfg.src_addr = port->mapbase + 1540 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1541 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1542 } 1543 1544 ret = dmaengine_slave_config(chan, &cfg); 1545 if (ret) { 1546 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1547 dma_release_channel(chan); 1548 return NULL; 1549 } 1550 1551 return chan; 1552 } 1553 1554 static void sci_request_dma(struct uart_port *port) 1555 { 1556 struct sci_port *s = to_sci_port(port); 1557 struct dma_chan *chan; 1558 1559 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1560 1561 /* 1562 * DMA on console may interfere with Kernel log messages which use 1563 * plain putchar(). So, simply don't use it with a console. 1564 */ 1565 if (uart_console(port)) 1566 return; 1567 1568 if (!port->dev->of_node) 1569 return; 1570 1571 s->cookie_tx = -EINVAL; 1572 1573 /* 1574 * Don't request a dma channel if no channel was specified 1575 * in the device tree. 1576 */ 1577 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1578 return; 1579 1580 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1581 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1582 if (chan) { 1583 /* UART circular tx buffer is an aligned page. */ 1584 s->tx_dma_addr = dma_map_single(chan->device->dev, 1585 port->state->xmit.buf, 1586 UART_XMIT_SIZE, 1587 DMA_TO_DEVICE); 1588 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1589 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1590 dma_release_channel(chan); 1591 } else { 1592 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1593 __func__, UART_XMIT_SIZE, 1594 port->state->xmit.buf, &s->tx_dma_addr); 1595 1596 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1597 s->chan_tx_saved = s->chan_tx = chan; 1598 } 1599 } 1600 1601 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1602 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1603 if (chan) { 1604 unsigned int i; 1605 dma_addr_t dma; 1606 void *buf; 1607 1608 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1609 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1610 &dma, GFP_KERNEL); 1611 if (!buf) { 1612 dev_warn(port->dev, 1613 "Failed to allocate Rx dma buffer, using PIO\n"); 1614 dma_release_channel(chan); 1615 return; 1616 } 1617 1618 for (i = 0; i < 2; i++) { 1619 struct scatterlist *sg = &s->sg_rx[i]; 1620 1621 sg_init_table(sg, 1); 1622 s->rx_buf[i] = buf; 1623 sg_dma_address(sg) = dma; 1624 sg_dma_len(sg) = s->buf_len_rx; 1625 1626 buf += s->buf_len_rx; 1627 dma += s->buf_len_rx; 1628 } 1629 1630 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1631 s->rx_timer.function = sci_dma_rx_timer_fn; 1632 1633 s->chan_rx_saved = s->chan_rx = chan; 1634 1635 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1636 sci_dma_rx_submit(s, false); 1637 } 1638 } 1639 1640 static void sci_free_dma(struct uart_port *port) 1641 { 1642 struct sci_port *s = to_sci_port(port); 1643 1644 if (s->chan_tx_saved) 1645 sci_dma_tx_release(s); 1646 if (s->chan_rx_saved) 1647 sci_dma_rx_release(s); 1648 } 1649 1650 static void sci_flush_buffer(struct uart_port *port) 1651 { 1652 struct sci_port *s = to_sci_port(port); 1653 1654 /* 1655 * In uart_flush_buffer(), the xmit circular buffer has just been 1656 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1657 * pending transfers 1658 */ 1659 s->tx_dma_len = 0; 1660 if (s->chan_tx) { 1661 dmaengine_terminate_async(s->chan_tx); 1662 s->cookie_tx = -EINVAL; 1663 } 1664 } 1665 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1666 static inline void sci_request_dma(struct uart_port *port) 1667 { 1668 } 1669 1670 static inline void sci_free_dma(struct uart_port *port) 1671 { 1672 } 1673 1674 #define sci_flush_buffer NULL 1675 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1676 1677 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1678 { 1679 struct uart_port *port = ptr; 1680 struct sci_port *s = to_sci_port(port); 1681 1682 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1683 if (s->chan_rx) { 1684 u16 scr = serial_port_in(port, SCSCR); 1685 u16 ssr = serial_port_in(port, SCxSR); 1686 1687 /* Disable future Rx interrupts */ 1688 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1689 disable_irq_nosync(irq); 1690 scr |= SCSCR_RDRQE; 1691 } else { 1692 if (sci_dma_rx_submit(s, false) < 0) 1693 goto handle_pio; 1694 1695 scr &= ~SCSCR_RIE; 1696 } 1697 serial_port_out(port, SCSCR, scr); 1698 /* Clear current interrupt */ 1699 serial_port_out(port, SCxSR, 1700 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1701 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1702 jiffies, s->rx_timeout); 1703 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1704 1705 return IRQ_HANDLED; 1706 } 1707 1708 handle_pio: 1709 #endif 1710 1711 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1712 if (!scif_rtrg_enabled(port)) 1713 scif_set_rtrg(port, s->rx_trigger); 1714 1715 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1716 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1717 } 1718 1719 /* I think sci_receive_chars has to be called irrespective 1720 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1721 * to be disabled? 1722 */ 1723 sci_receive_chars(port); 1724 1725 return IRQ_HANDLED; 1726 } 1727 1728 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1729 { 1730 struct uart_port *port = ptr; 1731 unsigned long flags; 1732 1733 spin_lock_irqsave(&port->lock, flags); 1734 sci_transmit_chars(port); 1735 spin_unlock_irqrestore(&port->lock, flags); 1736 1737 return IRQ_HANDLED; 1738 } 1739 1740 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1741 { 1742 struct uart_port *port = ptr; 1743 1744 /* Handle BREAKs */ 1745 sci_handle_breaks(port); 1746 1747 /* drop invalid character received before break was detected */ 1748 serial_port_in(port, SCxRDR); 1749 1750 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1751 1752 return IRQ_HANDLED; 1753 } 1754 1755 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1756 { 1757 struct uart_port *port = ptr; 1758 struct sci_port *s = to_sci_port(port); 1759 1760 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1761 /* Break and Error interrupts are muxed */ 1762 unsigned short ssr_status = serial_port_in(port, SCxSR); 1763 1764 /* Break Interrupt */ 1765 if (ssr_status & SCxSR_BRK(port)) 1766 sci_br_interrupt(irq, ptr); 1767 1768 /* Break only? */ 1769 if (!(ssr_status & SCxSR_ERRORS(port))) 1770 return IRQ_HANDLED; 1771 } 1772 1773 /* Handle errors */ 1774 if (port->type == PORT_SCI) { 1775 if (sci_handle_errors(port)) { 1776 /* discard character in rx buffer */ 1777 serial_port_in(port, SCxSR); 1778 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1779 } 1780 } else { 1781 sci_handle_fifo_overrun(port); 1782 if (!s->chan_rx) 1783 sci_receive_chars(port); 1784 } 1785 1786 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1787 1788 /* Kick the transmission */ 1789 if (!s->chan_tx) 1790 sci_tx_interrupt(irq, ptr); 1791 1792 return IRQ_HANDLED; 1793 } 1794 1795 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1796 { 1797 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1798 struct uart_port *port = ptr; 1799 struct sci_port *s = to_sci_port(port); 1800 irqreturn_t ret = IRQ_NONE; 1801 1802 ssr_status = serial_port_in(port, SCxSR); 1803 scr_status = serial_port_in(port, SCSCR); 1804 if (s->params->overrun_reg == SCxSR) 1805 orer_status = ssr_status; 1806 else if (sci_getreg(port, s->params->overrun_reg)->size) 1807 orer_status = serial_port_in(port, s->params->overrun_reg); 1808 1809 err_enabled = scr_status & port_rx_irq_mask(port); 1810 1811 /* Tx Interrupt */ 1812 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1813 !s->chan_tx) 1814 ret = sci_tx_interrupt(irq, ptr); 1815 1816 /* 1817 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1818 * DR flags 1819 */ 1820 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1821 (scr_status & SCSCR_RIE)) 1822 ret = sci_rx_interrupt(irq, ptr); 1823 1824 /* Error Interrupt */ 1825 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1826 ret = sci_er_interrupt(irq, ptr); 1827 1828 /* Break Interrupt */ 1829 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1830 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1831 ret = sci_br_interrupt(irq, ptr); 1832 1833 /* Overrun Interrupt */ 1834 if (orer_status & s->params->overrun_mask) { 1835 sci_handle_fifo_overrun(port); 1836 ret = IRQ_HANDLED; 1837 } 1838 1839 return ret; 1840 } 1841 1842 static const struct sci_irq_desc { 1843 const char *desc; 1844 irq_handler_t handler; 1845 } sci_irq_desc[] = { 1846 /* 1847 * Split out handlers, the default case. 1848 */ 1849 [SCIx_ERI_IRQ] = { 1850 .desc = "rx err", 1851 .handler = sci_er_interrupt, 1852 }, 1853 1854 [SCIx_RXI_IRQ] = { 1855 .desc = "rx full", 1856 .handler = sci_rx_interrupt, 1857 }, 1858 1859 [SCIx_TXI_IRQ] = { 1860 .desc = "tx empty", 1861 .handler = sci_tx_interrupt, 1862 }, 1863 1864 [SCIx_BRI_IRQ] = { 1865 .desc = "break", 1866 .handler = sci_br_interrupt, 1867 }, 1868 1869 [SCIx_DRI_IRQ] = { 1870 .desc = "rx ready", 1871 .handler = sci_rx_interrupt, 1872 }, 1873 1874 [SCIx_TEI_IRQ] = { 1875 .desc = "tx end", 1876 .handler = sci_tx_interrupt, 1877 }, 1878 1879 /* 1880 * Special muxed handler. 1881 */ 1882 [SCIx_MUX_IRQ] = { 1883 .desc = "mux", 1884 .handler = sci_mpxed_interrupt, 1885 }, 1886 }; 1887 1888 static int sci_request_irq(struct sci_port *port) 1889 { 1890 struct uart_port *up = &port->port; 1891 int i, j, w, ret = 0; 1892 1893 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1894 const struct sci_irq_desc *desc; 1895 int irq; 1896 1897 /* Check if already registered (muxed) */ 1898 for (w = 0; w < i; w++) 1899 if (port->irqs[w] == port->irqs[i]) 1900 w = i + 1; 1901 if (w > i) 1902 continue; 1903 1904 if (SCIx_IRQ_IS_MUXED(port)) { 1905 i = SCIx_MUX_IRQ; 1906 irq = up->irq; 1907 } else { 1908 irq = port->irqs[i]; 1909 1910 /* 1911 * Certain port types won't support all of the 1912 * available interrupt sources. 1913 */ 1914 if (unlikely(irq < 0)) 1915 continue; 1916 } 1917 1918 desc = sci_irq_desc + i; 1919 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1920 dev_name(up->dev), desc->desc); 1921 if (!port->irqstr[j]) { 1922 ret = -ENOMEM; 1923 goto out_nomem; 1924 } 1925 1926 ret = request_irq(irq, desc->handler, up->irqflags, 1927 port->irqstr[j], port); 1928 if (unlikely(ret)) { 1929 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1930 goto out_noirq; 1931 } 1932 } 1933 1934 return 0; 1935 1936 out_noirq: 1937 while (--i >= 0) 1938 free_irq(port->irqs[i], port); 1939 1940 out_nomem: 1941 while (--j >= 0) 1942 kfree(port->irqstr[j]); 1943 1944 return ret; 1945 } 1946 1947 static void sci_free_irq(struct sci_port *port) 1948 { 1949 int i, j; 1950 1951 /* 1952 * Intentionally in reverse order so we iterate over the muxed 1953 * IRQ first. 1954 */ 1955 for (i = 0; i < SCIx_NR_IRQS; i++) { 1956 int irq = port->irqs[i]; 1957 1958 /* 1959 * Certain port types won't support all of the available 1960 * interrupt sources. 1961 */ 1962 if (unlikely(irq < 0)) 1963 continue; 1964 1965 /* Check if already freed (irq was muxed) */ 1966 for (j = 0; j < i; j++) 1967 if (port->irqs[j] == irq) 1968 j = i + 1; 1969 if (j > i) 1970 continue; 1971 1972 free_irq(port->irqs[i], port); 1973 kfree(port->irqstr[i]); 1974 1975 if (SCIx_IRQ_IS_MUXED(port)) { 1976 /* If there's only one IRQ, we're done. */ 1977 return; 1978 } 1979 } 1980 } 1981 1982 static unsigned int sci_tx_empty(struct uart_port *port) 1983 { 1984 unsigned short status = serial_port_in(port, SCxSR); 1985 unsigned short in_tx_fifo = sci_txfill(port); 1986 1987 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1988 } 1989 1990 static void sci_set_rts(struct uart_port *port, bool state) 1991 { 1992 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1993 u16 data = serial_port_in(port, SCPDR); 1994 1995 /* Active low */ 1996 if (state) 1997 data &= ~SCPDR_RTSD; 1998 else 1999 data |= SCPDR_RTSD; 2000 serial_port_out(port, SCPDR, data); 2001 2002 /* RTS# is output */ 2003 serial_port_out(port, SCPCR, 2004 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2005 } else if (sci_getreg(port, SCSPTR)->size) { 2006 u16 ctrl = serial_port_in(port, SCSPTR); 2007 2008 /* Active low */ 2009 if (state) 2010 ctrl &= ~SCSPTR_RTSDT; 2011 else 2012 ctrl |= SCSPTR_RTSDT; 2013 serial_port_out(port, SCSPTR, ctrl); 2014 } 2015 } 2016 2017 static bool sci_get_cts(struct uart_port *port) 2018 { 2019 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2020 /* Active low */ 2021 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2022 } else if (sci_getreg(port, SCSPTR)->size) { 2023 /* Active low */ 2024 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2025 } 2026 2027 return true; 2028 } 2029 2030 /* 2031 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2032 * CTS/RTS is supported in hardware by at least one port and controlled 2033 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2034 * handled via the ->init_pins() op, which is a bit of a one-way street, 2035 * lacking any ability to defer pin control -- this will later be 2036 * converted over to the GPIO framework). 2037 * 2038 * Other modes (such as loopback) are supported generically on certain 2039 * port types, but not others. For these it's sufficient to test for the 2040 * existence of the support register and simply ignore the port type. 2041 */ 2042 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2043 { 2044 struct sci_port *s = to_sci_port(port); 2045 2046 if (mctrl & TIOCM_LOOP) { 2047 const struct plat_sci_reg *reg; 2048 2049 /* 2050 * Standard loopback mode for SCFCR ports. 2051 */ 2052 reg = sci_getreg(port, SCFCR); 2053 if (reg->size) 2054 serial_port_out(port, SCFCR, 2055 serial_port_in(port, SCFCR) | 2056 SCFCR_LOOP); 2057 } 2058 2059 mctrl_gpio_set(s->gpios, mctrl); 2060 2061 if (!s->has_rtscts) 2062 return; 2063 2064 if (!(mctrl & TIOCM_RTS)) { 2065 /* Disable Auto RTS */ 2066 serial_port_out(port, SCFCR, 2067 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2068 2069 /* Clear RTS */ 2070 sci_set_rts(port, 0); 2071 } else if (s->autorts) { 2072 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2073 /* Enable RTS# pin function */ 2074 serial_port_out(port, SCPCR, 2075 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2076 } 2077 2078 /* Enable Auto RTS */ 2079 serial_port_out(port, SCFCR, 2080 serial_port_in(port, SCFCR) | SCFCR_MCE); 2081 } else { 2082 /* Set RTS */ 2083 sci_set_rts(port, 1); 2084 } 2085 } 2086 2087 static unsigned int sci_get_mctrl(struct uart_port *port) 2088 { 2089 struct sci_port *s = to_sci_port(port); 2090 struct mctrl_gpios *gpios = s->gpios; 2091 unsigned int mctrl = 0; 2092 2093 mctrl_gpio_get(gpios, &mctrl); 2094 2095 /* 2096 * CTS/RTS is handled in hardware when supported, while nothing 2097 * else is wired up. 2098 */ 2099 if (s->autorts) { 2100 if (sci_get_cts(port)) 2101 mctrl |= TIOCM_CTS; 2102 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2103 mctrl |= TIOCM_CTS; 2104 } 2105 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2106 mctrl |= TIOCM_DSR; 2107 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2108 mctrl |= TIOCM_CAR; 2109 2110 return mctrl; 2111 } 2112 2113 static void sci_enable_ms(struct uart_port *port) 2114 { 2115 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2116 } 2117 2118 static void sci_break_ctl(struct uart_port *port, int break_state) 2119 { 2120 unsigned short scscr, scsptr; 2121 unsigned long flags; 2122 2123 /* check whether the port has SCSPTR */ 2124 if (!sci_getreg(port, SCSPTR)->size) { 2125 /* 2126 * Not supported by hardware. Most parts couple break and rx 2127 * interrupts together, with break detection always enabled. 2128 */ 2129 return; 2130 } 2131 2132 spin_lock_irqsave(&port->lock, flags); 2133 scsptr = serial_port_in(port, SCSPTR); 2134 scscr = serial_port_in(port, SCSCR); 2135 2136 if (break_state == -1) { 2137 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2138 scscr &= ~SCSCR_TE; 2139 } else { 2140 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2141 scscr |= SCSCR_TE; 2142 } 2143 2144 serial_port_out(port, SCSPTR, scsptr); 2145 serial_port_out(port, SCSCR, scscr); 2146 spin_unlock_irqrestore(&port->lock, flags); 2147 } 2148 2149 static int sci_startup(struct uart_port *port) 2150 { 2151 struct sci_port *s = to_sci_port(port); 2152 int ret; 2153 2154 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2155 2156 sci_request_dma(port); 2157 2158 ret = sci_request_irq(s); 2159 if (unlikely(ret < 0)) { 2160 sci_free_dma(port); 2161 return ret; 2162 } 2163 2164 return 0; 2165 } 2166 2167 static void sci_shutdown(struct uart_port *port) 2168 { 2169 struct sci_port *s = to_sci_port(port); 2170 unsigned long flags; 2171 u16 scr; 2172 2173 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2174 2175 s->autorts = false; 2176 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2177 2178 spin_lock_irqsave(&port->lock, flags); 2179 sci_stop_rx(port); 2180 sci_stop_tx(port); 2181 /* 2182 * Stop RX and TX, disable related interrupts, keep clock source 2183 * and HSCIF TOT bits 2184 */ 2185 scr = serial_port_in(port, SCSCR); 2186 serial_port_out(port, SCSCR, scr & 2187 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2188 spin_unlock_irqrestore(&port->lock, flags); 2189 2190 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2191 if (s->chan_rx_saved) { 2192 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2193 port->line); 2194 hrtimer_cancel(&s->rx_timer); 2195 } 2196 #endif 2197 2198 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2199 del_timer_sync(&s->rx_fifo_timer); 2200 sci_free_irq(s); 2201 sci_free_dma(port); 2202 } 2203 2204 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2205 unsigned int *srr) 2206 { 2207 unsigned long freq = s->clk_rates[SCI_SCK]; 2208 int err, min_err = INT_MAX; 2209 unsigned int sr; 2210 2211 if (s->port.type != PORT_HSCIF) 2212 freq *= 2; 2213 2214 for_each_sr(sr, s) { 2215 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2216 if (abs(err) >= abs(min_err)) 2217 continue; 2218 2219 min_err = err; 2220 *srr = sr - 1; 2221 2222 if (!err) 2223 break; 2224 } 2225 2226 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2227 *srr + 1); 2228 return min_err; 2229 } 2230 2231 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2232 unsigned long freq, unsigned int *dlr, 2233 unsigned int *srr) 2234 { 2235 int err, min_err = INT_MAX; 2236 unsigned int sr, dl; 2237 2238 if (s->port.type != PORT_HSCIF) 2239 freq *= 2; 2240 2241 for_each_sr(sr, s) { 2242 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2243 dl = clamp(dl, 1U, 65535U); 2244 2245 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2246 if (abs(err) >= abs(min_err)) 2247 continue; 2248 2249 min_err = err; 2250 *dlr = dl; 2251 *srr = sr - 1; 2252 2253 if (!err) 2254 break; 2255 } 2256 2257 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2258 min_err, *dlr, *srr + 1); 2259 return min_err; 2260 } 2261 2262 /* calculate sample rate, BRR, and clock select */ 2263 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2264 unsigned int *brr, unsigned int *srr, 2265 unsigned int *cks) 2266 { 2267 unsigned long freq = s->clk_rates[SCI_FCK]; 2268 unsigned int sr, br, prediv, scrate, c; 2269 int err, min_err = INT_MAX; 2270 2271 if (s->port.type != PORT_HSCIF) 2272 freq *= 2; 2273 2274 /* 2275 * Find the combination of sample rate and clock select with the 2276 * smallest deviation from the desired baud rate. 2277 * Prefer high sample rates to maximise the receive margin. 2278 * 2279 * M: Receive margin (%) 2280 * N: Ratio of bit rate to clock (N = sampling rate) 2281 * D: Clock duty (D = 0 to 1.0) 2282 * L: Frame length (L = 9 to 12) 2283 * F: Absolute value of clock frequency deviation 2284 * 2285 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2286 * (|D - 0.5| / N * (1 + F))| 2287 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2288 */ 2289 for_each_sr(sr, s) { 2290 for (c = 0; c <= 3; c++) { 2291 /* integerized formulas from HSCIF documentation */ 2292 prediv = sr << (2 * c + 1); 2293 2294 /* 2295 * We need to calculate: 2296 * 2297 * br = freq / (prediv * bps) clamped to [1..256] 2298 * err = freq / (br * prediv) - bps 2299 * 2300 * Watch out for overflow when calculating the desired 2301 * sampling clock rate! 2302 */ 2303 if (bps > UINT_MAX / prediv) 2304 break; 2305 2306 scrate = prediv * bps; 2307 br = DIV_ROUND_CLOSEST(freq, scrate); 2308 br = clamp(br, 1U, 256U); 2309 2310 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2311 if (abs(err) >= abs(min_err)) 2312 continue; 2313 2314 min_err = err; 2315 *brr = br - 1; 2316 *srr = sr - 1; 2317 *cks = c; 2318 2319 if (!err) 2320 goto found; 2321 } 2322 } 2323 2324 found: 2325 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2326 min_err, *brr, *srr + 1, *cks); 2327 return min_err; 2328 } 2329 2330 static void sci_reset(struct uart_port *port) 2331 { 2332 const struct plat_sci_reg *reg; 2333 unsigned int status; 2334 struct sci_port *s = to_sci_port(port); 2335 2336 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2337 2338 reg = sci_getreg(port, SCFCR); 2339 if (reg->size) 2340 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2341 2342 sci_clear_SCxSR(port, 2343 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2344 SCxSR_BREAK_CLEAR(port)); 2345 if (sci_getreg(port, SCLSR)->size) { 2346 status = serial_port_in(port, SCLSR); 2347 status &= ~(SCLSR_TO | SCLSR_ORER); 2348 serial_port_out(port, SCLSR, status); 2349 } 2350 2351 if (s->rx_trigger > 1) { 2352 if (s->rx_fifo_timeout) { 2353 scif_set_rtrg(port, 1); 2354 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2355 } else { 2356 if (port->type == PORT_SCIFA || 2357 port->type == PORT_SCIFB) 2358 scif_set_rtrg(port, 1); 2359 else 2360 scif_set_rtrg(port, s->rx_trigger); 2361 } 2362 } 2363 } 2364 2365 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2366 const struct ktermios *old) 2367 { 2368 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2369 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2370 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2371 struct sci_port *s = to_sci_port(port); 2372 const struct plat_sci_reg *reg; 2373 int min_err = INT_MAX, err; 2374 unsigned long max_freq = 0; 2375 int best_clk = -1; 2376 unsigned long flags; 2377 2378 if ((termios->c_cflag & CSIZE) == CS7) { 2379 smr_val |= SCSMR_CHR; 2380 } else { 2381 termios->c_cflag &= ~CSIZE; 2382 termios->c_cflag |= CS8; 2383 } 2384 if (termios->c_cflag & PARENB) 2385 smr_val |= SCSMR_PE; 2386 if (termios->c_cflag & PARODD) 2387 smr_val |= SCSMR_PE | SCSMR_ODD; 2388 if (termios->c_cflag & CSTOPB) 2389 smr_val |= SCSMR_STOP; 2390 2391 /* 2392 * earlyprintk comes here early on with port->uartclk set to zero. 2393 * the clock framework is not up and running at this point so here 2394 * we assume that 115200 is the maximum baud rate. please note that 2395 * the baud rate is not programmed during earlyprintk - it is assumed 2396 * that the previous boot loader has enabled required clocks and 2397 * setup the baud rate generator hardware for us already. 2398 */ 2399 if (!port->uartclk) { 2400 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2401 goto done; 2402 } 2403 2404 for (i = 0; i < SCI_NUM_CLKS; i++) 2405 max_freq = max(max_freq, s->clk_rates[i]); 2406 2407 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2408 if (!baud) 2409 goto done; 2410 2411 /* 2412 * There can be multiple sources for the sampling clock. Find the one 2413 * that gives us the smallest deviation from the desired baud rate. 2414 */ 2415 2416 /* Optional Undivided External Clock */ 2417 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2418 port->type != PORT_SCIFB) { 2419 err = sci_sck_calc(s, baud, &srr1); 2420 if (abs(err) < abs(min_err)) { 2421 best_clk = SCI_SCK; 2422 scr_val = SCSCR_CKE1; 2423 sccks = SCCKS_CKS; 2424 min_err = err; 2425 srr = srr1; 2426 if (!err) 2427 goto done; 2428 } 2429 } 2430 2431 /* Optional BRG Frequency Divided External Clock */ 2432 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2433 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2434 &srr1); 2435 if (abs(err) < abs(min_err)) { 2436 best_clk = SCI_SCIF_CLK; 2437 scr_val = SCSCR_CKE1; 2438 sccks = 0; 2439 min_err = err; 2440 dl = dl1; 2441 srr = srr1; 2442 if (!err) 2443 goto done; 2444 } 2445 } 2446 2447 /* Optional BRG Frequency Divided Internal Clock */ 2448 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2449 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2450 &srr1); 2451 if (abs(err) < abs(min_err)) { 2452 best_clk = SCI_BRG_INT; 2453 scr_val = SCSCR_CKE1; 2454 sccks = SCCKS_XIN; 2455 min_err = err; 2456 dl = dl1; 2457 srr = srr1; 2458 if (!min_err) 2459 goto done; 2460 } 2461 } 2462 2463 /* Divided Functional Clock using standard Bit Rate Register */ 2464 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2465 if (abs(err) < abs(min_err)) { 2466 best_clk = SCI_FCK; 2467 scr_val = 0; 2468 min_err = err; 2469 brr = brr1; 2470 srr = srr1; 2471 cks = cks1; 2472 } 2473 2474 done: 2475 if (best_clk >= 0) 2476 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2477 s->clks[best_clk], baud, min_err); 2478 2479 sci_port_enable(s); 2480 2481 /* 2482 * Program the optional External Baud Rate Generator (BRG) first. 2483 * It controls the mux to select (H)SCK or frequency divided clock. 2484 */ 2485 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2486 serial_port_out(port, SCDL, dl); 2487 serial_port_out(port, SCCKS, sccks); 2488 } 2489 2490 spin_lock_irqsave(&port->lock, flags); 2491 2492 sci_reset(port); 2493 2494 uart_update_timeout(port, termios->c_cflag, baud); 2495 2496 /* byte size and parity */ 2497 bits = tty_get_frame_size(termios->c_cflag); 2498 2499 if (sci_getreg(port, SEMR)->size) 2500 serial_port_out(port, SEMR, 0); 2501 2502 if (best_clk >= 0) { 2503 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2504 switch (srr + 1) { 2505 case 5: smr_val |= SCSMR_SRC_5; break; 2506 case 7: smr_val |= SCSMR_SRC_7; break; 2507 case 11: smr_val |= SCSMR_SRC_11; break; 2508 case 13: smr_val |= SCSMR_SRC_13; break; 2509 case 16: smr_val |= SCSMR_SRC_16; break; 2510 case 17: smr_val |= SCSMR_SRC_17; break; 2511 case 19: smr_val |= SCSMR_SRC_19; break; 2512 case 27: smr_val |= SCSMR_SRC_27; break; 2513 } 2514 smr_val |= cks; 2515 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2516 serial_port_out(port, SCSMR, smr_val); 2517 serial_port_out(port, SCBRR, brr); 2518 if (sci_getreg(port, HSSRR)->size) { 2519 unsigned int hssrr = srr | HSCIF_SRE; 2520 /* Calculate deviation from intended rate at the 2521 * center of the last stop bit in sampling clocks. 2522 */ 2523 int last_stop = bits * 2 - 1; 2524 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2525 (int)(srr + 1), 2526 2 * (int)baud); 2527 2528 if (abs(deviation) >= 2) { 2529 /* At least two sampling clocks off at the 2530 * last stop bit; we can increase the error 2531 * margin by shifting the sampling point. 2532 */ 2533 int shift = clamp(deviation / 2, -8, 7); 2534 2535 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2536 HSCIF_SRHP_MASK; 2537 hssrr |= HSCIF_SRDE; 2538 } 2539 serial_port_out(port, HSSRR, hssrr); 2540 } 2541 2542 /* Wait one bit interval */ 2543 udelay((1000000 + (baud - 1)) / baud); 2544 } else { 2545 /* Don't touch the bit rate configuration */ 2546 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2547 smr_val |= serial_port_in(port, SCSMR) & 2548 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2549 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2550 serial_port_out(port, SCSMR, smr_val); 2551 } 2552 2553 sci_init_pins(port, termios->c_cflag); 2554 2555 port->status &= ~UPSTAT_AUTOCTS; 2556 s->autorts = false; 2557 reg = sci_getreg(port, SCFCR); 2558 if (reg->size) { 2559 unsigned short ctrl = serial_port_in(port, SCFCR); 2560 2561 if ((port->flags & UPF_HARD_FLOW) && 2562 (termios->c_cflag & CRTSCTS)) { 2563 /* There is no CTS interrupt to restart the hardware */ 2564 port->status |= UPSTAT_AUTOCTS; 2565 /* MCE is enabled when RTS is raised */ 2566 s->autorts = true; 2567 } 2568 2569 /* 2570 * As we've done a sci_reset() above, ensure we don't 2571 * interfere with the FIFOs while toggling MCE. As the 2572 * reset values could still be set, simply mask them out. 2573 */ 2574 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2575 2576 serial_port_out(port, SCFCR, ctrl); 2577 } 2578 if (port->flags & UPF_HARD_FLOW) { 2579 /* Refresh (Auto) RTS */ 2580 sci_set_mctrl(port, port->mctrl); 2581 } 2582 2583 scr_val |= SCSCR_RE | SCSCR_TE | 2584 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2585 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2586 if ((srr + 1 == 5) && 2587 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2588 /* 2589 * In asynchronous mode, when the sampling rate is 1/5, first 2590 * received data may become invalid on some SCIFA and SCIFB. 2591 * To avoid this problem wait more than 1 serial data time (1 2592 * bit time x serial data number) after setting SCSCR.RE = 1. 2593 */ 2594 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2595 } 2596 2597 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2598 s->rx_frame = (10000 * bits) / (baud / 100); 2599 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2600 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2601 #endif 2602 2603 if ((termios->c_cflag & CREAD) != 0) 2604 sci_start_rx(port); 2605 2606 spin_unlock_irqrestore(&port->lock, flags); 2607 2608 sci_port_disable(s); 2609 2610 if (UART_ENABLE_MS(port, termios->c_cflag)) 2611 sci_enable_ms(port); 2612 } 2613 2614 static void sci_pm(struct uart_port *port, unsigned int state, 2615 unsigned int oldstate) 2616 { 2617 struct sci_port *sci_port = to_sci_port(port); 2618 2619 switch (state) { 2620 case UART_PM_STATE_OFF: 2621 sci_port_disable(sci_port); 2622 break; 2623 default: 2624 sci_port_enable(sci_port); 2625 break; 2626 } 2627 } 2628 2629 static const char *sci_type(struct uart_port *port) 2630 { 2631 switch (port->type) { 2632 case PORT_IRDA: 2633 return "irda"; 2634 case PORT_SCI: 2635 return "sci"; 2636 case PORT_SCIF: 2637 return "scif"; 2638 case PORT_SCIFA: 2639 return "scifa"; 2640 case PORT_SCIFB: 2641 return "scifb"; 2642 case PORT_HSCIF: 2643 return "hscif"; 2644 } 2645 2646 return NULL; 2647 } 2648 2649 static int sci_remap_port(struct uart_port *port) 2650 { 2651 struct sci_port *sport = to_sci_port(port); 2652 2653 /* 2654 * Nothing to do if there's already an established membase. 2655 */ 2656 if (port->membase) 2657 return 0; 2658 2659 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2660 port->membase = ioremap(port->mapbase, sport->reg_size); 2661 if (unlikely(!port->membase)) { 2662 dev_err(port->dev, "can't remap port#%d\n", port->line); 2663 return -ENXIO; 2664 } 2665 } else { 2666 /* 2667 * For the simple (and majority of) cases where we don't 2668 * need to do any remapping, just cast the cookie 2669 * directly. 2670 */ 2671 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2672 } 2673 2674 return 0; 2675 } 2676 2677 static void sci_release_port(struct uart_port *port) 2678 { 2679 struct sci_port *sport = to_sci_port(port); 2680 2681 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2682 iounmap(port->membase); 2683 port->membase = NULL; 2684 } 2685 2686 release_mem_region(port->mapbase, sport->reg_size); 2687 } 2688 2689 static int sci_request_port(struct uart_port *port) 2690 { 2691 struct resource *res; 2692 struct sci_port *sport = to_sci_port(port); 2693 int ret; 2694 2695 res = request_mem_region(port->mapbase, sport->reg_size, 2696 dev_name(port->dev)); 2697 if (unlikely(res == NULL)) { 2698 dev_err(port->dev, "request_mem_region failed."); 2699 return -EBUSY; 2700 } 2701 2702 ret = sci_remap_port(port); 2703 if (unlikely(ret != 0)) { 2704 release_resource(res); 2705 return ret; 2706 } 2707 2708 return 0; 2709 } 2710 2711 static void sci_config_port(struct uart_port *port, int flags) 2712 { 2713 if (flags & UART_CONFIG_TYPE) { 2714 struct sci_port *sport = to_sci_port(port); 2715 2716 port->type = sport->cfg->type; 2717 sci_request_port(port); 2718 } 2719 } 2720 2721 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2722 { 2723 if (ser->baud_base < 2400) 2724 /* No paper tape reader for Mitch.. */ 2725 return -EINVAL; 2726 2727 return 0; 2728 } 2729 2730 static const struct uart_ops sci_uart_ops = { 2731 .tx_empty = sci_tx_empty, 2732 .set_mctrl = sci_set_mctrl, 2733 .get_mctrl = sci_get_mctrl, 2734 .start_tx = sci_start_tx, 2735 .stop_tx = sci_stop_tx, 2736 .stop_rx = sci_stop_rx, 2737 .enable_ms = sci_enable_ms, 2738 .break_ctl = sci_break_ctl, 2739 .startup = sci_startup, 2740 .shutdown = sci_shutdown, 2741 .flush_buffer = sci_flush_buffer, 2742 .set_termios = sci_set_termios, 2743 .pm = sci_pm, 2744 .type = sci_type, 2745 .release_port = sci_release_port, 2746 .request_port = sci_request_port, 2747 .config_port = sci_config_port, 2748 .verify_port = sci_verify_port, 2749 #ifdef CONFIG_CONSOLE_POLL 2750 .poll_get_char = sci_poll_get_char, 2751 .poll_put_char = sci_poll_put_char, 2752 #endif 2753 }; 2754 2755 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2756 { 2757 const char *clk_names[] = { 2758 [SCI_FCK] = "fck", 2759 [SCI_SCK] = "sck", 2760 [SCI_BRG_INT] = "brg_int", 2761 [SCI_SCIF_CLK] = "scif_clk", 2762 }; 2763 struct clk *clk; 2764 unsigned int i; 2765 2766 if (sci_port->cfg->type == PORT_HSCIF) 2767 clk_names[SCI_SCK] = "hsck"; 2768 2769 for (i = 0; i < SCI_NUM_CLKS; i++) { 2770 clk = devm_clk_get_optional(dev, clk_names[i]); 2771 if (IS_ERR(clk)) 2772 return PTR_ERR(clk); 2773 2774 if (!clk && i == SCI_FCK) { 2775 /* 2776 * Not all SH platforms declare a clock lookup entry 2777 * for SCI devices, in which case we need to get the 2778 * global "peripheral_clk" clock. 2779 */ 2780 clk = devm_clk_get(dev, "peripheral_clk"); 2781 if (IS_ERR(clk)) 2782 return dev_err_probe(dev, PTR_ERR(clk), 2783 "failed to get %s\n", 2784 clk_names[i]); 2785 } 2786 2787 if (!clk) 2788 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2789 else 2790 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2791 clk, clk_get_rate(clk)); 2792 sci_port->clks[i] = clk; 2793 } 2794 return 0; 2795 } 2796 2797 static const struct sci_port_params * 2798 sci_probe_regmap(const struct plat_sci_port *cfg) 2799 { 2800 unsigned int regtype; 2801 2802 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2803 return &sci_port_params[cfg->regtype]; 2804 2805 switch (cfg->type) { 2806 case PORT_SCI: 2807 regtype = SCIx_SCI_REGTYPE; 2808 break; 2809 case PORT_IRDA: 2810 regtype = SCIx_IRDA_REGTYPE; 2811 break; 2812 case PORT_SCIFA: 2813 regtype = SCIx_SCIFA_REGTYPE; 2814 break; 2815 case PORT_SCIFB: 2816 regtype = SCIx_SCIFB_REGTYPE; 2817 break; 2818 case PORT_SCIF: 2819 /* 2820 * The SH-4 is a bit of a misnomer here, although that's 2821 * where this particular port layout originated. This 2822 * configuration (or some slight variation thereof) 2823 * remains the dominant model for all SCIFs. 2824 */ 2825 regtype = SCIx_SH4_SCIF_REGTYPE; 2826 break; 2827 case PORT_HSCIF: 2828 regtype = SCIx_HSCIF_REGTYPE; 2829 break; 2830 default: 2831 pr_err("Can't probe register map for given port\n"); 2832 return NULL; 2833 } 2834 2835 return &sci_port_params[regtype]; 2836 } 2837 2838 static int sci_init_single(struct platform_device *dev, 2839 struct sci_port *sci_port, unsigned int index, 2840 const struct plat_sci_port *p, bool early) 2841 { 2842 struct uart_port *port = &sci_port->port; 2843 const struct resource *res; 2844 unsigned int i; 2845 int ret; 2846 2847 sci_port->cfg = p; 2848 2849 port->ops = &sci_uart_ops; 2850 port->iotype = UPIO_MEM; 2851 port->line = index; 2852 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2853 2854 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2855 if (res == NULL) 2856 return -ENOMEM; 2857 2858 port->mapbase = res->start; 2859 sci_port->reg_size = resource_size(res); 2860 2861 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2862 if (i) 2863 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2864 else 2865 sci_port->irqs[i] = platform_get_irq(dev, i); 2866 } 2867 2868 /* 2869 * The fourth interrupt on SCI port is transmit end interrupt, so 2870 * shuffle the interrupts. 2871 */ 2872 if (p->type == PORT_SCI) 2873 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 2874 2875 /* The SCI generates several interrupts. They can be muxed together or 2876 * connected to different interrupt lines. In the muxed case only one 2877 * interrupt resource is specified as there is only one interrupt ID. 2878 * In the non-muxed case, up to 6 interrupt signals might be generated 2879 * from the SCI, however those signals might have their own individual 2880 * interrupt ID numbers, or muxed together with another interrupt. 2881 */ 2882 if (sci_port->irqs[0] < 0) 2883 return -ENXIO; 2884 2885 if (sci_port->irqs[1] < 0) 2886 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2887 sci_port->irqs[i] = sci_port->irqs[0]; 2888 2889 sci_port->params = sci_probe_regmap(p); 2890 if (unlikely(sci_port->params == NULL)) 2891 return -EINVAL; 2892 2893 switch (p->type) { 2894 case PORT_SCIFB: 2895 sci_port->rx_trigger = 48; 2896 break; 2897 case PORT_HSCIF: 2898 sci_port->rx_trigger = 64; 2899 break; 2900 case PORT_SCIFA: 2901 sci_port->rx_trigger = 32; 2902 break; 2903 case PORT_SCIF: 2904 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2905 /* RX triggering not implemented for this IP */ 2906 sci_port->rx_trigger = 1; 2907 else 2908 sci_port->rx_trigger = 8; 2909 break; 2910 default: 2911 sci_port->rx_trigger = 1; 2912 break; 2913 } 2914 2915 sci_port->rx_fifo_timeout = 0; 2916 sci_port->hscif_tot = 0; 2917 2918 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2919 * match the SoC datasheet, this should be investigated. Let platform 2920 * data override the sampling rate for now. 2921 */ 2922 sci_port->sampling_rate_mask = p->sampling_rate 2923 ? SCI_SR(p->sampling_rate) 2924 : sci_port->params->sampling_rate_mask; 2925 2926 if (!early) { 2927 ret = sci_init_clocks(sci_port, &dev->dev); 2928 if (ret < 0) 2929 return ret; 2930 2931 port->dev = &dev->dev; 2932 2933 pm_runtime_enable(&dev->dev); 2934 } 2935 2936 port->type = p->type; 2937 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2938 port->fifosize = sci_port->params->fifosize; 2939 2940 if (port->type == PORT_SCI && !dev->dev.of_node) { 2941 if (sci_port->reg_size >= 0x20) 2942 port->regshift = 2; 2943 else 2944 port->regshift = 1; 2945 } 2946 2947 /* 2948 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2949 * for the multi-IRQ ports, which is where we are primarily 2950 * concerned with the shutdown path synchronization. 2951 * 2952 * For the muxed case there's nothing more to do. 2953 */ 2954 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2955 port->irqflags = 0; 2956 2957 port->serial_in = sci_serial_in; 2958 port->serial_out = sci_serial_out; 2959 2960 return 0; 2961 } 2962 2963 static void sci_cleanup_single(struct sci_port *port) 2964 { 2965 pm_runtime_disable(port->port.dev); 2966 } 2967 2968 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2969 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2970 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 2971 { 2972 sci_poll_put_char(port, ch); 2973 } 2974 2975 /* 2976 * Print a string to the serial port trying not to disturb 2977 * any possible real use of the port... 2978 */ 2979 static void serial_console_write(struct console *co, const char *s, 2980 unsigned count) 2981 { 2982 struct sci_port *sci_port = &sci_ports[co->index]; 2983 struct uart_port *port = &sci_port->port; 2984 unsigned short bits, ctrl, ctrl_temp; 2985 unsigned long flags; 2986 int locked = 1; 2987 2988 if (port->sysrq) 2989 locked = 0; 2990 else if (oops_in_progress) 2991 locked = spin_trylock_irqsave(&port->lock, flags); 2992 else 2993 spin_lock_irqsave(&port->lock, flags); 2994 2995 /* first save SCSCR then disable interrupts, keep clock source */ 2996 ctrl = serial_port_in(port, SCSCR); 2997 ctrl_temp = SCSCR_RE | SCSCR_TE | 2998 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2999 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3000 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3001 3002 uart_console_write(port, s, count, serial_console_putchar); 3003 3004 /* wait until fifo is empty and last bit has been transmitted */ 3005 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3006 while ((serial_port_in(port, SCxSR) & bits) != bits) 3007 cpu_relax(); 3008 3009 /* restore the SCSCR */ 3010 serial_port_out(port, SCSCR, ctrl); 3011 3012 if (locked) 3013 spin_unlock_irqrestore(&port->lock, flags); 3014 } 3015 3016 static int serial_console_setup(struct console *co, char *options) 3017 { 3018 struct sci_port *sci_port; 3019 struct uart_port *port; 3020 int baud = 115200; 3021 int bits = 8; 3022 int parity = 'n'; 3023 int flow = 'n'; 3024 int ret; 3025 3026 /* 3027 * Refuse to handle any bogus ports. 3028 */ 3029 if (co->index < 0 || co->index >= SCI_NPORTS) 3030 return -ENODEV; 3031 3032 sci_port = &sci_ports[co->index]; 3033 port = &sci_port->port; 3034 3035 /* 3036 * Refuse to handle uninitialized ports. 3037 */ 3038 if (!port->ops) 3039 return -ENODEV; 3040 3041 ret = sci_remap_port(port); 3042 if (unlikely(ret != 0)) 3043 return ret; 3044 3045 if (options) 3046 uart_parse_options(options, &baud, &parity, &bits, &flow); 3047 3048 return uart_set_options(port, co, baud, parity, bits, flow); 3049 } 3050 3051 static struct console serial_console = { 3052 .name = "ttySC", 3053 .device = uart_console_device, 3054 .write = serial_console_write, 3055 .setup = serial_console_setup, 3056 .flags = CON_PRINTBUFFER, 3057 .index = -1, 3058 .data = &sci_uart_driver, 3059 }; 3060 3061 #ifdef CONFIG_SUPERH 3062 static char early_serial_buf[32]; 3063 3064 static int early_serial_console_setup(struct console *co, char *options) 3065 { 3066 /* 3067 * This early console is always registered using the earlyprintk= 3068 * parameter, which does not call add_preferred_console(). Thus 3069 * @options is always NULL and the options for this early console 3070 * are passed using a custom buffer. 3071 */ 3072 WARN_ON(options); 3073 3074 return serial_console_setup(co, early_serial_buf); 3075 } 3076 3077 static struct console early_serial_console = { 3078 .name = "early_ttySC", 3079 .write = serial_console_write, 3080 .setup = early_serial_console_setup, 3081 .flags = CON_PRINTBUFFER, 3082 .index = -1, 3083 }; 3084 3085 static int sci_probe_earlyprintk(struct platform_device *pdev) 3086 { 3087 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3088 3089 if (early_serial_console.data) 3090 return -EEXIST; 3091 3092 early_serial_console.index = pdev->id; 3093 3094 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3095 3096 if (!strstr(early_serial_buf, "keep")) 3097 early_serial_console.flags |= CON_BOOT; 3098 3099 register_console(&early_serial_console); 3100 return 0; 3101 } 3102 #endif 3103 3104 #define SCI_CONSOLE (&serial_console) 3105 3106 #else 3107 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3108 { 3109 return -EINVAL; 3110 } 3111 3112 #define SCI_CONSOLE NULL 3113 3114 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3115 3116 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3117 3118 static DEFINE_MUTEX(sci_uart_registration_lock); 3119 static struct uart_driver sci_uart_driver = { 3120 .owner = THIS_MODULE, 3121 .driver_name = "sci", 3122 .dev_name = "ttySC", 3123 .major = SCI_MAJOR, 3124 .minor = SCI_MINOR_START, 3125 .nr = SCI_NPORTS, 3126 .cons = SCI_CONSOLE, 3127 }; 3128 3129 static int sci_remove(struct platform_device *dev) 3130 { 3131 struct sci_port *port = platform_get_drvdata(dev); 3132 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3133 3134 sci_ports_in_use &= ~BIT(port->port.line); 3135 uart_remove_one_port(&sci_uart_driver, &port->port); 3136 3137 sci_cleanup_single(port); 3138 3139 if (port->port.fifosize > 1) 3140 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3141 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3142 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3143 3144 return 0; 3145 } 3146 3147 3148 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3149 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3150 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3151 3152 static const struct of_device_id of_sci_match[] = { 3153 /* SoC-specific types */ 3154 { 3155 .compatible = "renesas,scif-r7s72100", 3156 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3157 }, 3158 { 3159 .compatible = "renesas,scif-r7s9210", 3160 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3161 }, 3162 { 3163 .compatible = "renesas,scif-r9a07g044", 3164 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3165 }, 3166 /* Family-specific types */ 3167 { 3168 .compatible = "renesas,rcar-gen1-scif", 3169 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3170 }, { 3171 .compatible = "renesas,rcar-gen2-scif", 3172 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3173 }, { 3174 .compatible = "renesas,rcar-gen3-scif", 3175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3176 }, { 3177 .compatible = "renesas,rcar-gen4-scif", 3178 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3179 }, 3180 /* Generic types */ 3181 { 3182 .compatible = "renesas,scif", 3183 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3184 }, { 3185 .compatible = "renesas,scifa", 3186 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3187 }, { 3188 .compatible = "renesas,scifb", 3189 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3190 }, { 3191 .compatible = "renesas,hscif", 3192 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3193 }, { 3194 .compatible = "renesas,sci", 3195 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3196 }, { 3197 /* Terminator */ 3198 }, 3199 }; 3200 MODULE_DEVICE_TABLE(of, of_sci_match); 3201 3202 static void sci_reset_control_assert(void *data) 3203 { 3204 reset_control_assert(data); 3205 } 3206 3207 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3208 unsigned int *dev_id) 3209 { 3210 struct device_node *np = pdev->dev.of_node; 3211 struct reset_control *rstc; 3212 struct plat_sci_port *p; 3213 struct sci_port *sp; 3214 const void *data; 3215 int id, ret; 3216 3217 if (!IS_ENABLED(CONFIG_OF) || !np) 3218 return ERR_PTR(-EINVAL); 3219 3220 data = of_device_get_match_data(&pdev->dev); 3221 3222 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3223 if (IS_ERR(rstc)) 3224 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3225 "failed to get reset ctrl\n")); 3226 3227 ret = reset_control_deassert(rstc); 3228 if (ret) { 3229 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3230 return ERR_PTR(ret); 3231 } 3232 3233 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3234 if (ret) { 3235 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3236 ret); 3237 return ERR_PTR(ret); 3238 } 3239 3240 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3241 if (!p) 3242 return ERR_PTR(-ENOMEM); 3243 3244 /* Get the line number from the aliases node. */ 3245 id = of_alias_get_id(np, "serial"); 3246 if (id < 0 && ~sci_ports_in_use) 3247 id = ffz(sci_ports_in_use); 3248 if (id < 0) { 3249 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3250 return ERR_PTR(-EINVAL); 3251 } 3252 if (id >= ARRAY_SIZE(sci_ports)) { 3253 dev_err(&pdev->dev, "serial%d out of range\n", id); 3254 return ERR_PTR(-EINVAL); 3255 } 3256 3257 sp = &sci_ports[id]; 3258 *dev_id = id; 3259 3260 p->type = SCI_OF_TYPE(data); 3261 p->regtype = SCI_OF_REGTYPE(data); 3262 3263 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3264 3265 return p; 3266 } 3267 3268 static int sci_probe_single(struct platform_device *dev, 3269 unsigned int index, 3270 struct plat_sci_port *p, 3271 struct sci_port *sciport) 3272 { 3273 int ret; 3274 3275 /* Sanity check */ 3276 if (unlikely(index >= SCI_NPORTS)) { 3277 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3278 index+1, SCI_NPORTS); 3279 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3280 return -EINVAL; 3281 } 3282 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3283 if (sci_ports_in_use & BIT(index)) 3284 return -EBUSY; 3285 3286 mutex_lock(&sci_uart_registration_lock); 3287 if (!sci_uart_driver.state) { 3288 ret = uart_register_driver(&sci_uart_driver); 3289 if (ret) { 3290 mutex_unlock(&sci_uart_registration_lock); 3291 return ret; 3292 } 3293 } 3294 mutex_unlock(&sci_uart_registration_lock); 3295 3296 ret = sci_init_single(dev, sciport, index, p, false); 3297 if (ret) 3298 return ret; 3299 3300 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3301 if (IS_ERR(sciport->gpios)) 3302 return PTR_ERR(sciport->gpios); 3303 3304 if (sciport->has_rtscts) { 3305 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3306 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3307 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3308 return -EINVAL; 3309 } 3310 sciport->port.flags |= UPF_HARD_FLOW; 3311 } 3312 3313 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3314 if (ret) { 3315 sci_cleanup_single(sciport); 3316 return ret; 3317 } 3318 3319 return 0; 3320 } 3321 3322 static int sci_probe(struct platform_device *dev) 3323 { 3324 struct plat_sci_port *p; 3325 struct sci_port *sp; 3326 unsigned int dev_id; 3327 int ret; 3328 3329 /* 3330 * If we've come here via earlyprintk initialization, head off to 3331 * the special early probe. We don't have sufficient device state 3332 * to make it beyond this yet. 3333 */ 3334 #ifdef CONFIG_SUPERH 3335 if (is_sh_early_platform_device(dev)) 3336 return sci_probe_earlyprintk(dev); 3337 #endif 3338 3339 if (dev->dev.of_node) { 3340 p = sci_parse_dt(dev, &dev_id); 3341 if (IS_ERR(p)) 3342 return PTR_ERR(p); 3343 } else { 3344 p = dev->dev.platform_data; 3345 if (p == NULL) { 3346 dev_err(&dev->dev, "no platform data supplied\n"); 3347 return -EINVAL; 3348 } 3349 3350 dev_id = dev->id; 3351 } 3352 3353 sp = &sci_ports[dev_id]; 3354 platform_set_drvdata(dev, sp); 3355 3356 ret = sci_probe_single(dev, dev_id, p, sp); 3357 if (ret) 3358 return ret; 3359 3360 if (sp->port.fifosize > 1) { 3361 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3362 if (ret) 3363 return ret; 3364 } 3365 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3366 sp->port.type == PORT_HSCIF) { 3367 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3368 if (ret) { 3369 if (sp->port.fifosize > 1) { 3370 device_remove_file(&dev->dev, 3371 &dev_attr_rx_fifo_trigger); 3372 } 3373 return ret; 3374 } 3375 } 3376 3377 #ifdef CONFIG_SH_STANDARD_BIOS 3378 sh_bios_gdb_detach(); 3379 #endif 3380 3381 sci_ports_in_use |= BIT(dev_id); 3382 return 0; 3383 } 3384 3385 static __maybe_unused int sci_suspend(struct device *dev) 3386 { 3387 struct sci_port *sport = dev_get_drvdata(dev); 3388 3389 if (sport) 3390 uart_suspend_port(&sci_uart_driver, &sport->port); 3391 3392 return 0; 3393 } 3394 3395 static __maybe_unused int sci_resume(struct device *dev) 3396 { 3397 struct sci_port *sport = dev_get_drvdata(dev); 3398 3399 if (sport) 3400 uart_resume_port(&sci_uart_driver, &sport->port); 3401 3402 return 0; 3403 } 3404 3405 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3406 3407 static struct platform_driver sci_driver = { 3408 .probe = sci_probe, 3409 .remove = sci_remove, 3410 .driver = { 3411 .name = "sh-sci", 3412 .pm = &sci_dev_pm_ops, 3413 .of_match_table = of_match_ptr(of_sci_match), 3414 }, 3415 }; 3416 3417 static int __init sci_init(void) 3418 { 3419 pr_info("%s\n", banner); 3420 3421 return platform_driver_register(&sci_driver); 3422 } 3423 3424 static void __exit sci_exit(void) 3425 { 3426 platform_driver_unregister(&sci_driver); 3427 3428 if (sci_uart_driver.state) 3429 uart_unregister_driver(&sci_uart_driver); 3430 } 3431 3432 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3433 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3434 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3435 #endif 3436 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3437 static struct plat_sci_port port_cfg __initdata; 3438 3439 static int __init early_console_setup(struct earlycon_device *device, 3440 int type) 3441 { 3442 if (!device->port.membase) 3443 return -ENODEV; 3444 3445 device->port.serial_in = sci_serial_in; 3446 device->port.serial_out = sci_serial_out; 3447 device->port.type = type; 3448 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3449 port_cfg.type = type; 3450 sci_ports[0].cfg = &port_cfg; 3451 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3452 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3453 sci_serial_out(&sci_ports[0].port, SCSCR, 3454 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3455 3456 device->con->write = serial_console_write; 3457 return 0; 3458 } 3459 static int __init sci_early_console_setup(struct earlycon_device *device, 3460 const char *opt) 3461 { 3462 return early_console_setup(device, PORT_SCI); 3463 } 3464 static int __init scif_early_console_setup(struct earlycon_device *device, 3465 const char *opt) 3466 { 3467 return early_console_setup(device, PORT_SCIF); 3468 } 3469 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3470 const char *opt) 3471 { 3472 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3473 return early_console_setup(device, PORT_SCIF); 3474 } 3475 3476 static int __init scifa_early_console_setup(struct earlycon_device *device, 3477 const char *opt) 3478 { 3479 return early_console_setup(device, PORT_SCIFA); 3480 } 3481 static int __init scifb_early_console_setup(struct earlycon_device *device, 3482 const char *opt) 3483 { 3484 return early_console_setup(device, PORT_SCIFB); 3485 } 3486 static int __init hscif_early_console_setup(struct earlycon_device *device, 3487 const char *opt) 3488 { 3489 return early_console_setup(device, PORT_HSCIF); 3490 } 3491 3492 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3493 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3494 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3495 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3496 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3497 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3498 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3499 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3500 3501 module_init(sci_init); 3502 module_exit(sci_exit); 3503 3504 MODULE_LICENSE("GPL"); 3505 MODULE_ALIAS("platform:sh-sci"); 3506 MODULE_AUTHOR("Paul Mundt"); 3507 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3508