1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/module.h> 35 #include <linux/mm.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 }; 161 162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164 static struct sci_port sci_ports[SCI_NPORTS]; 165 static unsigned long sci_ports_in_use; 166 static struct uart_driver sci_uart_driver; 167 168 static inline struct sci_port * 169 to_sci_port(struct uart_port *uart) 170 { 171 return container_of(uart, struct sci_port, port); 172 } 173 174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * Common SH-3 SCIF definitions. 322 */ 323 [SCIx_SH3_SCIF_REGTYPE] = { 324 .regs = { 325 [SCSMR] = { 0x00, 8 }, 326 [SCBRR] = { 0x02, 8 }, 327 [SCSCR] = { 0x04, 8 }, 328 [SCxTDR] = { 0x06, 8 }, 329 [SCxSR] = { 0x08, 16 }, 330 [SCxRDR] = { 0x0a, 8 }, 331 [SCFCR] = { 0x0c, 8 }, 332 [SCFDR] = { 0x0e, 16 }, 333 }, 334 .fifosize = 16, 335 .overrun_reg = SCLSR, 336 .overrun_mask = SCLSR_ORER, 337 .sampling_rate_mask = SCI_SR(32), 338 .error_mask = SCIF_DEFAULT_ERROR_MASK, 339 .error_clear = SCIF_ERROR_CLEAR, 340 }, 341 342 /* 343 * Common SH-4(A) SCIF(B) definitions. 344 */ 345 [SCIx_SH4_SCIF_REGTYPE] = { 346 .regs = { 347 [SCSMR] = { 0x00, 16 }, 348 [SCBRR] = { 0x04, 8 }, 349 [SCSCR] = { 0x08, 16 }, 350 [SCxTDR] = { 0x0c, 8 }, 351 [SCxSR] = { 0x10, 16 }, 352 [SCxRDR] = { 0x14, 8 }, 353 [SCFCR] = { 0x18, 16 }, 354 [SCFDR] = { 0x1c, 16 }, 355 [SCSPTR] = { 0x20, 16 }, 356 [SCLSR] = { 0x24, 16 }, 357 }, 358 .fifosize = 16, 359 .overrun_reg = SCLSR, 360 .overrun_mask = SCLSR_ORER, 361 .sampling_rate_mask = SCI_SR(32), 362 .error_mask = SCIF_DEFAULT_ERROR_MASK, 363 .error_clear = SCIF_ERROR_CLEAR, 364 }, 365 366 /* 367 * Common SCIF definitions for ports with a Baud Rate Generator for 368 * External Clock (BRG). 369 */ 370 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 371 .regs = { 372 [SCSMR] = { 0x00, 16 }, 373 [SCBRR] = { 0x04, 8 }, 374 [SCSCR] = { 0x08, 16 }, 375 [SCxTDR] = { 0x0c, 8 }, 376 [SCxSR] = { 0x10, 16 }, 377 [SCxRDR] = { 0x14, 8 }, 378 [SCFCR] = { 0x18, 16 }, 379 [SCFDR] = { 0x1c, 16 }, 380 [SCSPTR] = { 0x20, 16 }, 381 [SCLSR] = { 0x24, 16 }, 382 [SCDL] = { 0x30, 16 }, 383 [SCCKS] = { 0x34, 16 }, 384 }, 385 .fifosize = 16, 386 .overrun_reg = SCLSR, 387 .overrun_mask = SCLSR_ORER, 388 .sampling_rate_mask = SCI_SR(32), 389 .error_mask = SCIF_DEFAULT_ERROR_MASK, 390 .error_clear = SCIF_ERROR_CLEAR, 391 }, 392 393 /* 394 * Common HSCIF definitions. 395 */ 396 [SCIx_HSCIF_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCSPTR] = { 0x20, 16 }, 407 [SCLSR] = { 0x24, 16 }, 408 [HSSRR] = { 0x40, 16 }, 409 [SCDL] = { 0x30, 16 }, 410 [SCCKS] = { 0x34, 16 }, 411 [HSRTRGR] = { 0x54, 16 }, 412 [HSTTRGR] = { 0x58, 16 }, 413 }, 414 .fifosize = 128, 415 .overrun_reg = SCLSR, 416 .overrun_mask = SCLSR_ORER, 417 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 418 .error_mask = SCIF_DEFAULT_ERROR_MASK, 419 .error_clear = SCIF_ERROR_CLEAR, 420 }, 421 422 /* 423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 424 * register. 425 */ 426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 427 .regs = { 428 [SCSMR] = { 0x00, 16 }, 429 [SCBRR] = { 0x04, 8 }, 430 [SCSCR] = { 0x08, 16 }, 431 [SCxTDR] = { 0x0c, 8 }, 432 [SCxSR] = { 0x10, 16 }, 433 [SCxRDR] = { 0x14, 8 }, 434 [SCFCR] = { 0x18, 16 }, 435 [SCFDR] = { 0x1c, 16 }, 436 [SCLSR] = { 0x24, 16 }, 437 }, 438 .fifosize = 16, 439 .overrun_reg = SCLSR, 440 .overrun_mask = SCLSR_ORER, 441 .sampling_rate_mask = SCI_SR(32), 442 .error_mask = SCIF_DEFAULT_ERROR_MASK, 443 .error_clear = SCIF_ERROR_CLEAR, 444 }, 445 446 /* 447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 448 * count registers. 449 */ 450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 451 .regs = { 452 [SCSMR] = { 0x00, 16 }, 453 [SCBRR] = { 0x04, 8 }, 454 [SCSCR] = { 0x08, 16 }, 455 [SCxTDR] = { 0x0c, 8 }, 456 [SCxSR] = { 0x10, 16 }, 457 [SCxRDR] = { 0x14, 8 }, 458 [SCFCR] = { 0x18, 16 }, 459 [SCFDR] = { 0x1c, 16 }, 460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 461 [SCRFDR] = { 0x20, 16 }, 462 [SCSPTR] = { 0x24, 16 }, 463 [SCLSR] = { 0x28, 16 }, 464 }, 465 .fifosize = 16, 466 .overrun_reg = SCLSR, 467 .overrun_mask = SCLSR_ORER, 468 .sampling_rate_mask = SCI_SR(32), 469 .error_mask = SCIF_DEFAULT_ERROR_MASK, 470 .error_clear = SCIF_ERROR_CLEAR, 471 }, 472 473 /* 474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 475 * registers. 476 */ 477 [SCIx_SH7705_SCIF_REGTYPE] = { 478 .regs = { 479 [SCSMR] = { 0x00, 16 }, 480 [SCBRR] = { 0x04, 8 }, 481 [SCSCR] = { 0x08, 16 }, 482 [SCxTDR] = { 0x20, 8 }, 483 [SCxSR] = { 0x14, 16 }, 484 [SCxRDR] = { 0x24, 8 }, 485 [SCFCR] = { 0x18, 16 }, 486 [SCFDR] = { 0x1c, 16 }, 487 }, 488 .fifosize = 64, 489 .overrun_reg = SCxSR, 490 .overrun_mask = SCIFA_ORER, 491 .sampling_rate_mask = SCI_SR(16), 492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 494 }, 495 }; 496 497 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 498 499 /* 500 * The "offset" here is rather misleading, in that it refers to an enum 501 * value relative to the port mapping rather than the fixed offset 502 * itself, which needs to be manually retrieved from the platform's 503 * register map for the given port. 504 */ 505 static unsigned int sci_serial_in(struct uart_port *p, int offset) 506 { 507 const struct plat_sci_reg *reg = sci_getreg(p, offset); 508 509 if (reg->size == 8) 510 return ioread8(p->membase + (reg->offset << p->regshift)); 511 else if (reg->size == 16) 512 return ioread16(p->membase + (reg->offset << p->regshift)); 513 else 514 WARN(1, "Invalid register access\n"); 515 516 return 0; 517 } 518 519 static void sci_serial_out(struct uart_port *p, int offset, int value) 520 { 521 const struct plat_sci_reg *reg = sci_getreg(p, offset); 522 523 if (reg->size == 8) 524 iowrite8(value, p->membase + (reg->offset << p->regshift)); 525 else if (reg->size == 16) 526 iowrite16(value, p->membase + (reg->offset << p->regshift)); 527 else 528 WARN(1, "Invalid register access\n"); 529 } 530 531 static void sci_port_enable(struct sci_port *sci_port) 532 { 533 unsigned int i; 534 535 if (!sci_port->port.dev) 536 return; 537 538 pm_runtime_get_sync(sci_port->port.dev); 539 540 for (i = 0; i < SCI_NUM_CLKS; i++) { 541 clk_prepare_enable(sci_port->clks[i]); 542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 543 } 544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 545 } 546 547 static void sci_port_disable(struct sci_port *sci_port) 548 { 549 unsigned int i; 550 551 if (!sci_port->port.dev) 552 return; 553 554 for (i = SCI_NUM_CLKS; i-- > 0; ) 555 clk_disable_unprepare(sci_port->clks[i]); 556 557 pm_runtime_put_sync(sci_port->port.dev); 558 } 559 560 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 561 { 562 /* 563 * Not all ports (such as SCIFA) will support REIE. Rather than 564 * special-casing the port type, we check the port initialization 565 * IRQ enable mask to see whether the IRQ is desired at all. If 566 * it's unset, it's logically inferred that there's no point in 567 * testing for it. 568 */ 569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 570 } 571 572 static void sci_start_tx(struct uart_port *port) 573 { 574 struct sci_port *s = to_sci_port(port); 575 unsigned short ctrl; 576 577 #ifdef CONFIG_SERIAL_SH_SCI_DMA 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 579 u16 new, scr = serial_port_in(port, SCSCR); 580 if (s->chan_tx) 581 new = scr | SCSCR_TDRQE; 582 else 583 new = scr & ~SCSCR_TDRQE; 584 if (new != scr) 585 serial_port_out(port, SCSCR, new); 586 } 587 588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 589 dma_submit_error(s->cookie_tx)) { 590 s->cookie_tx = 0; 591 schedule_work(&s->work_tx); 592 } 593 #endif 594 595 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 596 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 597 ctrl = serial_port_in(port, SCSCR); 598 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 599 } 600 } 601 602 static void sci_stop_tx(struct uart_port *port) 603 { 604 unsigned short ctrl; 605 606 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 607 ctrl = serial_port_in(port, SCSCR); 608 609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 610 ctrl &= ~SCSCR_TDRQE; 611 612 ctrl &= ~SCSCR_TIE; 613 614 serial_port_out(port, SCSCR, ctrl); 615 616 #ifdef CONFIG_SERIAL_SH_SCI_DMA 617 if (to_sci_port(port)->chan_tx && 618 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 619 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 620 to_sci_port(port)->cookie_tx = -EINVAL; 621 } 622 #endif 623 } 624 625 static void sci_start_rx(struct uart_port *port) 626 { 627 unsigned short ctrl; 628 629 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 630 631 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 632 ctrl &= ~SCSCR_RDRQE; 633 634 serial_port_out(port, SCSCR, ctrl); 635 } 636 637 static void sci_stop_rx(struct uart_port *port) 638 { 639 unsigned short ctrl; 640 641 ctrl = serial_port_in(port, SCSCR); 642 643 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 644 ctrl &= ~SCSCR_RDRQE; 645 646 ctrl &= ~port_rx_irq_mask(port); 647 648 serial_port_out(port, SCSCR, ctrl); 649 } 650 651 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 652 { 653 if (port->type == PORT_SCI) { 654 /* Just store the mask */ 655 serial_port_out(port, SCxSR, mask); 656 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 657 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 658 /* Only clear the status bits we want to clear */ 659 serial_port_out(port, SCxSR, 660 serial_port_in(port, SCxSR) & mask); 661 } else { 662 /* Store the mask, clear parity/framing errors */ 663 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 664 } 665 } 666 667 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 668 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 669 670 #ifdef CONFIG_CONSOLE_POLL 671 static int sci_poll_get_char(struct uart_port *port) 672 { 673 unsigned short status; 674 int c; 675 676 do { 677 status = serial_port_in(port, SCxSR); 678 if (status & SCxSR_ERRORS(port)) { 679 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 680 continue; 681 } 682 break; 683 } while (1); 684 685 if (!(status & SCxSR_RDxF(port))) 686 return NO_POLL_CHAR; 687 688 c = serial_port_in(port, SCxRDR); 689 690 /* Dummy read */ 691 serial_port_in(port, SCxSR); 692 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 693 694 return c; 695 } 696 #endif 697 698 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 699 { 700 unsigned short status; 701 702 do { 703 status = serial_port_in(port, SCxSR); 704 } while (!(status & SCxSR_TDxE(port))); 705 706 serial_port_out(port, SCxTDR, c); 707 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 708 } 709 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 710 CONFIG_SERIAL_SH_SCI_EARLYCON */ 711 712 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 713 { 714 struct sci_port *s = to_sci_port(port); 715 716 /* 717 * Use port-specific handler if provided. 718 */ 719 if (s->cfg->ops && s->cfg->ops->init_pins) { 720 s->cfg->ops->init_pins(port, cflag); 721 return; 722 } 723 724 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 725 u16 data = serial_port_in(port, SCPDR); 726 u16 ctrl = serial_port_in(port, SCPCR); 727 728 /* Enable RXD and TXD pin functions */ 729 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 730 if (to_sci_port(port)->has_rtscts) { 731 /* RTS# is output, active low, unless autorts */ 732 if (!(port->mctrl & TIOCM_RTS)) { 733 ctrl |= SCPCR_RTSC; 734 data |= SCPDR_RTSD; 735 } else if (!s->autorts) { 736 ctrl |= SCPCR_RTSC; 737 data &= ~SCPDR_RTSD; 738 } else { 739 /* Enable RTS# pin function */ 740 ctrl &= ~SCPCR_RTSC; 741 } 742 /* Enable CTS# pin function */ 743 ctrl &= ~SCPCR_CTSC; 744 } 745 serial_port_out(port, SCPDR, data); 746 serial_port_out(port, SCPCR, ctrl); 747 } else if (sci_getreg(port, SCSPTR)->size) { 748 u16 status = serial_port_in(port, SCSPTR); 749 750 /* RTS# is always output; and active low, unless autorts */ 751 status |= SCSPTR_RTSIO; 752 if (!(port->mctrl & TIOCM_RTS)) 753 status |= SCSPTR_RTSDT; 754 else if (!s->autorts) 755 status &= ~SCSPTR_RTSDT; 756 /* CTS# and SCK are inputs */ 757 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 758 serial_port_out(port, SCSPTR, status); 759 } 760 } 761 762 static int sci_txfill(struct uart_port *port) 763 { 764 struct sci_port *s = to_sci_port(port); 765 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 766 const struct plat_sci_reg *reg; 767 768 reg = sci_getreg(port, SCTFDR); 769 if (reg->size) 770 return serial_port_in(port, SCTFDR) & fifo_mask; 771 772 reg = sci_getreg(port, SCFDR); 773 if (reg->size) 774 return serial_port_in(port, SCFDR) >> 8; 775 776 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 777 } 778 779 static int sci_txroom(struct uart_port *port) 780 { 781 return port->fifosize - sci_txfill(port); 782 } 783 784 static int sci_rxfill(struct uart_port *port) 785 { 786 struct sci_port *s = to_sci_port(port); 787 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 788 const struct plat_sci_reg *reg; 789 790 reg = sci_getreg(port, SCRFDR); 791 if (reg->size) 792 return serial_port_in(port, SCRFDR) & fifo_mask; 793 794 reg = sci_getreg(port, SCFDR); 795 if (reg->size) 796 return serial_port_in(port, SCFDR) & fifo_mask; 797 798 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 799 } 800 801 /* ********************************************************************** * 802 * the interrupt related routines * 803 * ********************************************************************** */ 804 805 static void sci_transmit_chars(struct uart_port *port) 806 { 807 struct circ_buf *xmit = &port->state->xmit; 808 unsigned int stopped = uart_tx_stopped(port); 809 unsigned short status; 810 unsigned short ctrl; 811 int count; 812 813 status = serial_port_in(port, SCxSR); 814 if (!(status & SCxSR_TDxE(port))) { 815 ctrl = serial_port_in(port, SCSCR); 816 if (uart_circ_empty(xmit)) 817 ctrl &= ~SCSCR_TIE; 818 else 819 ctrl |= SCSCR_TIE; 820 serial_port_out(port, SCSCR, ctrl); 821 return; 822 } 823 824 count = sci_txroom(port); 825 826 do { 827 unsigned char c; 828 829 if (port->x_char) { 830 c = port->x_char; 831 port->x_char = 0; 832 } else if (!uart_circ_empty(xmit) && !stopped) { 833 c = xmit->buf[xmit->tail]; 834 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 835 } else { 836 break; 837 } 838 839 serial_port_out(port, SCxTDR, c); 840 841 port->icount.tx++; 842 } while (--count > 0); 843 844 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 845 846 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 847 uart_write_wakeup(port); 848 if (uart_circ_empty(xmit)) 849 sci_stop_tx(port); 850 851 } 852 853 static void sci_receive_chars(struct uart_port *port) 854 { 855 struct tty_port *tport = &port->state->port; 856 int i, count, copied = 0; 857 unsigned short status; 858 unsigned char flag; 859 860 status = serial_port_in(port, SCxSR); 861 if (!(status & SCxSR_RDxF(port))) 862 return; 863 864 while (1) { 865 /* Don't copy more bytes than there is room for in the buffer */ 866 count = tty_buffer_request_room(tport, sci_rxfill(port)); 867 868 /* If for any reason we can't copy more data, we're done! */ 869 if (count == 0) 870 break; 871 872 if (port->type == PORT_SCI) { 873 char c = serial_port_in(port, SCxRDR); 874 if (uart_handle_sysrq_char(port, c)) 875 count = 0; 876 else 877 tty_insert_flip_char(tport, c, TTY_NORMAL); 878 } else { 879 for (i = 0; i < count; i++) { 880 char c; 881 882 if (port->type == PORT_SCIF || 883 port->type == PORT_HSCIF) { 884 status = serial_port_in(port, SCxSR); 885 c = serial_port_in(port, SCxRDR); 886 } else { 887 c = serial_port_in(port, SCxRDR); 888 status = serial_port_in(port, SCxSR); 889 } 890 if (uart_handle_sysrq_char(port, c)) { 891 count--; i--; 892 continue; 893 } 894 895 /* Store data and status */ 896 if (status & SCxSR_FER(port)) { 897 flag = TTY_FRAME; 898 port->icount.frame++; 899 } else if (status & SCxSR_PER(port)) { 900 flag = TTY_PARITY; 901 port->icount.parity++; 902 } else 903 flag = TTY_NORMAL; 904 905 tty_insert_flip_char(tport, c, flag); 906 } 907 } 908 909 serial_port_in(port, SCxSR); /* dummy read */ 910 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 911 912 copied += count; 913 port->icount.rx += count; 914 } 915 916 if (copied) { 917 /* Tell the rest of the system the news. New characters! */ 918 tty_flip_buffer_push(tport); 919 } else { 920 /* TTY buffers full; read from RX reg to prevent lockup */ 921 serial_port_in(port, SCxRDR); 922 serial_port_in(port, SCxSR); /* dummy read */ 923 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 924 } 925 } 926 927 static int sci_handle_errors(struct uart_port *port) 928 { 929 int copied = 0; 930 unsigned short status = serial_port_in(port, SCxSR); 931 struct tty_port *tport = &port->state->port; 932 struct sci_port *s = to_sci_port(port); 933 934 /* Handle overruns */ 935 if (status & s->params->overrun_mask) { 936 port->icount.overrun++; 937 938 /* overrun error */ 939 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 940 copied++; 941 } 942 943 if (status & SCxSR_FER(port)) { 944 /* frame error */ 945 port->icount.frame++; 946 947 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 948 copied++; 949 } 950 951 if (status & SCxSR_PER(port)) { 952 /* parity error */ 953 port->icount.parity++; 954 955 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 956 copied++; 957 } 958 959 if (copied) 960 tty_flip_buffer_push(tport); 961 962 return copied; 963 } 964 965 static int sci_handle_fifo_overrun(struct uart_port *port) 966 { 967 struct tty_port *tport = &port->state->port; 968 struct sci_port *s = to_sci_port(port); 969 const struct plat_sci_reg *reg; 970 int copied = 0; 971 u16 status; 972 973 reg = sci_getreg(port, s->params->overrun_reg); 974 if (!reg->size) 975 return 0; 976 977 status = serial_port_in(port, s->params->overrun_reg); 978 if (status & s->params->overrun_mask) { 979 status &= ~s->params->overrun_mask; 980 serial_port_out(port, s->params->overrun_reg, status); 981 982 port->icount.overrun++; 983 984 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 985 tty_flip_buffer_push(tport); 986 copied++; 987 } 988 989 return copied; 990 } 991 992 static int sci_handle_breaks(struct uart_port *port) 993 { 994 int copied = 0; 995 unsigned short status = serial_port_in(port, SCxSR); 996 struct tty_port *tport = &port->state->port; 997 998 if (uart_handle_break(port)) 999 return 0; 1000 1001 if (status & SCxSR_BRK(port)) { 1002 port->icount.brk++; 1003 1004 /* Notify of BREAK */ 1005 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1006 copied++; 1007 } 1008 1009 if (copied) 1010 tty_flip_buffer_push(tport); 1011 1012 copied += sci_handle_fifo_overrun(port); 1013 1014 return copied; 1015 } 1016 1017 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1018 { 1019 unsigned int bits; 1020 1021 if (rx_trig >= port->fifosize) 1022 rx_trig = port->fifosize - 1; 1023 if (rx_trig < 1) 1024 rx_trig = 1; 1025 1026 /* HSCIF can be set to an arbitrary level. */ 1027 if (sci_getreg(port, HSRTRGR)->size) { 1028 serial_port_out(port, HSRTRGR, rx_trig); 1029 return rx_trig; 1030 } 1031 1032 switch (port->type) { 1033 case PORT_SCIF: 1034 if (rx_trig < 4) { 1035 bits = 0; 1036 rx_trig = 1; 1037 } else if (rx_trig < 8) { 1038 bits = SCFCR_RTRG0; 1039 rx_trig = 4; 1040 } else if (rx_trig < 14) { 1041 bits = SCFCR_RTRG1; 1042 rx_trig = 8; 1043 } else { 1044 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1045 rx_trig = 14; 1046 } 1047 break; 1048 case PORT_SCIFA: 1049 case PORT_SCIFB: 1050 if (rx_trig < 16) { 1051 bits = 0; 1052 rx_trig = 1; 1053 } else if (rx_trig < 32) { 1054 bits = SCFCR_RTRG0; 1055 rx_trig = 16; 1056 } else if (rx_trig < 48) { 1057 bits = SCFCR_RTRG1; 1058 rx_trig = 32; 1059 } else { 1060 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1061 rx_trig = 48; 1062 } 1063 break; 1064 default: 1065 WARN(1, "unknown FIFO configuration"); 1066 return 1; 1067 } 1068 1069 serial_port_out(port, SCFCR, 1070 (serial_port_in(port, SCFCR) & 1071 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1072 1073 return rx_trig; 1074 } 1075 1076 static int scif_rtrg_enabled(struct uart_port *port) 1077 { 1078 if (sci_getreg(port, HSRTRGR)->size) 1079 return serial_port_in(port, HSRTRGR) != 0; 1080 else 1081 return (serial_port_in(port, SCFCR) & 1082 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1083 } 1084 1085 static void rx_fifo_timer_fn(struct timer_list *t) 1086 { 1087 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1088 struct uart_port *port = &s->port; 1089 1090 dev_dbg(port->dev, "Rx timed out\n"); 1091 scif_set_rtrg(port, 1); 1092 } 1093 1094 static ssize_t rx_fifo_trigger_show(struct device *dev, 1095 struct device_attribute *attr, char *buf) 1096 { 1097 struct uart_port *port = dev_get_drvdata(dev); 1098 struct sci_port *sci = to_sci_port(port); 1099 1100 return sprintf(buf, "%d\n", sci->rx_trigger); 1101 } 1102 1103 static ssize_t rx_fifo_trigger_store(struct device *dev, 1104 struct device_attribute *attr, 1105 const char *buf, size_t count) 1106 { 1107 struct uart_port *port = dev_get_drvdata(dev); 1108 struct sci_port *sci = to_sci_port(port); 1109 int ret; 1110 long r; 1111 1112 ret = kstrtol(buf, 0, &r); 1113 if (ret) 1114 return ret; 1115 1116 sci->rx_trigger = scif_set_rtrg(port, r); 1117 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1118 scif_set_rtrg(port, 1); 1119 1120 return count; 1121 } 1122 1123 static DEVICE_ATTR_RW(rx_fifo_trigger); 1124 1125 static ssize_t rx_fifo_timeout_show(struct device *dev, 1126 struct device_attribute *attr, 1127 char *buf) 1128 { 1129 struct uart_port *port = dev_get_drvdata(dev); 1130 struct sci_port *sci = to_sci_port(port); 1131 int v; 1132 1133 if (port->type == PORT_HSCIF) 1134 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1135 else 1136 v = sci->rx_fifo_timeout; 1137 1138 return sprintf(buf, "%d\n", v); 1139 } 1140 1141 static ssize_t rx_fifo_timeout_store(struct device *dev, 1142 struct device_attribute *attr, 1143 const char *buf, 1144 size_t count) 1145 { 1146 struct uart_port *port = dev_get_drvdata(dev); 1147 struct sci_port *sci = to_sci_port(port); 1148 int ret; 1149 long r; 1150 1151 ret = kstrtol(buf, 0, &r); 1152 if (ret) 1153 return ret; 1154 1155 if (port->type == PORT_HSCIF) { 1156 if (r < 0 || r > 3) 1157 return -EINVAL; 1158 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1159 } else { 1160 sci->rx_fifo_timeout = r; 1161 scif_set_rtrg(port, 1); 1162 if (r > 0) 1163 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1164 } 1165 1166 return count; 1167 } 1168 1169 static DEVICE_ATTR_RW(rx_fifo_timeout); 1170 1171 1172 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1173 static void sci_dma_tx_complete(void *arg) 1174 { 1175 struct sci_port *s = arg; 1176 struct uart_port *port = &s->port; 1177 struct circ_buf *xmit = &port->state->xmit; 1178 unsigned long flags; 1179 1180 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1181 1182 spin_lock_irqsave(&port->lock, flags); 1183 1184 uart_xmit_advance(port, s->tx_dma_len); 1185 1186 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1187 uart_write_wakeup(port); 1188 1189 if (!uart_circ_empty(xmit)) { 1190 s->cookie_tx = 0; 1191 schedule_work(&s->work_tx); 1192 } else { 1193 s->cookie_tx = -EINVAL; 1194 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1195 u16 ctrl = serial_port_in(port, SCSCR); 1196 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1197 } 1198 } 1199 1200 spin_unlock_irqrestore(&port->lock, flags); 1201 } 1202 1203 /* Locking: called with port lock held */ 1204 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1205 { 1206 struct uart_port *port = &s->port; 1207 struct tty_port *tport = &port->state->port; 1208 int copied; 1209 1210 copied = tty_insert_flip_string(tport, buf, count); 1211 if (copied < count) 1212 port->icount.buf_overrun++; 1213 1214 port->icount.rx += copied; 1215 1216 return copied; 1217 } 1218 1219 static int sci_dma_rx_find_active(struct sci_port *s) 1220 { 1221 unsigned int i; 1222 1223 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1224 if (s->active_rx == s->cookie_rx[i]) 1225 return i; 1226 1227 return -1; 1228 } 1229 1230 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1231 { 1232 unsigned int i; 1233 1234 s->chan_rx = NULL; 1235 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1236 s->cookie_rx[i] = -EINVAL; 1237 s->active_rx = 0; 1238 } 1239 1240 static void sci_dma_rx_release(struct sci_port *s) 1241 { 1242 struct dma_chan *chan = s->chan_rx_saved; 1243 1244 s->chan_rx_saved = NULL; 1245 sci_dma_rx_chan_invalidate(s); 1246 dmaengine_terminate_sync(chan); 1247 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1248 sg_dma_address(&s->sg_rx[0])); 1249 dma_release_channel(chan); 1250 } 1251 1252 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1253 { 1254 long sec = usec / 1000000; 1255 long nsec = (usec % 1000000) * 1000; 1256 ktime_t t = ktime_set(sec, nsec); 1257 1258 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1259 } 1260 1261 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1262 { 1263 struct uart_port *port = &s->port; 1264 u16 scr; 1265 1266 /* Direct new serial port interrupts back to CPU */ 1267 scr = serial_port_in(port, SCSCR); 1268 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1269 scr &= ~SCSCR_RDRQE; 1270 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1271 } 1272 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1273 } 1274 1275 static void sci_dma_rx_complete(void *arg) 1276 { 1277 struct sci_port *s = arg; 1278 struct dma_chan *chan = s->chan_rx; 1279 struct uart_port *port = &s->port; 1280 struct dma_async_tx_descriptor *desc; 1281 unsigned long flags; 1282 int active, count = 0; 1283 1284 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1285 s->active_rx); 1286 1287 spin_lock_irqsave(&port->lock, flags); 1288 1289 active = sci_dma_rx_find_active(s); 1290 if (active >= 0) 1291 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1292 1293 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1294 1295 if (count) 1296 tty_flip_buffer_push(&port->state->port); 1297 1298 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1299 DMA_DEV_TO_MEM, 1300 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1301 if (!desc) 1302 goto fail; 1303 1304 desc->callback = sci_dma_rx_complete; 1305 desc->callback_param = s; 1306 s->cookie_rx[active] = dmaengine_submit(desc); 1307 if (dma_submit_error(s->cookie_rx[active])) 1308 goto fail; 1309 1310 s->active_rx = s->cookie_rx[!active]; 1311 1312 dma_async_issue_pending(chan); 1313 1314 spin_unlock_irqrestore(&port->lock, flags); 1315 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1316 __func__, s->cookie_rx[active], active, s->active_rx); 1317 return; 1318 1319 fail: 1320 spin_unlock_irqrestore(&port->lock, flags); 1321 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1322 /* Switch to PIO */ 1323 spin_lock_irqsave(&port->lock, flags); 1324 dmaengine_terminate_async(chan); 1325 sci_dma_rx_chan_invalidate(s); 1326 sci_dma_rx_reenable_irq(s); 1327 spin_unlock_irqrestore(&port->lock, flags); 1328 } 1329 1330 static void sci_dma_tx_release(struct sci_port *s) 1331 { 1332 struct dma_chan *chan = s->chan_tx_saved; 1333 1334 cancel_work_sync(&s->work_tx); 1335 s->chan_tx_saved = s->chan_tx = NULL; 1336 s->cookie_tx = -EINVAL; 1337 dmaengine_terminate_sync(chan); 1338 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1339 DMA_TO_DEVICE); 1340 dma_release_channel(chan); 1341 } 1342 1343 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1344 { 1345 struct dma_chan *chan = s->chan_rx; 1346 struct uart_port *port = &s->port; 1347 unsigned long flags; 1348 int i; 1349 1350 for (i = 0; i < 2; i++) { 1351 struct scatterlist *sg = &s->sg_rx[i]; 1352 struct dma_async_tx_descriptor *desc; 1353 1354 desc = dmaengine_prep_slave_sg(chan, 1355 sg, 1, DMA_DEV_TO_MEM, 1356 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1357 if (!desc) 1358 goto fail; 1359 1360 desc->callback = sci_dma_rx_complete; 1361 desc->callback_param = s; 1362 s->cookie_rx[i] = dmaengine_submit(desc); 1363 if (dma_submit_error(s->cookie_rx[i])) 1364 goto fail; 1365 1366 } 1367 1368 s->active_rx = s->cookie_rx[0]; 1369 1370 dma_async_issue_pending(chan); 1371 return 0; 1372 1373 fail: 1374 /* Switch to PIO */ 1375 if (!port_lock_held) 1376 spin_lock_irqsave(&port->lock, flags); 1377 if (i) 1378 dmaengine_terminate_async(chan); 1379 sci_dma_rx_chan_invalidate(s); 1380 sci_start_rx(port); 1381 if (!port_lock_held) 1382 spin_unlock_irqrestore(&port->lock, flags); 1383 return -EAGAIN; 1384 } 1385 1386 static void sci_dma_tx_work_fn(struct work_struct *work) 1387 { 1388 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1389 struct dma_async_tx_descriptor *desc; 1390 struct dma_chan *chan = s->chan_tx; 1391 struct uart_port *port = &s->port; 1392 struct circ_buf *xmit = &port->state->xmit; 1393 unsigned long flags; 1394 dma_addr_t buf; 1395 int head, tail; 1396 1397 /* 1398 * DMA is idle now. 1399 * Port xmit buffer is already mapped, and it is one page... Just adjust 1400 * offsets and lengths. Since it is a circular buffer, we have to 1401 * transmit till the end, and then the rest. Take the port lock to get a 1402 * consistent xmit buffer state. 1403 */ 1404 spin_lock_irq(&port->lock); 1405 head = xmit->head; 1406 tail = xmit->tail; 1407 buf = s->tx_dma_addr + tail; 1408 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1409 if (!s->tx_dma_len) { 1410 /* Transmit buffer has been flushed */ 1411 spin_unlock_irq(&port->lock); 1412 return; 1413 } 1414 1415 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1416 DMA_MEM_TO_DEV, 1417 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1418 if (!desc) { 1419 spin_unlock_irq(&port->lock); 1420 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1421 goto switch_to_pio; 1422 } 1423 1424 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1425 DMA_TO_DEVICE); 1426 1427 desc->callback = sci_dma_tx_complete; 1428 desc->callback_param = s; 1429 s->cookie_tx = dmaengine_submit(desc); 1430 if (dma_submit_error(s->cookie_tx)) { 1431 spin_unlock_irq(&port->lock); 1432 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1433 goto switch_to_pio; 1434 } 1435 1436 spin_unlock_irq(&port->lock); 1437 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1438 __func__, xmit->buf, tail, head, s->cookie_tx); 1439 1440 dma_async_issue_pending(chan); 1441 return; 1442 1443 switch_to_pio: 1444 spin_lock_irqsave(&port->lock, flags); 1445 s->chan_tx = NULL; 1446 sci_start_tx(port); 1447 spin_unlock_irqrestore(&port->lock, flags); 1448 return; 1449 } 1450 1451 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1452 { 1453 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1454 struct dma_chan *chan = s->chan_rx; 1455 struct uart_port *port = &s->port; 1456 struct dma_tx_state state; 1457 enum dma_status status; 1458 unsigned long flags; 1459 unsigned int read; 1460 int active, count; 1461 1462 dev_dbg(port->dev, "DMA Rx timed out\n"); 1463 1464 spin_lock_irqsave(&port->lock, flags); 1465 1466 active = sci_dma_rx_find_active(s); 1467 if (active < 0) { 1468 spin_unlock_irqrestore(&port->lock, flags); 1469 return HRTIMER_NORESTART; 1470 } 1471 1472 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1473 if (status == DMA_COMPLETE) { 1474 spin_unlock_irqrestore(&port->lock, flags); 1475 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1476 s->active_rx, active); 1477 1478 /* Let packet complete handler take care of the packet */ 1479 return HRTIMER_NORESTART; 1480 } 1481 1482 dmaengine_pause(chan); 1483 1484 /* 1485 * sometimes DMA transfer doesn't stop even if it is stopped and 1486 * data keeps on coming until transaction is complete so check 1487 * for DMA_COMPLETE again 1488 * Let packet complete handler take care of the packet 1489 */ 1490 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1491 if (status == DMA_COMPLETE) { 1492 spin_unlock_irqrestore(&port->lock, flags); 1493 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1494 return HRTIMER_NORESTART; 1495 } 1496 1497 /* Handle incomplete DMA receive */ 1498 dmaengine_terminate_async(s->chan_rx); 1499 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1500 1501 if (read) { 1502 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1503 if (count) 1504 tty_flip_buffer_push(&port->state->port); 1505 } 1506 1507 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1508 sci_dma_rx_submit(s, true); 1509 1510 sci_dma_rx_reenable_irq(s); 1511 1512 spin_unlock_irqrestore(&port->lock, flags); 1513 1514 return HRTIMER_NORESTART; 1515 } 1516 1517 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1518 enum dma_transfer_direction dir) 1519 { 1520 struct dma_chan *chan; 1521 struct dma_slave_config cfg; 1522 int ret; 1523 1524 chan = dma_request_slave_channel(port->dev, 1525 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1526 if (!chan) { 1527 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1528 return NULL; 1529 } 1530 1531 memset(&cfg, 0, sizeof(cfg)); 1532 cfg.direction = dir; 1533 if (dir == DMA_MEM_TO_DEV) { 1534 cfg.dst_addr = port->mapbase + 1535 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1537 } else { 1538 cfg.src_addr = port->mapbase + 1539 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1540 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1541 } 1542 1543 ret = dmaengine_slave_config(chan, &cfg); 1544 if (ret) { 1545 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1546 dma_release_channel(chan); 1547 return NULL; 1548 } 1549 1550 return chan; 1551 } 1552 1553 static void sci_request_dma(struct uart_port *port) 1554 { 1555 struct sci_port *s = to_sci_port(port); 1556 struct dma_chan *chan; 1557 1558 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1559 1560 /* 1561 * DMA on console may interfere with Kernel log messages which use 1562 * plain putchar(). So, simply don't use it with a console. 1563 */ 1564 if (uart_console(port)) 1565 return; 1566 1567 if (!port->dev->of_node) 1568 return; 1569 1570 s->cookie_tx = -EINVAL; 1571 1572 /* 1573 * Don't request a dma channel if no channel was specified 1574 * in the device tree. 1575 */ 1576 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1577 return; 1578 1579 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1580 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1581 if (chan) { 1582 /* UART circular tx buffer is an aligned page. */ 1583 s->tx_dma_addr = dma_map_single(chan->device->dev, 1584 port->state->xmit.buf, 1585 UART_XMIT_SIZE, 1586 DMA_TO_DEVICE); 1587 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1588 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1589 dma_release_channel(chan); 1590 } else { 1591 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1592 __func__, UART_XMIT_SIZE, 1593 port->state->xmit.buf, &s->tx_dma_addr); 1594 1595 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1596 s->chan_tx_saved = s->chan_tx = chan; 1597 } 1598 } 1599 1600 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1601 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1602 if (chan) { 1603 unsigned int i; 1604 dma_addr_t dma; 1605 void *buf; 1606 1607 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1608 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1609 &dma, GFP_KERNEL); 1610 if (!buf) { 1611 dev_warn(port->dev, 1612 "Failed to allocate Rx dma buffer, using PIO\n"); 1613 dma_release_channel(chan); 1614 return; 1615 } 1616 1617 for (i = 0; i < 2; i++) { 1618 struct scatterlist *sg = &s->sg_rx[i]; 1619 1620 sg_init_table(sg, 1); 1621 s->rx_buf[i] = buf; 1622 sg_dma_address(sg) = dma; 1623 sg_dma_len(sg) = s->buf_len_rx; 1624 1625 buf += s->buf_len_rx; 1626 dma += s->buf_len_rx; 1627 } 1628 1629 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1630 s->rx_timer.function = sci_dma_rx_timer_fn; 1631 1632 s->chan_rx_saved = s->chan_rx = chan; 1633 1634 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1635 sci_dma_rx_submit(s, false); 1636 } 1637 } 1638 1639 static void sci_free_dma(struct uart_port *port) 1640 { 1641 struct sci_port *s = to_sci_port(port); 1642 1643 if (s->chan_tx_saved) 1644 sci_dma_tx_release(s); 1645 if (s->chan_rx_saved) 1646 sci_dma_rx_release(s); 1647 } 1648 1649 static void sci_flush_buffer(struct uart_port *port) 1650 { 1651 struct sci_port *s = to_sci_port(port); 1652 1653 /* 1654 * In uart_flush_buffer(), the xmit circular buffer has just been 1655 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1656 * pending transfers 1657 */ 1658 s->tx_dma_len = 0; 1659 if (s->chan_tx) { 1660 dmaengine_terminate_async(s->chan_tx); 1661 s->cookie_tx = -EINVAL; 1662 } 1663 } 1664 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1665 static inline void sci_request_dma(struct uart_port *port) 1666 { 1667 } 1668 1669 static inline void sci_free_dma(struct uart_port *port) 1670 { 1671 } 1672 1673 #define sci_flush_buffer NULL 1674 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1675 1676 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1677 { 1678 struct uart_port *port = ptr; 1679 struct sci_port *s = to_sci_port(port); 1680 1681 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1682 if (s->chan_rx) { 1683 u16 scr = serial_port_in(port, SCSCR); 1684 u16 ssr = serial_port_in(port, SCxSR); 1685 1686 /* Disable future Rx interrupts */ 1687 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1688 disable_irq_nosync(irq); 1689 scr |= SCSCR_RDRQE; 1690 } else { 1691 if (sci_dma_rx_submit(s, false) < 0) 1692 goto handle_pio; 1693 1694 scr &= ~SCSCR_RIE; 1695 } 1696 serial_port_out(port, SCSCR, scr); 1697 /* Clear current interrupt */ 1698 serial_port_out(port, SCxSR, 1699 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1700 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1701 jiffies, s->rx_timeout); 1702 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1703 1704 return IRQ_HANDLED; 1705 } 1706 1707 handle_pio: 1708 #endif 1709 1710 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1711 if (!scif_rtrg_enabled(port)) 1712 scif_set_rtrg(port, s->rx_trigger); 1713 1714 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1715 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1716 } 1717 1718 /* I think sci_receive_chars has to be called irrespective 1719 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1720 * to be disabled? 1721 */ 1722 sci_receive_chars(port); 1723 1724 return IRQ_HANDLED; 1725 } 1726 1727 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1728 { 1729 struct uart_port *port = ptr; 1730 unsigned long flags; 1731 1732 spin_lock_irqsave(&port->lock, flags); 1733 sci_transmit_chars(port); 1734 spin_unlock_irqrestore(&port->lock, flags); 1735 1736 return IRQ_HANDLED; 1737 } 1738 1739 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1740 { 1741 struct uart_port *port = ptr; 1742 1743 /* Handle BREAKs */ 1744 sci_handle_breaks(port); 1745 1746 /* drop invalid character received before break was detected */ 1747 serial_port_in(port, SCxRDR); 1748 1749 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1750 1751 return IRQ_HANDLED; 1752 } 1753 1754 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1755 { 1756 struct uart_port *port = ptr; 1757 struct sci_port *s = to_sci_port(port); 1758 1759 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1760 /* Break and Error interrupts are muxed */ 1761 unsigned short ssr_status = serial_port_in(port, SCxSR); 1762 1763 /* Break Interrupt */ 1764 if (ssr_status & SCxSR_BRK(port)) 1765 sci_br_interrupt(irq, ptr); 1766 1767 /* Break only? */ 1768 if (!(ssr_status & SCxSR_ERRORS(port))) 1769 return IRQ_HANDLED; 1770 } 1771 1772 /* Handle errors */ 1773 if (port->type == PORT_SCI) { 1774 if (sci_handle_errors(port)) { 1775 /* discard character in rx buffer */ 1776 serial_port_in(port, SCxSR); 1777 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1778 } 1779 } else { 1780 sci_handle_fifo_overrun(port); 1781 if (!s->chan_rx) 1782 sci_receive_chars(port); 1783 } 1784 1785 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1786 1787 /* Kick the transmission */ 1788 if (!s->chan_tx) 1789 sci_tx_interrupt(irq, ptr); 1790 1791 return IRQ_HANDLED; 1792 } 1793 1794 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1795 { 1796 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1797 struct uart_port *port = ptr; 1798 struct sci_port *s = to_sci_port(port); 1799 irqreturn_t ret = IRQ_NONE; 1800 1801 ssr_status = serial_port_in(port, SCxSR); 1802 scr_status = serial_port_in(port, SCSCR); 1803 if (s->params->overrun_reg == SCxSR) 1804 orer_status = ssr_status; 1805 else if (sci_getreg(port, s->params->overrun_reg)->size) 1806 orer_status = serial_port_in(port, s->params->overrun_reg); 1807 1808 err_enabled = scr_status & port_rx_irq_mask(port); 1809 1810 /* Tx Interrupt */ 1811 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1812 !s->chan_tx) 1813 ret = sci_tx_interrupt(irq, ptr); 1814 1815 /* 1816 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1817 * DR flags 1818 */ 1819 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1820 (scr_status & SCSCR_RIE)) 1821 ret = sci_rx_interrupt(irq, ptr); 1822 1823 /* Error Interrupt */ 1824 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1825 ret = sci_er_interrupt(irq, ptr); 1826 1827 /* Break Interrupt */ 1828 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1829 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1830 ret = sci_br_interrupt(irq, ptr); 1831 1832 /* Overrun Interrupt */ 1833 if (orer_status & s->params->overrun_mask) { 1834 sci_handle_fifo_overrun(port); 1835 ret = IRQ_HANDLED; 1836 } 1837 1838 return ret; 1839 } 1840 1841 static const struct sci_irq_desc { 1842 const char *desc; 1843 irq_handler_t handler; 1844 } sci_irq_desc[] = { 1845 /* 1846 * Split out handlers, the default case. 1847 */ 1848 [SCIx_ERI_IRQ] = { 1849 .desc = "rx err", 1850 .handler = sci_er_interrupt, 1851 }, 1852 1853 [SCIx_RXI_IRQ] = { 1854 .desc = "rx full", 1855 .handler = sci_rx_interrupt, 1856 }, 1857 1858 [SCIx_TXI_IRQ] = { 1859 .desc = "tx empty", 1860 .handler = sci_tx_interrupt, 1861 }, 1862 1863 [SCIx_BRI_IRQ] = { 1864 .desc = "break", 1865 .handler = sci_br_interrupt, 1866 }, 1867 1868 [SCIx_DRI_IRQ] = { 1869 .desc = "rx ready", 1870 .handler = sci_rx_interrupt, 1871 }, 1872 1873 [SCIx_TEI_IRQ] = { 1874 .desc = "tx end", 1875 .handler = sci_tx_interrupt, 1876 }, 1877 1878 /* 1879 * Special muxed handler. 1880 */ 1881 [SCIx_MUX_IRQ] = { 1882 .desc = "mux", 1883 .handler = sci_mpxed_interrupt, 1884 }, 1885 }; 1886 1887 static int sci_request_irq(struct sci_port *port) 1888 { 1889 struct uart_port *up = &port->port; 1890 int i, j, w, ret = 0; 1891 1892 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1893 const struct sci_irq_desc *desc; 1894 int irq; 1895 1896 /* Check if already registered (muxed) */ 1897 for (w = 0; w < i; w++) 1898 if (port->irqs[w] == port->irqs[i]) 1899 w = i + 1; 1900 if (w > i) 1901 continue; 1902 1903 if (SCIx_IRQ_IS_MUXED(port)) { 1904 i = SCIx_MUX_IRQ; 1905 irq = up->irq; 1906 } else { 1907 irq = port->irqs[i]; 1908 1909 /* 1910 * Certain port types won't support all of the 1911 * available interrupt sources. 1912 */ 1913 if (unlikely(irq < 0)) 1914 continue; 1915 } 1916 1917 desc = sci_irq_desc + i; 1918 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1919 dev_name(up->dev), desc->desc); 1920 if (!port->irqstr[j]) { 1921 ret = -ENOMEM; 1922 goto out_nomem; 1923 } 1924 1925 ret = request_irq(irq, desc->handler, up->irqflags, 1926 port->irqstr[j], port); 1927 if (unlikely(ret)) { 1928 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1929 goto out_noirq; 1930 } 1931 } 1932 1933 return 0; 1934 1935 out_noirq: 1936 while (--i >= 0) 1937 free_irq(port->irqs[i], port); 1938 1939 out_nomem: 1940 while (--j >= 0) 1941 kfree(port->irqstr[j]); 1942 1943 return ret; 1944 } 1945 1946 static void sci_free_irq(struct sci_port *port) 1947 { 1948 int i, j; 1949 1950 /* 1951 * Intentionally in reverse order so we iterate over the muxed 1952 * IRQ first. 1953 */ 1954 for (i = 0; i < SCIx_NR_IRQS; i++) { 1955 int irq = port->irqs[i]; 1956 1957 /* 1958 * Certain port types won't support all of the available 1959 * interrupt sources. 1960 */ 1961 if (unlikely(irq < 0)) 1962 continue; 1963 1964 /* Check if already freed (irq was muxed) */ 1965 for (j = 0; j < i; j++) 1966 if (port->irqs[j] == irq) 1967 j = i + 1; 1968 if (j > i) 1969 continue; 1970 1971 free_irq(port->irqs[i], port); 1972 kfree(port->irqstr[i]); 1973 1974 if (SCIx_IRQ_IS_MUXED(port)) { 1975 /* If there's only one IRQ, we're done. */ 1976 return; 1977 } 1978 } 1979 } 1980 1981 static unsigned int sci_tx_empty(struct uart_port *port) 1982 { 1983 unsigned short status = serial_port_in(port, SCxSR); 1984 unsigned short in_tx_fifo = sci_txfill(port); 1985 1986 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1987 } 1988 1989 static void sci_set_rts(struct uart_port *port, bool state) 1990 { 1991 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1992 u16 data = serial_port_in(port, SCPDR); 1993 1994 /* Active low */ 1995 if (state) 1996 data &= ~SCPDR_RTSD; 1997 else 1998 data |= SCPDR_RTSD; 1999 serial_port_out(port, SCPDR, data); 2000 2001 /* RTS# is output */ 2002 serial_port_out(port, SCPCR, 2003 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2004 } else if (sci_getreg(port, SCSPTR)->size) { 2005 u16 ctrl = serial_port_in(port, SCSPTR); 2006 2007 /* Active low */ 2008 if (state) 2009 ctrl &= ~SCSPTR_RTSDT; 2010 else 2011 ctrl |= SCSPTR_RTSDT; 2012 serial_port_out(port, SCSPTR, ctrl); 2013 } 2014 } 2015 2016 static bool sci_get_cts(struct uart_port *port) 2017 { 2018 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2019 /* Active low */ 2020 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2021 } else if (sci_getreg(port, SCSPTR)->size) { 2022 /* Active low */ 2023 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2024 } 2025 2026 return true; 2027 } 2028 2029 /* 2030 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2031 * CTS/RTS is supported in hardware by at least one port and controlled 2032 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2033 * handled via the ->init_pins() op, which is a bit of a one-way street, 2034 * lacking any ability to defer pin control -- this will later be 2035 * converted over to the GPIO framework). 2036 * 2037 * Other modes (such as loopback) are supported generically on certain 2038 * port types, but not others. For these it's sufficient to test for the 2039 * existence of the support register and simply ignore the port type. 2040 */ 2041 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2042 { 2043 struct sci_port *s = to_sci_port(port); 2044 2045 if (mctrl & TIOCM_LOOP) { 2046 const struct plat_sci_reg *reg; 2047 2048 /* 2049 * Standard loopback mode for SCFCR ports. 2050 */ 2051 reg = sci_getreg(port, SCFCR); 2052 if (reg->size) 2053 serial_port_out(port, SCFCR, 2054 serial_port_in(port, SCFCR) | 2055 SCFCR_LOOP); 2056 } 2057 2058 mctrl_gpio_set(s->gpios, mctrl); 2059 2060 if (!s->has_rtscts) 2061 return; 2062 2063 if (!(mctrl & TIOCM_RTS)) { 2064 /* Disable Auto RTS */ 2065 serial_port_out(port, SCFCR, 2066 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2067 2068 /* Clear RTS */ 2069 sci_set_rts(port, 0); 2070 } else if (s->autorts) { 2071 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2072 /* Enable RTS# pin function */ 2073 serial_port_out(port, SCPCR, 2074 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2075 } 2076 2077 /* Enable Auto RTS */ 2078 serial_port_out(port, SCFCR, 2079 serial_port_in(port, SCFCR) | SCFCR_MCE); 2080 } else { 2081 /* Set RTS */ 2082 sci_set_rts(port, 1); 2083 } 2084 } 2085 2086 static unsigned int sci_get_mctrl(struct uart_port *port) 2087 { 2088 struct sci_port *s = to_sci_port(port); 2089 struct mctrl_gpios *gpios = s->gpios; 2090 unsigned int mctrl = 0; 2091 2092 mctrl_gpio_get(gpios, &mctrl); 2093 2094 /* 2095 * CTS/RTS is handled in hardware when supported, while nothing 2096 * else is wired up. 2097 */ 2098 if (s->autorts) { 2099 if (sci_get_cts(port)) 2100 mctrl |= TIOCM_CTS; 2101 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2102 mctrl |= TIOCM_CTS; 2103 } 2104 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2105 mctrl |= TIOCM_DSR; 2106 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2107 mctrl |= TIOCM_CAR; 2108 2109 return mctrl; 2110 } 2111 2112 static void sci_enable_ms(struct uart_port *port) 2113 { 2114 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2115 } 2116 2117 static void sci_break_ctl(struct uart_port *port, int break_state) 2118 { 2119 unsigned short scscr, scsptr; 2120 unsigned long flags; 2121 2122 /* check whether the port has SCSPTR */ 2123 if (!sci_getreg(port, SCSPTR)->size) { 2124 /* 2125 * Not supported by hardware. Most parts couple break and rx 2126 * interrupts together, with break detection always enabled. 2127 */ 2128 return; 2129 } 2130 2131 spin_lock_irqsave(&port->lock, flags); 2132 scsptr = serial_port_in(port, SCSPTR); 2133 scscr = serial_port_in(port, SCSCR); 2134 2135 if (break_state == -1) { 2136 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2137 scscr &= ~SCSCR_TE; 2138 } else { 2139 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2140 scscr |= SCSCR_TE; 2141 } 2142 2143 serial_port_out(port, SCSPTR, scsptr); 2144 serial_port_out(port, SCSCR, scscr); 2145 spin_unlock_irqrestore(&port->lock, flags); 2146 } 2147 2148 static int sci_startup(struct uart_port *port) 2149 { 2150 struct sci_port *s = to_sci_port(port); 2151 int ret; 2152 2153 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2154 2155 sci_request_dma(port); 2156 2157 ret = sci_request_irq(s); 2158 if (unlikely(ret < 0)) { 2159 sci_free_dma(port); 2160 return ret; 2161 } 2162 2163 return 0; 2164 } 2165 2166 static void sci_shutdown(struct uart_port *port) 2167 { 2168 struct sci_port *s = to_sci_port(port); 2169 unsigned long flags; 2170 u16 scr; 2171 2172 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2173 2174 s->autorts = false; 2175 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2176 2177 spin_lock_irqsave(&port->lock, flags); 2178 sci_stop_rx(port); 2179 sci_stop_tx(port); 2180 /* 2181 * Stop RX and TX, disable related interrupts, keep clock source 2182 * and HSCIF TOT bits 2183 */ 2184 scr = serial_port_in(port, SCSCR); 2185 serial_port_out(port, SCSCR, scr & 2186 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2187 spin_unlock_irqrestore(&port->lock, flags); 2188 2189 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2190 if (s->chan_rx_saved) { 2191 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2192 port->line); 2193 hrtimer_cancel(&s->rx_timer); 2194 } 2195 #endif 2196 2197 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2198 del_timer_sync(&s->rx_fifo_timer); 2199 sci_free_irq(s); 2200 sci_free_dma(port); 2201 } 2202 2203 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2204 unsigned int *srr) 2205 { 2206 unsigned long freq = s->clk_rates[SCI_SCK]; 2207 int err, min_err = INT_MAX; 2208 unsigned int sr; 2209 2210 if (s->port.type != PORT_HSCIF) 2211 freq *= 2; 2212 2213 for_each_sr(sr, s) { 2214 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2215 if (abs(err) >= abs(min_err)) 2216 continue; 2217 2218 min_err = err; 2219 *srr = sr - 1; 2220 2221 if (!err) 2222 break; 2223 } 2224 2225 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2226 *srr + 1); 2227 return min_err; 2228 } 2229 2230 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2231 unsigned long freq, unsigned int *dlr, 2232 unsigned int *srr) 2233 { 2234 int err, min_err = INT_MAX; 2235 unsigned int sr, dl; 2236 2237 if (s->port.type != PORT_HSCIF) 2238 freq *= 2; 2239 2240 for_each_sr(sr, s) { 2241 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2242 dl = clamp(dl, 1U, 65535U); 2243 2244 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2245 if (abs(err) >= abs(min_err)) 2246 continue; 2247 2248 min_err = err; 2249 *dlr = dl; 2250 *srr = sr - 1; 2251 2252 if (!err) 2253 break; 2254 } 2255 2256 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2257 min_err, *dlr, *srr + 1); 2258 return min_err; 2259 } 2260 2261 /* calculate sample rate, BRR, and clock select */ 2262 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2263 unsigned int *brr, unsigned int *srr, 2264 unsigned int *cks) 2265 { 2266 unsigned long freq = s->clk_rates[SCI_FCK]; 2267 unsigned int sr, br, prediv, scrate, c; 2268 int err, min_err = INT_MAX; 2269 2270 if (s->port.type != PORT_HSCIF) 2271 freq *= 2; 2272 2273 /* 2274 * Find the combination of sample rate and clock select with the 2275 * smallest deviation from the desired baud rate. 2276 * Prefer high sample rates to maximise the receive margin. 2277 * 2278 * M: Receive margin (%) 2279 * N: Ratio of bit rate to clock (N = sampling rate) 2280 * D: Clock duty (D = 0 to 1.0) 2281 * L: Frame length (L = 9 to 12) 2282 * F: Absolute value of clock frequency deviation 2283 * 2284 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2285 * (|D - 0.5| / N * (1 + F))| 2286 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2287 */ 2288 for_each_sr(sr, s) { 2289 for (c = 0; c <= 3; c++) { 2290 /* integerized formulas from HSCIF documentation */ 2291 prediv = sr << (2 * c + 1); 2292 2293 /* 2294 * We need to calculate: 2295 * 2296 * br = freq / (prediv * bps) clamped to [1..256] 2297 * err = freq / (br * prediv) - bps 2298 * 2299 * Watch out for overflow when calculating the desired 2300 * sampling clock rate! 2301 */ 2302 if (bps > UINT_MAX / prediv) 2303 break; 2304 2305 scrate = prediv * bps; 2306 br = DIV_ROUND_CLOSEST(freq, scrate); 2307 br = clamp(br, 1U, 256U); 2308 2309 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2310 if (abs(err) >= abs(min_err)) 2311 continue; 2312 2313 min_err = err; 2314 *brr = br - 1; 2315 *srr = sr - 1; 2316 *cks = c; 2317 2318 if (!err) 2319 goto found; 2320 } 2321 } 2322 2323 found: 2324 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2325 min_err, *brr, *srr + 1, *cks); 2326 return min_err; 2327 } 2328 2329 static void sci_reset(struct uart_port *port) 2330 { 2331 const struct plat_sci_reg *reg; 2332 unsigned int status; 2333 struct sci_port *s = to_sci_port(port); 2334 2335 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2336 2337 reg = sci_getreg(port, SCFCR); 2338 if (reg->size) 2339 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2340 2341 sci_clear_SCxSR(port, 2342 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2343 SCxSR_BREAK_CLEAR(port)); 2344 if (sci_getreg(port, SCLSR)->size) { 2345 status = serial_port_in(port, SCLSR); 2346 status &= ~(SCLSR_TO | SCLSR_ORER); 2347 serial_port_out(port, SCLSR, status); 2348 } 2349 2350 if (s->rx_trigger > 1) { 2351 if (s->rx_fifo_timeout) { 2352 scif_set_rtrg(port, 1); 2353 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2354 } else { 2355 if (port->type == PORT_SCIFA || 2356 port->type == PORT_SCIFB) 2357 scif_set_rtrg(port, 1); 2358 else 2359 scif_set_rtrg(port, s->rx_trigger); 2360 } 2361 } 2362 } 2363 2364 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2365 const struct ktermios *old) 2366 { 2367 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2368 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2369 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2370 struct sci_port *s = to_sci_port(port); 2371 const struct plat_sci_reg *reg; 2372 int min_err = INT_MAX, err; 2373 unsigned long max_freq = 0; 2374 int best_clk = -1; 2375 unsigned long flags; 2376 2377 if ((termios->c_cflag & CSIZE) == CS7) { 2378 smr_val |= SCSMR_CHR; 2379 } else { 2380 termios->c_cflag &= ~CSIZE; 2381 termios->c_cflag |= CS8; 2382 } 2383 if (termios->c_cflag & PARENB) 2384 smr_val |= SCSMR_PE; 2385 if (termios->c_cflag & PARODD) 2386 smr_val |= SCSMR_PE | SCSMR_ODD; 2387 if (termios->c_cflag & CSTOPB) 2388 smr_val |= SCSMR_STOP; 2389 2390 /* 2391 * earlyprintk comes here early on with port->uartclk set to zero. 2392 * the clock framework is not up and running at this point so here 2393 * we assume that 115200 is the maximum baud rate. please note that 2394 * the baud rate is not programmed during earlyprintk - it is assumed 2395 * that the previous boot loader has enabled required clocks and 2396 * setup the baud rate generator hardware for us already. 2397 */ 2398 if (!port->uartclk) { 2399 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2400 goto done; 2401 } 2402 2403 for (i = 0; i < SCI_NUM_CLKS; i++) 2404 max_freq = max(max_freq, s->clk_rates[i]); 2405 2406 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2407 if (!baud) 2408 goto done; 2409 2410 /* 2411 * There can be multiple sources for the sampling clock. Find the one 2412 * that gives us the smallest deviation from the desired baud rate. 2413 */ 2414 2415 /* Optional Undivided External Clock */ 2416 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2417 port->type != PORT_SCIFB) { 2418 err = sci_sck_calc(s, baud, &srr1); 2419 if (abs(err) < abs(min_err)) { 2420 best_clk = SCI_SCK; 2421 scr_val = SCSCR_CKE1; 2422 sccks = SCCKS_CKS; 2423 min_err = err; 2424 srr = srr1; 2425 if (!err) 2426 goto done; 2427 } 2428 } 2429 2430 /* Optional BRG Frequency Divided External Clock */ 2431 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2432 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2433 &srr1); 2434 if (abs(err) < abs(min_err)) { 2435 best_clk = SCI_SCIF_CLK; 2436 scr_val = SCSCR_CKE1; 2437 sccks = 0; 2438 min_err = err; 2439 dl = dl1; 2440 srr = srr1; 2441 if (!err) 2442 goto done; 2443 } 2444 } 2445 2446 /* Optional BRG Frequency Divided Internal Clock */ 2447 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2448 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2449 &srr1); 2450 if (abs(err) < abs(min_err)) { 2451 best_clk = SCI_BRG_INT; 2452 scr_val = SCSCR_CKE1; 2453 sccks = SCCKS_XIN; 2454 min_err = err; 2455 dl = dl1; 2456 srr = srr1; 2457 if (!min_err) 2458 goto done; 2459 } 2460 } 2461 2462 /* Divided Functional Clock using standard Bit Rate Register */ 2463 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2464 if (abs(err) < abs(min_err)) { 2465 best_clk = SCI_FCK; 2466 scr_val = 0; 2467 min_err = err; 2468 brr = brr1; 2469 srr = srr1; 2470 cks = cks1; 2471 } 2472 2473 done: 2474 if (best_clk >= 0) 2475 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2476 s->clks[best_clk], baud, min_err); 2477 2478 sci_port_enable(s); 2479 2480 /* 2481 * Program the optional External Baud Rate Generator (BRG) first. 2482 * It controls the mux to select (H)SCK or frequency divided clock. 2483 */ 2484 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2485 serial_port_out(port, SCDL, dl); 2486 serial_port_out(port, SCCKS, sccks); 2487 } 2488 2489 spin_lock_irqsave(&port->lock, flags); 2490 2491 sci_reset(port); 2492 2493 uart_update_timeout(port, termios->c_cflag, baud); 2494 2495 /* byte size and parity */ 2496 bits = tty_get_frame_size(termios->c_cflag); 2497 2498 if (sci_getreg(port, SEMR)->size) 2499 serial_port_out(port, SEMR, 0); 2500 2501 if (best_clk >= 0) { 2502 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2503 switch (srr + 1) { 2504 case 5: smr_val |= SCSMR_SRC_5; break; 2505 case 7: smr_val |= SCSMR_SRC_7; break; 2506 case 11: smr_val |= SCSMR_SRC_11; break; 2507 case 13: smr_val |= SCSMR_SRC_13; break; 2508 case 16: smr_val |= SCSMR_SRC_16; break; 2509 case 17: smr_val |= SCSMR_SRC_17; break; 2510 case 19: smr_val |= SCSMR_SRC_19; break; 2511 case 27: smr_val |= SCSMR_SRC_27; break; 2512 } 2513 smr_val |= cks; 2514 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2515 serial_port_out(port, SCSMR, smr_val); 2516 serial_port_out(port, SCBRR, brr); 2517 if (sci_getreg(port, HSSRR)->size) { 2518 unsigned int hssrr = srr | HSCIF_SRE; 2519 /* Calculate deviation from intended rate at the 2520 * center of the last stop bit in sampling clocks. 2521 */ 2522 int last_stop = bits * 2 - 1; 2523 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2524 (int)(srr + 1), 2525 2 * (int)baud); 2526 2527 if (abs(deviation) >= 2) { 2528 /* At least two sampling clocks off at the 2529 * last stop bit; we can increase the error 2530 * margin by shifting the sampling point. 2531 */ 2532 int shift = clamp(deviation / 2, -8, 7); 2533 2534 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2535 HSCIF_SRHP_MASK; 2536 hssrr |= HSCIF_SRDE; 2537 } 2538 serial_port_out(port, HSSRR, hssrr); 2539 } 2540 2541 /* Wait one bit interval */ 2542 udelay((1000000 + (baud - 1)) / baud); 2543 } else { 2544 /* Don't touch the bit rate configuration */ 2545 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2546 smr_val |= serial_port_in(port, SCSMR) & 2547 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2548 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2549 serial_port_out(port, SCSMR, smr_val); 2550 } 2551 2552 sci_init_pins(port, termios->c_cflag); 2553 2554 port->status &= ~UPSTAT_AUTOCTS; 2555 s->autorts = false; 2556 reg = sci_getreg(port, SCFCR); 2557 if (reg->size) { 2558 unsigned short ctrl = serial_port_in(port, SCFCR); 2559 2560 if ((port->flags & UPF_HARD_FLOW) && 2561 (termios->c_cflag & CRTSCTS)) { 2562 /* There is no CTS interrupt to restart the hardware */ 2563 port->status |= UPSTAT_AUTOCTS; 2564 /* MCE is enabled when RTS is raised */ 2565 s->autorts = true; 2566 } 2567 2568 /* 2569 * As we've done a sci_reset() above, ensure we don't 2570 * interfere with the FIFOs while toggling MCE. As the 2571 * reset values could still be set, simply mask them out. 2572 */ 2573 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2574 2575 serial_port_out(port, SCFCR, ctrl); 2576 } 2577 if (port->flags & UPF_HARD_FLOW) { 2578 /* Refresh (Auto) RTS */ 2579 sci_set_mctrl(port, port->mctrl); 2580 } 2581 2582 scr_val |= SCSCR_RE | SCSCR_TE | 2583 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2584 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2585 if ((srr + 1 == 5) && 2586 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2587 /* 2588 * In asynchronous mode, when the sampling rate is 1/5, first 2589 * received data may become invalid on some SCIFA and SCIFB. 2590 * To avoid this problem wait more than 1 serial data time (1 2591 * bit time x serial data number) after setting SCSCR.RE = 1. 2592 */ 2593 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2594 } 2595 2596 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2597 s->rx_frame = (10000 * bits) / (baud / 100); 2598 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2599 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2600 #endif 2601 2602 if ((termios->c_cflag & CREAD) != 0) 2603 sci_start_rx(port); 2604 2605 spin_unlock_irqrestore(&port->lock, flags); 2606 2607 sci_port_disable(s); 2608 2609 if (UART_ENABLE_MS(port, termios->c_cflag)) 2610 sci_enable_ms(port); 2611 } 2612 2613 static void sci_pm(struct uart_port *port, unsigned int state, 2614 unsigned int oldstate) 2615 { 2616 struct sci_port *sci_port = to_sci_port(port); 2617 2618 switch (state) { 2619 case UART_PM_STATE_OFF: 2620 sci_port_disable(sci_port); 2621 break; 2622 default: 2623 sci_port_enable(sci_port); 2624 break; 2625 } 2626 } 2627 2628 static const char *sci_type(struct uart_port *port) 2629 { 2630 switch (port->type) { 2631 case PORT_IRDA: 2632 return "irda"; 2633 case PORT_SCI: 2634 return "sci"; 2635 case PORT_SCIF: 2636 return "scif"; 2637 case PORT_SCIFA: 2638 return "scifa"; 2639 case PORT_SCIFB: 2640 return "scifb"; 2641 case PORT_HSCIF: 2642 return "hscif"; 2643 } 2644 2645 return NULL; 2646 } 2647 2648 static int sci_remap_port(struct uart_port *port) 2649 { 2650 struct sci_port *sport = to_sci_port(port); 2651 2652 /* 2653 * Nothing to do if there's already an established membase. 2654 */ 2655 if (port->membase) 2656 return 0; 2657 2658 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2659 port->membase = ioremap(port->mapbase, sport->reg_size); 2660 if (unlikely(!port->membase)) { 2661 dev_err(port->dev, "can't remap port#%d\n", port->line); 2662 return -ENXIO; 2663 } 2664 } else { 2665 /* 2666 * For the simple (and majority of) cases where we don't 2667 * need to do any remapping, just cast the cookie 2668 * directly. 2669 */ 2670 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2671 } 2672 2673 return 0; 2674 } 2675 2676 static void sci_release_port(struct uart_port *port) 2677 { 2678 struct sci_port *sport = to_sci_port(port); 2679 2680 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2681 iounmap(port->membase); 2682 port->membase = NULL; 2683 } 2684 2685 release_mem_region(port->mapbase, sport->reg_size); 2686 } 2687 2688 static int sci_request_port(struct uart_port *port) 2689 { 2690 struct resource *res; 2691 struct sci_port *sport = to_sci_port(port); 2692 int ret; 2693 2694 res = request_mem_region(port->mapbase, sport->reg_size, 2695 dev_name(port->dev)); 2696 if (unlikely(res == NULL)) { 2697 dev_err(port->dev, "request_mem_region failed."); 2698 return -EBUSY; 2699 } 2700 2701 ret = sci_remap_port(port); 2702 if (unlikely(ret != 0)) { 2703 release_resource(res); 2704 return ret; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static void sci_config_port(struct uart_port *port, int flags) 2711 { 2712 if (flags & UART_CONFIG_TYPE) { 2713 struct sci_port *sport = to_sci_port(port); 2714 2715 port->type = sport->cfg->type; 2716 sci_request_port(port); 2717 } 2718 } 2719 2720 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2721 { 2722 if (ser->baud_base < 2400) 2723 /* No paper tape reader for Mitch.. */ 2724 return -EINVAL; 2725 2726 return 0; 2727 } 2728 2729 static const struct uart_ops sci_uart_ops = { 2730 .tx_empty = sci_tx_empty, 2731 .set_mctrl = sci_set_mctrl, 2732 .get_mctrl = sci_get_mctrl, 2733 .start_tx = sci_start_tx, 2734 .stop_tx = sci_stop_tx, 2735 .stop_rx = sci_stop_rx, 2736 .enable_ms = sci_enable_ms, 2737 .break_ctl = sci_break_ctl, 2738 .startup = sci_startup, 2739 .shutdown = sci_shutdown, 2740 .flush_buffer = sci_flush_buffer, 2741 .set_termios = sci_set_termios, 2742 .pm = sci_pm, 2743 .type = sci_type, 2744 .release_port = sci_release_port, 2745 .request_port = sci_request_port, 2746 .config_port = sci_config_port, 2747 .verify_port = sci_verify_port, 2748 #ifdef CONFIG_CONSOLE_POLL 2749 .poll_get_char = sci_poll_get_char, 2750 .poll_put_char = sci_poll_put_char, 2751 #endif 2752 }; 2753 2754 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2755 { 2756 const char *clk_names[] = { 2757 [SCI_FCK] = "fck", 2758 [SCI_SCK] = "sck", 2759 [SCI_BRG_INT] = "brg_int", 2760 [SCI_SCIF_CLK] = "scif_clk", 2761 }; 2762 struct clk *clk; 2763 unsigned int i; 2764 2765 if (sci_port->cfg->type == PORT_HSCIF) 2766 clk_names[SCI_SCK] = "hsck"; 2767 2768 for (i = 0; i < SCI_NUM_CLKS; i++) { 2769 clk = devm_clk_get_optional(dev, clk_names[i]); 2770 if (IS_ERR(clk)) 2771 return PTR_ERR(clk); 2772 2773 if (!clk && i == SCI_FCK) { 2774 /* 2775 * Not all SH platforms declare a clock lookup entry 2776 * for SCI devices, in which case we need to get the 2777 * global "peripheral_clk" clock. 2778 */ 2779 clk = devm_clk_get(dev, "peripheral_clk"); 2780 if (IS_ERR(clk)) 2781 return dev_err_probe(dev, PTR_ERR(clk), 2782 "failed to get %s\n", 2783 clk_names[i]); 2784 } 2785 2786 if (!clk) 2787 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2788 else 2789 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2790 clk, clk_get_rate(clk)); 2791 sci_port->clks[i] = clk; 2792 } 2793 return 0; 2794 } 2795 2796 static const struct sci_port_params * 2797 sci_probe_regmap(const struct plat_sci_port *cfg) 2798 { 2799 unsigned int regtype; 2800 2801 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2802 return &sci_port_params[cfg->regtype]; 2803 2804 switch (cfg->type) { 2805 case PORT_SCI: 2806 regtype = SCIx_SCI_REGTYPE; 2807 break; 2808 case PORT_IRDA: 2809 regtype = SCIx_IRDA_REGTYPE; 2810 break; 2811 case PORT_SCIFA: 2812 regtype = SCIx_SCIFA_REGTYPE; 2813 break; 2814 case PORT_SCIFB: 2815 regtype = SCIx_SCIFB_REGTYPE; 2816 break; 2817 case PORT_SCIF: 2818 /* 2819 * The SH-4 is a bit of a misnomer here, although that's 2820 * where this particular port layout originated. This 2821 * configuration (or some slight variation thereof) 2822 * remains the dominant model for all SCIFs. 2823 */ 2824 regtype = SCIx_SH4_SCIF_REGTYPE; 2825 break; 2826 case PORT_HSCIF: 2827 regtype = SCIx_HSCIF_REGTYPE; 2828 break; 2829 default: 2830 pr_err("Can't probe register map for given port\n"); 2831 return NULL; 2832 } 2833 2834 return &sci_port_params[regtype]; 2835 } 2836 2837 static int sci_init_single(struct platform_device *dev, 2838 struct sci_port *sci_port, unsigned int index, 2839 const struct plat_sci_port *p, bool early) 2840 { 2841 struct uart_port *port = &sci_port->port; 2842 const struct resource *res; 2843 unsigned int i; 2844 int ret; 2845 2846 sci_port->cfg = p; 2847 2848 port->ops = &sci_uart_ops; 2849 port->iotype = UPIO_MEM; 2850 port->line = index; 2851 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2852 2853 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2854 if (res == NULL) 2855 return -ENOMEM; 2856 2857 port->mapbase = res->start; 2858 sci_port->reg_size = resource_size(res); 2859 2860 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2861 if (i) 2862 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2863 else 2864 sci_port->irqs[i] = platform_get_irq(dev, i); 2865 } 2866 2867 /* The SCI generates several interrupts. They can be muxed together or 2868 * connected to different interrupt lines. In the muxed case only one 2869 * interrupt resource is specified as there is only one interrupt ID. 2870 * In the non-muxed case, up to 6 interrupt signals might be generated 2871 * from the SCI, however those signals might have their own individual 2872 * interrupt ID numbers, or muxed together with another interrupt. 2873 */ 2874 if (sci_port->irqs[0] < 0) 2875 return -ENXIO; 2876 2877 if (sci_port->irqs[1] < 0) 2878 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2879 sci_port->irqs[i] = sci_port->irqs[0]; 2880 2881 sci_port->params = sci_probe_regmap(p); 2882 if (unlikely(sci_port->params == NULL)) 2883 return -EINVAL; 2884 2885 switch (p->type) { 2886 case PORT_SCIFB: 2887 sci_port->rx_trigger = 48; 2888 break; 2889 case PORT_HSCIF: 2890 sci_port->rx_trigger = 64; 2891 break; 2892 case PORT_SCIFA: 2893 sci_port->rx_trigger = 32; 2894 break; 2895 case PORT_SCIF: 2896 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2897 /* RX triggering not implemented for this IP */ 2898 sci_port->rx_trigger = 1; 2899 else 2900 sci_port->rx_trigger = 8; 2901 break; 2902 default: 2903 sci_port->rx_trigger = 1; 2904 break; 2905 } 2906 2907 sci_port->rx_fifo_timeout = 0; 2908 sci_port->hscif_tot = 0; 2909 2910 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2911 * match the SoC datasheet, this should be investigated. Let platform 2912 * data override the sampling rate for now. 2913 */ 2914 sci_port->sampling_rate_mask = p->sampling_rate 2915 ? SCI_SR(p->sampling_rate) 2916 : sci_port->params->sampling_rate_mask; 2917 2918 if (!early) { 2919 ret = sci_init_clocks(sci_port, &dev->dev); 2920 if (ret < 0) 2921 return ret; 2922 2923 port->dev = &dev->dev; 2924 2925 pm_runtime_enable(&dev->dev); 2926 } 2927 2928 port->type = p->type; 2929 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2930 port->fifosize = sci_port->params->fifosize; 2931 2932 if (port->type == PORT_SCI) { 2933 if (sci_port->reg_size >= 0x20) 2934 port->regshift = 2; 2935 else 2936 port->regshift = 1; 2937 } 2938 2939 /* 2940 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2941 * for the multi-IRQ ports, which is where we are primarily 2942 * concerned with the shutdown path synchronization. 2943 * 2944 * For the muxed case there's nothing more to do. 2945 */ 2946 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2947 port->irqflags = 0; 2948 2949 port->serial_in = sci_serial_in; 2950 port->serial_out = sci_serial_out; 2951 2952 return 0; 2953 } 2954 2955 static void sci_cleanup_single(struct sci_port *port) 2956 { 2957 pm_runtime_disable(port->port.dev); 2958 } 2959 2960 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2961 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2962 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 2963 { 2964 sci_poll_put_char(port, ch); 2965 } 2966 2967 /* 2968 * Print a string to the serial port trying not to disturb 2969 * any possible real use of the port... 2970 */ 2971 static void serial_console_write(struct console *co, const char *s, 2972 unsigned count) 2973 { 2974 struct sci_port *sci_port = &sci_ports[co->index]; 2975 struct uart_port *port = &sci_port->port; 2976 unsigned short bits, ctrl, ctrl_temp; 2977 unsigned long flags; 2978 int locked = 1; 2979 2980 if (port->sysrq) 2981 locked = 0; 2982 else if (oops_in_progress) 2983 locked = spin_trylock_irqsave(&port->lock, flags); 2984 else 2985 spin_lock_irqsave(&port->lock, flags); 2986 2987 /* first save SCSCR then disable interrupts, keep clock source */ 2988 ctrl = serial_port_in(port, SCSCR); 2989 ctrl_temp = SCSCR_RE | SCSCR_TE | 2990 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2991 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2992 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 2993 2994 uart_console_write(port, s, count, serial_console_putchar); 2995 2996 /* wait until fifo is empty and last bit has been transmitted */ 2997 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2998 while ((serial_port_in(port, SCxSR) & bits) != bits) 2999 cpu_relax(); 3000 3001 /* restore the SCSCR */ 3002 serial_port_out(port, SCSCR, ctrl); 3003 3004 if (locked) 3005 spin_unlock_irqrestore(&port->lock, flags); 3006 } 3007 3008 static int serial_console_setup(struct console *co, char *options) 3009 { 3010 struct sci_port *sci_port; 3011 struct uart_port *port; 3012 int baud = 115200; 3013 int bits = 8; 3014 int parity = 'n'; 3015 int flow = 'n'; 3016 int ret; 3017 3018 /* 3019 * Refuse to handle any bogus ports. 3020 */ 3021 if (co->index < 0 || co->index >= SCI_NPORTS) 3022 return -ENODEV; 3023 3024 sci_port = &sci_ports[co->index]; 3025 port = &sci_port->port; 3026 3027 /* 3028 * Refuse to handle uninitialized ports. 3029 */ 3030 if (!port->ops) 3031 return -ENODEV; 3032 3033 ret = sci_remap_port(port); 3034 if (unlikely(ret != 0)) 3035 return ret; 3036 3037 if (options) 3038 uart_parse_options(options, &baud, &parity, &bits, &flow); 3039 3040 return uart_set_options(port, co, baud, parity, bits, flow); 3041 } 3042 3043 static struct console serial_console = { 3044 .name = "ttySC", 3045 .device = uart_console_device, 3046 .write = serial_console_write, 3047 .setup = serial_console_setup, 3048 .flags = CON_PRINTBUFFER, 3049 .index = -1, 3050 .data = &sci_uart_driver, 3051 }; 3052 3053 #ifdef CONFIG_SUPERH 3054 static char early_serial_buf[32]; 3055 3056 static int early_serial_console_setup(struct console *co, char *options) 3057 { 3058 /* 3059 * This early console is always registered using the earlyprintk= 3060 * parameter, which does not call add_preferred_console(). Thus 3061 * @options is always NULL and the options for this early console 3062 * are passed using a custom buffer. 3063 */ 3064 WARN_ON(options); 3065 3066 return serial_console_setup(co, early_serial_buf); 3067 } 3068 3069 static struct console early_serial_console = { 3070 .name = "early_ttySC", 3071 .write = serial_console_write, 3072 .setup = early_serial_console_setup, 3073 .flags = CON_PRINTBUFFER, 3074 .index = -1, 3075 }; 3076 3077 static int sci_probe_earlyprintk(struct platform_device *pdev) 3078 { 3079 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3080 3081 if (early_serial_console.data) 3082 return -EEXIST; 3083 3084 early_serial_console.index = pdev->id; 3085 3086 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3087 3088 if (!strstr(early_serial_buf, "keep")) 3089 early_serial_console.flags |= CON_BOOT; 3090 3091 register_console(&early_serial_console); 3092 return 0; 3093 } 3094 #endif 3095 3096 #define SCI_CONSOLE (&serial_console) 3097 3098 #else 3099 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3100 { 3101 return -EINVAL; 3102 } 3103 3104 #define SCI_CONSOLE NULL 3105 3106 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3107 3108 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3109 3110 static DEFINE_MUTEX(sci_uart_registration_lock); 3111 static struct uart_driver sci_uart_driver = { 3112 .owner = THIS_MODULE, 3113 .driver_name = "sci", 3114 .dev_name = "ttySC", 3115 .major = SCI_MAJOR, 3116 .minor = SCI_MINOR_START, 3117 .nr = SCI_NPORTS, 3118 .cons = SCI_CONSOLE, 3119 }; 3120 3121 static int sci_remove(struct platform_device *dev) 3122 { 3123 struct sci_port *port = platform_get_drvdata(dev); 3124 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3125 3126 sci_ports_in_use &= ~BIT(port->port.line); 3127 uart_remove_one_port(&sci_uart_driver, &port->port); 3128 3129 sci_cleanup_single(port); 3130 3131 if (port->port.fifosize > 1) 3132 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3133 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3134 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3135 3136 return 0; 3137 } 3138 3139 3140 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3141 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3142 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3143 3144 static const struct of_device_id of_sci_match[] = { 3145 /* SoC-specific types */ 3146 { 3147 .compatible = "renesas,scif-r7s72100", 3148 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3149 }, 3150 { 3151 .compatible = "renesas,scif-r7s9210", 3152 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3153 }, 3154 { 3155 .compatible = "renesas,scif-r9a07g044", 3156 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3157 }, 3158 /* Family-specific types */ 3159 { 3160 .compatible = "renesas,rcar-gen1-scif", 3161 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3162 }, { 3163 .compatible = "renesas,rcar-gen2-scif", 3164 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3165 }, { 3166 .compatible = "renesas,rcar-gen3-scif", 3167 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3168 }, { 3169 .compatible = "renesas,rcar-gen4-scif", 3170 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3171 }, 3172 /* Generic types */ 3173 { 3174 .compatible = "renesas,scif", 3175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3176 }, { 3177 .compatible = "renesas,scifa", 3178 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3179 }, { 3180 .compatible = "renesas,scifb", 3181 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3182 }, { 3183 .compatible = "renesas,hscif", 3184 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3185 }, { 3186 .compatible = "renesas,sci", 3187 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3188 }, { 3189 /* Terminator */ 3190 }, 3191 }; 3192 MODULE_DEVICE_TABLE(of, of_sci_match); 3193 3194 static void sci_reset_control_assert(void *data) 3195 { 3196 reset_control_assert(data); 3197 } 3198 3199 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3200 unsigned int *dev_id) 3201 { 3202 struct device_node *np = pdev->dev.of_node; 3203 struct reset_control *rstc; 3204 struct plat_sci_port *p; 3205 struct sci_port *sp; 3206 const void *data; 3207 int id, ret; 3208 3209 if (!IS_ENABLED(CONFIG_OF) || !np) 3210 return ERR_PTR(-EINVAL); 3211 3212 data = of_device_get_match_data(&pdev->dev); 3213 3214 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3215 if (IS_ERR(rstc)) 3216 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3217 "failed to get reset ctrl\n")); 3218 3219 ret = reset_control_deassert(rstc); 3220 if (ret) { 3221 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3222 return ERR_PTR(ret); 3223 } 3224 3225 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3226 if (ret) { 3227 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3228 ret); 3229 return ERR_PTR(ret); 3230 } 3231 3232 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3233 if (!p) 3234 return ERR_PTR(-ENOMEM); 3235 3236 /* Get the line number from the aliases node. */ 3237 id = of_alias_get_id(np, "serial"); 3238 if (id < 0 && ~sci_ports_in_use) 3239 id = ffz(sci_ports_in_use); 3240 if (id < 0) { 3241 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3242 return ERR_PTR(-EINVAL); 3243 } 3244 if (id >= ARRAY_SIZE(sci_ports)) { 3245 dev_err(&pdev->dev, "serial%d out of range\n", id); 3246 return ERR_PTR(-EINVAL); 3247 } 3248 3249 sp = &sci_ports[id]; 3250 *dev_id = id; 3251 3252 p->type = SCI_OF_TYPE(data); 3253 p->regtype = SCI_OF_REGTYPE(data); 3254 3255 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3256 3257 return p; 3258 } 3259 3260 static int sci_probe_single(struct platform_device *dev, 3261 unsigned int index, 3262 struct plat_sci_port *p, 3263 struct sci_port *sciport) 3264 { 3265 int ret; 3266 3267 /* Sanity check */ 3268 if (unlikely(index >= SCI_NPORTS)) { 3269 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3270 index+1, SCI_NPORTS); 3271 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3272 return -EINVAL; 3273 } 3274 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3275 if (sci_ports_in_use & BIT(index)) 3276 return -EBUSY; 3277 3278 mutex_lock(&sci_uart_registration_lock); 3279 if (!sci_uart_driver.state) { 3280 ret = uart_register_driver(&sci_uart_driver); 3281 if (ret) { 3282 mutex_unlock(&sci_uart_registration_lock); 3283 return ret; 3284 } 3285 } 3286 mutex_unlock(&sci_uart_registration_lock); 3287 3288 ret = sci_init_single(dev, sciport, index, p, false); 3289 if (ret) 3290 return ret; 3291 3292 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3293 if (IS_ERR(sciport->gpios)) 3294 return PTR_ERR(sciport->gpios); 3295 3296 if (sciport->has_rtscts) { 3297 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3298 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3299 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3300 return -EINVAL; 3301 } 3302 sciport->port.flags |= UPF_HARD_FLOW; 3303 } 3304 3305 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3306 if (ret) { 3307 sci_cleanup_single(sciport); 3308 return ret; 3309 } 3310 3311 return 0; 3312 } 3313 3314 static int sci_probe(struct platform_device *dev) 3315 { 3316 struct plat_sci_port *p; 3317 struct sci_port *sp; 3318 unsigned int dev_id; 3319 int ret; 3320 3321 /* 3322 * If we've come here via earlyprintk initialization, head off to 3323 * the special early probe. We don't have sufficient device state 3324 * to make it beyond this yet. 3325 */ 3326 #ifdef CONFIG_SUPERH 3327 if (is_sh_early_platform_device(dev)) 3328 return sci_probe_earlyprintk(dev); 3329 #endif 3330 3331 if (dev->dev.of_node) { 3332 p = sci_parse_dt(dev, &dev_id); 3333 if (IS_ERR(p)) 3334 return PTR_ERR(p); 3335 } else { 3336 p = dev->dev.platform_data; 3337 if (p == NULL) { 3338 dev_err(&dev->dev, "no platform data supplied\n"); 3339 return -EINVAL; 3340 } 3341 3342 dev_id = dev->id; 3343 } 3344 3345 sp = &sci_ports[dev_id]; 3346 platform_set_drvdata(dev, sp); 3347 3348 ret = sci_probe_single(dev, dev_id, p, sp); 3349 if (ret) 3350 return ret; 3351 3352 if (sp->port.fifosize > 1) { 3353 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3354 if (ret) 3355 return ret; 3356 } 3357 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3358 sp->port.type == PORT_HSCIF) { 3359 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3360 if (ret) { 3361 if (sp->port.fifosize > 1) { 3362 device_remove_file(&dev->dev, 3363 &dev_attr_rx_fifo_trigger); 3364 } 3365 return ret; 3366 } 3367 } 3368 3369 #ifdef CONFIG_SH_STANDARD_BIOS 3370 sh_bios_gdb_detach(); 3371 #endif 3372 3373 sci_ports_in_use |= BIT(dev_id); 3374 return 0; 3375 } 3376 3377 static __maybe_unused int sci_suspend(struct device *dev) 3378 { 3379 struct sci_port *sport = dev_get_drvdata(dev); 3380 3381 if (sport) 3382 uart_suspend_port(&sci_uart_driver, &sport->port); 3383 3384 return 0; 3385 } 3386 3387 static __maybe_unused int sci_resume(struct device *dev) 3388 { 3389 struct sci_port *sport = dev_get_drvdata(dev); 3390 3391 if (sport) 3392 uart_resume_port(&sci_uart_driver, &sport->port); 3393 3394 return 0; 3395 } 3396 3397 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3398 3399 static struct platform_driver sci_driver = { 3400 .probe = sci_probe, 3401 .remove = sci_remove, 3402 .driver = { 3403 .name = "sh-sci", 3404 .pm = &sci_dev_pm_ops, 3405 .of_match_table = of_match_ptr(of_sci_match), 3406 }, 3407 }; 3408 3409 static int __init sci_init(void) 3410 { 3411 pr_info("%s\n", banner); 3412 3413 return platform_driver_register(&sci_driver); 3414 } 3415 3416 static void __exit sci_exit(void) 3417 { 3418 platform_driver_unregister(&sci_driver); 3419 3420 if (sci_uart_driver.state) 3421 uart_unregister_driver(&sci_uart_driver); 3422 } 3423 3424 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3425 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3426 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3427 #endif 3428 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3429 static struct plat_sci_port port_cfg __initdata; 3430 3431 static int __init early_console_setup(struct earlycon_device *device, 3432 int type) 3433 { 3434 if (!device->port.membase) 3435 return -ENODEV; 3436 3437 device->port.serial_in = sci_serial_in; 3438 device->port.serial_out = sci_serial_out; 3439 device->port.type = type; 3440 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3441 port_cfg.type = type; 3442 sci_ports[0].cfg = &port_cfg; 3443 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3444 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3445 sci_serial_out(&sci_ports[0].port, SCSCR, 3446 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3447 3448 device->con->write = serial_console_write; 3449 return 0; 3450 } 3451 static int __init sci_early_console_setup(struct earlycon_device *device, 3452 const char *opt) 3453 { 3454 return early_console_setup(device, PORT_SCI); 3455 } 3456 static int __init scif_early_console_setup(struct earlycon_device *device, 3457 const char *opt) 3458 { 3459 return early_console_setup(device, PORT_SCIF); 3460 } 3461 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3462 const char *opt) 3463 { 3464 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3465 return early_console_setup(device, PORT_SCIF); 3466 } 3467 3468 static int __init scifa_early_console_setup(struct earlycon_device *device, 3469 const char *opt) 3470 { 3471 return early_console_setup(device, PORT_SCIFA); 3472 } 3473 static int __init scifb_early_console_setup(struct earlycon_device *device, 3474 const char *opt) 3475 { 3476 return early_console_setup(device, PORT_SCIFB); 3477 } 3478 static int __init hscif_early_console_setup(struct earlycon_device *device, 3479 const char *opt) 3480 { 3481 return early_console_setup(device, PORT_HSCIF); 3482 } 3483 3484 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3485 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3486 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3487 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3488 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3489 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3490 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3491 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3492 3493 module_init(sci_init); 3494 module_exit(sci_exit); 3495 3496 MODULE_LICENSE("GPL"); 3497 MODULE_ALIAS("platform:sh-sci"); 3498 MODULE_AUTHOR("Paul Mundt"); 3499 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3500