1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/timer.h> 29 #include <linux/interrupt.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial.h> 33 #include <linux/major.h> 34 #include <linux/string.h> 35 #include <linux/sysrq.h> 36 #include <linux/ioport.h> 37 #include <linux/mm.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/console.h> 41 #include <linux/platform_device.h> 42 #include <linux/serial_sci.h> 43 #include <linux/notifier.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/cpufreq.h> 46 #include <linux/clk.h> 47 #include <linux/ctype.h> 48 #include <linux/err.h> 49 #include <linux/dmaengine.h> 50 #include <linux/scatterlist.h> 51 #include <linux/slab.h> 52 53 #ifdef CONFIG_SUPERH 54 #include <asm/sh_bios.h> 55 #endif 56 57 #include "sh-sci.h" 58 59 struct sci_port { 60 struct uart_port port; 61 62 /* Platform configuration */ 63 struct plat_sci_port *cfg; 64 65 /* Break timer */ 66 struct timer_list break_timer; 67 int break_flag; 68 69 /* Interface clock */ 70 struct clk *iclk; 71 /* Function clock */ 72 struct clk *fclk; 73 74 struct dma_chan *chan_tx; 75 struct dma_chan *chan_rx; 76 77 #ifdef CONFIG_SERIAL_SH_SCI_DMA 78 struct dma_async_tx_descriptor *desc_tx; 79 struct dma_async_tx_descriptor *desc_rx[2]; 80 dma_cookie_t cookie_tx; 81 dma_cookie_t cookie_rx[2]; 82 dma_cookie_t active_rx; 83 struct scatterlist sg_tx; 84 unsigned int sg_len_tx; 85 struct scatterlist sg_rx[2]; 86 size_t buf_len_rx; 87 struct sh_dmae_slave param_tx; 88 struct sh_dmae_slave param_rx; 89 struct work_struct work_tx; 90 struct work_struct work_rx; 91 struct timer_list rx_timer; 92 unsigned int rx_timeout; 93 #endif 94 95 struct notifier_block freq_transition; 96 }; 97 98 /* Function prototypes */ 99 static void sci_start_tx(struct uart_port *port); 100 static void sci_stop_tx(struct uart_port *port); 101 static void sci_start_rx(struct uart_port *port); 102 103 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 104 105 static struct sci_port sci_ports[SCI_NPORTS]; 106 static struct uart_driver sci_uart_driver; 107 108 static inline struct sci_port * 109 to_sci_port(struct uart_port *uart) 110 { 111 return container_of(uart, struct sci_port, port); 112 } 113 114 struct plat_sci_reg { 115 u8 offset, size; 116 }; 117 118 /* Helper for invalidating specific entries of an inherited map. */ 119 #define sci_reg_invalid { .offset = 0, .size = 0 } 120 121 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 122 [SCIx_PROBE_REGTYPE] = { 123 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 124 }, 125 126 /* 127 * Common SCI definitions, dependent on the port's regshift 128 * value. 129 */ 130 [SCIx_SCI_REGTYPE] = { 131 [SCSMR] = { 0x00, 8 }, 132 [SCBRR] = { 0x01, 8 }, 133 [SCSCR] = { 0x02, 8 }, 134 [SCxTDR] = { 0x03, 8 }, 135 [SCxSR] = { 0x04, 8 }, 136 [SCxRDR] = { 0x05, 8 }, 137 [SCFCR] = sci_reg_invalid, 138 [SCFDR] = sci_reg_invalid, 139 [SCTFDR] = sci_reg_invalid, 140 [SCRFDR] = sci_reg_invalid, 141 [SCSPTR] = sci_reg_invalid, 142 [SCLSR] = sci_reg_invalid, 143 }, 144 145 /* 146 * Common definitions for legacy IrDA ports, dependent on 147 * regshift value. 148 */ 149 [SCIx_IRDA_REGTYPE] = { 150 [SCSMR] = { 0x00, 8 }, 151 [SCBRR] = { 0x01, 8 }, 152 [SCSCR] = { 0x02, 8 }, 153 [SCxTDR] = { 0x03, 8 }, 154 [SCxSR] = { 0x04, 8 }, 155 [SCxRDR] = { 0x05, 8 }, 156 [SCFCR] = { 0x06, 8 }, 157 [SCFDR] = { 0x07, 16 }, 158 [SCTFDR] = sci_reg_invalid, 159 [SCRFDR] = sci_reg_invalid, 160 [SCSPTR] = sci_reg_invalid, 161 [SCLSR] = sci_reg_invalid, 162 }, 163 164 /* 165 * Common SCIFA definitions. 166 */ 167 [SCIx_SCIFA_REGTYPE] = { 168 [SCSMR] = { 0x00, 16 }, 169 [SCBRR] = { 0x04, 8 }, 170 [SCSCR] = { 0x08, 16 }, 171 [SCxTDR] = { 0x20, 8 }, 172 [SCxSR] = { 0x14, 16 }, 173 [SCxRDR] = { 0x24, 8 }, 174 [SCFCR] = { 0x18, 16 }, 175 [SCFDR] = { 0x1c, 16 }, 176 [SCTFDR] = sci_reg_invalid, 177 [SCRFDR] = sci_reg_invalid, 178 [SCSPTR] = sci_reg_invalid, 179 [SCLSR] = sci_reg_invalid, 180 }, 181 182 /* 183 * Common SCIFB definitions. 184 */ 185 [SCIx_SCIFB_REGTYPE] = { 186 [SCSMR] = { 0x00, 16 }, 187 [SCBRR] = { 0x04, 8 }, 188 [SCSCR] = { 0x08, 16 }, 189 [SCxTDR] = { 0x40, 8 }, 190 [SCxSR] = { 0x14, 16 }, 191 [SCxRDR] = { 0x60, 8 }, 192 [SCFCR] = { 0x18, 16 }, 193 [SCFDR] = { 0x1c, 16 }, 194 [SCTFDR] = sci_reg_invalid, 195 [SCRFDR] = sci_reg_invalid, 196 [SCSPTR] = sci_reg_invalid, 197 [SCLSR] = sci_reg_invalid, 198 }, 199 200 /* 201 * Common SH-3 SCIF definitions. 202 */ 203 [SCIx_SH3_SCIF_REGTYPE] = { 204 [SCSMR] = { 0x00, 8 }, 205 [SCBRR] = { 0x02, 8 }, 206 [SCSCR] = { 0x04, 8 }, 207 [SCxTDR] = { 0x06, 8 }, 208 [SCxSR] = { 0x08, 16 }, 209 [SCxRDR] = { 0x0a, 8 }, 210 [SCFCR] = { 0x0c, 8 }, 211 [SCFDR] = { 0x0e, 16 }, 212 [SCTFDR] = sci_reg_invalid, 213 [SCRFDR] = sci_reg_invalid, 214 [SCSPTR] = sci_reg_invalid, 215 [SCLSR] = sci_reg_invalid, 216 }, 217 218 /* 219 * Common SH-4(A) SCIF(B) definitions. 220 */ 221 [SCIx_SH4_SCIF_REGTYPE] = { 222 [SCSMR] = { 0x00, 16 }, 223 [SCBRR] = { 0x04, 8 }, 224 [SCSCR] = { 0x08, 16 }, 225 [SCxTDR] = { 0x0c, 8 }, 226 [SCxSR] = { 0x10, 16 }, 227 [SCxRDR] = { 0x14, 8 }, 228 [SCFCR] = { 0x18, 16 }, 229 [SCFDR] = { 0x1c, 16 }, 230 [SCTFDR] = sci_reg_invalid, 231 [SCRFDR] = sci_reg_invalid, 232 [SCSPTR] = { 0x20, 16 }, 233 [SCLSR] = { 0x24, 16 }, 234 }, 235 236 /* 237 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 238 * register. 239 */ 240 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 241 [SCSMR] = { 0x00, 16 }, 242 [SCBRR] = { 0x04, 8 }, 243 [SCSCR] = { 0x08, 16 }, 244 [SCxTDR] = { 0x0c, 8 }, 245 [SCxSR] = { 0x10, 16 }, 246 [SCxRDR] = { 0x14, 8 }, 247 [SCFCR] = { 0x18, 16 }, 248 [SCFDR] = { 0x1c, 16 }, 249 [SCTFDR] = sci_reg_invalid, 250 [SCRFDR] = sci_reg_invalid, 251 [SCSPTR] = sci_reg_invalid, 252 [SCLSR] = { 0x24, 16 }, 253 }, 254 255 /* 256 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 257 * count registers. 258 */ 259 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 260 [SCSMR] = { 0x00, 16 }, 261 [SCBRR] = { 0x04, 8 }, 262 [SCSCR] = { 0x08, 16 }, 263 [SCxTDR] = { 0x0c, 8 }, 264 [SCxSR] = { 0x10, 16 }, 265 [SCxRDR] = { 0x14, 8 }, 266 [SCFCR] = { 0x18, 16 }, 267 [SCFDR] = { 0x1c, 16 }, 268 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 269 [SCRFDR] = { 0x20, 16 }, 270 [SCSPTR] = { 0x24, 16 }, 271 [SCLSR] = { 0x28, 16 }, 272 }, 273 274 /* 275 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 276 * registers. 277 */ 278 [SCIx_SH7705_SCIF_REGTYPE] = { 279 [SCSMR] = { 0x00, 16 }, 280 [SCBRR] = { 0x04, 8 }, 281 [SCSCR] = { 0x08, 16 }, 282 [SCxTDR] = { 0x20, 8 }, 283 [SCxSR] = { 0x14, 16 }, 284 [SCxRDR] = { 0x24, 8 }, 285 [SCFCR] = { 0x18, 16 }, 286 [SCFDR] = { 0x1c, 16 }, 287 [SCTFDR] = sci_reg_invalid, 288 [SCRFDR] = sci_reg_invalid, 289 [SCSPTR] = sci_reg_invalid, 290 [SCLSR] = sci_reg_invalid, 291 }, 292 }; 293 294 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 295 296 /* 297 * The "offset" here is rather misleading, in that it refers to an enum 298 * value relative to the port mapping rather than the fixed offset 299 * itself, which needs to be manually retrieved from the platform's 300 * register map for the given port. 301 */ 302 static unsigned int sci_serial_in(struct uart_port *p, int offset) 303 { 304 struct plat_sci_reg *reg = sci_getreg(p, offset); 305 306 if (reg->size == 8) 307 return ioread8(p->membase + (reg->offset << p->regshift)); 308 else if (reg->size == 16) 309 return ioread16(p->membase + (reg->offset << p->regshift)); 310 else 311 WARN(1, "Invalid register access\n"); 312 313 return 0; 314 } 315 316 static void sci_serial_out(struct uart_port *p, int offset, int value) 317 { 318 struct plat_sci_reg *reg = sci_getreg(p, offset); 319 320 if (reg->size == 8) 321 iowrite8(value, p->membase + (reg->offset << p->regshift)); 322 else if (reg->size == 16) 323 iowrite16(value, p->membase + (reg->offset << p->regshift)); 324 else 325 WARN(1, "Invalid register access\n"); 326 } 327 328 #define sci_in(up, offset) (up->serial_in(up, offset)) 329 #define sci_out(up, offset, value) (up->serial_out(up, offset, value)) 330 331 static int sci_probe_regmap(struct plat_sci_port *cfg) 332 { 333 switch (cfg->type) { 334 case PORT_SCI: 335 cfg->regtype = SCIx_SCI_REGTYPE; 336 break; 337 case PORT_IRDA: 338 cfg->regtype = SCIx_IRDA_REGTYPE; 339 break; 340 case PORT_SCIFA: 341 cfg->regtype = SCIx_SCIFA_REGTYPE; 342 break; 343 case PORT_SCIFB: 344 cfg->regtype = SCIx_SCIFB_REGTYPE; 345 break; 346 case PORT_SCIF: 347 /* 348 * The SH-4 is a bit of a misnomer here, although that's 349 * where this particular port layout originated. This 350 * configuration (or some slight variation thereof) 351 * remains the dominant model for all SCIFs. 352 */ 353 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 354 break; 355 default: 356 printk(KERN_ERR "Can't probe register map for given port\n"); 357 return -EINVAL; 358 } 359 360 return 0; 361 } 362 363 static void sci_port_enable(struct sci_port *sci_port) 364 { 365 if (!sci_port->port.dev) 366 return; 367 368 pm_runtime_get_sync(sci_port->port.dev); 369 370 clk_enable(sci_port->iclk); 371 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 372 clk_enable(sci_port->fclk); 373 } 374 375 static void sci_port_disable(struct sci_port *sci_port) 376 { 377 if (!sci_port->port.dev) 378 return; 379 380 clk_disable(sci_port->fclk); 381 clk_disable(sci_port->iclk); 382 383 pm_runtime_put_sync(sci_port->port.dev); 384 } 385 386 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 387 388 #ifdef CONFIG_CONSOLE_POLL 389 static int sci_poll_get_char(struct uart_port *port) 390 { 391 unsigned short status; 392 int c; 393 394 do { 395 status = sci_in(port, SCxSR); 396 if (status & SCxSR_ERRORS(port)) { 397 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 398 continue; 399 } 400 break; 401 } while (1); 402 403 if (!(status & SCxSR_RDxF(port))) 404 return NO_POLL_CHAR; 405 406 c = sci_in(port, SCxRDR); 407 408 /* Dummy read */ 409 sci_in(port, SCxSR); 410 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 411 412 return c; 413 } 414 #endif 415 416 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 417 { 418 unsigned short status; 419 420 do { 421 status = sci_in(port, SCxSR); 422 } while (!(status & SCxSR_TDxE(port))); 423 424 sci_out(port, SCxTDR, c); 425 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 426 } 427 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 428 429 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 430 { 431 struct sci_port *s = to_sci_port(port); 432 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 433 434 /* 435 * Use port-specific handler if provided. 436 */ 437 if (s->cfg->ops && s->cfg->ops->init_pins) { 438 s->cfg->ops->init_pins(port, cflag); 439 return; 440 } 441 442 /* 443 * For the generic path SCSPTR is necessary. Bail out if that's 444 * unavailable, too. 445 */ 446 if (!reg->size) 447 return; 448 449 if (!(cflag & CRTSCTS)) 450 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */ 451 } 452 453 static int sci_txfill(struct uart_port *port) 454 { 455 struct plat_sci_reg *reg; 456 457 reg = sci_getreg(port, SCTFDR); 458 if (reg->size) 459 return sci_in(port, SCTFDR) & 0xff; 460 461 reg = sci_getreg(port, SCFDR); 462 if (reg->size) 463 return sci_in(port, SCFDR) >> 8; 464 465 return !(sci_in(port, SCxSR) & SCI_TDRE); 466 } 467 468 static int sci_txroom(struct uart_port *port) 469 { 470 return port->fifosize - sci_txfill(port); 471 } 472 473 static int sci_rxfill(struct uart_port *port) 474 { 475 struct plat_sci_reg *reg; 476 477 reg = sci_getreg(port, SCRFDR); 478 if (reg->size) 479 return sci_in(port, SCRFDR) & 0xff; 480 481 reg = sci_getreg(port, SCFDR); 482 if (reg->size) 483 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1); 484 485 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 486 } 487 488 /* 489 * SCI helper for checking the state of the muxed port/RXD pins. 490 */ 491 static inline int sci_rxd_in(struct uart_port *port) 492 { 493 struct sci_port *s = to_sci_port(port); 494 495 if (s->cfg->port_reg <= 0) 496 return 1; 497 498 return !!__raw_readb(s->cfg->port_reg); 499 } 500 501 /* ********************************************************************** * 502 * the interrupt related routines * 503 * ********************************************************************** */ 504 505 static void sci_transmit_chars(struct uart_port *port) 506 { 507 struct circ_buf *xmit = &port->state->xmit; 508 unsigned int stopped = uart_tx_stopped(port); 509 unsigned short status; 510 unsigned short ctrl; 511 int count; 512 513 status = sci_in(port, SCxSR); 514 if (!(status & SCxSR_TDxE(port))) { 515 ctrl = sci_in(port, SCSCR); 516 if (uart_circ_empty(xmit)) 517 ctrl &= ~SCSCR_TIE; 518 else 519 ctrl |= SCSCR_TIE; 520 sci_out(port, SCSCR, ctrl); 521 return; 522 } 523 524 count = sci_txroom(port); 525 526 do { 527 unsigned char c; 528 529 if (port->x_char) { 530 c = port->x_char; 531 port->x_char = 0; 532 } else if (!uart_circ_empty(xmit) && !stopped) { 533 c = xmit->buf[xmit->tail]; 534 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 535 } else { 536 break; 537 } 538 539 sci_out(port, SCxTDR, c); 540 541 port->icount.tx++; 542 } while (--count > 0); 543 544 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 545 546 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 547 uart_write_wakeup(port); 548 if (uart_circ_empty(xmit)) { 549 sci_stop_tx(port); 550 } else { 551 ctrl = sci_in(port, SCSCR); 552 553 if (port->type != PORT_SCI) { 554 sci_in(port, SCxSR); /* Dummy read */ 555 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 556 } 557 558 ctrl |= SCSCR_TIE; 559 sci_out(port, SCSCR, ctrl); 560 } 561 } 562 563 /* On SH3, SCIF may read end-of-break as a space->mark char */ 564 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 565 566 static void sci_receive_chars(struct uart_port *port) 567 { 568 struct sci_port *sci_port = to_sci_port(port); 569 struct tty_struct *tty = port->state->port.tty; 570 int i, count, copied = 0; 571 unsigned short status; 572 unsigned char flag; 573 574 status = sci_in(port, SCxSR); 575 if (!(status & SCxSR_RDxF(port))) 576 return; 577 578 while (1) { 579 /* Don't copy more bytes than there is room for in the buffer */ 580 count = tty_buffer_request_room(tty, sci_rxfill(port)); 581 582 /* If for any reason we can't copy more data, we're done! */ 583 if (count == 0) 584 break; 585 586 if (port->type == PORT_SCI) { 587 char c = sci_in(port, SCxRDR); 588 if (uart_handle_sysrq_char(port, c) || 589 sci_port->break_flag) 590 count = 0; 591 else 592 tty_insert_flip_char(tty, c, TTY_NORMAL); 593 } else { 594 for (i = 0; i < count; i++) { 595 char c = sci_in(port, SCxRDR); 596 status = sci_in(port, SCxSR); 597 #if defined(CONFIG_CPU_SH3) 598 /* Skip "chars" during break */ 599 if (sci_port->break_flag) { 600 if ((c == 0) && 601 (status & SCxSR_FER(port))) { 602 count--; i--; 603 continue; 604 } 605 606 /* Nonzero => end-of-break */ 607 dev_dbg(port->dev, "debounce<%02x>\n", c); 608 sci_port->break_flag = 0; 609 610 if (STEPFN(c)) { 611 count--; i--; 612 continue; 613 } 614 } 615 #endif /* CONFIG_CPU_SH3 */ 616 if (uart_handle_sysrq_char(port, c)) { 617 count--; i--; 618 continue; 619 } 620 621 /* Store data and status */ 622 if (status & SCxSR_FER(port)) { 623 flag = TTY_FRAME; 624 dev_notice(port->dev, "frame error\n"); 625 } else if (status & SCxSR_PER(port)) { 626 flag = TTY_PARITY; 627 dev_notice(port->dev, "parity error\n"); 628 } else 629 flag = TTY_NORMAL; 630 631 tty_insert_flip_char(tty, c, flag); 632 } 633 } 634 635 sci_in(port, SCxSR); /* dummy read */ 636 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 637 638 copied += count; 639 port->icount.rx += count; 640 } 641 642 if (copied) { 643 /* Tell the rest of the system the news. New characters! */ 644 tty_flip_buffer_push(tty); 645 } else { 646 sci_in(port, SCxSR); /* dummy read */ 647 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 648 } 649 } 650 651 #define SCI_BREAK_JIFFIES (HZ/20) 652 653 /* 654 * The sci generates interrupts during the break, 655 * 1 per millisecond or so during the break period, for 9600 baud. 656 * So dont bother disabling interrupts. 657 * But dont want more than 1 break event. 658 * Use a kernel timer to periodically poll the rx line until 659 * the break is finished. 660 */ 661 static inline void sci_schedule_break_timer(struct sci_port *port) 662 { 663 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 664 } 665 666 /* Ensure that two consecutive samples find the break over. */ 667 static void sci_break_timer(unsigned long data) 668 { 669 struct sci_port *port = (struct sci_port *)data; 670 671 sci_port_enable(port); 672 673 if (sci_rxd_in(&port->port) == 0) { 674 port->break_flag = 1; 675 sci_schedule_break_timer(port); 676 } else if (port->break_flag == 1) { 677 /* break is over. */ 678 port->break_flag = 2; 679 sci_schedule_break_timer(port); 680 } else 681 port->break_flag = 0; 682 683 sci_port_disable(port); 684 } 685 686 static int sci_handle_errors(struct uart_port *port) 687 { 688 int copied = 0; 689 unsigned short status = sci_in(port, SCxSR); 690 struct tty_struct *tty = port->state->port.tty; 691 struct sci_port *s = to_sci_port(port); 692 693 /* 694 * Handle overruns, if supported. 695 */ 696 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 697 if (status & (1 << s->cfg->overrun_bit)) { 698 /* overrun error */ 699 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 700 copied++; 701 702 dev_notice(port->dev, "overrun error"); 703 } 704 } 705 706 if (status & SCxSR_FER(port)) { 707 if (sci_rxd_in(port) == 0) { 708 /* Notify of BREAK */ 709 struct sci_port *sci_port = to_sci_port(port); 710 711 if (!sci_port->break_flag) { 712 sci_port->break_flag = 1; 713 sci_schedule_break_timer(sci_port); 714 715 /* Do sysrq handling. */ 716 if (uart_handle_break(port)) 717 return 0; 718 719 dev_dbg(port->dev, "BREAK detected\n"); 720 721 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 722 copied++; 723 } 724 725 } else { 726 /* frame error */ 727 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 728 copied++; 729 730 dev_notice(port->dev, "frame error\n"); 731 } 732 } 733 734 if (status & SCxSR_PER(port)) { 735 /* parity error */ 736 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 737 copied++; 738 739 dev_notice(port->dev, "parity error"); 740 } 741 742 if (copied) 743 tty_flip_buffer_push(tty); 744 745 return copied; 746 } 747 748 static int sci_handle_fifo_overrun(struct uart_port *port) 749 { 750 struct tty_struct *tty = port->state->port.tty; 751 struct sci_port *s = to_sci_port(port); 752 struct plat_sci_reg *reg; 753 int copied = 0; 754 755 reg = sci_getreg(port, SCLSR); 756 if (!reg->size) 757 return 0; 758 759 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 760 sci_out(port, SCLSR, 0); 761 762 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 763 tty_flip_buffer_push(tty); 764 765 dev_notice(port->dev, "overrun error\n"); 766 copied++; 767 } 768 769 return copied; 770 } 771 772 static int sci_handle_breaks(struct uart_port *port) 773 { 774 int copied = 0; 775 unsigned short status = sci_in(port, SCxSR); 776 struct tty_struct *tty = port->state->port.tty; 777 struct sci_port *s = to_sci_port(port); 778 779 if (uart_handle_break(port)) 780 return 0; 781 782 if (!s->break_flag && status & SCxSR_BRK(port)) { 783 #if defined(CONFIG_CPU_SH3) 784 /* Debounce break */ 785 s->break_flag = 1; 786 #endif 787 /* Notify of BREAK */ 788 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 789 copied++; 790 791 dev_dbg(port->dev, "BREAK detected\n"); 792 } 793 794 if (copied) 795 tty_flip_buffer_push(tty); 796 797 copied += sci_handle_fifo_overrun(port); 798 799 return copied; 800 } 801 802 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 803 { 804 #ifdef CONFIG_SERIAL_SH_SCI_DMA 805 struct uart_port *port = ptr; 806 struct sci_port *s = to_sci_port(port); 807 808 if (s->chan_rx) { 809 u16 scr = sci_in(port, SCSCR); 810 u16 ssr = sci_in(port, SCxSR); 811 812 /* Disable future Rx interrupts */ 813 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 814 disable_irq_nosync(irq); 815 scr |= 0x4000; 816 } else { 817 scr &= ~SCSCR_RIE; 818 } 819 sci_out(port, SCSCR, scr); 820 /* Clear current interrupt */ 821 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 822 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 823 jiffies, s->rx_timeout); 824 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 825 826 return IRQ_HANDLED; 827 } 828 #endif 829 830 /* I think sci_receive_chars has to be called irrespective 831 * of whether the I_IXOFF is set, otherwise, how is the interrupt 832 * to be disabled? 833 */ 834 sci_receive_chars(ptr); 835 836 return IRQ_HANDLED; 837 } 838 839 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 840 { 841 struct uart_port *port = ptr; 842 unsigned long flags; 843 844 spin_lock_irqsave(&port->lock, flags); 845 sci_transmit_chars(port); 846 spin_unlock_irqrestore(&port->lock, flags); 847 848 return IRQ_HANDLED; 849 } 850 851 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 852 { 853 struct uart_port *port = ptr; 854 855 /* Handle errors */ 856 if (port->type == PORT_SCI) { 857 if (sci_handle_errors(port)) { 858 /* discard character in rx buffer */ 859 sci_in(port, SCxSR); 860 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 861 } 862 } else { 863 sci_handle_fifo_overrun(port); 864 sci_rx_interrupt(irq, ptr); 865 } 866 867 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 868 869 /* Kick the transmission */ 870 sci_tx_interrupt(irq, ptr); 871 872 return IRQ_HANDLED; 873 } 874 875 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 876 { 877 struct uart_port *port = ptr; 878 879 /* Handle BREAKs */ 880 sci_handle_breaks(port); 881 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 882 883 return IRQ_HANDLED; 884 } 885 886 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 887 { 888 /* 889 * Not all ports (such as SCIFA) will support REIE. Rather than 890 * special-casing the port type, we check the port initialization 891 * IRQ enable mask to see whether the IRQ is desired at all. If 892 * it's unset, it's logically inferred that there's no point in 893 * testing for it. 894 */ 895 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 896 } 897 898 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 899 { 900 unsigned short ssr_status, scr_status, err_enabled; 901 struct uart_port *port = ptr; 902 struct sci_port *s = to_sci_port(port); 903 irqreturn_t ret = IRQ_NONE; 904 905 ssr_status = sci_in(port, SCxSR); 906 scr_status = sci_in(port, SCSCR); 907 err_enabled = scr_status & port_rx_irq_mask(port); 908 909 /* Tx Interrupt */ 910 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 911 !s->chan_tx) 912 ret = sci_tx_interrupt(irq, ptr); 913 914 /* 915 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 916 * DR flags 917 */ 918 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 919 (scr_status & SCSCR_RIE)) 920 ret = sci_rx_interrupt(irq, ptr); 921 922 /* Error Interrupt */ 923 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 924 ret = sci_er_interrupt(irq, ptr); 925 926 /* Break Interrupt */ 927 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 928 ret = sci_br_interrupt(irq, ptr); 929 930 return ret; 931 } 932 933 /* 934 * Here we define a transition notifier so that we can update all of our 935 * ports' baud rate when the peripheral clock changes. 936 */ 937 static int sci_notifier(struct notifier_block *self, 938 unsigned long phase, void *p) 939 { 940 struct sci_port *sci_port; 941 unsigned long flags; 942 943 sci_port = container_of(self, struct sci_port, freq_transition); 944 945 if ((phase == CPUFREQ_POSTCHANGE) || 946 (phase == CPUFREQ_RESUMECHANGE)) { 947 struct uart_port *port = &sci_port->port; 948 949 spin_lock_irqsave(&port->lock, flags); 950 port->uartclk = clk_get_rate(sci_port->iclk); 951 spin_unlock_irqrestore(&port->lock, flags); 952 } 953 954 return NOTIFY_OK; 955 } 956 957 static int sci_request_irq(struct sci_port *port) 958 { 959 int i; 960 irqreturn_t (*handlers[4])(int irq, void *ptr) = { 961 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, 962 sci_br_interrupt, 963 }; 964 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", 965 "SCI Transmit Data Empty", "SCI Break" }; 966 967 if (port->cfg->irqs[0] == port->cfg->irqs[1]) { 968 if (unlikely(!port->cfg->irqs[0])) 969 return -ENODEV; 970 971 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt, 972 IRQF_DISABLED, "sci", port)) { 973 dev_err(port->port.dev, "Can't allocate IRQ\n"); 974 return -ENODEV; 975 } 976 } else { 977 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 978 if (unlikely(!port->cfg->irqs[i])) 979 continue; 980 981 if (request_irq(port->cfg->irqs[i], handlers[i], 982 IRQF_DISABLED, desc[i], port)) { 983 dev_err(port->port.dev, "Can't allocate IRQ\n"); 984 return -ENODEV; 985 } 986 } 987 } 988 989 return 0; 990 } 991 992 static void sci_free_irq(struct sci_port *port) 993 { 994 int i; 995 996 if (port->cfg->irqs[0] == port->cfg->irqs[1]) 997 free_irq(port->cfg->irqs[0], port); 998 else { 999 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) { 1000 if (!port->cfg->irqs[i]) 1001 continue; 1002 1003 free_irq(port->cfg->irqs[i], port); 1004 } 1005 } 1006 } 1007 1008 static unsigned int sci_tx_empty(struct uart_port *port) 1009 { 1010 unsigned short status = sci_in(port, SCxSR); 1011 unsigned short in_tx_fifo = sci_txfill(port); 1012 1013 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1014 } 1015 1016 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1017 { 1018 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ 1019 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ 1020 /* If you have signals for DTR and DCD, please implement here. */ 1021 } 1022 1023 static unsigned int sci_get_mctrl(struct uart_port *port) 1024 { 1025 /* This routine is used for getting signals of: DTR, DCD, DSR, RI, 1026 and CTS/RTS */ 1027 1028 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; 1029 } 1030 1031 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1032 static void sci_dma_tx_complete(void *arg) 1033 { 1034 struct sci_port *s = arg; 1035 struct uart_port *port = &s->port; 1036 struct circ_buf *xmit = &port->state->xmit; 1037 unsigned long flags; 1038 1039 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1040 1041 spin_lock_irqsave(&port->lock, flags); 1042 1043 xmit->tail += sg_dma_len(&s->sg_tx); 1044 xmit->tail &= UART_XMIT_SIZE - 1; 1045 1046 port->icount.tx += sg_dma_len(&s->sg_tx); 1047 1048 async_tx_ack(s->desc_tx); 1049 s->cookie_tx = -EINVAL; 1050 s->desc_tx = NULL; 1051 1052 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1053 uart_write_wakeup(port); 1054 1055 if (!uart_circ_empty(xmit)) { 1056 schedule_work(&s->work_tx); 1057 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1058 u16 ctrl = sci_in(port, SCSCR); 1059 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1060 } 1061 1062 spin_unlock_irqrestore(&port->lock, flags); 1063 } 1064 1065 /* Locking: called with port lock held */ 1066 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, 1067 size_t count) 1068 { 1069 struct uart_port *port = &s->port; 1070 int i, active, room; 1071 1072 room = tty_buffer_request_room(tty, count); 1073 1074 if (s->active_rx == s->cookie_rx[0]) { 1075 active = 0; 1076 } else if (s->active_rx == s->cookie_rx[1]) { 1077 active = 1; 1078 } else { 1079 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1080 return 0; 1081 } 1082 1083 if (room < count) 1084 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 1085 count - room); 1086 if (!room) 1087 return room; 1088 1089 for (i = 0; i < room; i++) 1090 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1091 TTY_NORMAL); 1092 1093 port->icount.rx += room; 1094 1095 return room; 1096 } 1097 1098 static void sci_dma_rx_complete(void *arg) 1099 { 1100 struct sci_port *s = arg; 1101 struct uart_port *port = &s->port; 1102 struct tty_struct *tty = port->state->port.tty; 1103 unsigned long flags; 1104 int count; 1105 1106 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1107 1108 spin_lock_irqsave(&port->lock, flags); 1109 1110 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 1111 1112 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1113 1114 spin_unlock_irqrestore(&port->lock, flags); 1115 1116 if (count) 1117 tty_flip_buffer_push(tty); 1118 1119 schedule_work(&s->work_rx); 1120 } 1121 1122 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1123 { 1124 struct dma_chan *chan = s->chan_rx; 1125 struct uart_port *port = &s->port; 1126 1127 s->chan_rx = NULL; 1128 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1129 dma_release_channel(chan); 1130 if (sg_dma_address(&s->sg_rx[0])) 1131 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1132 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1133 if (enable_pio) 1134 sci_start_rx(port); 1135 } 1136 1137 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1138 { 1139 struct dma_chan *chan = s->chan_tx; 1140 struct uart_port *port = &s->port; 1141 1142 s->chan_tx = NULL; 1143 s->cookie_tx = -EINVAL; 1144 dma_release_channel(chan); 1145 if (enable_pio) 1146 sci_start_tx(port); 1147 } 1148 1149 static void sci_submit_rx(struct sci_port *s) 1150 { 1151 struct dma_chan *chan = s->chan_rx; 1152 int i; 1153 1154 for (i = 0; i < 2; i++) { 1155 struct scatterlist *sg = &s->sg_rx[i]; 1156 struct dma_async_tx_descriptor *desc; 1157 1158 desc = chan->device->device_prep_slave_sg(chan, 1159 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); 1160 1161 if (desc) { 1162 s->desc_rx[i] = desc; 1163 desc->callback = sci_dma_rx_complete; 1164 desc->callback_param = s; 1165 s->cookie_rx[i] = desc->tx_submit(desc); 1166 } 1167 1168 if (!desc || s->cookie_rx[i] < 0) { 1169 if (i) { 1170 async_tx_ack(s->desc_rx[0]); 1171 s->cookie_rx[0] = -EINVAL; 1172 } 1173 if (desc) { 1174 async_tx_ack(desc); 1175 s->cookie_rx[i] = -EINVAL; 1176 } 1177 dev_warn(s->port.dev, 1178 "failed to re-start DMA, using PIO\n"); 1179 sci_rx_dma_release(s, true); 1180 return; 1181 } 1182 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1183 s->cookie_rx[i], i); 1184 } 1185 1186 s->active_rx = s->cookie_rx[0]; 1187 1188 dma_async_issue_pending(chan); 1189 } 1190 1191 static void work_fn_rx(struct work_struct *work) 1192 { 1193 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1194 struct uart_port *port = &s->port; 1195 struct dma_async_tx_descriptor *desc; 1196 int new; 1197 1198 if (s->active_rx == s->cookie_rx[0]) { 1199 new = 0; 1200 } else if (s->active_rx == s->cookie_rx[1]) { 1201 new = 1; 1202 } else { 1203 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1204 return; 1205 } 1206 desc = s->desc_rx[new]; 1207 1208 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1209 DMA_SUCCESS) { 1210 /* Handle incomplete DMA receive */ 1211 struct tty_struct *tty = port->state->port.tty; 1212 struct dma_chan *chan = s->chan_rx; 1213 struct sh_desc *sh_desc = container_of(desc, struct sh_desc, 1214 async_tx); 1215 unsigned long flags; 1216 int count; 1217 1218 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1219 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1220 sh_desc->partial, sh_desc->cookie); 1221 1222 spin_lock_irqsave(&port->lock, flags); 1223 count = sci_dma_rx_push(s, tty, sh_desc->partial); 1224 spin_unlock_irqrestore(&port->lock, flags); 1225 1226 if (count) 1227 tty_flip_buffer_push(tty); 1228 1229 sci_submit_rx(s); 1230 1231 return; 1232 } 1233 1234 s->cookie_rx[new] = desc->tx_submit(desc); 1235 if (s->cookie_rx[new] < 0) { 1236 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1237 sci_rx_dma_release(s, true); 1238 return; 1239 } 1240 1241 s->active_rx = s->cookie_rx[!new]; 1242 1243 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1244 s->cookie_rx[new], new, s->active_rx); 1245 } 1246 1247 static void work_fn_tx(struct work_struct *work) 1248 { 1249 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1250 struct dma_async_tx_descriptor *desc; 1251 struct dma_chan *chan = s->chan_tx; 1252 struct uart_port *port = &s->port; 1253 struct circ_buf *xmit = &port->state->xmit; 1254 struct scatterlist *sg = &s->sg_tx; 1255 1256 /* 1257 * DMA is idle now. 1258 * Port xmit buffer is already mapped, and it is one page... Just adjust 1259 * offsets and lengths. Since it is a circular buffer, we have to 1260 * transmit till the end, and then the rest. Take the port lock to get a 1261 * consistent xmit buffer state. 1262 */ 1263 spin_lock_irq(&port->lock); 1264 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1265 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1266 sg->offset; 1267 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1268 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1269 spin_unlock_irq(&port->lock); 1270 1271 BUG_ON(!sg_dma_len(sg)); 1272 1273 desc = chan->device->device_prep_slave_sg(chan, 1274 sg, s->sg_len_tx, DMA_TO_DEVICE, 1275 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1276 if (!desc) { 1277 /* switch to PIO */ 1278 sci_tx_dma_release(s, true); 1279 return; 1280 } 1281 1282 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1283 1284 spin_lock_irq(&port->lock); 1285 s->desc_tx = desc; 1286 desc->callback = sci_dma_tx_complete; 1287 desc->callback_param = s; 1288 spin_unlock_irq(&port->lock); 1289 s->cookie_tx = desc->tx_submit(desc); 1290 if (s->cookie_tx < 0) { 1291 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1292 /* switch to PIO */ 1293 sci_tx_dma_release(s, true); 1294 return; 1295 } 1296 1297 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1298 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1299 1300 dma_async_issue_pending(chan); 1301 } 1302 #endif 1303 1304 static void sci_start_tx(struct uart_port *port) 1305 { 1306 struct sci_port *s = to_sci_port(port); 1307 unsigned short ctrl; 1308 1309 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1310 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1311 u16 new, scr = sci_in(port, SCSCR); 1312 if (s->chan_tx) 1313 new = scr | 0x8000; 1314 else 1315 new = scr & ~0x8000; 1316 if (new != scr) 1317 sci_out(port, SCSCR, new); 1318 } 1319 1320 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1321 s->cookie_tx < 0) 1322 schedule_work(&s->work_tx); 1323 #endif 1324 1325 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1326 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1327 ctrl = sci_in(port, SCSCR); 1328 sci_out(port, SCSCR, ctrl | SCSCR_TIE); 1329 } 1330 } 1331 1332 static void sci_stop_tx(struct uart_port *port) 1333 { 1334 unsigned short ctrl; 1335 1336 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1337 ctrl = sci_in(port, SCSCR); 1338 1339 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1340 ctrl &= ~0x8000; 1341 1342 ctrl &= ~SCSCR_TIE; 1343 1344 sci_out(port, SCSCR, ctrl); 1345 } 1346 1347 static void sci_start_rx(struct uart_port *port) 1348 { 1349 unsigned short ctrl; 1350 1351 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port); 1352 1353 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1354 ctrl &= ~0x4000; 1355 1356 sci_out(port, SCSCR, ctrl); 1357 } 1358 1359 static void sci_stop_rx(struct uart_port *port) 1360 { 1361 unsigned short ctrl; 1362 1363 ctrl = sci_in(port, SCSCR); 1364 1365 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1366 ctrl &= ~0x4000; 1367 1368 ctrl &= ~port_rx_irq_mask(port); 1369 1370 sci_out(port, SCSCR, ctrl); 1371 } 1372 1373 static void sci_enable_ms(struct uart_port *port) 1374 { 1375 /* Nothing here yet .. */ 1376 } 1377 1378 static void sci_break_ctl(struct uart_port *port, int break_state) 1379 { 1380 /* Nothing here yet .. */ 1381 } 1382 1383 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1384 static bool filter(struct dma_chan *chan, void *slave) 1385 { 1386 struct sh_dmae_slave *param = slave; 1387 1388 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1389 param->slave_id); 1390 1391 if (param->dma_dev == chan->device->dev) { 1392 chan->private = param; 1393 return true; 1394 } else { 1395 return false; 1396 } 1397 } 1398 1399 static void rx_timer_fn(unsigned long arg) 1400 { 1401 struct sci_port *s = (struct sci_port *)arg; 1402 struct uart_port *port = &s->port; 1403 u16 scr = sci_in(port, SCSCR); 1404 1405 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1406 scr &= ~0x4000; 1407 enable_irq(s->cfg->irqs[1]); 1408 } 1409 sci_out(port, SCSCR, scr | SCSCR_RIE); 1410 dev_dbg(port->dev, "DMA Rx timed out\n"); 1411 schedule_work(&s->work_rx); 1412 } 1413 1414 static void sci_request_dma(struct uart_port *port) 1415 { 1416 struct sci_port *s = to_sci_port(port); 1417 struct sh_dmae_slave *param; 1418 struct dma_chan *chan; 1419 dma_cap_mask_t mask; 1420 int nent; 1421 1422 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, 1423 port->line, s->cfg->dma_dev); 1424 1425 if (!s->cfg->dma_dev) 1426 return; 1427 1428 dma_cap_zero(mask); 1429 dma_cap_set(DMA_SLAVE, mask); 1430 1431 param = &s->param_tx; 1432 1433 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1434 param->slave_id = s->cfg->dma_slave_tx; 1435 param->dma_dev = s->cfg->dma_dev; 1436 1437 s->cookie_tx = -EINVAL; 1438 chan = dma_request_channel(mask, filter, param); 1439 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1440 if (chan) { 1441 s->chan_tx = chan; 1442 sg_init_table(&s->sg_tx, 1); 1443 /* UART circular tx buffer is an aligned page. */ 1444 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1445 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1446 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1447 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1448 if (!nent) 1449 sci_tx_dma_release(s, false); 1450 else 1451 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1452 sg_dma_len(&s->sg_tx), 1453 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1454 1455 s->sg_len_tx = nent; 1456 1457 INIT_WORK(&s->work_tx, work_fn_tx); 1458 } 1459 1460 param = &s->param_rx; 1461 1462 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1463 param->slave_id = s->cfg->dma_slave_rx; 1464 param->dma_dev = s->cfg->dma_dev; 1465 1466 chan = dma_request_channel(mask, filter, param); 1467 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1468 if (chan) { 1469 dma_addr_t dma[2]; 1470 void *buf[2]; 1471 int i; 1472 1473 s->chan_rx = chan; 1474 1475 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1476 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1477 &dma[0], GFP_KERNEL); 1478 1479 if (!buf[0]) { 1480 dev_warn(port->dev, 1481 "failed to allocate dma buffer, using PIO\n"); 1482 sci_rx_dma_release(s, true); 1483 return; 1484 } 1485 1486 buf[1] = buf[0] + s->buf_len_rx; 1487 dma[1] = dma[0] + s->buf_len_rx; 1488 1489 for (i = 0; i < 2; i++) { 1490 struct scatterlist *sg = &s->sg_rx[i]; 1491 1492 sg_init_table(sg, 1); 1493 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1494 (int)buf[i] & ~PAGE_MASK); 1495 sg_dma_address(sg) = dma[i]; 1496 } 1497 1498 INIT_WORK(&s->work_rx, work_fn_rx); 1499 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1500 1501 sci_submit_rx(s); 1502 } 1503 } 1504 1505 static void sci_free_dma(struct uart_port *port) 1506 { 1507 struct sci_port *s = to_sci_port(port); 1508 1509 if (!s->cfg->dma_dev) 1510 return; 1511 1512 if (s->chan_tx) 1513 sci_tx_dma_release(s, false); 1514 if (s->chan_rx) 1515 sci_rx_dma_release(s, false); 1516 } 1517 #else 1518 static inline void sci_request_dma(struct uart_port *port) 1519 { 1520 } 1521 1522 static inline void sci_free_dma(struct uart_port *port) 1523 { 1524 } 1525 #endif 1526 1527 static int sci_startup(struct uart_port *port) 1528 { 1529 struct sci_port *s = to_sci_port(port); 1530 int ret; 1531 1532 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1533 1534 sci_port_enable(s); 1535 1536 ret = sci_request_irq(s); 1537 if (unlikely(ret < 0)) 1538 return ret; 1539 1540 sci_request_dma(port); 1541 1542 sci_start_tx(port); 1543 sci_start_rx(port); 1544 1545 return 0; 1546 } 1547 1548 static void sci_shutdown(struct uart_port *port) 1549 { 1550 struct sci_port *s = to_sci_port(port); 1551 1552 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1553 1554 sci_stop_rx(port); 1555 sci_stop_tx(port); 1556 1557 sci_free_dma(port); 1558 sci_free_irq(s); 1559 1560 sci_port_disable(s); 1561 } 1562 1563 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1564 unsigned long freq) 1565 { 1566 switch (algo_id) { 1567 case SCBRR_ALGO_1: 1568 return ((freq + 16 * bps) / (16 * bps) - 1); 1569 case SCBRR_ALGO_2: 1570 return ((freq + 16 * bps) / (32 * bps) - 1); 1571 case SCBRR_ALGO_3: 1572 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1573 case SCBRR_ALGO_4: 1574 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1575 case SCBRR_ALGO_5: 1576 return (((freq * 1000 / 32) / bps) - 1); 1577 } 1578 1579 /* Warn, but use a safe default */ 1580 WARN_ON(1); 1581 1582 return ((freq + 16 * bps) / (32 * bps) - 1); 1583 } 1584 1585 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1586 struct ktermios *old) 1587 { 1588 struct sci_port *s = to_sci_port(port); 1589 unsigned int status, baud, smr_val, max_baud; 1590 int t = -1; 1591 u16 scfcr = 0; 1592 1593 /* 1594 * earlyprintk comes here early on with port->uartclk set to zero. 1595 * the clock framework is not up and running at this point so here 1596 * we assume that 115200 is the maximum baud rate. please note that 1597 * the baud rate is not programmed during earlyprintk - it is assumed 1598 * that the previous boot loader has enabled required clocks and 1599 * setup the baud rate generator hardware for us already. 1600 */ 1601 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1602 1603 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1604 if (likely(baud && port->uartclk)) 1605 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1606 1607 sci_port_enable(s); 1608 1609 do { 1610 status = sci_in(port, SCxSR); 1611 } while (!(status & SCxSR_TEND(port))); 1612 1613 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1614 1615 if (port->type != PORT_SCI) 1616 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST); 1617 1618 smr_val = sci_in(port, SCSMR) & 3; 1619 1620 if ((termios->c_cflag & CSIZE) == CS7) 1621 smr_val |= 0x40; 1622 if (termios->c_cflag & PARENB) 1623 smr_val |= 0x20; 1624 if (termios->c_cflag & PARODD) 1625 smr_val |= 0x30; 1626 if (termios->c_cflag & CSTOPB) 1627 smr_val |= 0x08; 1628 1629 uart_update_timeout(port, termios->c_cflag, baud); 1630 1631 sci_out(port, SCSMR, smr_val); 1632 1633 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, 1634 s->cfg->scscr); 1635 1636 if (t > 0) { 1637 if (t >= 256) { 1638 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1639 t >>= 2; 1640 } else 1641 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); 1642 1643 sci_out(port, SCBRR, t); 1644 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1645 } 1646 1647 sci_init_pins(port, termios->c_cflag); 1648 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); 1649 1650 sci_out(port, SCSCR, s->cfg->scscr); 1651 1652 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1653 /* 1654 * Calculate delay for 1.5 DMA buffers: see 1655 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1656 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1657 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1658 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1659 * sizes), but it has been found out experimentally, that this is not 1660 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1661 * as a minimum seem to work perfectly. 1662 */ 1663 if (s->chan_rx) { 1664 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1665 port->fifosize / 2; 1666 dev_dbg(port->dev, 1667 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1668 s->rx_timeout * 1000 / HZ, port->timeout); 1669 if (s->rx_timeout < msecs_to_jiffies(20)) 1670 s->rx_timeout = msecs_to_jiffies(20); 1671 } 1672 #endif 1673 1674 if ((termios->c_cflag & CREAD) != 0) 1675 sci_start_rx(port); 1676 1677 sci_port_disable(s); 1678 } 1679 1680 static const char *sci_type(struct uart_port *port) 1681 { 1682 switch (port->type) { 1683 case PORT_IRDA: 1684 return "irda"; 1685 case PORT_SCI: 1686 return "sci"; 1687 case PORT_SCIF: 1688 return "scif"; 1689 case PORT_SCIFA: 1690 return "scifa"; 1691 case PORT_SCIFB: 1692 return "scifb"; 1693 } 1694 1695 return NULL; 1696 } 1697 1698 static inline unsigned long sci_port_size(struct uart_port *port) 1699 { 1700 /* 1701 * Pick an arbitrary size that encapsulates all of the base 1702 * registers by default. This can be optimized later, or derived 1703 * from platform resource data at such a time that ports begin to 1704 * behave more erratically. 1705 */ 1706 return 64; 1707 } 1708 1709 static int sci_remap_port(struct uart_port *port) 1710 { 1711 unsigned long size = sci_port_size(port); 1712 1713 /* 1714 * Nothing to do if there's already an established membase. 1715 */ 1716 if (port->membase) 1717 return 0; 1718 1719 if (port->flags & UPF_IOREMAP) { 1720 port->membase = ioremap_nocache(port->mapbase, size); 1721 if (unlikely(!port->membase)) { 1722 dev_err(port->dev, "can't remap port#%d\n", port->line); 1723 return -ENXIO; 1724 } 1725 } else { 1726 /* 1727 * For the simple (and majority of) cases where we don't 1728 * need to do any remapping, just cast the cookie 1729 * directly. 1730 */ 1731 port->membase = (void __iomem *)port->mapbase; 1732 } 1733 1734 return 0; 1735 } 1736 1737 static void sci_release_port(struct uart_port *port) 1738 { 1739 if (port->flags & UPF_IOREMAP) { 1740 iounmap(port->membase); 1741 port->membase = NULL; 1742 } 1743 1744 release_mem_region(port->mapbase, sci_port_size(port)); 1745 } 1746 1747 static int sci_request_port(struct uart_port *port) 1748 { 1749 unsigned long size = sci_port_size(port); 1750 struct resource *res; 1751 int ret; 1752 1753 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 1754 if (unlikely(res == NULL)) 1755 return -EBUSY; 1756 1757 ret = sci_remap_port(port); 1758 if (unlikely(ret != 0)) { 1759 release_resource(res); 1760 return ret; 1761 } 1762 1763 return 0; 1764 } 1765 1766 static void sci_config_port(struct uart_port *port, int flags) 1767 { 1768 if (flags & UART_CONFIG_TYPE) { 1769 struct sci_port *sport = to_sci_port(port); 1770 1771 port->type = sport->cfg->type; 1772 sci_request_port(port); 1773 } 1774 } 1775 1776 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1777 { 1778 struct sci_port *s = to_sci_port(port); 1779 1780 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1781 return -EINVAL; 1782 if (ser->baud_base < 2400) 1783 /* No paper tape reader for Mitch.. */ 1784 return -EINVAL; 1785 1786 return 0; 1787 } 1788 1789 static struct uart_ops sci_uart_ops = { 1790 .tx_empty = sci_tx_empty, 1791 .set_mctrl = sci_set_mctrl, 1792 .get_mctrl = sci_get_mctrl, 1793 .start_tx = sci_start_tx, 1794 .stop_tx = sci_stop_tx, 1795 .stop_rx = sci_stop_rx, 1796 .enable_ms = sci_enable_ms, 1797 .break_ctl = sci_break_ctl, 1798 .startup = sci_startup, 1799 .shutdown = sci_shutdown, 1800 .set_termios = sci_set_termios, 1801 .type = sci_type, 1802 .release_port = sci_release_port, 1803 .request_port = sci_request_port, 1804 .config_port = sci_config_port, 1805 .verify_port = sci_verify_port, 1806 #ifdef CONFIG_CONSOLE_POLL 1807 .poll_get_char = sci_poll_get_char, 1808 .poll_put_char = sci_poll_put_char, 1809 #endif 1810 }; 1811 1812 static int __devinit sci_init_single(struct platform_device *dev, 1813 struct sci_port *sci_port, 1814 unsigned int index, 1815 struct plat_sci_port *p) 1816 { 1817 struct uart_port *port = &sci_port->port; 1818 int ret; 1819 1820 port->ops = &sci_uart_ops; 1821 port->iotype = UPIO_MEM; 1822 port->line = index; 1823 1824 switch (p->type) { 1825 case PORT_SCIFB: 1826 port->fifosize = 256; 1827 break; 1828 case PORT_SCIFA: 1829 port->fifosize = 64; 1830 break; 1831 case PORT_SCIF: 1832 port->fifosize = 16; 1833 break; 1834 default: 1835 port->fifosize = 1; 1836 break; 1837 } 1838 1839 if (p->regtype == SCIx_PROBE_REGTYPE) { 1840 ret = sci_probe_regmap(p); 1841 if (unlikely(!ret)) 1842 return ret; 1843 } 1844 1845 if (dev) { 1846 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1847 if (IS_ERR(sci_port->iclk)) { 1848 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 1849 if (IS_ERR(sci_port->iclk)) { 1850 dev_err(&dev->dev, "can't get iclk\n"); 1851 return PTR_ERR(sci_port->iclk); 1852 } 1853 } 1854 1855 /* 1856 * The function clock is optional, ignore it if we can't 1857 * find it. 1858 */ 1859 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 1860 if (IS_ERR(sci_port->fclk)) 1861 sci_port->fclk = NULL; 1862 1863 port->dev = &dev->dev; 1864 1865 pm_runtime_enable(&dev->dev); 1866 } 1867 1868 sci_port->break_timer.data = (unsigned long)sci_port; 1869 sci_port->break_timer.function = sci_break_timer; 1870 init_timer(&sci_port->break_timer); 1871 1872 /* 1873 * Establish some sensible defaults for the error detection. 1874 */ 1875 if (!p->error_mask) 1876 p->error_mask = (p->type == PORT_SCI) ? 1877 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 1878 1879 /* 1880 * Establish sensible defaults for the overrun detection, unless 1881 * the part has explicitly disabled support for it. 1882 */ 1883 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 1884 if (p->type == PORT_SCI) 1885 p->overrun_bit = 5; 1886 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 1887 p->overrun_bit = 9; 1888 else 1889 p->overrun_bit = 0; 1890 1891 /* 1892 * Make the error mask inclusive of overrun detection, if 1893 * supported. 1894 */ 1895 p->error_mask |= (1 << p->overrun_bit); 1896 } 1897 1898 sci_port->cfg = p; 1899 1900 port->mapbase = p->mapbase; 1901 port->type = p->type; 1902 port->flags = p->flags; 1903 port->regshift = p->regshift; 1904 1905 /* 1906 * The UART port needs an IRQ value, so we peg this to the RX IRQ 1907 * for the multi-IRQ ports, which is where we are primarily 1908 * concerned with the shutdown path synchronization. 1909 * 1910 * For the muxed case there's nothing more to do. 1911 */ 1912 port->irq = p->irqs[SCIx_RXI_IRQ]; 1913 1914 port->serial_in = sci_serial_in; 1915 port->serial_out = sci_serial_out; 1916 1917 if (p->dma_dev) 1918 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", 1919 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); 1920 1921 return 0; 1922 } 1923 1924 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1925 static void serial_console_putchar(struct uart_port *port, int ch) 1926 { 1927 sci_poll_put_char(port, ch); 1928 } 1929 1930 /* 1931 * Print a string to the serial port trying not to disturb 1932 * any possible real use of the port... 1933 */ 1934 static void serial_console_write(struct console *co, const char *s, 1935 unsigned count) 1936 { 1937 struct sci_port *sci_port = &sci_ports[co->index]; 1938 struct uart_port *port = &sci_port->port; 1939 unsigned short bits; 1940 1941 sci_port_enable(sci_port); 1942 1943 uart_console_write(port, s, count, serial_console_putchar); 1944 1945 /* wait until fifo is empty and last bit has been transmitted */ 1946 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 1947 while ((sci_in(port, SCxSR) & bits) != bits) 1948 cpu_relax(); 1949 1950 sci_port_disable(sci_port); 1951 } 1952 1953 static int __devinit serial_console_setup(struct console *co, char *options) 1954 { 1955 struct sci_port *sci_port; 1956 struct uart_port *port; 1957 int baud = 115200; 1958 int bits = 8; 1959 int parity = 'n'; 1960 int flow = 'n'; 1961 int ret; 1962 1963 /* 1964 * Refuse to handle any bogus ports. 1965 */ 1966 if (co->index < 0 || co->index >= SCI_NPORTS) 1967 return -ENODEV; 1968 1969 sci_port = &sci_ports[co->index]; 1970 port = &sci_port->port; 1971 1972 /* 1973 * Refuse to handle uninitialized ports. 1974 */ 1975 if (!port->ops) 1976 return -ENODEV; 1977 1978 ret = sci_remap_port(port); 1979 if (unlikely(ret != 0)) 1980 return ret; 1981 1982 sci_port_enable(sci_port); 1983 1984 if (options) 1985 uart_parse_options(options, &baud, &parity, &bits, &flow); 1986 1987 /* TODO: disable clock */ 1988 return uart_set_options(port, co, baud, parity, bits, flow); 1989 } 1990 1991 static struct console serial_console = { 1992 .name = "ttySC", 1993 .device = uart_console_device, 1994 .write = serial_console_write, 1995 .setup = serial_console_setup, 1996 .flags = CON_PRINTBUFFER, 1997 .index = -1, 1998 .data = &sci_uart_driver, 1999 }; 2000 2001 static struct console early_serial_console = { 2002 .name = "early_ttySC", 2003 .write = serial_console_write, 2004 .flags = CON_PRINTBUFFER, 2005 .index = -1, 2006 }; 2007 2008 static char early_serial_buf[32]; 2009 2010 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2011 { 2012 struct plat_sci_port *cfg = pdev->dev.platform_data; 2013 2014 if (early_serial_console.data) 2015 return -EEXIST; 2016 2017 early_serial_console.index = pdev->id; 2018 2019 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2020 2021 serial_console_setup(&early_serial_console, early_serial_buf); 2022 2023 if (!strstr(early_serial_buf, "keep")) 2024 early_serial_console.flags |= CON_BOOT; 2025 2026 register_console(&early_serial_console); 2027 return 0; 2028 } 2029 2030 #define SCI_CONSOLE (&serial_console) 2031 2032 #else 2033 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2034 { 2035 return -EINVAL; 2036 } 2037 2038 #define SCI_CONSOLE NULL 2039 2040 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2041 2042 static char banner[] __initdata = 2043 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2044 2045 static struct uart_driver sci_uart_driver = { 2046 .owner = THIS_MODULE, 2047 .driver_name = "sci", 2048 .dev_name = "ttySC", 2049 .major = SCI_MAJOR, 2050 .minor = SCI_MINOR_START, 2051 .nr = SCI_NPORTS, 2052 .cons = SCI_CONSOLE, 2053 }; 2054 2055 static int sci_remove(struct platform_device *dev) 2056 { 2057 struct sci_port *port = platform_get_drvdata(dev); 2058 2059 cpufreq_unregister_notifier(&port->freq_transition, 2060 CPUFREQ_TRANSITION_NOTIFIER); 2061 2062 uart_remove_one_port(&sci_uart_driver, &port->port); 2063 2064 clk_put(port->iclk); 2065 clk_put(port->fclk); 2066 2067 pm_runtime_disable(&dev->dev); 2068 return 0; 2069 } 2070 2071 static int __devinit sci_probe_single(struct platform_device *dev, 2072 unsigned int index, 2073 struct plat_sci_port *p, 2074 struct sci_port *sciport) 2075 { 2076 int ret; 2077 2078 /* Sanity check */ 2079 if (unlikely(index >= SCI_NPORTS)) { 2080 dev_notice(&dev->dev, "Attempting to register port " 2081 "%d when only %d are available.\n", 2082 index+1, SCI_NPORTS); 2083 dev_notice(&dev->dev, "Consider bumping " 2084 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2085 return 0; 2086 } 2087 2088 ret = sci_init_single(dev, sciport, index, p); 2089 if (ret) 2090 return ret; 2091 2092 return uart_add_one_port(&sci_uart_driver, &sciport->port); 2093 } 2094 2095 static int __devinit sci_probe(struct platform_device *dev) 2096 { 2097 struct plat_sci_port *p = dev->dev.platform_data; 2098 struct sci_port *sp = &sci_ports[dev->id]; 2099 int ret; 2100 2101 /* 2102 * If we've come here via earlyprintk initialization, head off to 2103 * the special early probe. We don't have sufficient device state 2104 * to make it beyond this yet. 2105 */ 2106 if (is_early_platform_device(dev)) 2107 return sci_probe_earlyprintk(dev); 2108 2109 platform_set_drvdata(dev, sp); 2110 2111 ret = sci_probe_single(dev, dev->id, p, sp); 2112 if (ret) 2113 goto err_unreg; 2114 2115 sp->freq_transition.notifier_call = sci_notifier; 2116 2117 ret = cpufreq_register_notifier(&sp->freq_transition, 2118 CPUFREQ_TRANSITION_NOTIFIER); 2119 if (unlikely(ret < 0)) 2120 goto err_unreg; 2121 2122 #ifdef CONFIG_SH_STANDARD_BIOS 2123 sh_bios_gdb_detach(); 2124 #endif 2125 2126 return 0; 2127 2128 err_unreg: 2129 sci_remove(dev); 2130 return ret; 2131 } 2132 2133 static int sci_suspend(struct device *dev) 2134 { 2135 struct sci_port *sport = dev_get_drvdata(dev); 2136 2137 if (sport) 2138 uart_suspend_port(&sci_uart_driver, &sport->port); 2139 2140 return 0; 2141 } 2142 2143 static int sci_resume(struct device *dev) 2144 { 2145 struct sci_port *sport = dev_get_drvdata(dev); 2146 2147 if (sport) 2148 uart_resume_port(&sci_uart_driver, &sport->port); 2149 2150 return 0; 2151 } 2152 2153 static const struct dev_pm_ops sci_dev_pm_ops = { 2154 .suspend = sci_suspend, 2155 .resume = sci_resume, 2156 }; 2157 2158 static struct platform_driver sci_driver = { 2159 .probe = sci_probe, 2160 .remove = sci_remove, 2161 .driver = { 2162 .name = "sh-sci", 2163 .owner = THIS_MODULE, 2164 .pm = &sci_dev_pm_ops, 2165 }, 2166 }; 2167 2168 static int __init sci_init(void) 2169 { 2170 int ret; 2171 2172 printk(banner); 2173 2174 ret = uart_register_driver(&sci_uart_driver); 2175 if (likely(ret == 0)) { 2176 ret = platform_driver_register(&sci_driver); 2177 if (unlikely(ret)) 2178 uart_unregister_driver(&sci_uart_driver); 2179 } 2180 2181 return ret; 2182 } 2183 2184 static void __exit sci_exit(void) 2185 { 2186 platform_driver_unregister(&sci_driver); 2187 uart_unregister_driver(&sci_uart_driver); 2188 } 2189 2190 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2191 early_platform_init_buffer("earlyprintk", &sci_driver, 2192 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2193 #endif 2194 module_init(sci_init); 2195 module_exit(sci_exit); 2196 2197 MODULE_LICENSE("GPL"); 2198 MODULE_ALIAS("platform:sh-sci"); 2199 MODULE_AUTHOR("Paul Mundt"); 2200 MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2201