1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "serial_mctrl_gpio.h" 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_DRI_IRQ, 69 SCIx_TEI_IRQ, 70 SCIx_NR_IRQS, 71 72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 73 }; 74 75 #define SCIx_IRQ_IS_MUXED(port) \ 76 ((port)->irqs[SCIx_ERI_IRQ] == \ 77 (port)->irqs[SCIx_RXI_IRQ]) || \ 78 ((port)->irqs[SCIx_ERI_IRQ] && \ 79 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 80 81 enum SCI_CLKS { 82 SCI_FCK, /* Functional Clock */ 83 SCI_SCK, /* Optional External Clock */ 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 86 SCI_NUM_CLKS 87 }; 88 89 /* Bit x set means sampling rate x + 1 is supported */ 90 #define SCI_SR(x) BIT((x) - 1) 91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 92 93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 95 SCI_SR(19) | SCI_SR(27) 96 97 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 98 #define max_sr(_port) fls((_port)->sampling_rate_mask) 99 100 /* Iterate over all supported sampling rates, from high to low */ 101 #define for_each_sr(_sr, _port) \ 102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 103 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 104 105 struct plat_sci_reg { 106 u8 offset, size; 107 }; 108 109 struct sci_port_params { 110 const struct plat_sci_reg regs[SCIx_NR_REGS]; 111 unsigned int fifosize; 112 unsigned int overrun_reg; 113 unsigned int overrun_mask; 114 unsigned int sampling_rate_mask; 115 unsigned int error_mask; 116 unsigned int error_clear; 117 }; 118 119 struct sci_port { 120 struct uart_port port; 121 122 /* Platform configuration */ 123 const struct sci_port_params *params; 124 const struct plat_sci_port *cfg; 125 unsigned int sampling_rate_mask; 126 resource_size_t reg_size; 127 struct mctrl_gpios *gpios; 128 129 /* Clocks */ 130 struct clk *clks[SCI_NUM_CLKS]; 131 unsigned long clk_rates[SCI_NUM_CLKS]; 132 133 int irqs[SCIx_NR_IRQS]; 134 char *irqstr[SCIx_NR_IRQS]; 135 136 struct dma_chan *chan_tx; 137 struct dma_chan *chan_rx; 138 139 #ifdef CONFIG_SERIAL_SH_SCI_DMA 140 struct dma_chan *chan_tx_saved; 141 struct dma_chan *chan_rx_saved; 142 dma_cookie_t cookie_tx; 143 dma_cookie_t cookie_rx[2]; 144 dma_cookie_t active_rx; 145 dma_addr_t tx_dma_addr; 146 unsigned int tx_dma_len; 147 struct scatterlist sg_rx[2]; 148 void *rx_buf[2]; 149 size_t buf_len_rx; 150 struct work_struct work_tx; 151 struct hrtimer rx_timer; 152 unsigned int rx_timeout; /* microseconds */ 153 #endif 154 unsigned int rx_frame; 155 int rx_trigger; 156 struct timer_list rx_fifo_timer; 157 int rx_fifo_timeout; 158 u16 hscif_tot; 159 160 bool has_rtscts; 161 bool autorts; 162 }; 163 164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 165 166 static struct sci_port sci_ports[SCI_NPORTS]; 167 static unsigned long sci_ports_in_use; 168 static struct uart_driver sci_uart_driver; 169 170 static inline struct sci_port * 171 to_sci_port(struct uart_port *uart) 172 { 173 return container_of(uart, struct sci_port, port); 174 } 175 176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 177 /* 178 * Common SCI definitions, dependent on the port's regshift 179 * value. 180 */ 181 [SCIx_SCI_REGTYPE] = { 182 .regs = { 183 [SCSMR] = { 0x00, 8 }, 184 [SCBRR] = { 0x01, 8 }, 185 [SCSCR] = { 0x02, 8 }, 186 [SCxTDR] = { 0x03, 8 }, 187 [SCxSR] = { 0x04, 8 }, 188 [SCxRDR] = { 0x05, 8 }, 189 }, 190 .fifosize = 1, 191 .overrun_reg = SCxSR, 192 .overrun_mask = SCI_ORER, 193 .sampling_rate_mask = SCI_SR(32), 194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 196 }, 197 198 /* 199 * Common definitions for legacy IrDA ports. 200 */ 201 [SCIx_IRDA_REGTYPE] = { 202 .regs = { 203 [SCSMR] = { 0x00, 8 }, 204 [SCBRR] = { 0x02, 8 }, 205 [SCSCR] = { 0x04, 8 }, 206 [SCxTDR] = { 0x06, 8 }, 207 [SCxSR] = { 0x08, 16 }, 208 [SCxRDR] = { 0x0a, 8 }, 209 [SCFCR] = { 0x0c, 8 }, 210 [SCFDR] = { 0x0e, 16 }, 211 }, 212 .fifosize = 1, 213 .overrun_reg = SCxSR, 214 .overrun_mask = SCI_ORER, 215 .sampling_rate_mask = SCI_SR(32), 216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 218 }, 219 220 /* 221 * Common SCIFA definitions. 222 */ 223 [SCIx_SCIFA_REGTYPE] = { 224 .regs = { 225 [SCSMR] = { 0x00, 16 }, 226 [SCBRR] = { 0x04, 8 }, 227 [SCSCR] = { 0x08, 16 }, 228 [SCxTDR] = { 0x20, 8 }, 229 [SCxSR] = { 0x14, 16 }, 230 [SCxRDR] = { 0x24, 8 }, 231 [SCFCR] = { 0x18, 16 }, 232 [SCFDR] = { 0x1c, 16 }, 233 [SCPCR] = { 0x30, 16 }, 234 [SCPDR] = { 0x34, 16 }, 235 }, 236 .fifosize = 64, 237 .overrun_reg = SCxSR, 238 .overrun_mask = SCIFA_ORER, 239 .sampling_rate_mask = SCI_SR_SCIFAB, 240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 242 }, 243 244 /* 245 * Common SCIFB definitions. 246 */ 247 [SCIx_SCIFB_REGTYPE] = { 248 .regs = { 249 [SCSMR] = { 0x00, 16 }, 250 [SCBRR] = { 0x04, 8 }, 251 [SCSCR] = { 0x08, 16 }, 252 [SCxTDR] = { 0x40, 8 }, 253 [SCxSR] = { 0x14, 16 }, 254 [SCxRDR] = { 0x60, 8 }, 255 [SCFCR] = { 0x18, 16 }, 256 [SCTFDR] = { 0x38, 16 }, 257 [SCRFDR] = { 0x3c, 16 }, 258 [SCPCR] = { 0x30, 16 }, 259 [SCPDR] = { 0x34, 16 }, 260 }, 261 .fifosize = 256, 262 .overrun_reg = SCxSR, 263 .overrun_mask = SCIFA_ORER, 264 .sampling_rate_mask = SCI_SR_SCIFAB, 265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 267 }, 268 269 /* 270 * Common SH-2(A) SCIF definitions for ports with FIFO data 271 * count registers. 272 */ 273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 274 .regs = { 275 [SCSMR] = { 0x00, 16 }, 276 [SCBRR] = { 0x04, 8 }, 277 [SCSCR] = { 0x08, 16 }, 278 [SCxTDR] = { 0x0c, 8 }, 279 [SCxSR] = { 0x10, 16 }, 280 [SCxRDR] = { 0x14, 8 }, 281 [SCFCR] = { 0x18, 16 }, 282 [SCFDR] = { 0x1c, 16 }, 283 [SCSPTR] = { 0x20, 16 }, 284 [SCLSR] = { 0x24, 16 }, 285 }, 286 .fifosize = 16, 287 .overrun_reg = SCLSR, 288 .overrun_mask = SCLSR_ORER, 289 .sampling_rate_mask = SCI_SR(32), 290 .error_mask = SCIF_DEFAULT_ERROR_MASK, 291 .error_clear = SCIF_ERROR_CLEAR, 292 }, 293 294 /* 295 * The "SCIFA" that is in RZ/T and RZ/A2. 296 * It looks like a normal SCIF with FIFO data, but with a 297 * compressed address space. Also, the break out of interrupts 298 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 299 */ 300 [SCIx_RZ_SCIFA_REGTYPE] = { 301 .regs = { 302 [SCSMR] = { 0x00, 16 }, 303 [SCBRR] = { 0x02, 8 }, 304 [SCSCR] = { 0x04, 16 }, 305 [SCxTDR] = { 0x06, 8 }, 306 [SCxSR] = { 0x08, 16 }, 307 [SCxRDR] = { 0x0A, 8 }, 308 [SCFCR] = { 0x0C, 16 }, 309 [SCFDR] = { 0x0E, 16 }, 310 [SCSPTR] = { 0x10, 16 }, 311 [SCLSR] = { 0x12, 16 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ 506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 s->cookie_tx = 0; 592 schedule_work(&s->work_tx); 593 } 594 #endif 595 596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 598 ctrl = serial_port_in(port, SCSCR); 599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 600 } 601 } 602 603 static void sci_stop_tx(struct uart_port *port) 604 { 605 unsigned short ctrl; 606 607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 608 ctrl = serial_port_in(port, SCSCR); 609 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 611 ctrl &= ~SCSCR_TDRQE; 612 613 ctrl &= ~SCSCR_TIE; 614 615 serial_port_out(port, SCSCR, ctrl); 616 } 617 618 static void sci_start_rx(struct uart_port *port) 619 { 620 unsigned short ctrl; 621 622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 623 624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 625 ctrl &= ~SCSCR_RDRQE; 626 627 serial_port_out(port, SCSCR, ctrl); 628 } 629 630 static void sci_stop_rx(struct uart_port *port) 631 { 632 unsigned short ctrl; 633 634 ctrl = serial_port_in(port, SCSCR); 635 636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 637 ctrl &= ~SCSCR_RDRQE; 638 639 ctrl &= ~port_rx_irq_mask(port); 640 641 serial_port_out(port, SCSCR, ctrl); 642 } 643 644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 645 { 646 if (port->type == PORT_SCI) { 647 /* Just store the mask */ 648 serial_port_out(port, SCxSR, mask); 649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 651 /* Only clear the status bits we want to clear */ 652 serial_port_out(port, SCxSR, 653 serial_port_in(port, SCxSR) & mask); 654 } else { 655 /* Store the mask, clear parity/framing errors */ 656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 657 } 658 } 659 660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 662 663 #ifdef CONFIG_CONSOLE_POLL 664 static int sci_poll_get_char(struct uart_port *port) 665 { 666 unsigned short status; 667 int c; 668 669 do { 670 status = serial_port_in(port, SCxSR); 671 if (status & SCxSR_ERRORS(port)) { 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 673 continue; 674 } 675 break; 676 } while (1); 677 678 if (!(status & SCxSR_RDxF(port))) 679 return NO_POLL_CHAR; 680 681 c = serial_port_in(port, SCxRDR); 682 683 /* Dummy read */ 684 serial_port_in(port, SCxSR); 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 686 687 return c; 688 } 689 #endif 690 691 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 692 { 693 unsigned short status; 694 695 do { 696 status = serial_port_in(port, SCxSR); 697 } while (!(status & SCxSR_TDxE(port))); 698 699 serial_port_out(port, SCxTDR, c); 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 701 } 702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 703 CONFIG_SERIAL_SH_SCI_EARLYCON */ 704 705 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 706 { 707 struct sci_port *s = to_sci_port(port); 708 709 /* 710 * Use port-specific handler if provided. 711 */ 712 if (s->cfg->ops && s->cfg->ops->init_pins) { 713 s->cfg->ops->init_pins(port, cflag); 714 return; 715 } 716 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 718 u16 data = serial_port_in(port, SCPDR); 719 u16 ctrl = serial_port_in(port, SCPCR); 720 721 /* Enable RXD and TXD pin functions */ 722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 723 if (to_sci_port(port)->has_rtscts) { 724 /* RTS# is output, active low, unless autorts */ 725 if (!(port->mctrl & TIOCM_RTS)) { 726 ctrl |= SCPCR_RTSC; 727 data |= SCPDR_RTSD; 728 } else if (!s->autorts) { 729 ctrl |= SCPCR_RTSC; 730 data &= ~SCPDR_RTSD; 731 } else { 732 /* Enable RTS# pin function */ 733 ctrl &= ~SCPCR_RTSC; 734 } 735 /* Enable CTS# pin function */ 736 ctrl &= ~SCPCR_CTSC; 737 } 738 serial_port_out(port, SCPDR, data); 739 serial_port_out(port, SCPCR, ctrl); 740 } else if (sci_getreg(port, SCSPTR)->size) { 741 u16 status = serial_port_in(port, SCSPTR); 742 743 /* RTS# is always output; and active low, unless autorts */ 744 status |= SCSPTR_RTSIO; 745 if (!(port->mctrl & TIOCM_RTS)) 746 status |= SCSPTR_RTSDT; 747 else if (!s->autorts) 748 status &= ~SCSPTR_RTSDT; 749 /* CTS# and SCK are inputs */ 750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 751 serial_port_out(port, SCSPTR, status); 752 } 753 } 754 755 static int sci_txfill(struct uart_port *port) 756 { 757 struct sci_port *s = to_sci_port(port); 758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 759 const struct plat_sci_reg *reg; 760 761 reg = sci_getreg(port, SCTFDR); 762 if (reg->size) 763 return serial_port_in(port, SCTFDR) & fifo_mask; 764 765 reg = sci_getreg(port, SCFDR); 766 if (reg->size) 767 return serial_port_in(port, SCFDR) >> 8; 768 769 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 770 } 771 772 static int sci_txroom(struct uart_port *port) 773 { 774 return port->fifosize - sci_txfill(port); 775 } 776 777 static int sci_rxfill(struct uart_port *port) 778 { 779 struct sci_port *s = to_sci_port(port); 780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 781 const struct plat_sci_reg *reg; 782 783 reg = sci_getreg(port, SCRFDR); 784 if (reg->size) 785 return serial_port_in(port, SCRFDR) & fifo_mask; 786 787 reg = sci_getreg(port, SCFDR); 788 if (reg->size) 789 return serial_port_in(port, SCFDR) & fifo_mask; 790 791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 792 } 793 794 /* ********************************************************************** * 795 * the interrupt related routines * 796 * ********************************************************************** */ 797 798 static void sci_transmit_chars(struct uart_port *port) 799 { 800 struct circ_buf *xmit = &port->state->xmit; 801 unsigned int stopped = uart_tx_stopped(port); 802 unsigned short status; 803 unsigned short ctrl; 804 int count; 805 806 status = serial_port_in(port, SCxSR); 807 if (!(status & SCxSR_TDxE(port))) { 808 ctrl = serial_port_in(port, SCSCR); 809 if (uart_circ_empty(xmit)) 810 ctrl &= ~SCSCR_TIE; 811 else 812 ctrl |= SCSCR_TIE; 813 serial_port_out(port, SCSCR, ctrl); 814 return; 815 } 816 817 count = sci_txroom(port); 818 819 do { 820 unsigned char c; 821 822 if (port->x_char) { 823 c = port->x_char; 824 port->x_char = 0; 825 } else if (!uart_circ_empty(xmit) && !stopped) { 826 c = xmit->buf[xmit->tail]; 827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 828 } else { 829 break; 830 } 831 832 serial_port_out(port, SCxTDR, c); 833 834 port->icount.tx++; 835 } while (--count > 0); 836 837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 838 839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 840 uart_write_wakeup(port); 841 if (uart_circ_empty(xmit)) 842 sci_stop_tx(port); 843 844 } 845 846 /* On SH3, SCIF may read end-of-break as a space->mark char */ 847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 848 849 static void sci_receive_chars(struct uart_port *port) 850 { 851 struct tty_port *tport = &port->state->port; 852 int i, count, copied = 0; 853 unsigned short status; 854 unsigned char flag; 855 856 status = serial_port_in(port, SCxSR); 857 if (!(status & SCxSR_RDxF(port))) 858 return; 859 860 while (1) { 861 /* Don't copy more bytes than there is room for in the buffer */ 862 count = tty_buffer_request_room(tport, sci_rxfill(port)); 863 864 /* If for any reason we can't copy more data, we're done! */ 865 if (count == 0) 866 break; 867 868 if (port->type == PORT_SCI) { 869 char c = serial_port_in(port, SCxRDR); 870 if (uart_handle_sysrq_char(port, c)) 871 count = 0; 872 else 873 tty_insert_flip_char(tport, c, TTY_NORMAL); 874 } else { 875 for (i = 0; i < count; i++) { 876 char c = serial_port_in(port, SCxRDR); 877 878 status = serial_port_in(port, SCxSR); 879 if (uart_handle_sysrq_char(port, c)) { 880 count--; i--; 881 continue; 882 } 883 884 /* Store data and status */ 885 if (status & SCxSR_FER(port)) { 886 flag = TTY_FRAME; 887 port->icount.frame++; 888 dev_notice(port->dev, "frame error\n"); 889 } else if (status & SCxSR_PER(port)) { 890 flag = TTY_PARITY; 891 port->icount.parity++; 892 dev_notice(port->dev, "parity error\n"); 893 } else 894 flag = TTY_NORMAL; 895 896 tty_insert_flip_char(tport, c, flag); 897 } 898 } 899 900 serial_port_in(port, SCxSR); /* dummy read */ 901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 902 903 copied += count; 904 port->icount.rx += count; 905 } 906 907 if (copied) { 908 /* Tell the rest of the system the news. New characters! */ 909 tty_flip_buffer_push(tport); 910 } else { 911 /* TTY buffers full; read from RX reg to prevent lockup */ 912 serial_port_in(port, SCxRDR); 913 serial_port_in(port, SCxSR); /* dummy read */ 914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 915 } 916 } 917 918 static int sci_handle_errors(struct uart_port *port) 919 { 920 int copied = 0; 921 unsigned short status = serial_port_in(port, SCxSR); 922 struct tty_port *tport = &port->state->port; 923 struct sci_port *s = to_sci_port(port); 924 925 /* Handle overruns */ 926 if (status & s->params->overrun_mask) { 927 port->icount.overrun++; 928 929 /* overrun error */ 930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 931 copied++; 932 933 dev_notice(port->dev, "overrun error\n"); 934 } 935 936 if (status & SCxSR_FER(port)) { 937 /* frame error */ 938 port->icount.frame++; 939 940 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 941 copied++; 942 943 dev_notice(port->dev, "frame error\n"); 944 } 945 946 if (status & SCxSR_PER(port)) { 947 /* parity error */ 948 port->icount.parity++; 949 950 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 951 copied++; 952 953 dev_notice(port->dev, "parity error\n"); 954 } 955 956 if (copied) 957 tty_flip_buffer_push(tport); 958 959 return copied; 960 } 961 962 static int sci_handle_fifo_overrun(struct uart_port *port) 963 { 964 struct tty_port *tport = &port->state->port; 965 struct sci_port *s = to_sci_port(port); 966 const struct plat_sci_reg *reg; 967 int copied = 0; 968 u16 status; 969 970 reg = sci_getreg(port, s->params->overrun_reg); 971 if (!reg->size) 972 return 0; 973 974 status = serial_port_in(port, s->params->overrun_reg); 975 if (status & s->params->overrun_mask) { 976 status &= ~s->params->overrun_mask; 977 serial_port_out(port, s->params->overrun_reg, status); 978 979 port->icount.overrun++; 980 981 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 982 tty_flip_buffer_push(tport); 983 984 dev_dbg(port->dev, "overrun error\n"); 985 copied++; 986 } 987 988 return copied; 989 } 990 991 static int sci_handle_breaks(struct uart_port *port) 992 { 993 int copied = 0; 994 unsigned short status = serial_port_in(port, SCxSR); 995 struct tty_port *tport = &port->state->port; 996 997 if (uart_handle_break(port)) 998 return 0; 999 1000 if (status & SCxSR_BRK(port)) { 1001 port->icount.brk++; 1002 1003 /* Notify of BREAK */ 1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1005 copied++; 1006 1007 dev_dbg(port->dev, "BREAK detected\n"); 1008 } 1009 1010 if (copied) 1011 tty_flip_buffer_push(tport); 1012 1013 copied += sci_handle_fifo_overrun(port); 1014 1015 return copied; 1016 } 1017 1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1019 { 1020 unsigned int bits; 1021 1022 if (rx_trig < 1) 1023 rx_trig = 1; 1024 if (rx_trig >= port->fifosize) 1025 rx_trig = port->fifosize; 1026 1027 /* HSCIF can be set to an arbitrary level. */ 1028 if (sci_getreg(port, HSRTRGR)->size) { 1029 serial_port_out(port, HSRTRGR, rx_trig); 1030 return rx_trig; 1031 } 1032 1033 switch (port->type) { 1034 case PORT_SCIF: 1035 if (rx_trig < 4) { 1036 bits = 0; 1037 rx_trig = 1; 1038 } else if (rx_trig < 8) { 1039 bits = SCFCR_RTRG0; 1040 rx_trig = 4; 1041 } else if (rx_trig < 14) { 1042 bits = SCFCR_RTRG1; 1043 rx_trig = 8; 1044 } else { 1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1046 rx_trig = 14; 1047 } 1048 break; 1049 case PORT_SCIFA: 1050 case PORT_SCIFB: 1051 if (rx_trig < 16) { 1052 bits = 0; 1053 rx_trig = 1; 1054 } else if (rx_trig < 32) { 1055 bits = SCFCR_RTRG0; 1056 rx_trig = 16; 1057 } else if (rx_trig < 48) { 1058 bits = SCFCR_RTRG1; 1059 rx_trig = 32; 1060 } else { 1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1062 rx_trig = 48; 1063 } 1064 break; 1065 default: 1066 WARN(1, "unknown FIFO configuration"); 1067 return 1; 1068 } 1069 1070 serial_port_out(port, SCFCR, 1071 (serial_port_in(port, SCFCR) & 1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1073 1074 return rx_trig; 1075 } 1076 1077 static int scif_rtrg_enabled(struct uart_port *port) 1078 { 1079 if (sci_getreg(port, HSRTRGR)->size) 1080 return serial_port_in(port, HSRTRGR) != 0; 1081 else 1082 return (serial_port_in(port, SCFCR) & 1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1084 } 1085 1086 static void rx_fifo_timer_fn(struct timer_list *t) 1087 { 1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1089 struct uart_port *port = &s->port; 1090 1091 dev_dbg(port->dev, "Rx timed out\n"); 1092 scif_set_rtrg(port, 1); 1093 } 1094 1095 static ssize_t rx_trigger_show(struct device *dev, 1096 struct device_attribute *attr, 1097 char *buf) 1098 { 1099 struct uart_port *port = dev_get_drvdata(dev); 1100 struct sci_port *sci = to_sci_port(port); 1101 1102 return sprintf(buf, "%d\n", sci->rx_trigger); 1103 } 1104 1105 static ssize_t rx_trigger_store(struct device *dev, 1106 struct device_attribute *attr, 1107 const char *buf, 1108 size_t count) 1109 { 1110 struct uart_port *port = dev_get_drvdata(dev); 1111 struct sci_port *sci = to_sci_port(port); 1112 int ret; 1113 long r; 1114 1115 ret = kstrtol(buf, 0, &r); 1116 if (ret) 1117 return ret; 1118 1119 sci->rx_trigger = scif_set_rtrg(port, r); 1120 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1121 scif_set_rtrg(port, 1); 1122 1123 return count; 1124 } 1125 1126 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1127 1128 static ssize_t rx_fifo_timeout_show(struct device *dev, 1129 struct device_attribute *attr, 1130 char *buf) 1131 { 1132 struct uart_port *port = dev_get_drvdata(dev); 1133 struct sci_port *sci = to_sci_port(port); 1134 int v; 1135 1136 if (port->type == PORT_HSCIF) 1137 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1138 else 1139 v = sci->rx_fifo_timeout; 1140 1141 return sprintf(buf, "%d\n", v); 1142 } 1143 1144 static ssize_t rx_fifo_timeout_store(struct device *dev, 1145 struct device_attribute *attr, 1146 const char *buf, 1147 size_t count) 1148 { 1149 struct uart_port *port = dev_get_drvdata(dev); 1150 struct sci_port *sci = to_sci_port(port); 1151 int ret; 1152 long r; 1153 1154 ret = kstrtol(buf, 0, &r); 1155 if (ret) 1156 return ret; 1157 1158 if (port->type == PORT_HSCIF) { 1159 if (r < 0 || r > 3) 1160 return -EINVAL; 1161 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1162 } else { 1163 sci->rx_fifo_timeout = r; 1164 scif_set_rtrg(port, 1); 1165 if (r > 0) 1166 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1167 } 1168 1169 return count; 1170 } 1171 1172 static DEVICE_ATTR_RW(rx_fifo_timeout); 1173 1174 1175 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1176 static void sci_dma_tx_complete(void *arg) 1177 { 1178 struct sci_port *s = arg; 1179 struct uart_port *port = &s->port; 1180 struct circ_buf *xmit = &port->state->xmit; 1181 unsigned long flags; 1182 1183 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1184 1185 spin_lock_irqsave(&port->lock, flags); 1186 1187 xmit->tail += s->tx_dma_len; 1188 xmit->tail &= UART_XMIT_SIZE - 1; 1189 1190 port->icount.tx += s->tx_dma_len; 1191 1192 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1193 uart_write_wakeup(port); 1194 1195 if (!uart_circ_empty(xmit)) { 1196 s->cookie_tx = 0; 1197 schedule_work(&s->work_tx); 1198 } else { 1199 s->cookie_tx = -EINVAL; 1200 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1201 u16 ctrl = serial_port_in(port, SCSCR); 1202 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1203 } 1204 } 1205 1206 spin_unlock_irqrestore(&port->lock, flags); 1207 } 1208 1209 /* Locking: called with port lock held */ 1210 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1211 { 1212 struct uart_port *port = &s->port; 1213 struct tty_port *tport = &port->state->port; 1214 int copied; 1215 1216 copied = tty_insert_flip_string(tport, buf, count); 1217 if (copied < count) 1218 port->icount.buf_overrun++; 1219 1220 port->icount.rx += copied; 1221 1222 return copied; 1223 } 1224 1225 static int sci_dma_rx_find_active(struct sci_port *s) 1226 { 1227 unsigned int i; 1228 1229 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1230 if (s->active_rx == s->cookie_rx[i]) 1231 return i; 1232 1233 return -1; 1234 } 1235 1236 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1237 { 1238 unsigned int i; 1239 1240 s->chan_rx = NULL; 1241 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1242 s->cookie_rx[i] = -EINVAL; 1243 s->active_rx = 0; 1244 } 1245 1246 static void sci_dma_rx_release(struct sci_port *s) 1247 { 1248 struct dma_chan *chan = s->chan_rx_saved; 1249 1250 s->chan_rx_saved = NULL; 1251 sci_dma_rx_chan_invalidate(s); 1252 dmaengine_terminate_sync(chan); 1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1254 sg_dma_address(&s->sg_rx[0])); 1255 dma_release_channel(chan); 1256 } 1257 1258 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1259 { 1260 long sec = usec / 1000000; 1261 long nsec = (usec % 1000000) * 1000; 1262 ktime_t t = ktime_set(sec, nsec); 1263 1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1265 } 1266 1267 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1268 { 1269 struct uart_port *port = &s->port; 1270 u16 scr; 1271 1272 /* Direct new serial port interrupts back to CPU */ 1273 scr = serial_port_in(port, SCSCR); 1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1275 scr &= ~SCSCR_RDRQE; 1276 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1277 } 1278 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1279 } 1280 1281 static void sci_dma_rx_complete(void *arg) 1282 { 1283 struct sci_port *s = arg; 1284 struct dma_chan *chan = s->chan_rx; 1285 struct uart_port *port = &s->port; 1286 struct dma_async_tx_descriptor *desc; 1287 unsigned long flags; 1288 int active, count = 0; 1289 1290 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1291 s->active_rx); 1292 1293 spin_lock_irqsave(&port->lock, flags); 1294 1295 active = sci_dma_rx_find_active(s); 1296 if (active >= 0) 1297 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1298 1299 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1300 1301 if (count) 1302 tty_flip_buffer_push(&port->state->port); 1303 1304 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1305 DMA_DEV_TO_MEM, 1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1307 if (!desc) 1308 goto fail; 1309 1310 desc->callback = sci_dma_rx_complete; 1311 desc->callback_param = s; 1312 s->cookie_rx[active] = dmaengine_submit(desc); 1313 if (dma_submit_error(s->cookie_rx[active])) 1314 goto fail; 1315 1316 s->active_rx = s->cookie_rx[!active]; 1317 1318 dma_async_issue_pending(chan); 1319 1320 spin_unlock_irqrestore(&port->lock, flags); 1321 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1322 __func__, s->cookie_rx[active], active, s->active_rx); 1323 return; 1324 1325 fail: 1326 spin_unlock_irqrestore(&port->lock, flags); 1327 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1328 /* Switch to PIO */ 1329 spin_lock_irqsave(&port->lock, flags); 1330 dmaengine_terminate_async(chan); 1331 sci_dma_rx_chan_invalidate(s); 1332 sci_dma_rx_reenable_irq(s); 1333 spin_unlock_irqrestore(&port->lock, flags); 1334 } 1335 1336 static void sci_dma_tx_release(struct sci_port *s) 1337 { 1338 struct dma_chan *chan = s->chan_tx_saved; 1339 1340 cancel_work_sync(&s->work_tx); 1341 s->chan_tx_saved = s->chan_tx = NULL; 1342 s->cookie_tx = -EINVAL; 1343 dmaengine_terminate_sync(chan); 1344 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1345 DMA_TO_DEVICE); 1346 dma_release_channel(chan); 1347 } 1348 1349 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1350 { 1351 struct dma_chan *chan = s->chan_rx; 1352 struct uart_port *port = &s->port; 1353 unsigned long flags; 1354 int i; 1355 1356 for (i = 0; i < 2; i++) { 1357 struct scatterlist *sg = &s->sg_rx[i]; 1358 struct dma_async_tx_descriptor *desc; 1359 1360 desc = dmaengine_prep_slave_sg(chan, 1361 sg, 1, DMA_DEV_TO_MEM, 1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1363 if (!desc) 1364 goto fail; 1365 1366 desc->callback = sci_dma_rx_complete; 1367 desc->callback_param = s; 1368 s->cookie_rx[i] = dmaengine_submit(desc); 1369 if (dma_submit_error(s->cookie_rx[i])) 1370 goto fail; 1371 1372 } 1373 1374 s->active_rx = s->cookie_rx[0]; 1375 1376 dma_async_issue_pending(chan); 1377 return 0; 1378 1379 fail: 1380 /* Switch to PIO */ 1381 if (!port_lock_held) 1382 spin_lock_irqsave(&port->lock, flags); 1383 if (i) 1384 dmaengine_terminate_async(chan); 1385 sci_dma_rx_chan_invalidate(s); 1386 sci_start_rx(port); 1387 if (!port_lock_held) 1388 spin_unlock_irqrestore(&port->lock, flags); 1389 return -EAGAIN; 1390 } 1391 1392 static void sci_dma_tx_work_fn(struct work_struct *work) 1393 { 1394 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1395 struct dma_async_tx_descriptor *desc; 1396 struct dma_chan *chan = s->chan_tx; 1397 struct uart_port *port = &s->port; 1398 struct circ_buf *xmit = &port->state->xmit; 1399 unsigned long flags; 1400 dma_addr_t buf; 1401 int head, tail; 1402 1403 /* 1404 * DMA is idle now. 1405 * Port xmit buffer is already mapped, and it is one page... Just adjust 1406 * offsets and lengths. Since it is a circular buffer, we have to 1407 * transmit till the end, and then the rest. Take the port lock to get a 1408 * consistent xmit buffer state. 1409 */ 1410 spin_lock_irq(&port->lock); 1411 head = xmit->head; 1412 tail = xmit->tail; 1413 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1414 s->tx_dma_len = min_t(unsigned int, 1415 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1416 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1417 if (!s->tx_dma_len) { 1418 /* Transmit buffer has been flushed */ 1419 spin_unlock_irq(&port->lock); 1420 return; 1421 } 1422 1423 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1424 DMA_MEM_TO_DEV, 1425 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1426 if (!desc) { 1427 spin_unlock_irq(&port->lock); 1428 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1429 goto switch_to_pio; 1430 } 1431 1432 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1433 DMA_TO_DEVICE); 1434 1435 desc->callback = sci_dma_tx_complete; 1436 desc->callback_param = s; 1437 s->cookie_tx = dmaengine_submit(desc); 1438 if (dma_submit_error(s->cookie_tx)) { 1439 spin_unlock_irq(&port->lock); 1440 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1441 goto switch_to_pio; 1442 } 1443 1444 spin_unlock_irq(&port->lock); 1445 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1446 __func__, xmit->buf, tail, head, s->cookie_tx); 1447 1448 dma_async_issue_pending(chan); 1449 return; 1450 1451 switch_to_pio: 1452 spin_lock_irqsave(&port->lock, flags); 1453 s->chan_tx = NULL; 1454 sci_start_tx(port); 1455 spin_unlock_irqrestore(&port->lock, flags); 1456 return; 1457 } 1458 1459 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1460 { 1461 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1462 struct dma_chan *chan = s->chan_rx; 1463 struct uart_port *port = &s->port; 1464 struct dma_tx_state state; 1465 enum dma_status status; 1466 unsigned long flags; 1467 unsigned int read; 1468 int active, count; 1469 1470 dev_dbg(port->dev, "DMA Rx timed out\n"); 1471 1472 spin_lock_irqsave(&port->lock, flags); 1473 1474 active = sci_dma_rx_find_active(s); 1475 if (active < 0) { 1476 spin_unlock_irqrestore(&port->lock, flags); 1477 return HRTIMER_NORESTART; 1478 } 1479 1480 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1481 if (status == DMA_COMPLETE) { 1482 spin_unlock_irqrestore(&port->lock, flags); 1483 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1484 s->active_rx, active); 1485 1486 /* Let packet complete handler take care of the packet */ 1487 return HRTIMER_NORESTART; 1488 } 1489 1490 dmaengine_pause(chan); 1491 1492 /* 1493 * sometimes DMA transfer doesn't stop even if it is stopped and 1494 * data keeps on coming until transaction is complete so check 1495 * for DMA_COMPLETE again 1496 * Let packet complete handler take care of the packet 1497 */ 1498 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1499 if (status == DMA_COMPLETE) { 1500 spin_unlock_irqrestore(&port->lock, flags); 1501 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1502 return HRTIMER_NORESTART; 1503 } 1504 1505 /* Handle incomplete DMA receive */ 1506 dmaengine_terminate_async(s->chan_rx); 1507 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1508 1509 if (read) { 1510 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1511 if (count) 1512 tty_flip_buffer_push(&port->state->port); 1513 } 1514 1515 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1516 sci_dma_rx_submit(s, true); 1517 1518 sci_dma_rx_reenable_irq(s); 1519 1520 spin_unlock_irqrestore(&port->lock, flags); 1521 1522 return HRTIMER_NORESTART; 1523 } 1524 1525 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1526 enum dma_transfer_direction dir) 1527 { 1528 struct dma_chan *chan; 1529 struct dma_slave_config cfg; 1530 int ret; 1531 1532 chan = dma_request_slave_channel(port->dev, 1533 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1534 if (!chan) { 1535 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1536 return NULL; 1537 } 1538 1539 memset(&cfg, 0, sizeof(cfg)); 1540 cfg.direction = dir; 1541 if (dir == DMA_MEM_TO_DEV) { 1542 cfg.dst_addr = port->mapbase + 1543 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1544 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1545 } else { 1546 cfg.src_addr = port->mapbase + 1547 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1548 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1549 } 1550 1551 ret = dmaengine_slave_config(chan, &cfg); 1552 if (ret) { 1553 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1554 dma_release_channel(chan); 1555 return NULL; 1556 } 1557 1558 return chan; 1559 } 1560 1561 static void sci_request_dma(struct uart_port *port) 1562 { 1563 struct sci_port *s = to_sci_port(port); 1564 struct dma_chan *chan; 1565 1566 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1567 1568 /* 1569 * DMA on console may interfere with Kernel log messages which use 1570 * plain putchar(). So, simply don't use it with a console. 1571 */ 1572 if (uart_console(port)) 1573 return; 1574 1575 if (!port->dev->of_node) 1576 return; 1577 1578 s->cookie_tx = -EINVAL; 1579 1580 /* 1581 * Don't request a dma channel if no channel was specified 1582 * in the device tree. 1583 */ 1584 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1585 return; 1586 1587 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1588 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1589 if (chan) { 1590 /* UART circular tx buffer is an aligned page. */ 1591 s->tx_dma_addr = dma_map_single(chan->device->dev, 1592 port->state->xmit.buf, 1593 UART_XMIT_SIZE, 1594 DMA_TO_DEVICE); 1595 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1596 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1597 dma_release_channel(chan); 1598 } else { 1599 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1600 __func__, UART_XMIT_SIZE, 1601 port->state->xmit.buf, &s->tx_dma_addr); 1602 1603 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1604 s->chan_tx_saved = s->chan_tx = chan; 1605 } 1606 } 1607 1608 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1609 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1610 if (chan) { 1611 unsigned int i; 1612 dma_addr_t dma; 1613 void *buf; 1614 1615 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1616 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1617 &dma, GFP_KERNEL); 1618 if (!buf) { 1619 dev_warn(port->dev, 1620 "Failed to allocate Rx dma buffer, using PIO\n"); 1621 dma_release_channel(chan); 1622 return; 1623 } 1624 1625 for (i = 0; i < 2; i++) { 1626 struct scatterlist *sg = &s->sg_rx[i]; 1627 1628 sg_init_table(sg, 1); 1629 s->rx_buf[i] = buf; 1630 sg_dma_address(sg) = dma; 1631 sg_dma_len(sg) = s->buf_len_rx; 1632 1633 buf += s->buf_len_rx; 1634 dma += s->buf_len_rx; 1635 } 1636 1637 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1638 s->rx_timer.function = sci_dma_rx_timer_fn; 1639 1640 s->chan_rx_saved = s->chan_rx = chan; 1641 1642 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1643 sci_dma_rx_submit(s, false); 1644 } 1645 } 1646 1647 static void sci_free_dma(struct uart_port *port) 1648 { 1649 struct sci_port *s = to_sci_port(port); 1650 1651 if (s->chan_tx_saved) 1652 sci_dma_tx_release(s); 1653 if (s->chan_rx_saved) 1654 sci_dma_rx_release(s); 1655 } 1656 1657 static void sci_flush_buffer(struct uart_port *port) 1658 { 1659 struct sci_port *s = to_sci_port(port); 1660 1661 /* 1662 * In uart_flush_buffer(), the xmit circular buffer has just been 1663 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1664 * pending transfers 1665 */ 1666 s->tx_dma_len = 0; 1667 if (s->chan_tx) { 1668 dmaengine_terminate_async(s->chan_tx); 1669 s->cookie_tx = -EINVAL; 1670 } 1671 } 1672 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1673 static inline void sci_request_dma(struct uart_port *port) 1674 { 1675 } 1676 1677 static inline void sci_free_dma(struct uart_port *port) 1678 { 1679 } 1680 1681 #define sci_flush_buffer NULL 1682 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1683 1684 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1685 { 1686 struct uart_port *port = ptr; 1687 struct sci_port *s = to_sci_port(port); 1688 1689 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1690 if (s->chan_rx) { 1691 u16 scr = serial_port_in(port, SCSCR); 1692 u16 ssr = serial_port_in(port, SCxSR); 1693 1694 /* Disable future Rx interrupts */ 1695 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1696 disable_irq_nosync(irq); 1697 scr |= SCSCR_RDRQE; 1698 } else { 1699 if (sci_dma_rx_submit(s, false) < 0) 1700 goto handle_pio; 1701 1702 scr &= ~SCSCR_RIE; 1703 } 1704 serial_port_out(port, SCSCR, scr); 1705 /* Clear current interrupt */ 1706 serial_port_out(port, SCxSR, 1707 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1708 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1709 jiffies, s->rx_timeout); 1710 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1711 1712 return IRQ_HANDLED; 1713 } 1714 1715 handle_pio: 1716 #endif 1717 1718 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1719 if (!scif_rtrg_enabled(port)) 1720 scif_set_rtrg(port, s->rx_trigger); 1721 1722 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1723 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1724 } 1725 1726 /* I think sci_receive_chars has to be called irrespective 1727 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1728 * to be disabled? 1729 */ 1730 sci_receive_chars(port); 1731 1732 return IRQ_HANDLED; 1733 } 1734 1735 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1736 { 1737 struct uart_port *port = ptr; 1738 unsigned long flags; 1739 1740 spin_lock_irqsave(&port->lock, flags); 1741 sci_transmit_chars(port); 1742 spin_unlock_irqrestore(&port->lock, flags); 1743 1744 return IRQ_HANDLED; 1745 } 1746 1747 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1748 { 1749 struct uart_port *port = ptr; 1750 1751 /* Handle BREAKs */ 1752 sci_handle_breaks(port); 1753 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1754 1755 return IRQ_HANDLED; 1756 } 1757 1758 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1759 { 1760 struct uart_port *port = ptr; 1761 struct sci_port *s = to_sci_port(port); 1762 1763 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1764 /* Break and Error interrupts are muxed */ 1765 unsigned short ssr_status = serial_port_in(port, SCxSR); 1766 1767 /* Break Interrupt */ 1768 if (ssr_status & SCxSR_BRK(port)) 1769 sci_br_interrupt(irq, ptr); 1770 1771 /* Break only? */ 1772 if (!(ssr_status & SCxSR_ERRORS(port))) 1773 return IRQ_HANDLED; 1774 } 1775 1776 /* Handle errors */ 1777 if (port->type == PORT_SCI) { 1778 if (sci_handle_errors(port)) { 1779 /* discard character in rx buffer */ 1780 serial_port_in(port, SCxSR); 1781 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1782 } 1783 } else { 1784 sci_handle_fifo_overrun(port); 1785 if (!s->chan_rx) 1786 sci_receive_chars(port); 1787 } 1788 1789 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1790 1791 /* Kick the transmission */ 1792 if (!s->chan_tx) 1793 sci_tx_interrupt(irq, ptr); 1794 1795 return IRQ_HANDLED; 1796 } 1797 1798 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1799 { 1800 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1801 struct uart_port *port = ptr; 1802 struct sci_port *s = to_sci_port(port); 1803 irqreturn_t ret = IRQ_NONE; 1804 1805 ssr_status = serial_port_in(port, SCxSR); 1806 scr_status = serial_port_in(port, SCSCR); 1807 if (s->params->overrun_reg == SCxSR) 1808 orer_status = ssr_status; 1809 else if (sci_getreg(port, s->params->overrun_reg)->size) 1810 orer_status = serial_port_in(port, s->params->overrun_reg); 1811 1812 err_enabled = scr_status & port_rx_irq_mask(port); 1813 1814 /* Tx Interrupt */ 1815 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1816 !s->chan_tx) 1817 ret = sci_tx_interrupt(irq, ptr); 1818 1819 /* 1820 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1821 * DR flags 1822 */ 1823 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1824 (scr_status & SCSCR_RIE)) 1825 ret = sci_rx_interrupt(irq, ptr); 1826 1827 /* Error Interrupt */ 1828 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1829 ret = sci_er_interrupt(irq, ptr); 1830 1831 /* Break Interrupt */ 1832 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1833 ret = sci_br_interrupt(irq, ptr); 1834 1835 /* Overrun Interrupt */ 1836 if (orer_status & s->params->overrun_mask) { 1837 sci_handle_fifo_overrun(port); 1838 ret = IRQ_HANDLED; 1839 } 1840 1841 return ret; 1842 } 1843 1844 static const struct sci_irq_desc { 1845 const char *desc; 1846 irq_handler_t handler; 1847 } sci_irq_desc[] = { 1848 /* 1849 * Split out handlers, the default case. 1850 */ 1851 [SCIx_ERI_IRQ] = { 1852 .desc = "rx err", 1853 .handler = sci_er_interrupt, 1854 }, 1855 1856 [SCIx_RXI_IRQ] = { 1857 .desc = "rx full", 1858 .handler = sci_rx_interrupt, 1859 }, 1860 1861 [SCIx_TXI_IRQ] = { 1862 .desc = "tx empty", 1863 .handler = sci_tx_interrupt, 1864 }, 1865 1866 [SCIx_BRI_IRQ] = { 1867 .desc = "break", 1868 .handler = sci_br_interrupt, 1869 }, 1870 1871 [SCIx_DRI_IRQ] = { 1872 .desc = "rx ready", 1873 .handler = sci_rx_interrupt, 1874 }, 1875 1876 [SCIx_TEI_IRQ] = { 1877 .desc = "tx end", 1878 .handler = sci_tx_interrupt, 1879 }, 1880 1881 /* 1882 * Special muxed handler. 1883 */ 1884 [SCIx_MUX_IRQ] = { 1885 .desc = "mux", 1886 .handler = sci_mpxed_interrupt, 1887 }, 1888 }; 1889 1890 static int sci_request_irq(struct sci_port *port) 1891 { 1892 struct uart_port *up = &port->port; 1893 int i, j, w, ret = 0; 1894 1895 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1896 const struct sci_irq_desc *desc; 1897 int irq; 1898 1899 /* Check if already registered (muxed) */ 1900 for (w = 0; w < i; w++) 1901 if (port->irqs[w] == port->irqs[i]) 1902 w = i + 1; 1903 if (w > i) 1904 continue; 1905 1906 if (SCIx_IRQ_IS_MUXED(port)) { 1907 i = SCIx_MUX_IRQ; 1908 irq = up->irq; 1909 } else { 1910 irq = port->irqs[i]; 1911 1912 /* 1913 * Certain port types won't support all of the 1914 * available interrupt sources. 1915 */ 1916 if (unlikely(irq < 0)) 1917 continue; 1918 } 1919 1920 desc = sci_irq_desc + i; 1921 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1922 dev_name(up->dev), desc->desc); 1923 if (!port->irqstr[j]) { 1924 ret = -ENOMEM; 1925 goto out_nomem; 1926 } 1927 1928 ret = request_irq(irq, desc->handler, up->irqflags, 1929 port->irqstr[j], port); 1930 if (unlikely(ret)) { 1931 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1932 goto out_noirq; 1933 } 1934 } 1935 1936 return 0; 1937 1938 out_noirq: 1939 while (--i >= 0) 1940 free_irq(port->irqs[i], port); 1941 1942 out_nomem: 1943 while (--j >= 0) 1944 kfree(port->irqstr[j]); 1945 1946 return ret; 1947 } 1948 1949 static void sci_free_irq(struct sci_port *port) 1950 { 1951 int i, j; 1952 1953 /* 1954 * Intentionally in reverse order so we iterate over the muxed 1955 * IRQ first. 1956 */ 1957 for (i = 0; i < SCIx_NR_IRQS; i++) { 1958 int irq = port->irqs[i]; 1959 1960 /* 1961 * Certain port types won't support all of the available 1962 * interrupt sources. 1963 */ 1964 if (unlikely(irq < 0)) 1965 continue; 1966 1967 /* Check if already freed (irq was muxed) */ 1968 for (j = 0; j < i; j++) 1969 if (port->irqs[j] == irq) 1970 j = i + 1; 1971 if (j > i) 1972 continue; 1973 1974 free_irq(port->irqs[i], port); 1975 kfree(port->irqstr[i]); 1976 1977 if (SCIx_IRQ_IS_MUXED(port)) { 1978 /* If there's only one IRQ, we're done. */ 1979 return; 1980 } 1981 } 1982 } 1983 1984 static unsigned int sci_tx_empty(struct uart_port *port) 1985 { 1986 unsigned short status = serial_port_in(port, SCxSR); 1987 unsigned short in_tx_fifo = sci_txfill(port); 1988 1989 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1990 } 1991 1992 static void sci_set_rts(struct uart_port *port, bool state) 1993 { 1994 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1995 u16 data = serial_port_in(port, SCPDR); 1996 1997 /* Active low */ 1998 if (state) 1999 data &= ~SCPDR_RTSD; 2000 else 2001 data |= SCPDR_RTSD; 2002 serial_port_out(port, SCPDR, data); 2003 2004 /* RTS# is output */ 2005 serial_port_out(port, SCPCR, 2006 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2007 } else if (sci_getreg(port, SCSPTR)->size) { 2008 u16 ctrl = serial_port_in(port, SCSPTR); 2009 2010 /* Active low */ 2011 if (state) 2012 ctrl &= ~SCSPTR_RTSDT; 2013 else 2014 ctrl |= SCSPTR_RTSDT; 2015 serial_port_out(port, SCSPTR, ctrl); 2016 } 2017 } 2018 2019 static bool sci_get_cts(struct uart_port *port) 2020 { 2021 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2022 /* Active low */ 2023 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2024 } else if (sci_getreg(port, SCSPTR)->size) { 2025 /* Active low */ 2026 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2027 } 2028 2029 return true; 2030 } 2031 2032 /* 2033 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2034 * CTS/RTS is supported in hardware by at least one port and controlled 2035 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2036 * handled via the ->init_pins() op, which is a bit of a one-way street, 2037 * lacking any ability to defer pin control -- this will later be 2038 * converted over to the GPIO framework). 2039 * 2040 * Other modes (such as loopback) are supported generically on certain 2041 * port types, but not others. For these it's sufficient to test for the 2042 * existence of the support register and simply ignore the port type. 2043 */ 2044 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2045 { 2046 struct sci_port *s = to_sci_port(port); 2047 2048 if (mctrl & TIOCM_LOOP) { 2049 const struct plat_sci_reg *reg; 2050 2051 /* 2052 * Standard loopback mode for SCFCR ports. 2053 */ 2054 reg = sci_getreg(port, SCFCR); 2055 if (reg->size) 2056 serial_port_out(port, SCFCR, 2057 serial_port_in(port, SCFCR) | 2058 SCFCR_LOOP); 2059 } 2060 2061 mctrl_gpio_set(s->gpios, mctrl); 2062 2063 if (!s->has_rtscts) 2064 return; 2065 2066 if (!(mctrl & TIOCM_RTS)) { 2067 /* Disable Auto RTS */ 2068 serial_port_out(port, SCFCR, 2069 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2070 2071 /* Clear RTS */ 2072 sci_set_rts(port, 0); 2073 } else if (s->autorts) { 2074 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2075 /* Enable RTS# pin function */ 2076 serial_port_out(port, SCPCR, 2077 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2078 } 2079 2080 /* Enable Auto RTS */ 2081 serial_port_out(port, SCFCR, 2082 serial_port_in(port, SCFCR) | SCFCR_MCE); 2083 } else { 2084 /* Set RTS */ 2085 sci_set_rts(port, 1); 2086 } 2087 } 2088 2089 static unsigned int sci_get_mctrl(struct uart_port *port) 2090 { 2091 struct sci_port *s = to_sci_port(port); 2092 struct mctrl_gpios *gpios = s->gpios; 2093 unsigned int mctrl = 0; 2094 2095 mctrl_gpio_get(gpios, &mctrl); 2096 2097 /* 2098 * CTS/RTS is handled in hardware when supported, while nothing 2099 * else is wired up. 2100 */ 2101 if (s->autorts) { 2102 if (sci_get_cts(port)) 2103 mctrl |= TIOCM_CTS; 2104 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 2105 mctrl |= TIOCM_CTS; 2106 } 2107 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 2108 mctrl |= TIOCM_DSR; 2109 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 2110 mctrl |= TIOCM_CAR; 2111 2112 return mctrl; 2113 } 2114 2115 static void sci_enable_ms(struct uart_port *port) 2116 { 2117 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2118 } 2119 2120 static void sci_break_ctl(struct uart_port *port, int break_state) 2121 { 2122 unsigned short scscr, scsptr; 2123 unsigned long flags; 2124 2125 /* check wheter the port has SCSPTR */ 2126 if (!sci_getreg(port, SCSPTR)->size) { 2127 /* 2128 * Not supported by hardware. Most parts couple break and rx 2129 * interrupts together, with break detection always enabled. 2130 */ 2131 return; 2132 } 2133 2134 spin_lock_irqsave(&port->lock, flags); 2135 scsptr = serial_port_in(port, SCSPTR); 2136 scscr = serial_port_in(port, SCSCR); 2137 2138 if (break_state == -1) { 2139 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2140 scscr &= ~SCSCR_TE; 2141 } else { 2142 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2143 scscr |= SCSCR_TE; 2144 } 2145 2146 serial_port_out(port, SCSPTR, scsptr); 2147 serial_port_out(port, SCSCR, scscr); 2148 spin_unlock_irqrestore(&port->lock, flags); 2149 } 2150 2151 static int sci_startup(struct uart_port *port) 2152 { 2153 struct sci_port *s = to_sci_port(port); 2154 int ret; 2155 2156 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2157 2158 sci_request_dma(port); 2159 2160 ret = sci_request_irq(s); 2161 if (unlikely(ret < 0)) { 2162 sci_free_dma(port); 2163 return ret; 2164 } 2165 2166 return 0; 2167 } 2168 2169 static void sci_shutdown(struct uart_port *port) 2170 { 2171 struct sci_port *s = to_sci_port(port); 2172 unsigned long flags; 2173 u16 scr; 2174 2175 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2176 2177 s->autorts = false; 2178 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2179 2180 spin_lock_irqsave(&port->lock, flags); 2181 sci_stop_rx(port); 2182 sci_stop_tx(port); 2183 /* 2184 * Stop RX and TX, disable related interrupts, keep clock source 2185 * and HSCIF TOT bits 2186 */ 2187 scr = serial_port_in(port, SCSCR); 2188 serial_port_out(port, SCSCR, scr & 2189 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2190 spin_unlock_irqrestore(&port->lock, flags); 2191 2192 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2193 if (s->chan_rx_saved) { 2194 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2195 port->line); 2196 hrtimer_cancel(&s->rx_timer); 2197 } 2198 #endif 2199 2200 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2201 del_timer_sync(&s->rx_fifo_timer); 2202 sci_free_irq(s); 2203 sci_free_dma(port); 2204 } 2205 2206 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2207 unsigned int *srr) 2208 { 2209 unsigned long freq = s->clk_rates[SCI_SCK]; 2210 int err, min_err = INT_MAX; 2211 unsigned int sr; 2212 2213 if (s->port.type != PORT_HSCIF) 2214 freq *= 2; 2215 2216 for_each_sr(sr, s) { 2217 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2218 if (abs(err) >= abs(min_err)) 2219 continue; 2220 2221 min_err = err; 2222 *srr = sr - 1; 2223 2224 if (!err) 2225 break; 2226 } 2227 2228 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2229 *srr + 1); 2230 return min_err; 2231 } 2232 2233 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2234 unsigned long freq, unsigned int *dlr, 2235 unsigned int *srr) 2236 { 2237 int err, min_err = INT_MAX; 2238 unsigned int sr, dl; 2239 2240 if (s->port.type != PORT_HSCIF) 2241 freq *= 2; 2242 2243 for_each_sr(sr, s) { 2244 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2245 dl = clamp(dl, 1U, 65535U); 2246 2247 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2248 if (abs(err) >= abs(min_err)) 2249 continue; 2250 2251 min_err = err; 2252 *dlr = dl; 2253 *srr = sr - 1; 2254 2255 if (!err) 2256 break; 2257 } 2258 2259 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2260 min_err, *dlr, *srr + 1); 2261 return min_err; 2262 } 2263 2264 /* calculate sample rate, BRR, and clock select */ 2265 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2266 unsigned int *brr, unsigned int *srr, 2267 unsigned int *cks) 2268 { 2269 unsigned long freq = s->clk_rates[SCI_FCK]; 2270 unsigned int sr, br, prediv, scrate, c; 2271 int err, min_err = INT_MAX; 2272 2273 if (s->port.type != PORT_HSCIF) 2274 freq *= 2; 2275 2276 /* 2277 * Find the combination of sample rate and clock select with the 2278 * smallest deviation from the desired baud rate. 2279 * Prefer high sample rates to maximise the receive margin. 2280 * 2281 * M: Receive margin (%) 2282 * N: Ratio of bit rate to clock (N = sampling rate) 2283 * D: Clock duty (D = 0 to 1.0) 2284 * L: Frame length (L = 9 to 12) 2285 * F: Absolute value of clock frequency deviation 2286 * 2287 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2288 * (|D - 0.5| / N * (1 + F))| 2289 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2290 */ 2291 for_each_sr(sr, s) { 2292 for (c = 0; c <= 3; c++) { 2293 /* integerized formulas from HSCIF documentation */ 2294 prediv = sr * (1 << (2 * c + 1)); 2295 2296 /* 2297 * We need to calculate: 2298 * 2299 * br = freq / (prediv * bps) clamped to [1..256] 2300 * err = freq / (br * prediv) - bps 2301 * 2302 * Watch out for overflow when calculating the desired 2303 * sampling clock rate! 2304 */ 2305 if (bps > UINT_MAX / prediv) 2306 break; 2307 2308 scrate = prediv * bps; 2309 br = DIV_ROUND_CLOSEST(freq, scrate); 2310 br = clamp(br, 1U, 256U); 2311 2312 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2313 if (abs(err) >= abs(min_err)) 2314 continue; 2315 2316 min_err = err; 2317 *brr = br - 1; 2318 *srr = sr - 1; 2319 *cks = c; 2320 2321 if (!err) 2322 goto found; 2323 } 2324 } 2325 2326 found: 2327 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2328 min_err, *brr, *srr + 1, *cks); 2329 return min_err; 2330 } 2331 2332 static void sci_reset(struct uart_port *port) 2333 { 2334 const struct plat_sci_reg *reg; 2335 unsigned int status; 2336 struct sci_port *s = to_sci_port(port); 2337 2338 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2339 2340 reg = sci_getreg(port, SCFCR); 2341 if (reg->size) 2342 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2343 2344 sci_clear_SCxSR(port, 2345 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2346 SCxSR_BREAK_CLEAR(port)); 2347 if (sci_getreg(port, SCLSR)->size) { 2348 status = serial_port_in(port, SCLSR); 2349 status &= ~(SCLSR_TO | SCLSR_ORER); 2350 serial_port_out(port, SCLSR, status); 2351 } 2352 2353 if (s->rx_trigger > 1) { 2354 if (s->rx_fifo_timeout) { 2355 scif_set_rtrg(port, 1); 2356 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2357 } else { 2358 if (port->type == PORT_SCIFA || 2359 port->type == PORT_SCIFB) 2360 scif_set_rtrg(port, 1); 2361 else 2362 scif_set_rtrg(port, s->rx_trigger); 2363 } 2364 } 2365 } 2366 2367 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2368 struct ktermios *old) 2369 { 2370 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2371 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2372 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2373 struct sci_port *s = to_sci_port(port); 2374 const struct plat_sci_reg *reg; 2375 int min_err = INT_MAX, err; 2376 unsigned long max_freq = 0; 2377 int best_clk = -1; 2378 unsigned long flags; 2379 2380 if ((termios->c_cflag & CSIZE) == CS7) 2381 smr_val |= SCSMR_CHR; 2382 if (termios->c_cflag & PARENB) 2383 smr_val |= SCSMR_PE; 2384 if (termios->c_cflag & PARODD) 2385 smr_val |= SCSMR_PE | SCSMR_ODD; 2386 if (termios->c_cflag & CSTOPB) 2387 smr_val |= SCSMR_STOP; 2388 2389 /* 2390 * earlyprintk comes here early on with port->uartclk set to zero. 2391 * the clock framework is not up and running at this point so here 2392 * we assume that 115200 is the maximum baud rate. please note that 2393 * the baud rate is not programmed during earlyprintk - it is assumed 2394 * that the previous boot loader has enabled required clocks and 2395 * setup the baud rate generator hardware for us already. 2396 */ 2397 if (!port->uartclk) { 2398 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2399 goto done; 2400 } 2401 2402 for (i = 0; i < SCI_NUM_CLKS; i++) 2403 max_freq = max(max_freq, s->clk_rates[i]); 2404 2405 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2406 if (!baud) 2407 goto done; 2408 2409 /* 2410 * There can be multiple sources for the sampling clock. Find the one 2411 * that gives us the smallest deviation from the desired baud rate. 2412 */ 2413 2414 /* Optional Undivided External Clock */ 2415 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2416 port->type != PORT_SCIFB) { 2417 err = sci_sck_calc(s, baud, &srr1); 2418 if (abs(err) < abs(min_err)) { 2419 best_clk = SCI_SCK; 2420 scr_val = SCSCR_CKE1; 2421 sccks = SCCKS_CKS; 2422 min_err = err; 2423 srr = srr1; 2424 if (!err) 2425 goto done; 2426 } 2427 } 2428 2429 /* Optional BRG Frequency Divided External Clock */ 2430 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2431 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2432 &srr1); 2433 if (abs(err) < abs(min_err)) { 2434 best_clk = SCI_SCIF_CLK; 2435 scr_val = SCSCR_CKE1; 2436 sccks = 0; 2437 min_err = err; 2438 dl = dl1; 2439 srr = srr1; 2440 if (!err) 2441 goto done; 2442 } 2443 } 2444 2445 /* Optional BRG Frequency Divided Internal Clock */ 2446 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2447 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2448 &srr1); 2449 if (abs(err) < abs(min_err)) { 2450 best_clk = SCI_BRG_INT; 2451 scr_val = SCSCR_CKE1; 2452 sccks = SCCKS_XIN; 2453 min_err = err; 2454 dl = dl1; 2455 srr = srr1; 2456 if (!min_err) 2457 goto done; 2458 } 2459 } 2460 2461 /* Divided Functional Clock using standard Bit Rate Register */ 2462 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2463 if (abs(err) < abs(min_err)) { 2464 best_clk = SCI_FCK; 2465 scr_val = 0; 2466 min_err = err; 2467 brr = brr1; 2468 srr = srr1; 2469 cks = cks1; 2470 } 2471 2472 done: 2473 if (best_clk >= 0) 2474 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2475 s->clks[best_clk], baud, min_err); 2476 2477 sci_port_enable(s); 2478 2479 /* 2480 * Program the optional External Baud Rate Generator (BRG) first. 2481 * It controls the mux to select (H)SCK or frequency divided clock. 2482 */ 2483 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2484 serial_port_out(port, SCDL, dl); 2485 serial_port_out(port, SCCKS, sccks); 2486 } 2487 2488 spin_lock_irqsave(&port->lock, flags); 2489 2490 sci_reset(port); 2491 2492 uart_update_timeout(port, termios->c_cflag, baud); 2493 2494 /* byte size and parity */ 2495 switch (termios->c_cflag & CSIZE) { 2496 case CS5: 2497 bits = 7; 2498 break; 2499 case CS6: 2500 bits = 8; 2501 break; 2502 case CS7: 2503 bits = 9; 2504 break; 2505 default: 2506 bits = 10; 2507 break; 2508 } 2509 2510 if (termios->c_cflag & CSTOPB) 2511 bits++; 2512 if (termios->c_cflag & PARENB) 2513 bits++; 2514 2515 if (best_clk >= 0) { 2516 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2517 switch (srr + 1) { 2518 case 5: smr_val |= SCSMR_SRC_5; break; 2519 case 7: smr_val |= SCSMR_SRC_7; break; 2520 case 11: smr_val |= SCSMR_SRC_11; break; 2521 case 13: smr_val |= SCSMR_SRC_13; break; 2522 case 16: smr_val |= SCSMR_SRC_16; break; 2523 case 17: smr_val |= SCSMR_SRC_17; break; 2524 case 19: smr_val |= SCSMR_SRC_19; break; 2525 case 27: smr_val |= SCSMR_SRC_27; break; 2526 } 2527 smr_val |= cks; 2528 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2529 serial_port_out(port, SCSMR, smr_val); 2530 serial_port_out(port, SCBRR, brr); 2531 if (sci_getreg(port, HSSRR)->size) { 2532 unsigned int hssrr = srr | HSCIF_SRE; 2533 /* Calculate deviation from intended rate at the 2534 * center of the last stop bit in sampling clocks. 2535 */ 2536 int last_stop = bits * 2 - 1; 2537 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2538 (int)(srr + 1), 2539 2 * (int)baud); 2540 2541 if (abs(deviation) >= 2) { 2542 /* At least two sampling clocks off at the 2543 * last stop bit; we can increase the error 2544 * margin by shifting the sampling point. 2545 */ 2546 int shift = clamp(deviation / 2, -8, 7); 2547 2548 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2549 HSCIF_SRHP_MASK; 2550 hssrr |= HSCIF_SRDE; 2551 } 2552 serial_port_out(port, HSSRR, hssrr); 2553 } 2554 2555 /* Wait one bit interval */ 2556 udelay((1000000 + (baud - 1)) / baud); 2557 } else { 2558 /* Don't touch the bit rate configuration */ 2559 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2560 smr_val |= serial_port_in(port, SCSMR) & 2561 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2562 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2563 serial_port_out(port, SCSMR, smr_val); 2564 } 2565 2566 sci_init_pins(port, termios->c_cflag); 2567 2568 port->status &= ~UPSTAT_AUTOCTS; 2569 s->autorts = false; 2570 reg = sci_getreg(port, SCFCR); 2571 if (reg->size) { 2572 unsigned short ctrl = serial_port_in(port, SCFCR); 2573 2574 if ((port->flags & UPF_HARD_FLOW) && 2575 (termios->c_cflag & CRTSCTS)) { 2576 /* There is no CTS interrupt to restart the hardware */ 2577 port->status |= UPSTAT_AUTOCTS; 2578 /* MCE is enabled when RTS is raised */ 2579 s->autorts = true; 2580 } 2581 2582 /* 2583 * As we've done a sci_reset() above, ensure we don't 2584 * interfere with the FIFOs while toggling MCE. As the 2585 * reset values could still be set, simply mask them out. 2586 */ 2587 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2588 2589 serial_port_out(port, SCFCR, ctrl); 2590 } 2591 if (port->flags & UPF_HARD_FLOW) { 2592 /* Refresh (Auto) RTS */ 2593 sci_set_mctrl(port, port->mctrl); 2594 } 2595 2596 scr_val |= SCSCR_RE | SCSCR_TE | 2597 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2598 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2599 if ((srr + 1 == 5) && 2600 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2601 /* 2602 * In asynchronous mode, when the sampling rate is 1/5, first 2603 * received data may become invalid on some SCIFA and SCIFB. 2604 * To avoid this problem wait more than 1 serial data time (1 2605 * bit time x serial data number) after setting SCSCR.RE = 1. 2606 */ 2607 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2608 } 2609 2610 /* 2611 * Calculate delay for 2 DMA buffers (4 FIFO). 2612 * See serial_core.c::uart_update_timeout(). 2613 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2614 * function calculates 1 jiffie for the data plus 5 jiffies for the 2615 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2616 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2617 * value obtained by this formula is too small. Therefore, if the value 2618 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2619 */ 2620 s->rx_frame = (10000 * bits) / (baud / 100); 2621 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2622 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2623 if (s->rx_timeout < 20) 2624 s->rx_timeout = 20; 2625 #endif 2626 2627 if ((termios->c_cflag & CREAD) != 0) 2628 sci_start_rx(port); 2629 2630 spin_unlock_irqrestore(&port->lock, flags); 2631 2632 sci_port_disable(s); 2633 2634 if (UART_ENABLE_MS(port, termios->c_cflag)) 2635 sci_enable_ms(port); 2636 } 2637 2638 static void sci_pm(struct uart_port *port, unsigned int state, 2639 unsigned int oldstate) 2640 { 2641 struct sci_port *sci_port = to_sci_port(port); 2642 2643 switch (state) { 2644 case UART_PM_STATE_OFF: 2645 sci_port_disable(sci_port); 2646 break; 2647 default: 2648 sci_port_enable(sci_port); 2649 break; 2650 } 2651 } 2652 2653 static const char *sci_type(struct uart_port *port) 2654 { 2655 switch (port->type) { 2656 case PORT_IRDA: 2657 return "irda"; 2658 case PORT_SCI: 2659 return "sci"; 2660 case PORT_SCIF: 2661 return "scif"; 2662 case PORT_SCIFA: 2663 return "scifa"; 2664 case PORT_SCIFB: 2665 return "scifb"; 2666 case PORT_HSCIF: 2667 return "hscif"; 2668 } 2669 2670 return NULL; 2671 } 2672 2673 static int sci_remap_port(struct uart_port *port) 2674 { 2675 struct sci_port *sport = to_sci_port(port); 2676 2677 /* 2678 * Nothing to do if there's already an established membase. 2679 */ 2680 if (port->membase) 2681 return 0; 2682 2683 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2684 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2685 if (unlikely(!port->membase)) { 2686 dev_err(port->dev, "can't remap port#%d\n", port->line); 2687 return -ENXIO; 2688 } 2689 } else { 2690 /* 2691 * For the simple (and majority of) cases where we don't 2692 * need to do any remapping, just cast the cookie 2693 * directly. 2694 */ 2695 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2696 } 2697 2698 return 0; 2699 } 2700 2701 static void sci_release_port(struct uart_port *port) 2702 { 2703 struct sci_port *sport = to_sci_port(port); 2704 2705 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2706 iounmap(port->membase); 2707 port->membase = NULL; 2708 } 2709 2710 release_mem_region(port->mapbase, sport->reg_size); 2711 } 2712 2713 static int sci_request_port(struct uart_port *port) 2714 { 2715 struct resource *res; 2716 struct sci_port *sport = to_sci_port(port); 2717 int ret; 2718 2719 res = request_mem_region(port->mapbase, sport->reg_size, 2720 dev_name(port->dev)); 2721 if (unlikely(res == NULL)) { 2722 dev_err(port->dev, "request_mem_region failed."); 2723 return -EBUSY; 2724 } 2725 2726 ret = sci_remap_port(port); 2727 if (unlikely(ret != 0)) { 2728 release_resource(res); 2729 return ret; 2730 } 2731 2732 return 0; 2733 } 2734 2735 static void sci_config_port(struct uart_port *port, int flags) 2736 { 2737 if (flags & UART_CONFIG_TYPE) { 2738 struct sci_port *sport = to_sci_port(port); 2739 2740 port->type = sport->cfg->type; 2741 sci_request_port(port); 2742 } 2743 } 2744 2745 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2746 { 2747 if (ser->baud_base < 2400) 2748 /* No paper tape reader for Mitch.. */ 2749 return -EINVAL; 2750 2751 return 0; 2752 } 2753 2754 static const struct uart_ops sci_uart_ops = { 2755 .tx_empty = sci_tx_empty, 2756 .set_mctrl = sci_set_mctrl, 2757 .get_mctrl = sci_get_mctrl, 2758 .start_tx = sci_start_tx, 2759 .stop_tx = sci_stop_tx, 2760 .stop_rx = sci_stop_rx, 2761 .enable_ms = sci_enable_ms, 2762 .break_ctl = sci_break_ctl, 2763 .startup = sci_startup, 2764 .shutdown = sci_shutdown, 2765 .flush_buffer = sci_flush_buffer, 2766 .set_termios = sci_set_termios, 2767 .pm = sci_pm, 2768 .type = sci_type, 2769 .release_port = sci_release_port, 2770 .request_port = sci_request_port, 2771 .config_port = sci_config_port, 2772 .verify_port = sci_verify_port, 2773 #ifdef CONFIG_CONSOLE_POLL 2774 .poll_get_char = sci_poll_get_char, 2775 .poll_put_char = sci_poll_put_char, 2776 #endif 2777 }; 2778 2779 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2780 { 2781 const char *clk_names[] = { 2782 [SCI_FCK] = "fck", 2783 [SCI_SCK] = "sck", 2784 [SCI_BRG_INT] = "brg_int", 2785 [SCI_SCIF_CLK] = "scif_clk", 2786 }; 2787 struct clk *clk; 2788 unsigned int i; 2789 2790 if (sci_port->cfg->type == PORT_HSCIF) 2791 clk_names[SCI_SCK] = "hsck"; 2792 2793 for (i = 0; i < SCI_NUM_CLKS; i++) { 2794 clk = devm_clk_get(dev, clk_names[i]); 2795 if (PTR_ERR(clk) == -EPROBE_DEFER) 2796 return -EPROBE_DEFER; 2797 2798 if (IS_ERR(clk) && i == SCI_FCK) { 2799 /* 2800 * "fck" used to be called "sci_ick", and we need to 2801 * maintain DT backward compatibility. 2802 */ 2803 clk = devm_clk_get(dev, "sci_ick"); 2804 if (PTR_ERR(clk) == -EPROBE_DEFER) 2805 return -EPROBE_DEFER; 2806 2807 if (!IS_ERR(clk)) 2808 goto found; 2809 2810 /* 2811 * Not all SH platforms declare a clock lookup entry 2812 * for SCI devices, in which case we need to get the 2813 * global "peripheral_clk" clock. 2814 */ 2815 clk = devm_clk_get(dev, "peripheral_clk"); 2816 if (!IS_ERR(clk)) 2817 goto found; 2818 2819 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2820 PTR_ERR(clk)); 2821 return PTR_ERR(clk); 2822 } 2823 2824 found: 2825 if (IS_ERR(clk)) 2826 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2827 PTR_ERR(clk)); 2828 else 2829 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2830 clk, clk_get_rate(clk)); 2831 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2832 } 2833 return 0; 2834 } 2835 2836 static const struct sci_port_params * 2837 sci_probe_regmap(const struct plat_sci_port *cfg) 2838 { 2839 unsigned int regtype; 2840 2841 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2842 return &sci_port_params[cfg->regtype]; 2843 2844 switch (cfg->type) { 2845 case PORT_SCI: 2846 regtype = SCIx_SCI_REGTYPE; 2847 break; 2848 case PORT_IRDA: 2849 regtype = SCIx_IRDA_REGTYPE; 2850 break; 2851 case PORT_SCIFA: 2852 regtype = SCIx_SCIFA_REGTYPE; 2853 break; 2854 case PORT_SCIFB: 2855 regtype = SCIx_SCIFB_REGTYPE; 2856 break; 2857 case PORT_SCIF: 2858 /* 2859 * The SH-4 is a bit of a misnomer here, although that's 2860 * where this particular port layout originated. This 2861 * configuration (or some slight variation thereof) 2862 * remains the dominant model for all SCIFs. 2863 */ 2864 regtype = SCIx_SH4_SCIF_REGTYPE; 2865 break; 2866 case PORT_HSCIF: 2867 regtype = SCIx_HSCIF_REGTYPE; 2868 break; 2869 default: 2870 pr_err("Can't probe register map for given port\n"); 2871 return NULL; 2872 } 2873 2874 return &sci_port_params[regtype]; 2875 } 2876 2877 static int sci_init_single(struct platform_device *dev, 2878 struct sci_port *sci_port, unsigned int index, 2879 const struct plat_sci_port *p, bool early) 2880 { 2881 struct uart_port *port = &sci_port->port; 2882 const struct resource *res; 2883 unsigned int i; 2884 int ret; 2885 2886 sci_port->cfg = p; 2887 2888 port->ops = &sci_uart_ops; 2889 port->iotype = UPIO_MEM; 2890 port->line = index; 2891 2892 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2893 if (res == NULL) 2894 return -ENOMEM; 2895 2896 port->mapbase = res->start; 2897 sci_port->reg_size = resource_size(res); 2898 2899 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2900 sci_port->irqs[i] = platform_get_irq(dev, i); 2901 2902 /* The SCI generates several interrupts. They can be muxed together or 2903 * connected to different interrupt lines. In the muxed case only one 2904 * interrupt resource is specified as there is only one interrupt ID. 2905 * In the non-muxed case, up to 6 interrupt signals might be generated 2906 * from the SCI, however those signals might have their own individual 2907 * interrupt ID numbers, or muxed together with another interrupt. 2908 */ 2909 if (sci_port->irqs[0] < 0) 2910 return -ENXIO; 2911 2912 if (sci_port->irqs[1] < 0) 2913 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2914 sci_port->irqs[i] = sci_port->irqs[0]; 2915 2916 sci_port->params = sci_probe_regmap(p); 2917 if (unlikely(sci_port->params == NULL)) 2918 return -EINVAL; 2919 2920 switch (p->type) { 2921 case PORT_SCIFB: 2922 sci_port->rx_trigger = 48; 2923 break; 2924 case PORT_HSCIF: 2925 sci_port->rx_trigger = 64; 2926 break; 2927 case PORT_SCIFA: 2928 sci_port->rx_trigger = 32; 2929 break; 2930 case PORT_SCIF: 2931 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2932 /* RX triggering not implemented for this IP */ 2933 sci_port->rx_trigger = 1; 2934 else 2935 sci_port->rx_trigger = 8; 2936 break; 2937 default: 2938 sci_port->rx_trigger = 1; 2939 break; 2940 } 2941 2942 sci_port->rx_fifo_timeout = 0; 2943 sci_port->hscif_tot = 0; 2944 2945 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2946 * match the SoC datasheet, this should be investigated. Let platform 2947 * data override the sampling rate for now. 2948 */ 2949 sci_port->sampling_rate_mask = p->sampling_rate 2950 ? SCI_SR(p->sampling_rate) 2951 : sci_port->params->sampling_rate_mask; 2952 2953 if (!early) { 2954 ret = sci_init_clocks(sci_port, &dev->dev); 2955 if (ret < 0) 2956 return ret; 2957 2958 port->dev = &dev->dev; 2959 2960 pm_runtime_enable(&dev->dev); 2961 } 2962 2963 port->type = p->type; 2964 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2965 port->fifosize = sci_port->params->fifosize; 2966 2967 if (port->type == PORT_SCI) { 2968 if (sci_port->reg_size >= 0x20) 2969 port->regshift = 2; 2970 else 2971 port->regshift = 1; 2972 } 2973 2974 /* 2975 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2976 * for the multi-IRQ ports, which is where we are primarily 2977 * concerned with the shutdown path synchronization. 2978 * 2979 * For the muxed case there's nothing more to do. 2980 */ 2981 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2982 port->irqflags = 0; 2983 2984 port->serial_in = sci_serial_in; 2985 port->serial_out = sci_serial_out; 2986 2987 return 0; 2988 } 2989 2990 static void sci_cleanup_single(struct sci_port *port) 2991 { 2992 pm_runtime_disable(port->port.dev); 2993 } 2994 2995 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2996 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2997 static void serial_console_putchar(struct uart_port *port, int ch) 2998 { 2999 sci_poll_put_char(port, ch); 3000 } 3001 3002 /* 3003 * Print a string to the serial port trying not to disturb 3004 * any possible real use of the port... 3005 */ 3006 static void serial_console_write(struct console *co, const char *s, 3007 unsigned count) 3008 { 3009 struct sci_port *sci_port = &sci_ports[co->index]; 3010 struct uart_port *port = &sci_port->port; 3011 unsigned short bits, ctrl, ctrl_temp; 3012 unsigned long flags; 3013 int locked = 1; 3014 3015 #if defined(SUPPORT_SYSRQ) 3016 if (port->sysrq) 3017 locked = 0; 3018 else 3019 #endif 3020 if (oops_in_progress) 3021 locked = spin_trylock_irqsave(&port->lock, flags); 3022 else 3023 spin_lock_irqsave(&port->lock, flags); 3024 3025 /* first save SCSCR then disable interrupts, keep clock source */ 3026 ctrl = serial_port_in(port, SCSCR); 3027 ctrl_temp = SCSCR_RE | SCSCR_TE | 3028 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3029 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3030 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3031 3032 uart_console_write(port, s, count, serial_console_putchar); 3033 3034 /* wait until fifo is empty and last bit has been transmitted */ 3035 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3036 while ((serial_port_in(port, SCxSR) & bits) != bits) 3037 cpu_relax(); 3038 3039 /* restore the SCSCR */ 3040 serial_port_out(port, SCSCR, ctrl); 3041 3042 if (locked) 3043 spin_unlock_irqrestore(&port->lock, flags); 3044 } 3045 3046 static int serial_console_setup(struct console *co, char *options) 3047 { 3048 struct sci_port *sci_port; 3049 struct uart_port *port; 3050 int baud = 115200; 3051 int bits = 8; 3052 int parity = 'n'; 3053 int flow = 'n'; 3054 int ret; 3055 3056 /* 3057 * Refuse to handle any bogus ports. 3058 */ 3059 if (co->index < 0 || co->index >= SCI_NPORTS) 3060 return -ENODEV; 3061 3062 sci_port = &sci_ports[co->index]; 3063 port = &sci_port->port; 3064 3065 /* 3066 * Refuse to handle uninitialized ports. 3067 */ 3068 if (!port->ops) 3069 return -ENODEV; 3070 3071 ret = sci_remap_port(port); 3072 if (unlikely(ret != 0)) 3073 return ret; 3074 3075 if (options) 3076 uart_parse_options(options, &baud, &parity, &bits, &flow); 3077 3078 return uart_set_options(port, co, baud, parity, bits, flow); 3079 } 3080 3081 static struct console serial_console = { 3082 .name = "ttySC", 3083 .device = uart_console_device, 3084 .write = serial_console_write, 3085 .setup = serial_console_setup, 3086 .flags = CON_PRINTBUFFER, 3087 .index = -1, 3088 .data = &sci_uart_driver, 3089 }; 3090 3091 static struct console early_serial_console = { 3092 .name = "early_ttySC", 3093 .write = serial_console_write, 3094 .flags = CON_PRINTBUFFER, 3095 .index = -1, 3096 }; 3097 3098 static char early_serial_buf[32]; 3099 3100 static int sci_probe_earlyprintk(struct platform_device *pdev) 3101 { 3102 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3103 3104 if (early_serial_console.data) 3105 return -EEXIST; 3106 3107 early_serial_console.index = pdev->id; 3108 3109 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3110 3111 serial_console_setup(&early_serial_console, early_serial_buf); 3112 3113 if (!strstr(early_serial_buf, "keep")) 3114 early_serial_console.flags |= CON_BOOT; 3115 3116 register_console(&early_serial_console); 3117 return 0; 3118 } 3119 3120 #define SCI_CONSOLE (&serial_console) 3121 3122 #else 3123 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3124 { 3125 return -EINVAL; 3126 } 3127 3128 #define SCI_CONSOLE NULL 3129 3130 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3131 3132 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3133 3134 static DEFINE_MUTEX(sci_uart_registration_lock); 3135 static struct uart_driver sci_uart_driver = { 3136 .owner = THIS_MODULE, 3137 .driver_name = "sci", 3138 .dev_name = "ttySC", 3139 .major = SCI_MAJOR, 3140 .minor = SCI_MINOR_START, 3141 .nr = SCI_NPORTS, 3142 .cons = SCI_CONSOLE, 3143 }; 3144 3145 static int sci_remove(struct platform_device *dev) 3146 { 3147 struct sci_port *port = platform_get_drvdata(dev); 3148 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3149 3150 sci_ports_in_use &= ~BIT(port->port.line); 3151 uart_remove_one_port(&sci_uart_driver, &port->port); 3152 3153 sci_cleanup_single(port); 3154 3155 if (port->port.fifosize > 1) { 3156 sysfs_remove_file(&dev->dev.kobj, 3157 &dev_attr_rx_fifo_trigger.attr); 3158 } 3159 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) { 3160 sysfs_remove_file(&dev->dev.kobj, 3161 &dev_attr_rx_fifo_timeout.attr); 3162 } 3163 3164 return 0; 3165 } 3166 3167 3168 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3169 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3170 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3171 3172 static const struct of_device_id of_sci_match[] = { 3173 /* SoC-specific types */ 3174 { 3175 .compatible = "renesas,scif-r7s72100", 3176 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3177 }, 3178 { 3179 .compatible = "renesas,scif-r7s9210", 3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3181 }, 3182 /* Family-specific types */ 3183 { 3184 .compatible = "renesas,rcar-gen1-scif", 3185 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3186 }, { 3187 .compatible = "renesas,rcar-gen2-scif", 3188 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3189 }, { 3190 .compatible = "renesas,rcar-gen3-scif", 3191 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3192 }, 3193 /* Generic types */ 3194 { 3195 .compatible = "renesas,scif", 3196 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3197 }, { 3198 .compatible = "renesas,scifa", 3199 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3200 }, { 3201 .compatible = "renesas,scifb", 3202 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3203 }, { 3204 .compatible = "renesas,hscif", 3205 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3206 }, { 3207 .compatible = "renesas,sci", 3208 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3209 }, { 3210 /* Terminator */ 3211 }, 3212 }; 3213 MODULE_DEVICE_TABLE(of, of_sci_match); 3214 3215 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3216 unsigned int *dev_id) 3217 { 3218 struct device_node *np = pdev->dev.of_node; 3219 struct plat_sci_port *p; 3220 struct sci_port *sp; 3221 const void *data; 3222 int id; 3223 3224 if (!IS_ENABLED(CONFIG_OF) || !np) 3225 return NULL; 3226 3227 data = of_device_get_match_data(&pdev->dev); 3228 3229 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3230 if (!p) 3231 return NULL; 3232 3233 /* Get the line number from the aliases node. */ 3234 id = of_alias_get_id(np, "serial"); 3235 if (id < 0 && ~sci_ports_in_use) 3236 id = ffz(sci_ports_in_use); 3237 if (id < 0) { 3238 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3239 return NULL; 3240 } 3241 if (id >= ARRAY_SIZE(sci_ports)) { 3242 dev_err(&pdev->dev, "serial%d out of range\n", id); 3243 return NULL; 3244 } 3245 3246 sp = &sci_ports[id]; 3247 *dev_id = id; 3248 3249 p->type = SCI_OF_TYPE(data); 3250 p->regtype = SCI_OF_REGTYPE(data); 3251 3252 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3253 3254 return p; 3255 } 3256 3257 static int sci_probe_single(struct platform_device *dev, 3258 unsigned int index, 3259 struct plat_sci_port *p, 3260 struct sci_port *sciport) 3261 { 3262 int ret; 3263 3264 /* Sanity check */ 3265 if (unlikely(index >= SCI_NPORTS)) { 3266 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3267 index+1, SCI_NPORTS); 3268 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3269 return -EINVAL; 3270 } 3271 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3272 if (sci_ports_in_use & BIT(index)) 3273 return -EBUSY; 3274 3275 mutex_lock(&sci_uart_registration_lock); 3276 if (!sci_uart_driver.state) { 3277 ret = uart_register_driver(&sci_uart_driver); 3278 if (ret) { 3279 mutex_unlock(&sci_uart_registration_lock); 3280 return ret; 3281 } 3282 } 3283 mutex_unlock(&sci_uart_registration_lock); 3284 3285 ret = sci_init_single(dev, sciport, index, p, false); 3286 if (ret) 3287 return ret; 3288 3289 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3290 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3291 return PTR_ERR(sciport->gpios); 3292 3293 if (sciport->has_rtscts) { 3294 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3295 UART_GPIO_CTS)) || 3296 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3297 UART_GPIO_RTS))) { 3298 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3299 return -EINVAL; 3300 } 3301 sciport->port.flags |= UPF_HARD_FLOW; 3302 } 3303 3304 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3305 if (ret) { 3306 sci_cleanup_single(sciport); 3307 return ret; 3308 } 3309 3310 return 0; 3311 } 3312 3313 static int sci_probe(struct platform_device *dev) 3314 { 3315 struct plat_sci_port *p; 3316 struct sci_port *sp; 3317 unsigned int dev_id; 3318 int ret; 3319 3320 /* 3321 * If we've come here via earlyprintk initialization, head off to 3322 * the special early probe. We don't have sufficient device state 3323 * to make it beyond this yet. 3324 */ 3325 if (is_early_platform_device(dev)) 3326 return sci_probe_earlyprintk(dev); 3327 3328 if (dev->dev.of_node) { 3329 p = sci_parse_dt(dev, &dev_id); 3330 if (p == NULL) 3331 return -EINVAL; 3332 } else { 3333 p = dev->dev.platform_data; 3334 if (p == NULL) { 3335 dev_err(&dev->dev, "no platform data supplied\n"); 3336 return -EINVAL; 3337 } 3338 3339 dev_id = dev->id; 3340 } 3341 3342 sp = &sci_ports[dev_id]; 3343 platform_set_drvdata(dev, sp); 3344 3345 ret = sci_probe_single(dev, dev_id, p, sp); 3346 if (ret) 3347 return ret; 3348 3349 if (sp->port.fifosize > 1) { 3350 ret = sysfs_create_file(&dev->dev.kobj, 3351 &dev_attr_rx_fifo_trigger.attr); 3352 if (ret) 3353 return ret; 3354 } 3355 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3356 sp->port.type == PORT_HSCIF) { 3357 ret = sysfs_create_file(&dev->dev.kobj, 3358 &dev_attr_rx_fifo_timeout.attr); 3359 if (ret) { 3360 if (sp->port.fifosize > 1) { 3361 sysfs_remove_file(&dev->dev.kobj, 3362 &dev_attr_rx_fifo_trigger.attr); 3363 } 3364 return ret; 3365 } 3366 } 3367 3368 #ifdef CONFIG_SH_STANDARD_BIOS 3369 sh_bios_gdb_detach(); 3370 #endif 3371 3372 sci_ports_in_use |= BIT(dev_id); 3373 return 0; 3374 } 3375 3376 static __maybe_unused int sci_suspend(struct device *dev) 3377 { 3378 struct sci_port *sport = dev_get_drvdata(dev); 3379 3380 if (sport) 3381 uart_suspend_port(&sci_uart_driver, &sport->port); 3382 3383 return 0; 3384 } 3385 3386 static __maybe_unused int sci_resume(struct device *dev) 3387 { 3388 struct sci_port *sport = dev_get_drvdata(dev); 3389 3390 if (sport) 3391 uart_resume_port(&sci_uart_driver, &sport->port); 3392 3393 return 0; 3394 } 3395 3396 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3397 3398 static struct platform_driver sci_driver = { 3399 .probe = sci_probe, 3400 .remove = sci_remove, 3401 .driver = { 3402 .name = "sh-sci", 3403 .pm = &sci_dev_pm_ops, 3404 .of_match_table = of_match_ptr(of_sci_match), 3405 }, 3406 }; 3407 3408 static int __init sci_init(void) 3409 { 3410 pr_info("%s\n", banner); 3411 3412 return platform_driver_register(&sci_driver); 3413 } 3414 3415 static void __exit sci_exit(void) 3416 { 3417 platform_driver_unregister(&sci_driver); 3418 3419 if (sci_uart_driver.state) 3420 uart_unregister_driver(&sci_uart_driver); 3421 } 3422 3423 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3424 early_platform_init_buffer("earlyprintk", &sci_driver, 3425 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3426 #endif 3427 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3428 static struct plat_sci_port port_cfg __initdata; 3429 3430 static int __init early_console_setup(struct earlycon_device *device, 3431 int type) 3432 { 3433 if (!device->port.membase) 3434 return -ENODEV; 3435 3436 device->port.serial_in = sci_serial_in; 3437 device->port.serial_out = sci_serial_out; 3438 device->port.type = type; 3439 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3440 port_cfg.type = type; 3441 sci_ports[0].cfg = &port_cfg; 3442 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3443 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3444 sci_serial_out(&sci_ports[0].port, SCSCR, 3445 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3446 3447 device->con->write = serial_console_write; 3448 return 0; 3449 } 3450 static int __init sci_early_console_setup(struct earlycon_device *device, 3451 const char *opt) 3452 { 3453 return early_console_setup(device, PORT_SCI); 3454 } 3455 static int __init scif_early_console_setup(struct earlycon_device *device, 3456 const char *opt) 3457 { 3458 return early_console_setup(device, PORT_SCIF); 3459 } 3460 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3461 const char *opt) 3462 { 3463 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3464 return early_console_setup(device, PORT_SCIF); 3465 } 3466 static int __init scifa_early_console_setup(struct earlycon_device *device, 3467 const char *opt) 3468 { 3469 return early_console_setup(device, PORT_SCIFA); 3470 } 3471 static int __init scifb_early_console_setup(struct earlycon_device *device, 3472 const char *opt) 3473 { 3474 return early_console_setup(device, PORT_SCIFB); 3475 } 3476 static int __init hscif_early_console_setup(struct earlycon_device *device, 3477 const char *opt) 3478 { 3479 return early_console_setup(device, PORT_HSCIF); 3480 } 3481 3482 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3483 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3484 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3485 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3486 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3487 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3488 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3489 3490 module_init(sci_init); 3491 module_exit(sci_exit); 3492 3493 MODULE_LICENSE("GPL"); 3494 MODULE_ALIAS("platform:sh-sci"); 3495 MODULE_AUTHOR("Paul Mundt"); 3496 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3497