1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/module.h> 35 #include <linux/mm.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/scatterlist.h> 41 #include <linux/serial.h> 42 #include <linux/serial_sci.h> 43 #include <linux/sh_dma.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/sysrq.h> 47 #include <linux/timer.h> 48 #include <linux/tty.h> 49 #include <linux/tty_flip.h> 50 51 #ifdef CONFIG_SUPERH 52 #include <asm/sh_bios.h> 53 #include <asm/platform_early.h> 54 #endif 55 56 #include "serial_mctrl_gpio.h" 57 #include "sh-sci.h" 58 59 /* Offsets into the sci_port->irqs array */ 60 enum { 61 SCIx_ERI_IRQ, 62 SCIx_RXI_IRQ, 63 SCIx_TXI_IRQ, 64 SCIx_BRI_IRQ, 65 SCIx_DRI_IRQ, 66 SCIx_TEI_IRQ, 67 SCIx_NR_IRQS, 68 69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 70 }; 71 72 #define SCIx_IRQ_IS_MUXED(port) \ 73 ((port)->irqs[SCIx_ERI_IRQ] == \ 74 (port)->irqs[SCIx_RXI_IRQ]) || \ 75 ((port)->irqs[SCIx_ERI_IRQ] && \ 76 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 77 78 enum SCI_CLKS { 79 SCI_FCK, /* Functional Clock */ 80 SCI_SCK, /* Optional External Clock */ 81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 83 SCI_NUM_CLKS 84 }; 85 86 /* Bit x set means sampling rate x + 1 is supported */ 87 #define SCI_SR(x) BIT((x) - 1) 88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 89 90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 92 SCI_SR(19) | SCI_SR(27) 93 94 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 95 #define max_sr(_port) fls((_port)->sampling_rate_mask) 96 97 /* Iterate over all supported sampling rates, from high to low */ 98 #define for_each_sr(_sr, _port) \ 99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 100 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 101 102 struct plat_sci_reg { 103 u8 offset, size; 104 }; 105 106 struct sci_port_params { 107 const struct plat_sci_reg regs[SCIx_NR_REGS]; 108 unsigned int fifosize; 109 unsigned int overrun_reg; 110 unsigned int overrun_mask; 111 unsigned int sampling_rate_mask; 112 unsigned int error_mask; 113 unsigned int error_clear; 114 }; 115 116 struct sci_port { 117 struct uart_port port; 118 119 /* Platform configuration */ 120 const struct sci_port_params *params; 121 const struct plat_sci_port *cfg; 122 unsigned int sampling_rate_mask; 123 resource_size_t reg_size; 124 struct mctrl_gpios *gpios; 125 126 /* Clocks */ 127 struct clk *clks[SCI_NUM_CLKS]; 128 unsigned long clk_rates[SCI_NUM_CLKS]; 129 130 int irqs[SCIx_NR_IRQS]; 131 char *irqstr[SCIx_NR_IRQS]; 132 133 struct dma_chan *chan_tx; 134 struct dma_chan *chan_rx; 135 136 #ifdef CONFIG_SERIAL_SH_SCI_DMA 137 struct dma_chan *chan_tx_saved; 138 struct dma_chan *chan_rx_saved; 139 dma_cookie_t cookie_tx; 140 dma_cookie_t cookie_rx[2]; 141 dma_cookie_t active_rx; 142 dma_addr_t tx_dma_addr; 143 unsigned int tx_dma_len; 144 struct scatterlist sg_rx[2]; 145 void *rx_buf[2]; 146 size_t buf_len_rx; 147 struct work_struct work_tx; 148 struct hrtimer rx_timer; 149 unsigned int rx_timeout; /* microseconds */ 150 #endif 151 unsigned int rx_frame; 152 int rx_trigger; 153 struct timer_list rx_fifo_timer; 154 int rx_fifo_timeout; 155 u16 hscif_tot; 156 157 bool has_rtscts; 158 bool autorts; 159 }; 160 161 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 162 163 static struct sci_port sci_ports[SCI_NPORTS]; 164 static unsigned long sci_ports_in_use; 165 static struct uart_driver sci_uart_driver; 166 167 static inline struct sci_port * 168 to_sci_port(struct uart_port *uart) 169 { 170 return container_of(uart, struct sci_port, port); 171 } 172 173 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 174 /* 175 * Common SCI definitions, dependent on the port's regshift 176 * value. 177 */ 178 [SCIx_SCI_REGTYPE] = { 179 .regs = { 180 [SCSMR] = { 0x00, 8 }, 181 [SCBRR] = { 0x01, 8 }, 182 [SCSCR] = { 0x02, 8 }, 183 [SCxTDR] = { 0x03, 8 }, 184 [SCxSR] = { 0x04, 8 }, 185 [SCxRDR] = { 0x05, 8 }, 186 }, 187 .fifosize = 1, 188 .overrun_reg = SCxSR, 189 .overrun_mask = SCI_ORER, 190 .sampling_rate_mask = SCI_SR(32), 191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 193 }, 194 195 /* 196 * Common definitions for legacy IrDA ports. 197 */ 198 [SCIx_IRDA_REGTYPE] = { 199 .regs = { 200 [SCSMR] = { 0x00, 8 }, 201 [SCBRR] = { 0x02, 8 }, 202 [SCSCR] = { 0x04, 8 }, 203 [SCxTDR] = { 0x06, 8 }, 204 [SCxSR] = { 0x08, 16 }, 205 [SCxRDR] = { 0x0a, 8 }, 206 [SCFCR] = { 0x0c, 8 }, 207 [SCFDR] = { 0x0e, 16 }, 208 }, 209 .fifosize = 1, 210 .overrun_reg = SCxSR, 211 .overrun_mask = SCI_ORER, 212 .sampling_rate_mask = SCI_SR(32), 213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 215 }, 216 217 /* 218 * Common SCIFA definitions. 219 */ 220 [SCIx_SCIFA_REGTYPE] = { 221 .regs = { 222 [SCSMR] = { 0x00, 16 }, 223 [SCBRR] = { 0x04, 8 }, 224 [SCSCR] = { 0x08, 16 }, 225 [SCxTDR] = { 0x20, 8 }, 226 [SCxSR] = { 0x14, 16 }, 227 [SCxRDR] = { 0x24, 8 }, 228 [SCFCR] = { 0x18, 16 }, 229 [SCFDR] = { 0x1c, 16 }, 230 [SCPCR] = { 0x30, 16 }, 231 [SCPDR] = { 0x34, 16 }, 232 }, 233 .fifosize = 64, 234 .overrun_reg = SCxSR, 235 .overrun_mask = SCIFA_ORER, 236 .sampling_rate_mask = SCI_SR_SCIFAB, 237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 239 }, 240 241 /* 242 * Common SCIFB definitions. 243 */ 244 [SCIx_SCIFB_REGTYPE] = { 245 .regs = { 246 [SCSMR] = { 0x00, 16 }, 247 [SCBRR] = { 0x04, 8 }, 248 [SCSCR] = { 0x08, 16 }, 249 [SCxTDR] = { 0x40, 8 }, 250 [SCxSR] = { 0x14, 16 }, 251 [SCxRDR] = { 0x60, 8 }, 252 [SCFCR] = { 0x18, 16 }, 253 [SCTFDR] = { 0x38, 16 }, 254 [SCRFDR] = { 0x3c, 16 }, 255 [SCPCR] = { 0x30, 16 }, 256 [SCPDR] = { 0x34, 16 }, 257 }, 258 .fifosize = 256, 259 .overrun_reg = SCxSR, 260 .overrun_mask = SCIFA_ORER, 261 .sampling_rate_mask = SCI_SR_SCIFAB, 262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 264 }, 265 266 /* 267 * Common SH-2(A) SCIF definitions for ports with FIFO data 268 * count registers. 269 */ 270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 271 .regs = { 272 [SCSMR] = { 0x00, 16 }, 273 [SCBRR] = { 0x04, 8 }, 274 [SCSCR] = { 0x08, 16 }, 275 [SCxTDR] = { 0x0c, 8 }, 276 [SCxSR] = { 0x10, 16 }, 277 [SCxRDR] = { 0x14, 8 }, 278 [SCFCR] = { 0x18, 16 }, 279 [SCFDR] = { 0x1c, 16 }, 280 [SCSPTR] = { 0x20, 16 }, 281 [SCLSR] = { 0x24, 16 }, 282 }, 283 .fifosize = 16, 284 .overrun_reg = SCLSR, 285 .overrun_mask = SCLSR_ORER, 286 .sampling_rate_mask = SCI_SR(32), 287 .error_mask = SCIF_DEFAULT_ERROR_MASK, 288 .error_clear = SCIF_ERROR_CLEAR, 289 }, 290 291 /* 292 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 293 * It looks like a normal SCIF with FIFO data, but with a 294 * compressed address space. Also, the break out of interrupts 295 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 296 */ 297 [SCIx_RZ_SCIFA_REGTYPE] = { 298 .regs = { 299 [SCSMR] = { 0x00, 16 }, 300 [SCBRR] = { 0x02, 8 }, 301 [SCSCR] = { 0x04, 16 }, 302 [SCxTDR] = { 0x06, 8 }, 303 [SCxSR] = { 0x08, 16 }, 304 [SCxRDR] = { 0x0A, 8 }, 305 [SCFCR] = { 0x0C, 16 }, 306 [SCFDR] = { 0x0E, 16 }, 307 [SCSPTR] = { 0x10, 16 }, 308 [SCLSR] = { 0x12, 16 }, 309 [SEMR] = { 0x14, 8 }, 310 }, 311 .fifosize = 16, 312 .overrun_reg = SCLSR, 313 .overrun_mask = SCLSR_ORER, 314 .sampling_rate_mask = SCI_SR(32), 315 .error_mask = SCIF_DEFAULT_ERROR_MASK, 316 .error_clear = SCIF_ERROR_CLEAR, 317 }, 318 319 /* 320 * Common SH-3 SCIF definitions. 321 */ 322 [SCIx_SH3_SCIF_REGTYPE] = { 323 .regs = { 324 [SCSMR] = { 0x00, 8 }, 325 [SCBRR] = { 0x02, 8 }, 326 [SCSCR] = { 0x04, 8 }, 327 [SCxTDR] = { 0x06, 8 }, 328 [SCxSR] = { 0x08, 16 }, 329 [SCxRDR] = { 0x0a, 8 }, 330 [SCFCR] = { 0x0c, 8 }, 331 [SCFDR] = { 0x0e, 16 }, 332 }, 333 .fifosize = 16, 334 .overrun_reg = SCLSR, 335 .overrun_mask = SCLSR_ORER, 336 .sampling_rate_mask = SCI_SR(32), 337 .error_mask = SCIF_DEFAULT_ERROR_MASK, 338 .error_clear = SCIF_ERROR_CLEAR, 339 }, 340 341 /* 342 * Common SH-4(A) SCIF(B) definitions. 343 */ 344 [SCIx_SH4_SCIF_REGTYPE] = { 345 .regs = { 346 [SCSMR] = { 0x00, 16 }, 347 [SCBRR] = { 0x04, 8 }, 348 [SCSCR] = { 0x08, 16 }, 349 [SCxTDR] = { 0x0c, 8 }, 350 [SCxSR] = { 0x10, 16 }, 351 [SCxRDR] = { 0x14, 8 }, 352 [SCFCR] = { 0x18, 16 }, 353 [SCFDR] = { 0x1c, 16 }, 354 [SCSPTR] = { 0x20, 16 }, 355 [SCLSR] = { 0x24, 16 }, 356 }, 357 .fifosize = 16, 358 .overrun_reg = SCLSR, 359 .overrun_mask = SCLSR_ORER, 360 .sampling_rate_mask = SCI_SR(32), 361 .error_mask = SCIF_DEFAULT_ERROR_MASK, 362 .error_clear = SCIF_ERROR_CLEAR, 363 }, 364 365 /* 366 * Common SCIF definitions for ports with a Baud Rate Generator for 367 * External Clock (BRG). 368 */ 369 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 370 .regs = { 371 [SCSMR] = { 0x00, 16 }, 372 [SCBRR] = { 0x04, 8 }, 373 [SCSCR] = { 0x08, 16 }, 374 [SCxTDR] = { 0x0c, 8 }, 375 [SCxSR] = { 0x10, 16 }, 376 [SCxRDR] = { 0x14, 8 }, 377 [SCFCR] = { 0x18, 16 }, 378 [SCFDR] = { 0x1c, 16 }, 379 [SCSPTR] = { 0x20, 16 }, 380 [SCLSR] = { 0x24, 16 }, 381 [SCDL] = { 0x30, 16 }, 382 [SCCKS] = { 0x34, 16 }, 383 }, 384 .fifosize = 16, 385 .overrun_reg = SCLSR, 386 .overrun_mask = SCLSR_ORER, 387 .sampling_rate_mask = SCI_SR(32), 388 .error_mask = SCIF_DEFAULT_ERROR_MASK, 389 .error_clear = SCIF_ERROR_CLEAR, 390 }, 391 392 /* 393 * Common HSCIF definitions. 394 */ 395 [SCIx_HSCIF_REGTYPE] = { 396 .regs = { 397 [SCSMR] = { 0x00, 16 }, 398 [SCBRR] = { 0x04, 8 }, 399 [SCSCR] = { 0x08, 16 }, 400 [SCxTDR] = { 0x0c, 8 }, 401 [SCxSR] = { 0x10, 16 }, 402 [SCxRDR] = { 0x14, 8 }, 403 [SCFCR] = { 0x18, 16 }, 404 [SCFDR] = { 0x1c, 16 }, 405 [SCSPTR] = { 0x20, 16 }, 406 [SCLSR] = { 0x24, 16 }, 407 [HSSRR] = { 0x40, 16 }, 408 [SCDL] = { 0x30, 16 }, 409 [SCCKS] = { 0x34, 16 }, 410 [HSRTRGR] = { 0x54, 16 }, 411 [HSTTRGR] = { 0x58, 16 }, 412 }, 413 .fifosize = 128, 414 .overrun_reg = SCLSR, 415 .overrun_mask = SCLSR_ORER, 416 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 417 .error_mask = SCIF_DEFAULT_ERROR_MASK, 418 .error_clear = SCIF_ERROR_CLEAR, 419 }, 420 421 /* 422 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 423 * register. 424 */ 425 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 426 .regs = { 427 [SCSMR] = { 0x00, 16 }, 428 [SCBRR] = { 0x04, 8 }, 429 [SCSCR] = { 0x08, 16 }, 430 [SCxTDR] = { 0x0c, 8 }, 431 [SCxSR] = { 0x10, 16 }, 432 [SCxRDR] = { 0x14, 8 }, 433 [SCFCR] = { 0x18, 16 }, 434 [SCFDR] = { 0x1c, 16 }, 435 [SCLSR] = { 0x24, 16 }, 436 }, 437 .fifosize = 16, 438 .overrun_reg = SCLSR, 439 .overrun_mask = SCLSR_ORER, 440 .sampling_rate_mask = SCI_SR(32), 441 .error_mask = SCIF_DEFAULT_ERROR_MASK, 442 .error_clear = SCIF_ERROR_CLEAR, 443 }, 444 445 /* 446 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 447 * count registers. 448 */ 449 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 450 .regs = { 451 [SCSMR] = { 0x00, 16 }, 452 [SCBRR] = { 0x04, 8 }, 453 [SCSCR] = { 0x08, 16 }, 454 [SCxTDR] = { 0x0c, 8 }, 455 [SCxSR] = { 0x10, 16 }, 456 [SCxRDR] = { 0x14, 8 }, 457 [SCFCR] = { 0x18, 16 }, 458 [SCFDR] = { 0x1c, 16 }, 459 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 460 [SCRFDR] = { 0x20, 16 }, 461 [SCSPTR] = { 0x24, 16 }, 462 [SCLSR] = { 0x28, 16 }, 463 }, 464 .fifosize = 16, 465 .overrun_reg = SCLSR, 466 .overrun_mask = SCLSR_ORER, 467 .sampling_rate_mask = SCI_SR(32), 468 .error_mask = SCIF_DEFAULT_ERROR_MASK, 469 .error_clear = SCIF_ERROR_CLEAR, 470 }, 471 472 /* 473 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 474 * registers. 475 */ 476 [SCIx_SH7705_SCIF_REGTYPE] = { 477 .regs = { 478 [SCSMR] = { 0x00, 16 }, 479 [SCBRR] = { 0x04, 8 }, 480 [SCSCR] = { 0x08, 16 }, 481 [SCxTDR] = { 0x20, 8 }, 482 [SCxSR] = { 0x14, 16 }, 483 [SCxRDR] = { 0x24, 8 }, 484 [SCFCR] = { 0x18, 16 }, 485 [SCFDR] = { 0x1c, 16 }, 486 }, 487 .fifosize = 64, 488 .overrun_reg = SCxSR, 489 .overrun_mask = SCIFA_ORER, 490 .sampling_rate_mask = SCI_SR(16), 491 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 492 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 493 }, 494 }; 495 496 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 497 498 /* 499 * The "offset" here is rather misleading, in that it refers to an enum 500 * value relative to the port mapping rather than the fixed offset 501 * itself, which needs to be manually retrieved from the platform's 502 * register map for the given port. 503 */ 504 static unsigned int sci_serial_in(struct uart_port *p, int offset) 505 { 506 const struct plat_sci_reg *reg = sci_getreg(p, offset); 507 508 if (reg->size == 8) 509 return ioread8(p->membase + (reg->offset << p->regshift)); 510 else if (reg->size == 16) 511 return ioread16(p->membase + (reg->offset << p->regshift)); 512 else 513 WARN(1, "Invalid register access\n"); 514 515 return 0; 516 } 517 518 static void sci_serial_out(struct uart_port *p, int offset, int value) 519 { 520 const struct plat_sci_reg *reg = sci_getreg(p, offset); 521 522 if (reg->size == 8) 523 iowrite8(value, p->membase + (reg->offset << p->regshift)); 524 else if (reg->size == 16) 525 iowrite16(value, p->membase + (reg->offset << p->regshift)); 526 else 527 WARN(1, "Invalid register access\n"); 528 } 529 530 static void sci_port_enable(struct sci_port *sci_port) 531 { 532 unsigned int i; 533 534 if (!sci_port->port.dev) 535 return; 536 537 pm_runtime_get_sync(sci_port->port.dev); 538 539 for (i = 0; i < SCI_NUM_CLKS; i++) { 540 clk_prepare_enable(sci_port->clks[i]); 541 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 542 } 543 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 544 } 545 546 static void sci_port_disable(struct sci_port *sci_port) 547 { 548 unsigned int i; 549 550 if (!sci_port->port.dev) 551 return; 552 553 for (i = SCI_NUM_CLKS; i-- > 0; ) 554 clk_disable_unprepare(sci_port->clks[i]); 555 556 pm_runtime_put_sync(sci_port->port.dev); 557 } 558 559 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 560 { 561 /* 562 * Not all ports (such as SCIFA) will support REIE. Rather than 563 * special-casing the port type, we check the port initialization 564 * IRQ enable mask to see whether the IRQ is desired at all. If 565 * it's unset, it's logically inferred that there's no point in 566 * testing for it. 567 */ 568 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 569 } 570 571 static void sci_start_tx(struct uart_port *port) 572 { 573 struct sci_port *s = to_sci_port(port); 574 unsigned short ctrl; 575 576 #ifdef CONFIG_SERIAL_SH_SCI_DMA 577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 578 u16 new, scr = serial_port_in(port, SCSCR); 579 if (s->chan_tx) 580 new = scr | SCSCR_TDRQE; 581 else 582 new = scr & ~SCSCR_TDRQE; 583 if (new != scr) 584 serial_port_out(port, SCSCR, new); 585 } 586 587 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 588 dma_submit_error(s->cookie_tx)) { 589 s->cookie_tx = 0; 590 schedule_work(&s->work_tx); 591 } 592 #endif 593 594 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 595 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 596 ctrl = serial_port_in(port, SCSCR); 597 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 598 } 599 } 600 601 static void sci_stop_tx(struct uart_port *port) 602 { 603 unsigned short ctrl; 604 605 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 606 ctrl = serial_port_in(port, SCSCR); 607 608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 609 ctrl &= ~SCSCR_TDRQE; 610 611 ctrl &= ~SCSCR_TIE; 612 613 serial_port_out(port, SCSCR, ctrl); 614 615 #ifdef CONFIG_SERIAL_SH_SCI_DMA 616 if (to_sci_port(port)->chan_tx && 617 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 618 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 619 to_sci_port(port)->cookie_tx = -EINVAL; 620 } 621 #endif 622 } 623 624 static void sci_start_rx(struct uart_port *port) 625 { 626 unsigned short ctrl; 627 628 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 629 630 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 631 ctrl &= ~SCSCR_RDRQE; 632 633 serial_port_out(port, SCSCR, ctrl); 634 } 635 636 static void sci_stop_rx(struct uart_port *port) 637 { 638 unsigned short ctrl; 639 640 ctrl = serial_port_in(port, SCSCR); 641 642 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 643 ctrl &= ~SCSCR_RDRQE; 644 645 ctrl &= ~port_rx_irq_mask(port); 646 647 serial_port_out(port, SCSCR, ctrl); 648 } 649 650 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 651 { 652 if (port->type == PORT_SCI) { 653 /* Just store the mask */ 654 serial_port_out(port, SCxSR, mask); 655 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 656 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 657 /* Only clear the status bits we want to clear */ 658 serial_port_out(port, SCxSR, 659 serial_port_in(port, SCxSR) & mask); 660 } else { 661 /* Store the mask, clear parity/framing errors */ 662 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 663 } 664 } 665 666 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 667 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 668 669 #ifdef CONFIG_CONSOLE_POLL 670 static int sci_poll_get_char(struct uart_port *port) 671 { 672 unsigned short status; 673 int c; 674 675 do { 676 status = serial_port_in(port, SCxSR); 677 if (status & SCxSR_ERRORS(port)) { 678 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 679 continue; 680 } 681 break; 682 } while (1); 683 684 if (!(status & SCxSR_RDxF(port))) 685 return NO_POLL_CHAR; 686 687 c = serial_port_in(port, SCxRDR); 688 689 /* Dummy read */ 690 serial_port_in(port, SCxSR); 691 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 692 693 return c; 694 } 695 #endif 696 697 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 698 { 699 unsigned short status; 700 701 do { 702 status = serial_port_in(port, SCxSR); 703 } while (!(status & SCxSR_TDxE(port))); 704 705 serial_port_out(port, SCxTDR, c); 706 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 707 } 708 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 709 CONFIG_SERIAL_SH_SCI_EARLYCON */ 710 711 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 712 { 713 struct sci_port *s = to_sci_port(port); 714 715 /* 716 * Use port-specific handler if provided. 717 */ 718 if (s->cfg->ops && s->cfg->ops->init_pins) { 719 s->cfg->ops->init_pins(port, cflag); 720 return; 721 } 722 723 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 724 u16 data = serial_port_in(port, SCPDR); 725 u16 ctrl = serial_port_in(port, SCPCR); 726 727 /* Enable RXD and TXD pin functions */ 728 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 729 if (to_sci_port(port)->has_rtscts) { 730 /* RTS# is output, active low, unless autorts */ 731 if (!(port->mctrl & TIOCM_RTS)) { 732 ctrl |= SCPCR_RTSC; 733 data |= SCPDR_RTSD; 734 } else if (!s->autorts) { 735 ctrl |= SCPCR_RTSC; 736 data &= ~SCPDR_RTSD; 737 } else { 738 /* Enable RTS# pin function */ 739 ctrl &= ~SCPCR_RTSC; 740 } 741 /* Enable CTS# pin function */ 742 ctrl &= ~SCPCR_CTSC; 743 } 744 serial_port_out(port, SCPDR, data); 745 serial_port_out(port, SCPCR, ctrl); 746 } else if (sci_getreg(port, SCSPTR)->size) { 747 u16 status = serial_port_in(port, SCSPTR); 748 749 /* RTS# is always output; and active low, unless autorts */ 750 status |= SCSPTR_RTSIO; 751 if (!(port->mctrl & TIOCM_RTS)) 752 status |= SCSPTR_RTSDT; 753 else if (!s->autorts) 754 status &= ~SCSPTR_RTSDT; 755 /* CTS# and SCK are inputs */ 756 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 757 serial_port_out(port, SCSPTR, status); 758 } 759 } 760 761 static int sci_txfill(struct uart_port *port) 762 { 763 struct sci_port *s = to_sci_port(port); 764 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 765 const struct plat_sci_reg *reg; 766 767 reg = sci_getreg(port, SCTFDR); 768 if (reg->size) 769 return serial_port_in(port, SCTFDR) & fifo_mask; 770 771 reg = sci_getreg(port, SCFDR); 772 if (reg->size) 773 return serial_port_in(port, SCFDR) >> 8; 774 775 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 776 } 777 778 static int sci_txroom(struct uart_port *port) 779 { 780 return port->fifosize - sci_txfill(port); 781 } 782 783 static int sci_rxfill(struct uart_port *port) 784 { 785 struct sci_port *s = to_sci_port(port); 786 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 787 const struct plat_sci_reg *reg; 788 789 reg = sci_getreg(port, SCRFDR); 790 if (reg->size) 791 return serial_port_in(port, SCRFDR) & fifo_mask; 792 793 reg = sci_getreg(port, SCFDR); 794 if (reg->size) 795 return serial_port_in(port, SCFDR) & fifo_mask; 796 797 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 798 } 799 800 /* ********************************************************************** * 801 * the interrupt related routines * 802 * ********************************************************************** */ 803 804 static void sci_transmit_chars(struct uart_port *port) 805 { 806 struct circ_buf *xmit = &port->state->xmit; 807 unsigned int stopped = uart_tx_stopped(port); 808 unsigned short status; 809 unsigned short ctrl; 810 int count; 811 812 status = serial_port_in(port, SCxSR); 813 if (!(status & SCxSR_TDxE(port))) { 814 ctrl = serial_port_in(port, SCSCR); 815 if (uart_circ_empty(xmit)) 816 ctrl &= ~SCSCR_TIE; 817 else 818 ctrl |= SCSCR_TIE; 819 serial_port_out(port, SCSCR, ctrl); 820 return; 821 } 822 823 count = sci_txroom(port); 824 825 do { 826 unsigned char c; 827 828 if (port->x_char) { 829 c = port->x_char; 830 port->x_char = 0; 831 } else if (!uart_circ_empty(xmit) && !stopped) { 832 c = xmit->buf[xmit->tail]; 833 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 834 } else { 835 break; 836 } 837 838 serial_port_out(port, SCxTDR, c); 839 840 port->icount.tx++; 841 } while (--count > 0); 842 843 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 844 845 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 846 uart_write_wakeup(port); 847 if (uart_circ_empty(xmit)) 848 sci_stop_tx(port); 849 850 } 851 852 static void sci_receive_chars(struct uart_port *port) 853 { 854 struct tty_port *tport = &port->state->port; 855 int i, count, copied = 0; 856 unsigned short status; 857 unsigned char flag; 858 859 status = serial_port_in(port, SCxSR); 860 if (!(status & SCxSR_RDxF(port))) 861 return; 862 863 while (1) { 864 /* Don't copy more bytes than there is room for in the buffer */ 865 count = tty_buffer_request_room(tport, sci_rxfill(port)); 866 867 /* If for any reason we can't copy more data, we're done! */ 868 if (count == 0) 869 break; 870 871 if (port->type == PORT_SCI) { 872 char c = serial_port_in(port, SCxRDR); 873 if (uart_handle_sysrq_char(port, c)) 874 count = 0; 875 else 876 tty_insert_flip_char(tport, c, TTY_NORMAL); 877 } else { 878 for (i = 0; i < count; i++) { 879 char c; 880 881 if (port->type == PORT_SCIF || 882 port->type == PORT_HSCIF) { 883 status = serial_port_in(port, SCxSR); 884 c = serial_port_in(port, SCxRDR); 885 } else { 886 c = serial_port_in(port, SCxRDR); 887 status = serial_port_in(port, SCxSR); 888 } 889 if (uart_handle_sysrq_char(port, c)) { 890 count--; i--; 891 continue; 892 } 893 894 /* Store data and status */ 895 if (status & SCxSR_FER(port)) { 896 flag = TTY_FRAME; 897 port->icount.frame++; 898 dev_notice(port->dev, "frame error\n"); 899 } else if (status & SCxSR_PER(port)) { 900 flag = TTY_PARITY; 901 port->icount.parity++; 902 dev_notice(port->dev, "parity error\n"); 903 } else 904 flag = TTY_NORMAL; 905 906 tty_insert_flip_char(tport, c, flag); 907 } 908 } 909 910 serial_port_in(port, SCxSR); /* dummy read */ 911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 912 913 copied += count; 914 port->icount.rx += count; 915 } 916 917 if (copied) { 918 /* Tell the rest of the system the news. New characters! */ 919 tty_flip_buffer_push(tport); 920 } else { 921 /* TTY buffers full; read from RX reg to prevent lockup */ 922 serial_port_in(port, SCxRDR); 923 serial_port_in(port, SCxSR); /* dummy read */ 924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 925 } 926 } 927 928 static int sci_handle_errors(struct uart_port *port) 929 { 930 int copied = 0; 931 unsigned short status = serial_port_in(port, SCxSR); 932 struct tty_port *tport = &port->state->port; 933 struct sci_port *s = to_sci_port(port); 934 935 /* Handle overruns */ 936 if (status & s->params->overrun_mask) { 937 port->icount.overrun++; 938 939 /* overrun error */ 940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 941 copied++; 942 943 dev_notice(port->dev, "overrun error\n"); 944 } 945 946 if (status & SCxSR_FER(port)) { 947 /* frame error */ 948 port->icount.frame++; 949 950 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 951 copied++; 952 953 dev_notice(port->dev, "frame error\n"); 954 } 955 956 if (status & SCxSR_PER(port)) { 957 /* parity error */ 958 port->icount.parity++; 959 960 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 961 copied++; 962 963 dev_notice(port->dev, "parity error\n"); 964 } 965 966 if (copied) 967 tty_flip_buffer_push(tport); 968 969 return copied; 970 } 971 972 static int sci_handle_fifo_overrun(struct uart_port *port) 973 { 974 struct tty_port *tport = &port->state->port; 975 struct sci_port *s = to_sci_port(port); 976 const struct plat_sci_reg *reg; 977 int copied = 0; 978 u16 status; 979 980 reg = sci_getreg(port, s->params->overrun_reg); 981 if (!reg->size) 982 return 0; 983 984 status = serial_port_in(port, s->params->overrun_reg); 985 if (status & s->params->overrun_mask) { 986 status &= ~s->params->overrun_mask; 987 serial_port_out(port, s->params->overrun_reg, status); 988 989 port->icount.overrun++; 990 991 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 992 tty_flip_buffer_push(tport); 993 994 dev_dbg(port->dev, "overrun error\n"); 995 copied++; 996 } 997 998 return copied; 999 } 1000 1001 static int sci_handle_breaks(struct uart_port *port) 1002 { 1003 int copied = 0; 1004 unsigned short status = serial_port_in(port, SCxSR); 1005 struct tty_port *tport = &port->state->port; 1006 1007 if (uart_handle_break(port)) 1008 return 0; 1009 1010 if (status & SCxSR_BRK(port)) { 1011 port->icount.brk++; 1012 1013 /* Notify of BREAK */ 1014 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1015 copied++; 1016 1017 dev_dbg(port->dev, "BREAK detected\n"); 1018 } 1019 1020 if (copied) 1021 tty_flip_buffer_push(tport); 1022 1023 copied += sci_handle_fifo_overrun(port); 1024 1025 return copied; 1026 } 1027 1028 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1029 { 1030 unsigned int bits; 1031 1032 if (rx_trig >= port->fifosize) 1033 rx_trig = port->fifosize - 1; 1034 if (rx_trig < 1) 1035 rx_trig = 1; 1036 1037 /* HSCIF can be set to an arbitrary level. */ 1038 if (sci_getreg(port, HSRTRGR)->size) { 1039 serial_port_out(port, HSRTRGR, rx_trig); 1040 return rx_trig; 1041 } 1042 1043 switch (port->type) { 1044 case PORT_SCIF: 1045 if (rx_trig < 4) { 1046 bits = 0; 1047 rx_trig = 1; 1048 } else if (rx_trig < 8) { 1049 bits = SCFCR_RTRG0; 1050 rx_trig = 4; 1051 } else if (rx_trig < 14) { 1052 bits = SCFCR_RTRG1; 1053 rx_trig = 8; 1054 } else { 1055 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1056 rx_trig = 14; 1057 } 1058 break; 1059 case PORT_SCIFA: 1060 case PORT_SCIFB: 1061 if (rx_trig < 16) { 1062 bits = 0; 1063 rx_trig = 1; 1064 } else if (rx_trig < 32) { 1065 bits = SCFCR_RTRG0; 1066 rx_trig = 16; 1067 } else if (rx_trig < 48) { 1068 bits = SCFCR_RTRG1; 1069 rx_trig = 32; 1070 } else { 1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1072 rx_trig = 48; 1073 } 1074 break; 1075 default: 1076 WARN(1, "unknown FIFO configuration"); 1077 return 1; 1078 } 1079 1080 serial_port_out(port, SCFCR, 1081 (serial_port_in(port, SCFCR) & 1082 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1083 1084 return rx_trig; 1085 } 1086 1087 static int scif_rtrg_enabled(struct uart_port *port) 1088 { 1089 if (sci_getreg(port, HSRTRGR)->size) 1090 return serial_port_in(port, HSRTRGR) != 0; 1091 else 1092 return (serial_port_in(port, SCFCR) & 1093 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1094 } 1095 1096 static void rx_fifo_timer_fn(struct timer_list *t) 1097 { 1098 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1099 struct uart_port *port = &s->port; 1100 1101 dev_dbg(port->dev, "Rx timed out\n"); 1102 scif_set_rtrg(port, 1); 1103 } 1104 1105 static ssize_t rx_fifo_trigger_show(struct device *dev, 1106 struct device_attribute *attr, char *buf) 1107 { 1108 struct uart_port *port = dev_get_drvdata(dev); 1109 struct sci_port *sci = to_sci_port(port); 1110 1111 return sprintf(buf, "%d\n", sci->rx_trigger); 1112 } 1113 1114 static ssize_t rx_fifo_trigger_store(struct device *dev, 1115 struct device_attribute *attr, 1116 const char *buf, size_t count) 1117 { 1118 struct uart_port *port = dev_get_drvdata(dev); 1119 struct sci_port *sci = to_sci_port(port); 1120 int ret; 1121 long r; 1122 1123 ret = kstrtol(buf, 0, &r); 1124 if (ret) 1125 return ret; 1126 1127 sci->rx_trigger = scif_set_rtrg(port, r); 1128 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1129 scif_set_rtrg(port, 1); 1130 1131 return count; 1132 } 1133 1134 static DEVICE_ATTR_RW(rx_fifo_trigger); 1135 1136 static ssize_t rx_fifo_timeout_show(struct device *dev, 1137 struct device_attribute *attr, 1138 char *buf) 1139 { 1140 struct uart_port *port = dev_get_drvdata(dev); 1141 struct sci_port *sci = to_sci_port(port); 1142 int v; 1143 1144 if (port->type == PORT_HSCIF) 1145 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1146 else 1147 v = sci->rx_fifo_timeout; 1148 1149 return sprintf(buf, "%d\n", v); 1150 } 1151 1152 static ssize_t rx_fifo_timeout_store(struct device *dev, 1153 struct device_attribute *attr, 1154 const char *buf, 1155 size_t count) 1156 { 1157 struct uart_port *port = dev_get_drvdata(dev); 1158 struct sci_port *sci = to_sci_port(port); 1159 int ret; 1160 long r; 1161 1162 ret = kstrtol(buf, 0, &r); 1163 if (ret) 1164 return ret; 1165 1166 if (port->type == PORT_HSCIF) { 1167 if (r < 0 || r > 3) 1168 return -EINVAL; 1169 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1170 } else { 1171 sci->rx_fifo_timeout = r; 1172 scif_set_rtrg(port, 1); 1173 if (r > 0) 1174 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1175 } 1176 1177 return count; 1178 } 1179 1180 static DEVICE_ATTR_RW(rx_fifo_timeout); 1181 1182 1183 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1184 static void sci_dma_tx_complete(void *arg) 1185 { 1186 struct sci_port *s = arg; 1187 struct uart_port *port = &s->port; 1188 struct circ_buf *xmit = &port->state->xmit; 1189 unsigned long flags; 1190 1191 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1192 1193 spin_lock_irqsave(&port->lock, flags); 1194 1195 xmit->tail += s->tx_dma_len; 1196 xmit->tail &= UART_XMIT_SIZE - 1; 1197 1198 port->icount.tx += s->tx_dma_len; 1199 1200 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1201 uart_write_wakeup(port); 1202 1203 if (!uart_circ_empty(xmit)) { 1204 s->cookie_tx = 0; 1205 schedule_work(&s->work_tx); 1206 } else { 1207 s->cookie_tx = -EINVAL; 1208 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1209 u16 ctrl = serial_port_in(port, SCSCR); 1210 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1211 } 1212 } 1213 1214 spin_unlock_irqrestore(&port->lock, flags); 1215 } 1216 1217 /* Locking: called with port lock held */ 1218 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1219 { 1220 struct uart_port *port = &s->port; 1221 struct tty_port *tport = &port->state->port; 1222 int copied; 1223 1224 copied = tty_insert_flip_string(tport, buf, count); 1225 if (copied < count) 1226 port->icount.buf_overrun++; 1227 1228 port->icount.rx += copied; 1229 1230 return copied; 1231 } 1232 1233 static int sci_dma_rx_find_active(struct sci_port *s) 1234 { 1235 unsigned int i; 1236 1237 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1238 if (s->active_rx == s->cookie_rx[i]) 1239 return i; 1240 1241 return -1; 1242 } 1243 1244 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1245 { 1246 unsigned int i; 1247 1248 s->chan_rx = NULL; 1249 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1250 s->cookie_rx[i] = -EINVAL; 1251 s->active_rx = 0; 1252 } 1253 1254 static void sci_dma_rx_release(struct sci_port *s) 1255 { 1256 struct dma_chan *chan = s->chan_rx_saved; 1257 1258 s->chan_rx_saved = NULL; 1259 sci_dma_rx_chan_invalidate(s); 1260 dmaengine_terminate_sync(chan); 1261 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1262 sg_dma_address(&s->sg_rx[0])); 1263 dma_release_channel(chan); 1264 } 1265 1266 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1267 { 1268 long sec = usec / 1000000; 1269 long nsec = (usec % 1000000) * 1000; 1270 ktime_t t = ktime_set(sec, nsec); 1271 1272 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1273 } 1274 1275 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1276 { 1277 struct uart_port *port = &s->port; 1278 u16 scr; 1279 1280 /* Direct new serial port interrupts back to CPU */ 1281 scr = serial_port_in(port, SCSCR); 1282 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1283 scr &= ~SCSCR_RDRQE; 1284 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1285 } 1286 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1287 } 1288 1289 static void sci_dma_rx_complete(void *arg) 1290 { 1291 struct sci_port *s = arg; 1292 struct dma_chan *chan = s->chan_rx; 1293 struct uart_port *port = &s->port; 1294 struct dma_async_tx_descriptor *desc; 1295 unsigned long flags; 1296 int active, count = 0; 1297 1298 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1299 s->active_rx); 1300 1301 spin_lock_irqsave(&port->lock, flags); 1302 1303 active = sci_dma_rx_find_active(s); 1304 if (active >= 0) 1305 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1306 1307 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1308 1309 if (count) 1310 tty_flip_buffer_push(&port->state->port); 1311 1312 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1313 DMA_DEV_TO_MEM, 1314 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1315 if (!desc) 1316 goto fail; 1317 1318 desc->callback = sci_dma_rx_complete; 1319 desc->callback_param = s; 1320 s->cookie_rx[active] = dmaengine_submit(desc); 1321 if (dma_submit_error(s->cookie_rx[active])) 1322 goto fail; 1323 1324 s->active_rx = s->cookie_rx[!active]; 1325 1326 dma_async_issue_pending(chan); 1327 1328 spin_unlock_irqrestore(&port->lock, flags); 1329 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1330 __func__, s->cookie_rx[active], active, s->active_rx); 1331 return; 1332 1333 fail: 1334 spin_unlock_irqrestore(&port->lock, flags); 1335 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1336 /* Switch to PIO */ 1337 spin_lock_irqsave(&port->lock, flags); 1338 dmaengine_terminate_async(chan); 1339 sci_dma_rx_chan_invalidate(s); 1340 sci_dma_rx_reenable_irq(s); 1341 spin_unlock_irqrestore(&port->lock, flags); 1342 } 1343 1344 static void sci_dma_tx_release(struct sci_port *s) 1345 { 1346 struct dma_chan *chan = s->chan_tx_saved; 1347 1348 cancel_work_sync(&s->work_tx); 1349 s->chan_tx_saved = s->chan_tx = NULL; 1350 s->cookie_tx = -EINVAL; 1351 dmaengine_terminate_sync(chan); 1352 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1353 DMA_TO_DEVICE); 1354 dma_release_channel(chan); 1355 } 1356 1357 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1358 { 1359 struct dma_chan *chan = s->chan_rx; 1360 struct uart_port *port = &s->port; 1361 unsigned long flags; 1362 int i; 1363 1364 for (i = 0; i < 2; i++) { 1365 struct scatterlist *sg = &s->sg_rx[i]; 1366 struct dma_async_tx_descriptor *desc; 1367 1368 desc = dmaengine_prep_slave_sg(chan, 1369 sg, 1, DMA_DEV_TO_MEM, 1370 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1371 if (!desc) 1372 goto fail; 1373 1374 desc->callback = sci_dma_rx_complete; 1375 desc->callback_param = s; 1376 s->cookie_rx[i] = dmaengine_submit(desc); 1377 if (dma_submit_error(s->cookie_rx[i])) 1378 goto fail; 1379 1380 } 1381 1382 s->active_rx = s->cookie_rx[0]; 1383 1384 dma_async_issue_pending(chan); 1385 return 0; 1386 1387 fail: 1388 /* Switch to PIO */ 1389 if (!port_lock_held) 1390 spin_lock_irqsave(&port->lock, flags); 1391 if (i) 1392 dmaengine_terminate_async(chan); 1393 sci_dma_rx_chan_invalidate(s); 1394 sci_start_rx(port); 1395 if (!port_lock_held) 1396 spin_unlock_irqrestore(&port->lock, flags); 1397 return -EAGAIN; 1398 } 1399 1400 static void sci_dma_tx_work_fn(struct work_struct *work) 1401 { 1402 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1403 struct dma_async_tx_descriptor *desc; 1404 struct dma_chan *chan = s->chan_tx; 1405 struct uart_port *port = &s->port; 1406 struct circ_buf *xmit = &port->state->xmit; 1407 unsigned long flags; 1408 dma_addr_t buf; 1409 int head, tail; 1410 1411 /* 1412 * DMA is idle now. 1413 * Port xmit buffer is already mapped, and it is one page... Just adjust 1414 * offsets and lengths. Since it is a circular buffer, we have to 1415 * transmit till the end, and then the rest. Take the port lock to get a 1416 * consistent xmit buffer state. 1417 */ 1418 spin_lock_irq(&port->lock); 1419 head = xmit->head; 1420 tail = xmit->tail; 1421 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1422 s->tx_dma_len = min_t(unsigned int, 1423 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1424 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1425 if (!s->tx_dma_len) { 1426 /* Transmit buffer has been flushed */ 1427 spin_unlock_irq(&port->lock); 1428 return; 1429 } 1430 1431 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1432 DMA_MEM_TO_DEV, 1433 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1434 if (!desc) { 1435 spin_unlock_irq(&port->lock); 1436 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1437 goto switch_to_pio; 1438 } 1439 1440 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1441 DMA_TO_DEVICE); 1442 1443 desc->callback = sci_dma_tx_complete; 1444 desc->callback_param = s; 1445 s->cookie_tx = dmaengine_submit(desc); 1446 if (dma_submit_error(s->cookie_tx)) { 1447 spin_unlock_irq(&port->lock); 1448 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1449 goto switch_to_pio; 1450 } 1451 1452 spin_unlock_irq(&port->lock); 1453 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1454 __func__, xmit->buf, tail, head, s->cookie_tx); 1455 1456 dma_async_issue_pending(chan); 1457 return; 1458 1459 switch_to_pio: 1460 spin_lock_irqsave(&port->lock, flags); 1461 s->chan_tx = NULL; 1462 sci_start_tx(port); 1463 spin_unlock_irqrestore(&port->lock, flags); 1464 return; 1465 } 1466 1467 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1468 { 1469 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1470 struct dma_chan *chan = s->chan_rx; 1471 struct uart_port *port = &s->port; 1472 struct dma_tx_state state; 1473 enum dma_status status; 1474 unsigned long flags; 1475 unsigned int read; 1476 int active, count; 1477 1478 dev_dbg(port->dev, "DMA Rx timed out\n"); 1479 1480 spin_lock_irqsave(&port->lock, flags); 1481 1482 active = sci_dma_rx_find_active(s); 1483 if (active < 0) { 1484 spin_unlock_irqrestore(&port->lock, flags); 1485 return HRTIMER_NORESTART; 1486 } 1487 1488 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1489 if (status == DMA_COMPLETE) { 1490 spin_unlock_irqrestore(&port->lock, flags); 1491 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1492 s->active_rx, active); 1493 1494 /* Let packet complete handler take care of the packet */ 1495 return HRTIMER_NORESTART; 1496 } 1497 1498 dmaengine_pause(chan); 1499 1500 /* 1501 * sometimes DMA transfer doesn't stop even if it is stopped and 1502 * data keeps on coming until transaction is complete so check 1503 * for DMA_COMPLETE again 1504 * Let packet complete handler take care of the packet 1505 */ 1506 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1507 if (status == DMA_COMPLETE) { 1508 spin_unlock_irqrestore(&port->lock, flags); 1509 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1510 return HRTIMER_NORESTART; 1511 } 1512 1513 /* Handle incomplete DMA receive */ 1514 dmaengine_terminate_async(s->chan_rx); 1515 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1516 1517 if (read) { 1518 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1519 if (count) 1520 tty_flip_buffer_push(&port->state->port); 1521 } 1522 1523 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1524 sci_dma_rx_submit(s, true); 1525 1526 sci_dma_rx_reenable_irq(s); 1527 1528 spin_unlock_irqrestore(&port->lock, flags); 1529 1530 return HRTIMER_NORESTART; 1531 } 1532 1533 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1534 enum dma_transfer_direction dir) 1535 { 1536 struct dma_chan *chan; 1537 struct dma_slave_config cfg; 1538 int ret; 1539 1540 chan = dma_request_slave_channel(port->dev, 1541 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1542 if (!chan) { 1543 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1544 return NULL; 1545 } 1546 1547 memset(&cfg, 0, sizeof(cfg)); 1548 cfg.direction = dir; 1549 if (dir == DMA_MEM_TO_DEV) { 1550 cfg.dst_addr = port->mapbase + 1551 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1552 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1553 } else { 1554 cfg.src_addr = port->mapbase + 1555 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1556 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1557 } 1558 1559 ret = dmaengine_slave_config(chan, &cfg); 1560 if (ret) { 1561 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1562 dma_release_channel(chan); 1563 return NULL; 1564 } 1565 1566 return chan; 1567 } 1568 1569 static void sci_request_dma(struct uart_port *port) 1570 { 1571 struct sci_port *s = to_sci_port(port); 1572 struct dma_chan *chan; 1573 1574 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1575 1576 /* 1577 * DMA on console may interfere with Kernel log messages which use 1578 * plain putchar(). So, simply don't use it with a console. 1579 */ 1580 if (uart_console(port)) 1581 return; 1582 1583 if (!port->dev->of_node) 1584 return; 1585 1586 s->cookie_tx = -EINVAL; 1587 1588 /* 1589 * Don't request a dma channel if no channel was specified 1590 * in the device tree. 1591 */ 1592 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1593 return; 1594 1595 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1596 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1597 if (chan) { 1598 /* UART circular tx buffer is an aligned page. */ 1599 s->tx_dma_addr = dma_map_single(chan->device->dev, 1600 port->state->xmit.buf, 1601 UART_XMIT_SIZE, 1602 DMA_TO_DEVICE); 1603 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1604 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1605 dma_release_channel(chan); 1606 } else { 1607 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1608 __func__, UART_XMIT_SIZE, 1609 port->state->xmit.buf, &s->tx_dma_addr); 1610 1611 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1612 s->chan_tx_saved = s->chan_tx = chan; 1613 } 1614 } 1615 1616 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1617 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1618 if (chan) { 1619 unsigned int i; 1620 dma_addr_t dma; 1621 void *buf; 1622 1623 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1624 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1625 &dma, GFP_KERNEL); 1626 if (!buf) { 1627 dev_warn(port->dev, 1628 "Failed to allocate Rx dma buffer, using PIO\n"); 1629 dma_release_channel(chan); 1630 return; 1631 } 1632 1633 for (i = 0; i < 2; i++) { 1634 struct scatterlist *sg = &s->sg_rx[i]; 1635 1636 sg_init_table(sg, 1); 1637 s->rx_buf[i] = buf; 1638 sg_dma_address(sg) = dma; 1639 sg_dma_len(sg) = s->buf_len_rx; 1640 1641 buf += s->buf_len_rx; 1642 dma += s->buf_len_rx; 1643 } 1644 1645 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1646 s->rx_timer.function = sci_dma_rx_timer_fn; 1647 1648 s->chan_rx_saved = s->chan_rx = chan; 1649 1650 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1651 sci_dma_rx_submit(s, false); 1652 } 1653 } 1654 1655 static void sci_free_dma(struct uart_port *port) 1656 { 1657 struct sci_port *s = to_sci_port(port); 1658 1659 if (s->chan_tx_saved) 1660 sci_dma_tx_release(s); 1661 if (s->chan_rx_saved) 1662 sci_dma_rx_release(s); 1663 } 1664 1665 static void sci_flush_buffer(struct uart_port *port) 1666 { 1667 struct sci_port *s = to_sci_port(port); 1668 1669 /* 1670 * In uart_flush_buffer(), the xmit circular buffer has just been 1671 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1672 * pending transfers 1673 */ 1674 s->tx_dma_len = 0; 1675 if (s->chan_tx) { 1676 dmaengine_terminate_async(s->chan_tx); 1677 s->cookie_tx = -EINVAL; 1678 } 1679 } 1680 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1681 static inline void sci_request_dma(struct uart_port *port) 1682 { 1683 } 1684 1685 static inline void sci_free_dma(struct uart_port *port) 1686 { 1687 } 1688 1689 #define sci_flush_buffer NULL 1690 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1691 1692 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1693 { 1694 struct uart_port *port = ptr; 1695 struct sci_port *s = to_sci_port(port); 1696 1697 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1698 if (s->chan_rx) { 1699 u16 scr = serial_port_in(port, SCSCR); 1700 u16 ssr = serial_port_in(port, SCxSR); 1701 1702 /* Disable future Rx interrupts */ 1703 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1704 disable_irq_nosync(irq); 1705 scr |= SCSCR_RDRQE; 1706 } else { 1707 if (sci_dma_rx_submit(s, false) < 0) 1708 goto handle_pio; 1709 1710 scr &= ~SCSCR_RIE; 1711 } 1712 serial_port_out(port, SCSCR, scr); 1713 /* Clear current interrupt */ 1714 serial_port_out(port, SCxSR, 1715 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1716 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1717 jiffies, s->rx_timeout); 1718 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1719 1720 return IRQ_HANDLED; 1721 } 1722 1723 handle_pio: 1724 #endif 1725 1726 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1727 if (!scif_rtrg_enabled(port)) 1728 scif_set_rtrg(port, s->rx_trigger); 1729 1730 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1731 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1732 } 1733 1734 /* I think sci_receive_chars has to be called irrespective 1735 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1736 * to be disabled? 1737 */ 1738 sci_receive_chars(port); 1739 1740 return IRQ_HANDLED; 1741 } 1742 1743 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1744 { 1745 struct uart_port *port = ptr; 1746 unsigned long flags; 1747 1748 spin_lock_irqsave(&port->lock, flags); 1749 sci_transmit_chars(port); 1750 spin_unlock_irqrestore(&port->lock, flags); 1751 1752 return IRQ_HANDLED; 1753 } 1754 1755 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1756 { 1757 struct uart_port *port = ptr; 1758 1759 /* Handle BREAKs */ 1760 sci_handle_breaks(port); 1761 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1762 1763 return IRQ_HANDLED; 1764 } 1765 1766 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1767 { 1768 struct uart_port *port = ptr; 1769 struct sci_port *s = to_sci_port(port); 1770 1771 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1772 /* Break and Error interrupts are muxed */ 1773 unsigned short ssr_status = serial_port_in(port, SCxSR); 1774 1775 /* Break Interrupt */ 1776 if (ssr_status & SCxSR_BRK(port)) 1777 sci_br_interrupt(irq, ptr); 1778 1779 /* Break only? */ 1780 if (!(ssr_status & SCxSR_ERRORS(port))) 1781 return IRQ_HANDLED; 1782 } 1783 1784 /* Handle errors */ 1785 if (port->type == PORT_SCI) { 1786 if (sci_handle_errors(port)) { 1787 /* discard character in rx buffer */ 1788 serial_port_in(port, SCxSR); 1789 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1790 } 1791 } else { 1792 sci_handle_fifo_overrun(port); 1793 if (!s->chan_rx) 1794 sci_receive_chars(port); 1795 } 1796 1797 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1798 1799 /* Kick the transmission */ 1800 if (!s->chan_tx) 1801 sci_tx_interrupt(irq, ptr); 1802 1803 return IRQ_HANDLED; 1804 } 1805 1806 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1807 { 1808 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1809 struct uart_port *port = ptr; 1810 struct sci_port *s = to_sci_port(port); 1811 irqreturn_t ret = IRQ_NONE; 1812 1813 ssr_status = serial_port_in(port, SCxSR); 1814 scr_status = serial_port_in(port, SCSCR); 1815 if (s->params->overrun_reg == SCxSR) 1816 orer_status = ssr_status; 1817 else if (sci_getreg(port, s->params->overrun_reg)->size) 1818 orer_status = serial_port_in(port, s->params->overrun_reg); 1819 1820 err_enabled = scr_status & port_rx_irq_mask(port); 1821 1822 /* Tx Interrupt */ 1823 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1824 !s->chan_tx) 1825 ret = sci_tx_interrupt(irq, ptr); 1826 1827 /* 1828 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1829 * DR flags 1830 */ 1831 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1832 (scr_status & SCSCR_RIE)) 1833 ret = sci_rx_interrupt(irq, ptr); 1834 1835 /* Error Interrupt */ 1836 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1837 ret = sci_er_interrupt(irq, ptr); 1838 1839 /* Break Interrupt */ 1840 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1841 ret = sci_br_interrupt(irq, ptr); 1842 1843 /* Overrun Interrupt */ 1844 if (orer_status & s->params->overrun_mask) { 1845 sci_handle_fifo_overrun(port); 1846 ret = IRQ_HANDLED; 1847 } 1848 1849 return ret; 1850 } 1851 1852 static const struct sci_irq_desc { 1853 const char *desc; 1854 irq_handler_t handler; 1855 } sci_irq_desc[] = { 1856 /* 1857 * Split out handlers, the default case. 1858 */ 1859 [SCIx_ERI_IRQ] = { 1860 .desc = "rx err", 1861 .handler = sci_er_interrupt, 1862 }, 1863 1864 [SCIx_RXI_IRQ] = { 1865 .desc = "rx full", 1866 .handler = sci_rx_interrupt, 1867 }, 1868 1869 [SCIx_TXI_IRQ] = { 1870 .desc = "tx empty", 1871 .handler = sci_tx_interrupt, 1872 }, 1873 1874 [SCIx_BRI_IRQ] = { 1875 .desc = "break", 1876 .handler = sci_br_interrupt, 1877 }, 1878 1879 [SCIx_DRI_IRQ] = { 1880 .desc = "rx ready", 1881 .handler = sci_rx_interrupt, 1882 }, 1883 1884 [SCIx_TEI_IRQ] = { 1885 .desc = "tx end", 1886 .handler = sci_tx_interrupt, 1887 }, 1888 1889 /* 1890 * Special muxed handler. 1891 */ 1892 [SCIx_MUX_IRQ] = { 1893 .desc = "mux", 1894 .handler = sci_mpxed_interrupt, 1895 }, 1896 }; 1897 1898 static int sci_request_irq(struct sci_port *port) 1899 { 1900 struct uart_port *up = &port->port; 1901 int i, j, w, ret = 0; 1902 1903 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1904 const struct sci_irq_desc *desc; 1905 int irq; 1906 1907 /* Check if already registered (muxed) */ 1908 for (w = 0; w < i; w++) 1909 if (port->irqs[w] == port->irqs[i]) 1910 w = i + 1; 1911 if (w > i) 1912 continue; 1913 1914 if (SCIx_IRQ_IS_MUXED(port)) { 1915 i = SCIx_MUX_IRQ; 1916 irq = up->irq; 1917 } else { 1918 irq = port->irqs[i]; 1919 1920 /* 1921 * Certain port types won't support all of the 1922 * available interrupt sources. 1923 */ 1924 if (unlikely(irq < 0)) 1925 continue; 1926 } 1927 1928 desc = sci_irq_desc + i; 1929 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1930 dev_name(up->dev), desc->desc); 1931 if (!port->irqstr[j]) { 1932 ret = -ENOMEM; 1933 goto out_nomem; 1934 } 1935 1936 ret = request_irq(irq, desc->handler, up->irqflags, 1937 port->irqstr[j], port); 1938 if (unlikely(ret)) { 1939 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1940 goto out_noirq; 1941 } 1942 } 1943 1944 return 0; 1945 1946 out_noirq: 1947 while (--i >= 0) 1948 free_irq(port->irqs[i], port); 1949 1950 out_nomem: 1951 while (--j >= 0) 1952 kfree(port->irqstr[j]); 1953 1954 return ret; 1955 } 1956 1957 static void sci_free_irq(struct sci_port *port) 1958 { 1959 int i, j; 1960 1961 /* 1962 * Intentionally in reverse order so we iterate over the muxed 1963 * IRQ first. 1964 */ 1965 for (i = 0; i < SCIx_NR_IRQS; i++) { 1966 int irq = port->irqs[i]; 1967 1968 /* 1969 * Certain port types won't support all of the available 1970 * interrupt sources. 1971 */ 1972 if (unlikely(irq < 0)) 1973 continue; 1974 1975 /* Check if already freed (irq was muxed) */ 1976 for (j = 0; j < i; j++) 1977 if (port->irqs[j] == irq) 1978 j = i + 1; 1979 if (j > i) 1980 continue; 1981 1982 free_irq(port->irqs[i], port); 1983 kfree(port->irqstr[i]); 1984 1985 if (SCIx_IRQ_IS_MUXED(port)) { 1986 /* If there's only one IRQ, we're done. */ 1987 return; 1988 } 1989 } 1990 } 1991 1992 static unsigned int sci_tx_empty(struct uart_port *port) 1993 { 1994 unsigned short status = serial_port_in(port, SCxSR); 1995 unsigned short in_tx_fifo = sci_txfill(port); 1996 1997 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1998 } 1999 2000 static void sci_set_rts(struct uart_port *port, bool state) 2001 { 2002 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2003 u16 data = serial_port_in(port, SCPDR); 2004 2005 /* Active low */ 2006 if (state) 2007 data &= ~SCPDR_RTSD; 2008 else 2009 data |= SCPDR_RTSD; 2010 serial_port_out(port, SCPDR, data); 2011 2012 /* RTS# is output */ 2013 serial_port_out(port, SCPCR, 2014 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2015 } else if (sci_getreg(port, SCSPTR)->size) { 2016 u16 ctrl = serial_port_in(port, SCSPTR); 2017 2018 /* Active low */ 2019 if (state) 2020 ctrl &= ~SCSPTR_RTSDT; 2021 else 2022 ctrl |= SCSPTR_RTSDT; 2023 serial_port_out(port, SCSPTR, ctrl); 2024 } 2025 } 2026 2027 static bool sci_get_cts(struct uart_port *port) 2028 { 2029 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2030 /* Active low */ 2031 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2032 } else if (sci_getreg(port, SCSPTR)->size) { 2033 /* Active low */ 2034 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2035 } 2036 2037 return true; 2038 } 2039 2040 /* 2041 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2042 * CTS/RTS is supported in hardware by at least one port and controlled 2043 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2044 * handled via the ->init_pins() op, which is a bit of a one-way street, 2045 * lacking any ability to defer pin control -- this will later be 2046 * converted over to the GPIO framework). 2047 * 2048 * Other modes (such as loopback) are supported generically on certain 2049 * port types, but not others. For these it's sufficient to test for the 2050 * existence of the support register and simply ignore the port type. 2051 */ 2052 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2053 { 2054 struct sci_port *s = to_sci_port(port); 2055 2056 if (mctrl & TIOCM_LOOP) { 2057 const struct plat_sci_reg *reg; 2058 2059 /* 2060 * Standard loopback mode for SCFCR ports. 2061 */ 2062 reg = sci_getreg(port, SCFCR); 2063 if (reg->size) 2064 serial_port_out(port, SCFCR, 2065 serial_port_in(port, SCFCR) | 2066 SCFCR_LOOP); 2067 } 2068 2069 mctrl_gpio_set(s->gpios, mctrl); 2070 2071 if (!s->has_rtscts) 2072 return; 2073 2074 if (!(mctrl & TIOCM_RTS)) { 2075 /* Disable Auto RTS */ 2076 serial_port_out(port, SCFCR, 2077 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2078 2079 /* Clear RTS */ 2080 sci_set_rts(port, 0); 2081 } else if (s->autorts) { 2082 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2083 /* Enable RTS# pin function */ 2084 serial_port_out(port, SCPCR, 2085 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2086 } 2087 2088 /* Enable Auto RTS */ 2089 serial_port_out(port, SCFCR, 2090 serial_port_in(port, SCFCR) | SCFCR_MCE); 2091 } else { 2092 /* Set RTS */ 2093 sci_set_rts(port, 1); 2094 } 2095 } 2096 2097 static unsigned int sci_get_mctrl(struct uart_port *port) 2098 { 2099 struct sci_port *s = to_sci_port(port); 2100 struct mctrl_gpios *gpios = s->gpios; 2101 unsigned int mctrl = 0; 2102 2103 mctrl_gpio_get(gpios, &mctrl); 2104 2105 /* 2106 * CTS/RTS is handled in hardware when supported, while nothing 2107 * else is wired up. 2108 */ 2109 if (s->autorts) { 2110 if (sci_get_cts(port)) 2111 mctrl |= TIOCM_CTS; 2112 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2113 mctrl |= TIOCM_CTS; 2114 } 2115 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2116 mctrl |= TIOCM_DSR; 2117 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2118 mctrl |= TIOCM_CAR; 2119 2120 return mctrl; 2121 } 2122 2123 static void sci_enable_ms(struct uart_port *port) 2124 { 2125 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2126 } 2127 2128 static void sci_break_ctl(struct uart_port *port, int break_state) 2129 { 2130 unsigned short scscr, scsptr; 2131 unsigned long flags; 2132 2133 /* check whether the port has SCSPTR */ 2134 if (!sci_getreg(port, SCSPTR)->size) { 2135 /* 2136 * Not supported by hardware. Most parts couple break and rx 2137 * interrupts together, with break detection always enabled. 2138 */ 2139 return; 2140 } 2141 2142 spin_lock_irqsave(&port->lock, flags); 2143 scsptr = serial_port_in(port, SCSPTR); 2144 scscr = serial_port_in(port, SCSCR); 2145 2146 if (break_state == -1) { 2147 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2148 scscr &= ~SCSCR_TE; 2149 } else { 2150 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2151 scscr |= SCSCR_TE; 2152 } 2153 2154 serial_port_out(port, SCSPTR, scsptr); 2155 serial_port_out(port, SCSCR, scscr); 2156 spin_unlock_irqrestore(&port->lock, flags); 2157 } 2158 2159 static int sci_startup(struct uart_port *port) 2160 { 2161 struct sci_port *s = to_sci_port(port); 2162 int ret; 2163 2164 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2165 2166 sci_request_dma(port); 2167 2168 ret = sci_request_irq(s); 2169 if (unlikely(ret < 0)) { 2170 sci_free_dma(port); 2171 return ret; 2172 } 2173 2174 return 0; 2175 } 2176 2177 static void sci_shutdown(struct uart_port *port) 2178 { 2179 struct sci_port *s = to_sci_port(port); 2180 unsigned long flags; 2181 u16 scr; 2182 2183 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2184 2185 s->autorts = false; 2186 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2187 2188 spin_lock_irqsave(&port->lock, flags); 2189 sci_stop_rx(port); 2190 sci_stop_tx(port); 2191 /* 2192 * Stop RX and TX, disable related interrupts, keep clock source 2193 * and HSCIF TOT bits 2194 */ 2195 scr = serial_port_in(port, SCSCR); 2196 serial_port_out(port, SCSCR, scr & 2197 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2198 spin_unlock_irqrestore(&port->lock, flags); 2199 2200 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2201 if (s->chan_rx_saved) { 2202 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2203 port->line); 2204 hrtimer_cancel(&s->rx_timer); 2205 } 2206 #endif 2207 2208 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2209 del_timer_sync(&s->rx_fifo_timer); 2210 sci_free_irq(s); 2211 sci_free_dma(port); 2212 } 2213 2214 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2215 unsigned int *srr) 2216 { 2217 unsigned long freq = s->clk_rates[SCI_SCK]; 2218 int err, min_err = INT_MAX; 2219 unsigned int sr; 2220 2221 if (s->port.type != PORT_HSCIF) 2222 freq *= 2; 2223 2224 for_each_sr(sr, s) { 2225 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2226 if (abs(err) >= abs(min_err)) 2227 continue; 2228 2229 min_err = err; 2230 *srr = sr - 1; 2231 2232 if (!err) 2233 break; 2234 } 2235 2236 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2237 *srr + 1); 2238 return min_err; 2239 } 2240 2241 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2242 unsigned long freq, unsigned int *dlr, 2243 unsigned int *srr) 2244 { 2245 int err, min_err = INT_MAX; 2246 unsigned int sr, dl; 2247 2248 if (s->port.type != PORT_HSCIF) 2249 freq *= 2; 2250 2251 for_each_sr(sr, s) { 2252 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2253 dl = clamp(dl, 1U, 65535U); 2254 2255 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2256 if (abs(err) >= abs(min_err)) 2257 continue; 2258 2259 min_err = err; 2260 *dlr = dl; 2261 *srr = sr - 1; 2262 2263 if (!err) 2264 break; 2265 } 2266 2267 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2268 min_err, *dlr, *srr + 1); 2269 return min_err; 2270 } 2271 2272 /* calculate sample rate, BRR, and clock select */ 2273 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2274 unsigned int *brr, unsigned int *srr, 2275 unsigned int *cks) 2276 { 2277 unsigned long freq = s->clk_rates[SCI_FCK]; 2278 unsigned int sr, br, prediv, scrate, c; 2279 int err, min_err = INT_MAX; 2280 2281 if (s->port.type != PORT_HSCIF) 2282 freq *= 2; 2283 2284 /* 2285 * Find the combination of sample rate and clock select with the 2286 * smallest deviation from the desired baud rate. 2287 * Prefer high sample rates to maximise the receive margin. 2288 * 2289 * M: Receive margin (%) 2290 * N: Ratio of bit rate to clock (N = sampling rate) 2291 * D: Clock duty (D = 0 to 1.0) 2292 * L: Frame length (L = 9 to 12) 2293 * F: Absolute value of clock frequency deviation 2294 * 2295 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2296 * (|D - 0.5| / N * (1 + F))| 2297 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2298 */ 2299 for_each_sr(sr, s) { 2300 for (c = 0; c <= 3; c++) { 2301 /* integerized formulas from HSCIF documentation */ 2302 prediv = sr * (1 << (2 * c + 1)); 2303 2304 /* 2305 * We need to calculate: 2306 * 2307 * br = freq / (prediv * bps) clamped to [1..256] 2308 * err = freq / (br * prediv) - bps 2309 * 2310 * Watch out for overflow when calculating the desired 2311 * sampling clock rate! 2312 */ 2313 if (bps > UINT_MAX / prediv) 2314 break; 2315 2316 scrate = prediv * bps; 2317 br = DIV_ROUND_CLOSEST(freq, scrate); 2318 br = clamp(br, 1U, 256U); 2319 2320 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2321 if (abs(err) >= abs(min_err)) 2322 continue; 2323 2324 min_err = err; 2325 *brr = br - 1; 2326 *srr = sr - 1; 2327 *cks = c; 2328 2329 if (!err) 2330 goto found; 2331 } 2332 } 2333 2334 found: 2335 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2336 min_err, *brr, *srr + 1, *cks); 2337 return min_err; 2338 } 2339 2340 static void sci_reset(struct uart_port *port) 2341 { 2342 const struct plat_sci_reg *reg; 2343 unsigned int status; 2344 struct sci_port *s = to_sci_port(port); 2345 2346 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2347 2348 reg = sci_getreg(port, SCFCR); 2349 if (reg->size) 2350 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2351 2352 sci_clear_SCxSR(port, 2353 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2354 SCxSR_BREAK_CLEAR(port)); 2355 if (sci_getreg(port, SCLSR)->size) { 2356 status = serial_port_in(port, SCLSR); 2357 status &= ~(SCLSR_TO | SCLSR_ORER); 2358 serial_port_out(port, SCLSR, status); 2359 } 2360 2361 if (s->rx_trigger > 1) { 2362 if (s->rx_fifo_timeout) { 2363 scif_set_rtrg(port, 1); 2364 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2365 } else { 2366 if (port->type == PORT_SCIFA || 2367 port->type == PORT_SCIFB) 2368 scif_set_rtrg(port, 1); 2369 else 2370 scif_set_rtrg(port, s->rx_trigger); 2371 } 2372 } 2373 } 2374 2375 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2376 struct ktermios *old) 2377 { 2378 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2379 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2380 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2381 struct sci_port *s = to_sci_port(port); 2382 const struct plat_sci_reg *reg; 2383 int min_err = INT_MAX, err; 2384 unsigned long max_freq = 0; 2385 int best_clk = -1; 2386 unsigned long flags; 2387 2388 if ((termios->c_cflag & CSIZE) == CS7) 2389 smr_val |= SCSMR_CHR; 2390 if (termios->c_cflag & PARENB) 2391 smr_val |= SCSMR_PE; 2392 if (termios->c_cflag & PARODD) 2393 smr_val |= SCSMR_PE | SCSMR_ODD; 2394 if (termios->c_cflag & CSTOPB) 2395 smr_val |= SCSMR_STOP; 2396 2397 /* 2398 * earlyprintk comes here early on with port->uartclk set to zero. 2399 * the clock framework is not up and running at this point so here 2400 * we assume that 115200 is the maximum baud rate. please note that 2401 * the baud rate is not programmed during earlyprintk - it is assumed 2402 * that the previous boot loader has enabled required clocks and 2403 * setup the baud rate generator hardware for us already. 2404 */ 2405 if (!port->uartclk) { 2406 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2407 goto done; 2408 } 2409 2410 for (i = 0; i < SCI_NUM_CLKS; i++) 2411 max_freq = max(max_freq, s->clk_rates[i]); 2412 2413 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2414 if (!baud) 2415 goto done; 2416 2417 /* 2418 * There can be multiple sources for the sampling clock. Find the one 2419 * that gives us the smallest deviation from the desired baud rate. 2420 */ 2421 2422 /* Optional Undivided External Clock */ 2423 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2424 port->type != PORT_SCIFB) { 2425 err = sci_sck_calc(s, baud, &srr1); 2426 if (abs(err) < abs(min_err)) { 2427 best_clk = SCI_SCK; 2428 scr_val = SCSCR_CKE1; 2429 sccks = SCCKS_CKS; 2430 min_err = err; 2431 srr = srr1; 2432 if (!err) 2433 goto done; 2434 } 2435 } 2436 2437 /* Optional BRG Frequency Divided External Clock */ 2438 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2439 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2440 &srr1); 2441 if (abs(err) < abs(min_err)) { 2442 best_clk = SCI_SCIF_CLK; 2443 scr_val = SCSCR_CKE1; 2444 sccks = 0; 2445 min_err = err; 2446 dl = dl1; 2447 srr = srr1; 2448 if (!err) 2449 goto done; 2450 } 2451 } 2452 2453 /* Optional BRG Frequency Divided Internal Clock */ 2454 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2455 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2456 &srr1); 2457 if (abs(err) < abs(min_err)) { 2458 best_clk = SCI_BRG_INT; 2459 scr_val = SCSCR_CKE1; 2460 sccks = SCCKS_XIN; 2461 min_err = err; 2462 dl = dl1; 2463 srr = srr1; 2464 if (!min_err) 2465 goto done; 2466 } 2467 } 2468 2469 /* Divided Functional Clock using standard Bit Rate Register */ 2470 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2471 if (abs(err) < abs(min_err)) { 2472 best_clk = SCI_FCK; 2473 scr_val = 0; 2474 min_err = err; 2475 brr = brr1; 2476 srr = srr1; 2477 cks = cks1; 2478 } 2479 2480 done: 2481 if (best_clk >= 0) 2482 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2483 s->clks[best_clk], baud, min_err); 2484 2485 sci_port_enable(s); 2486 2487 /* 2488 * Program the optional External Baud Rate Generator (BRG) first. 2489 * It controls the mux to select (H)SCK or frequency divided clock. 2490 */ 2491 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2492 serial_port_out(port, SCDL, dl); 2493 serial_port_out(port, SCCKS, sccks); 2494 } 2495 2496 spin_lock_irqsave(&port->lock, flags); 2497 2498 sci_reset(port); 2499 2500 uart_update_timeout(port, termios->c_cflag, baud); 2501 2502 /* byte size and parity */ 2503 bits = tty_get_frame_size(termios->c_cflag); 2504 2505 if (sci_getreg(port, SEMR)->size) 2506 serial_port_out(port, SEMR, 0); 2507 2508 if (best_clk >= 0) { 2509 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2510 switch (srr + 1) { 2511 case 5: smr_val |= SCSMR_SRC_5; break; 2512 case 7: smr_val |= SCSMR_SRC_7; break; 2513 case 11: smr_val |= SCSMR_SRC_11; break; 2514 case 13: smr_val |= SCSMR_SRC_13; break; 2515 case 16: smr_val |= SCSMR_SRC_16; break; 2516 case 17: smr_val |= SCSMR_SRC_17; break; 2517 case 19: smr_val |= SCSMR_SRC_19; break; 2518 case 27: smr_val |= SCSMR_SRC_27; break; 2519 } 2520 smr_val |= cks; 2521 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2522 serial_port_out(port, SCSMR, smr_val); 2523 serial_port_out(port, SCBRR, brr); 2524 if (sci_getreg(port, HSSRR)->size) { 2525 unsigned int hssrr = srr | HSCIF_SRE; 2526 /* Calculate deviation from intended rate at the 2527 * center of the last stop bit in sampling clocks. 2528 */ 2529 int last_stop = bits * 2 - 1; 2530 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2531 (int)(srr + 1), 2532 2 * (int)baud); 2533 2534 if (abs(deviation) >= 2) { 2535 /* At least two sampling clocks off at the 2536 * last stop bit; we can increase the error 2537 * margin by shifting the sampling point. 2538 */ 2539 int shift = clamp(deviation / 2, -8, 7); 2540 2541 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2542 HSCIF_SRHP_MASK; 2543 hssrr |= HSCIF_SRDE; 2544 } 2545 serial_port_out(port, HSSRR, hssrr); 2546 } 2547 2548 /* Wait one bit interval */ 2549 udelay((1000000 + (baud - 1)) / baud); 2550 } else { 2551 /* Don't touch the bit rate configuration */ 2552 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2553 smr_val |= serial_port_in(port, SCSMR) & 2554 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2555 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2556 serial_port_out(port, SCSMR, smr_val); 2557 } 2558 2559 sci_init_pins(port, termios->c_cflag); 2560 2561 port->status &= ~UPSTAT_AUTOCTS; 2562 s->autorts = false; 2563 reg = sci_getreg(port, SCFCR); 2564 if (reg->size) { 2565 unsigned short ctrl = serial_port_in(port, SCFCR); 2566 2567 if ((port->flags & UPF_HARD_FLOW) && 2568 (termios->c_cflag & CRTSCTS)) { 2569 /* There is no CTS interrupt to restart the hardware */ 2570 port->status |= UPSTAT_AUTOCTS; 2571 /* MCE is enabled when RTS is raised */ 2572 s->autorts = true; 2573 } 2574 2575 /* 2576 * As we've done a sci_reset() above, ensure we don't 2577 * interfere with the FIFOs while toggling MCE. As the 2578 * reset values could still be set, simply mask them out. 2579 */ 2580 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2581 2582 serial_port_out(port, SCFCR, ctrl); 2583 } 2584 if (port->flags & UPF_HARD_FLOW) { 2585 /* Refresh (Auto) RTS */ 2586 sci_set_mctrl(port, port->mctrl); 2587 } 2588 2589 scr_val |= SCSCR_RE | SCSCR_TE | 2590 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2591 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2592 if ((srr + 1 == 5) && 2593 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2594 /* 2595 * In asynchronous mode, when the sampling rate is 1/5, first 2596 * received data may become invalid on some SCIFA and SCIFB. 2597 * To avoid this problem wait more than 1 serial data time (1 2598 * bit time x serial data number) after setting SCSCR.RE = 1. 2599 */ 2600 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2601 } 2602 2603 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2604 s->rx_frame = (10000 * bits) / (baud / 100); 2605 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2606 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2607 #endif 2608 2609 if ((termios->c_cflag & CREAD) != 0) 2610 sci_start_rx(port); 2611 2612 spin_unlock_irqrestore(&port->lock, flags); 2613 2614 sci_port_disable(s); 2615 2616 if (UART_ENABLE_MS(port, termios->c_cflag)) 2617 sci_enable_ms(port); 2618 } 2619 2620 static void sci_pm(struct uart_port *port, unsigned int state, 2621 unsigned int oldstate) 2622 { 2623 struct sci_port *sci_port = to_sci_port(port); 2624 2625 switch (state) { 2626 case UART_PM_STATE_OFF: 2627 sci_port_disable(sci_port); 2628 break; 2629 default: 2630 sci_port_enable(sci_port); 2631 break; 2632 } 2633 } 2634 2635 static const char *sci_type(struct uart_port *port) 2636 { 2637 switch (port->type) { 2638 case PORT_IRDA: 2639 return "irda"; 2640 case PORT_SCI: 2641 return "sci"; 2642 case PORT_SCIF: 2643 return "scif"; 2644 case PORT_SCIFA: 2645 return "scifa"; 2646 case PORT_SCIFB: 2647 return "scifb"; 2648 case PORT_HSCIF: 2649 return "hscif"; 2650 } 2651 2652 return NULL; 2653 } 2654 2655 static int sci_remap_port(struct uart_port *port) 2656 { 2657 struct sci_port *sport = to_sci_port(port); 2658 2659 /* 2660 * Nothing to do if there's already an established membase. 2661 */ 2662 if (port->membase) 2663 return 0; 2664 2665 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2666 port->membase = ioremap(port->mapbase, sport->reg_size); 2667 if (unlikely(!port->membase)) { 2668 dev_err(port->dev, "can't remap port#%d\n", port->line); 2669 return -ENXIO; 2670 } 2671 } else { 2672 /* 2673 * For the simple (and majority of) cases where we don't 2674 * need to do any remapping, just cast the cookie 2675 * directly. 2676 */ 2677 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2678 } 2679 2680 return 0; 2681 } 2682 2683 static void sci_release_port(struct uart_port *port) 2684 { 2685 struct sci_port *sport = to_sci_port(port); 2686 2687 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2688 iounmap(port->membase); 2689 port->membase = NULL; 2690 } 2691 2692 release_mem_region(port->mapbase, sport->reg_size); 2693 } 2694 2695 static int sci_request_port(struct uart_port *port) 2696 { 2697 struct resource *res; 2698 struct sci_port *sport = to_sci_port(port); 2699 int ret; 2700 2701 res = request_mem_region(port->mapbase, sport->reg_size, 2702 dev_name(port->dev)); 2703 if (unlikely(res == NULL)) { 2704 dev_err(port->dev, "request_mem_region failed."); 2705 return -EBUSY; 2706 } 2707 2708 ret = sci_remap_port(port); 2709 if (unlikely(ret != 0)) { 2710 release_resource(res); 2711 return ret; 2712 } 2713 2714 return 0; 2715 } 2716 2717 static void sci_config_port(struct uart_port *port, int flags) 2718 { 2719 if (flags & UART_CONFIG_TYPE) { 2720 struct sci_port *sport = to_sci_port(port); 2721 2722 port->type = sport->cfg->type; 2723 sci_request_port(port); 2724 } 2725 } 2726 2727 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2728 { 2729 if (ser->baud_base < 2400) 2730 /* No paper tape reader for Mitch.. */ 2731 return -EINVAL; 2732 2733 return 0; 2734 } 2735 2736 static const struct uart_ops sci_uart_ops = { 2737 .tx_empty = sci_tx_empty, 2738 .set_mctrl = sci_set_mctrl, 2739 .get_mctrl = sci_get_mctrl, 2740 .start_tx = sci_start_tx, 2741 .stop_tx = sci_stop_tx, 2742 .stop_rx = sci_stop_rx, 2743 .enable_ms = sci_enable_ms, 2744 .break_ctl = sci_break_ctl, 2745 .startup = sci_startup, 2746 .shutdown = sci_shutdown, 2747 .flush_buffer = sci_flush_buffer, 2748 .set_termios = sci_set_termios, 2749 .pm = sci_pm, 2750 .type = sci_type, 2751 .release_port = sci_release_port, 2752 .request_port = sci_request_port, 2753 .config_port = sci_config_port, 2754 .verify_port = sci_verify_port, 2755 #ifdef CONFIG_CONSOLE_POLL 2756 .poll_get_char = sci_poll_get_char, 2757 .poll_put_char = sci_poll_put_char, 2758 #endif 2759 }; 2760 2761 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2762 { 2763 const char *clk_names[] = { 2764 [SCI_FCK] = "fck", 2765 [SCI_SCK] = "sck", 2766 [SCI_BRG_INT] = "brg_int", 2767 [SCI_SCIF_CLK] = "scif_clk", 2768 }; 2769 struct clk *clk; 2770 unsigned int i; 2771 2772 if (sci_port->cfg->type == PORT_HSCIF) 2773 clk_names[SCI_SCK] = "hsck"; 2774 2775 for (i = 0; i < SCI_NUM_CLKS; i++) { 2776 clk = devm_clk_get(dev, clk_names[i]); 2777 if (PTR_ERR(clk) == -EPROBE_DEFER) 2778 return -EPROBE_DEFER; 2779 2780 if (IS_ERR(clk) && i == SCI_FCK) { 2781 /* 2782 * "fck" used to be called "sci_ick", and we need to 2783 * maintain DT backward compatibility. 2784 */ 2785 clk = devm_clk_get(dev, "sci_ick"); 2786 if (PTR_ERR(clk) == -EPROBE_DEFER) 2787 return -EPROBE_DEFER; 2788 2789 if (!IS_ERR(clk)) 2790 goto found; 2791 2792 /* 2793 * Not all SH platforms declare a clock lookup entry 2794 * for SCI devices, in which case we need to get the 2795 * global "peripheral_clk" clock. 2796 */ 2797 clk = devm_clk_get(dev, "peripheral_clk"); 2798 if (!IS_ERR(clk)) 2799 goto found; 2800 2801 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2802 PTR_ERR(clk)); 2803 return PTR_ERR(clk); 2804 } 2805 2806 found: 2807 if (IS_ERR(clk)) 2808 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2809 PTR_ERR(clk)); 2810 else 2811 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2812 clk, clk_get_rate(clk)); 2813 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2814 } 2815 return 0; 2816 } 2817 2818 static const struct sci_port_params * 2819 sci_probe_regmap(const struct plat_sci_port *cfg) 2820 { 2821 unsigned int regtype; 2822 2823 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2824 return &sci_port_params[cfg->regtype]; 2825 2826 switch (cfg->type) { 2827 case PORT_SCI: 2828 regtype = SCIx_SCI_REGTYPE; 2829 break; 2830 case PORT_IRDA: 2831 regtype = SCIx_IRDA_REGTYPE; 2832 break; 2833 case PORT_SCIFA: 2834 regtype = SCIx_SCIFA_REGTYPE; 2835 break; 2836 case PORT_SCIFB: 2837 regtype = SCIx_SCIFB_REGTYPE; 2838 break; 2839 case PORT_SCIF: 2840 /* 2841 * The SH-4 is a bit of a misnomer here, although that's 2842 * where this particular port layout originated. This 2843 * configuration (or some slight variation thereof) 2844 * remains the dominant model for all SCIFs. 2845 */ 2846 regtype = SCIx_SH4_SCIF_REGTYPE; 2847 break; 2848 case PORT_HSCIF: 2849 regtype = SCIx_HSCIF_REGTYPE; 2850 break; 2851 default: 2852 pr_err("Can't probe register map for given port\n"); 2853 return NULL; 2854 } 2855 2856 return &sci_port_params[regtype]; 2857 } 2858 2859 static int sci_init_single(struct platform_device *dev, 2860 struct sci_port *sci_port, unsigned int index, 2861 const struct plat_sci_port *p, bool early) 2862 { 2863 struct uart_port *port = &sci_port->port; 2864 const struct resource *res; 2865 unsigned int i; 2866 int ret; 2867 2868 sci_port->cfg = p; 2869 2870 port->ops = &sci_uart_ops; 2871 port->iotype = UPIO_MEM; 2872 port->line = index; 2873 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2874 2875 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2876 if (res == NULL) 2877 return -ENOMEM; 2878 2879 port->mapbase = res->start; 2880 sci_port->reg_size = resource_size(res); 2881 2882 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2883 if (i) 2884 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2885 else 2886 sci_port->irqs[i] = platform_get_irq(dev, i); 2887 } 2888 2889 /* The SCI generates several interrupts. They can be muxed together or 2890 * connected to different interrupt lines. In the muxed case only one 2891 * interrupt resource is specified as there is only one interrupt ID. 2892 * In the non-muxed case, up to 6 interrupt signals might be generated 2893 * from the SCI, however those signals might have their own individual 2894 * interrupt ID numbers, or muxed together with another interrupt. 2895 */ 2896 if (sci_port->irqs[0] < 0) 2897 return -ENXIO; 2898 2899 if (sci_port->irqs[1] < 0) 2900 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2901 sci_port->irqs[i] = sci_port->irqs[0]; 2902 2903 sci_port->params = sci_probe_regmap(p); 2904 if (unlikely(sci_port->params == NULL)) 2905 return -EINVAL; 2906 2907 switch (p->type) { 2908 case PORT_SCIFB: 2909 sci_port->rx_trigger = 48; 2910 break; 2911 case PORT_HSCIF: 2912 sci_port->rx_trigger = 64; 2913 break; 2914 case PORT_SCIFA: 2915 sci_port->rx_trigger = 32; 2916 break; 2917 case PORT_SCIF: 2918 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2919 /* RX triggering not implemented for this IP */ 2920 sci_port->rx_trigger = 1; 2921 else 2922 sci_port->rx_trigger = 8; 2923 break; 2924 default: 2925 sci_port->rx_trigger = 1; 2926 break; 2927 } 2928 2929 sci_port->rx_fifo_timeout = 0; 2930 sci_port->hscif_tot = 0; 2931 2932 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2933 * match the SoC datasheet, this should be investigated. Let platform 2934 * data override the sampling rate for now. 2935 */ 2936 sci_port->sampling_rate_mask = p->sampling_rate 2937 ? SCI_SR(p->sampling_rate) 2938 : sci_port->params->sampling_rate_mask; 2939 2940 if (!early) { 2941 ret = sci_init_clocks(sci_port, &dev->dev); 2942 if (ret < 0) 2943 return ret; 2944 2945 port->dev = &dev->dev; 2946 2947 pm_runtime_enable(&dev->dev); 2948 } 2949 2950 port->type = p->type; 2951 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2952 port->fifosize = sci_port->params->fifosize; 2953 2954 if (port->type == PORT_SCI) { 2955 if (sci_port->reg_size >= 0x20) 2956 port->regshift = 2; 2957 else 2958 port->regshift = 1; 2959 } 2960 2961 /* 2962 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2963 * for the multi-IRQ ports, which is where we are primarily 2964 * concerned with the shutdown path synchronization. 2965 * 2966 * For the muxed case there's nothing more to do. 2967 */ 2968 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2969 port->irqflags = 0; 2970 2971 port->serial_in = sci_serial_in; 2972 port->serial_out = sci_serial_out; 2973 2974 return 0; 2975 } 2976 2977 static void sci_cleanup_single(struct sci_port *port) 2978 { 2979 pm_runtime_disable(port->port.dev); 2980 } 2981 2982 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2983 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2984 static void serial_console_putchar(struct uart_port *port, int ch) 2985 { 2986 sci_poll_put_char(port, ch); 2987 } 2988 2989 /* 2990 * Print a string to the serial port trying not to disturb 2991 * any possible real use of the port... 2992 */ 2993 static void serial_console_write(struct console *co, const char *s, 2994 unsigned count) 2995 { 2996 struct sci_port *sci_port = &sci_ports[co->index]; 2997 struct uart_port *port = &sci_port->port; 2998 unsigned short bits, ctrl, ctrl_temp; 2999 unsigned long flags; 3000 int locked = 1; 3001 3002 if (port->sysrq) 3003 locked = 0; 3004 else if (oops_in_progress) 3005 locked = spin_trylock_irqsave(&port->lock, flags); 3006 else 3007 spin_lock_irqsave(&port->lock, flags); 3008 3009 /* first save SCSCR then disable interrupts, keep clock source */ 3010 ctrl = serial_port_in(port, SCSCR); 3011 ctrl_temp = SCSCR_RE | SCSCR_TE | 3012 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3013 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3014 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3015 3016 uart_console_write(port, s, count, serial_console_putchar); 3017 3018 /* wait until fifo is empty and last bit has been transmitted */ 3019 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3020 while ((serial_port_in(port, SCxSR) & bits) != bits) 3021 cpu_relax(); 3022 3023 /* restore the SCSCR */ 3024 serial_port_out(port, SCSCR, ctrl); 3025 3026 if (locked) 3027 spin_unlock_irqrestore(&port->lock, flags); 3028 } 3029 3030 static int serial_console_setup(struct console *co, char *options) 3031 { 3032 struct sci_port *sci_port; 3033 struct uart_port *port; 3034 int baud = 115200; 3035 int bits = 8; 3036 int parity = 'n'; 3037 int flow = 'n'; 3038 int ret; 3039 3040 /* 3041 * Refuse to handle any bogus ports. 3042 */ 3043 if (co->index < 0 || co->index >= SCI_NPORTS) 3044 return -ENODEV; 3045 3046 sci_port = &sci_ports[co->index]; 3047 port = &sci_port->port; 3048 3049 /* 3050 * Refuse to handle uninitialized ports. 3051 */ 3052 if (!port->ops) 3053 return -ENODEV; 3054 3055 ret = sci_remap_port(port); 3056 if (unlikely(ret != 0)) 3057 return ret; 3058 3059 if (options) 3060 uart_parse_options(options, &baud, &parity, &bits, &flow); 3061 3062 return uart_set_options(port, co, baud, parity, bits, flow); 3063 } 3064 3065 static struct console serial_console = { 3066 .name = "ttySC", 3067 .device = uart_console_device, 3068 .write = serial_console_write, 3069 .setup = serial_console_setup, 3070 .flags = CON_PRINTBUFFER, 3071 .index = -1, 3072 .data = &sci_uart_driver, 3073 }; 3074 3075 #ifdef CONFIG_SUPERH 3076 static struct console early_serial_console = { 3077 .name = "early_ttySC", 3078 .write = serial_console_write, 3079 .flags = CON_PRINTBUFFER, 3080 .index = -1, 3081 }; 3082 3083 static char early_serial_buf[32]; 3084 3085 static int sci_probe_earlyprintk(struct platform_device *pdev) 3086 { 3087 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3088 3089 if (early_serial_console.data) 3090 return -EEXIST; 3091 3092 early_serial_console.index = pdev->id; 3093 3094 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3095 3096 serial_console_setup(&early_serial_console, early_serial_buf); 3097 3098 if (!strstr(early_serial_buf, "keep")) 3099 early_serial_console.flags |= CON_BOOT; 3100 3101 register_console(&early_serial_console); 3102 return 0; 3103 } 3104 #endif 3105 3106 #define SCI_CONSOLE (&serial_console) 3107 3108 #else 3109 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3110 { 3111 return -EINVAL; 3112 } 3113 3114 #define SCI_CONSOLE NULL 3115 3116 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3117 3118 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3119 3120 static DEFINE_MUTEX(sci_uart_registration_lock); 3121 static struct uart_driver sci_uart_driver = { 3122 .owner = THIS_MODULE, 3123 .driver_name = "sci", 3124 .dev_name = "ttySC", 3125 .major = SCI_MAJOR, 3126 .minor = SCI_MINOR_START, 3127 .nr = SCI_NPORTS, 3128 .cons = SCI_CONSOLE, 3129 }; 3130 3131 static int sci_remove(struct platform_device *dev) 3132 { 3133 struct sci_port *port = platform_get_drvdata(dev); 3134 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3135 3136 sci_ports_in_use &= ~BIT(port->port.line); 3137 uart_remove_one_port(&sci_uart_driver, &port->port); 3138 3139 sci_cleanup_single(port); 3140 3141 if (port->port.fifosize > 1) 3142 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3143 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3144 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3145 3146 return 0; 3147 } 3148 3149 3150 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3151 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3152 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3153 3154 static const struct of_device_id of_sci_match[] = { 3155 /* SoC-specific types */ 3156 { 3157 .compatible = "renesas,scif-r7s72100", 3158 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3159 }, 3160 { 3161 .compatible = "renesas,scif-r7s9210", 3162 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3163 }, 3164 { 3165 .compatible = "renesas,scif-r9a07g044", 3166 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3167 }, 3168 /* Family-specific types */ 3169 { 3170 .compatible = "renesas,rcar-gen1-scif", 3171 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3172 }, { 3173 .compatible = "renesas,rcar-gen2-scif", 3174 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3175 }, { 3176 .compatible = "renesas,rcar-gen3-scif", 3177 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3178 }, 3179 /* Generic types */ 3180 { 3181 .compatible = "renesas,scif", 3182 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3183 }, { 3184 .compatible = "renesas,scifa", 3185 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3186 }, { 3187 .compatible = "renesas,scifb", 3188 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3189 }, { 3190 .compatible = "renesas,hscif", 3191 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3192 }, { 3193 .compatible = "renesas,sci", 3194 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3195 }, { 3196 /* Terminator */ 3197 }, 3198 }; 3199 MODULE_DEVICE_TABLE(of, of_sci_match); 3200 3201 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3202 unsigned int *dev_id) 3203 { 3204 struct device_node *np = pdev->dev.of_node; 3205 struct plat_sci_port *p; 3206 struct sci_port *sp; 3207 const void *data; 3208 int id; 3209 3210 if (!IS_ENABLED(CONFIG_OF) || !np) 3211 return NULL; 3212 3213 data = of_device_get_match_data(&pdev->dev); 3214 3215 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3216 if (!p) 3217 return NULL; 3218 3219 /* Get the line number from the aliases node. */ 3220 id = of_alias_get_id(np, "serial"); 3221 if (id < 0 && ~sci_ports_in_use) 3222 id = ffz(sci_ports_in_use); 3223 if (id < 0) { 3224 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3225 return NULL; 3226 } 3227 if (id >= ARRAY_SIZE(sci_ports)) { 3228 dev_err(&pdev->dev, "serial%d out of range\n", id); 3229 return NULL; 3230 } 3231 3232 sp = &sci_ports[id]; 3233 *dev_id = id; 3234 3235 p->type = SCI_OF_TYPE(data); 3236 p->regtype = SCI_OF_REGTYPE(data); 3237 3238 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3239 3240 return p; 3241 } 3242 3243 static int sci_probe_single(struct platform_device *dev, 3244 unsigned int index, 3245 struct plat_sci_port *p, 3246 struct sci_port *sciport) 3247 { 3248 int ret; 3249 3250 /* Sanity check */ 3251 if (unlikely(index >= SCI_NPORTS)) { 3252 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3253 index+1, SCI_NPORTS); 3254 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3255 return -EINVAL; 3256 } 3257 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3258 if (sci_ports_in_use & BIT(index)) 3259 return -EBUSY; 3260 3261 mutex_lock(&sci_uart_registration_lock); 3262 if (!sci_uart_driver.state) { 3263 ret = uart_register_driver(&sci_uart_driver); 3264 if (ret) { 3265 mutex_unlock(&sci_uart_registration_lock); 3266 return ret; 3267 } 3268 } 3269 mutex_unlock(&sci_uart_registration_lock); 3270 3271 ret = sci_init_single(dev, sciport, index, p, false); 3272 if (ret) 3273 return ret; 3274 3275 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3276 if (IS_ERR(sciport->gpios)) 3277 return PTR_ERR(sciport->gpios); 3278 3279 if (sciport->has_rtscts) { 3280 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3281 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3282 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3283 return -EINVAL; 3284 } 3285 sciport->port.flags |= UPF_HARD_FLOW; 3286 } 3287 3288 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3289 if (ret) { 3290 sci_cleanup_single(sciport); 3291 return ret; 3292 } 3293 3294 return 0; 3295 } 3296 3297 static int sci_probe(struct platform_device *dev) 3298 { 3299 struct plat_sci_port *p; 3300 struct sci_port *sp; 3301 unsigned int dev_id; 3302 int ret; 3303 3304 /* 3305 * If we've come here via earlyprintk initialization, head off to 3306 * the special early probe. We don't have sufficient device state 3307 * to make it beyond this yet. 3308 */ 3309 #ifdef CONFIG_SUPERH 3310 if (is_sh_early_platform_device(dev)) 3311 return sci_probe_earlyprintk(dev); 3312 #endif 3313 3314 if (dev->dev.of_node) { 3315 p = sci_parse_dt(dev, &dev_id); 3316 if (p == NULL) 3317 return -EINVAL; 3318 } else { 3319 p = dev->dev.platform_data; 3320 if (p == NULL) { 3321 dev_err(&dev->dev, "no platform data supplied\n"); 3322 return -EINVAL; 3323 } 3324 3325 dev_id = dev->id; 3326 } 3327 3328 sp = &sci_ports[dev_id]; 3329 platform_set_drvdata(dev, sp); 3330 3331 ret = sci_probe_single(dev, dev_id, p, sp); 3332 if (ret) 3333 return ret; 3334 3335 if (sp->port.fifosize > 1) { 3336 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3337 if (ret) 3338 return ret; 3339 } 3340 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3341 sp->port.type == PORT_HSCIF) { 3342 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3343 if (ret) { 3344 if (sp->port.fifosize > 1) { 3345 device_remove_file(&dev->dev, 3346 &dev_attr_rx_fifo_trigger); 3347 } 3348 return ret; 3349 } 3350 } 3351 3352 #ifdef CONFIG_SH_STANDARD_BIOS 3353 sh_bios_gdb_detach(); 3354 #endif 3355 3356 sci_ports_in_use |= BIT(dev_id); 3357 return 0; 3358 } 3359 3360 static __maybe_unused int sci_suspend(struct device *dev) 3361 { 3362 struct sci_port *sport = dev_get_drvdata(dev); 3363 3364 if (sport) 3365 uart_suspend_port(&sci_uart_driver, &sport->port); 3366 3367 return 0; 3368 } 3369 3370 static __maybe_unused int sci_resume(struct device *dev) 3371 { 3372 struct sci_port *sport = dev_get_drvdata(dev); 3373 3374 if (sport) 3375 uart_resume_port(&sci_uart_driver, &sport->port); 3376 3377 return 0; 3378 } 3379 3380 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3381 3382 static struct platform_driver sci_driver = { 3383 .probe = sci_probe, 3384 .remove = sci_remove, 3385 .driver = { 3386 .name = "sh-sci", 3387 .pm = &sci_dev_pm_ops, 3388 .of_match_table = of_match_ptr(of_sci_match), 3389 }, 3390 }; 3391 3392 static int __init sci_init(void) 3393 { 3394 pr_info("%s\n", banner); 3395 3396 return platform_driver_register(&sci_driver); 3397 } 3398 3399 static void __exit sci_exit(void) 3400 { 3401 platform_driver_unregister(&sci_driver); 3402 3403 if (sci_uart_driver.state) 3404 uart_unregister_driver(&sci_uart_driver); 3405 } 3406 3407 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3408 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3409 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3410 #endif 3411 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3412 static struct plat_sci_port port_cfg __initdata; 3413 3414 static int __init early_console_setup(struct earlycon_device *device, 3415 int type) 3416 { 3417 if (!device->port.membase) 3418 return -ENODEV; 3419 3420 device->port.serial_in = sci_serial_in; 3421 device->port.serial_out = sci_serial_out; 3422 device->port.type = type; 3423 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3424 port_cfg.type = type; 3425 sci_ports[0].cfg = &port_cfg; 3426 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3427 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3428 sci_serial_out(&sci_ports[0].port, SCSCR, 3429 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3430 3431 device->con->write = serial_console_write; 3432 return 0; 3433 } 3434 static int __init sci_early_console_setup(struct earlycon_device *device, 3435 const char *opt) 3436 { 3437 return early_console_setup(device, PORT_SCI); 3438 } 3439 static int __init scif_early_console_setup(struct earlycon_device *device, 3440 const char *opt) 3441 { 3442 return early_console_setup(device, PORT_SCIF); 3443 } 3444 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3445 const char *opt) 3446 { 3447 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3448 return early_console_setup(device, PORT_SCIF); 3449 } 3450 3451 static int __init scifa_early_console_setup(struct earlycon_device *device, 3452 const char *opt) 3453 { 3454 return early_console_setup(device, PORT_SCIFA); 3455 } 3456 static int __init scifb_early_console_setup(struct earlycon_device *device, 3457 const char *opt) 3458 { 3459 return early_console_setup(device, PORT_SCIFB); 3460 } 3461 static int __init hscif_early_console_setup(struct earlycon_device *device, 3462 const char *opt) 3463 { 3464 return early_console_setup(device, PORT_HSCIF); 3465 } 3466 3467 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3468 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3469 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3470 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3471 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3472 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3473 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3474 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3475 3476 module_init(sci_init); 3477 module_exit(sci_exit); 3478 3479 MODULE_LICENSE("GPL"); 3480 MODULE_ALIAS("platform:sh-sci"); 3481 MODULE_AUTHOR("Paul Mundt"); 3482 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3483