1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/sh_dma.h> 29 #include <linux/timer.h> 30 #include <linux/interrupt.h> 31 #include <linux/tty.h> 32 #include <linux/tty_flip.h> 33 #include <linux/serial.h> 34 #include <linux/major.h> 35 #include <linux/string.h> 36 #include <linux/sysrq.h> 37 #include <linux/ioport.h> 38 #include <linux/mm.h> 39 #include <linux/init.h> 40 #include <linux/delay.h> 41 #include <linux/console.h> 42 #include <linux/platform_device.h> 43 #include <linux/serial_sci.h> 44 #include <linux/notifier.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/cpufreq.h> 47 #include <linux/clk.h> 48 #include <linux/ctype.h> 49 #include <linux/err.h> 50 #include <linux/dmaengine.h> 51 #include <linux/dma-mapping.h> 52 #include <linux/scatterlist.h> 53 #include <linux/slab.h> 54 #include <linux/gpio.h> 55 56 #ifdef CONFIG_SUPERH 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "sh-sci.h" 61 62 struct sci_port { 63 struct uart_port port; 64 65 /* Platform configuration */ 66 struct plat_sci_port *cfg; 67 68 /* Break timer */ 69 struct timer_list break_timer; 70 int break_flag; 71 72 /* Interface clock */ 73 struct clk *iclk; 74 /* Function clock */ 75 struct clk *fclk; 76 77 char *irqstr[SCIx_NR_IRQS]; 78 char *gpiostr[SCIx_NR_FNS]; 79 80 struct dma_chan *chan_tx; 81 struct dma_chan *chan_rx; 82 83 #ifdef CONFIG_SERIAL_SH_SCI_DMA 84 struct dma_async_tx_descriptor *desc_tx; 85 struct dma_async_tx_descriptor *desc_rx[2]; 86 dma_cookie_t cookie_tx; 87 dma_cookie_t cookie_rx[2]; 88 dma_cookie_t active_rx; 89 struct scatterlist sg_tx; 90 unsigned int sg_len_tx; 91 struct scatterlist sg_rx[2]; 92 size_t buf_len_rx; 93 struct sh_dmae_slave param_tx; 94 struct sh_dmae_slave param_rx; 95 struct work_struct work_tx; 96 struct work_struct work_rx; 97 struct timer_list rx_timer; 98 unsigned int rx_timeout; 99 #endif 100 101 struct notifier_block freq_transition; 102 103 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 104 unsigned short saved_smr; 105 unsigned short saved_fcr; 106 unsigned char saved_brr; 107 #endif 108 }; 109 110 /* Function prototypes */ 111 static void sci_start_tx(struct uart_port *port); 112 static void sci_stop_tx(struct uart_port *port); 113 static void sci_start_rx(struct uart_port *port); 114 115 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 116 117 static struct sci_port sci_ports[SCI_NPORTS]; 118 static struct uart_driver sci_uart_driver; 119 120 static inline struct sci_port * 121 to_sci_port(struct uart_port *uart) 122 { 123 return container_of(uart, struct sci_port, port); 124 } 125 126 struct plat_sci_reg { 127 u8 offset, size; 128 }; 129 130 /* Helper for invalidating specific entries of an inherited map. */ 131 #define sci_reg_invalid { .offset = 0, .size = 0 } 132 133 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 134 [SCIx_PROBE_REGTYPE] = { 135 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 136 }, 137 138 /* 139 * Common SCI definitions, dependent on the port's regshift 140 * value. 141 */ 142 [SCIx_SCI_REGTYPE] = { 143 [SCSMR] = { 0x00, 8 }, 144 [SCBRR] = { 0x01, 8 }, 145 [SCSCR] = { 0x02, 8 }, 146 [SCxTDR] = { 0x03, 8 }, 147 [SCxSR] = { 0x04, 8 }, 148 [SCxRDR] = { 0x05, 8 }, 149 [SCFCR] = sci_reg_invalid, 150 [SCFDR] = sci_reg_invalid, 151 [SCTFDR] = sci_reg_invalid, 152 [SCRFDR] = sci_reg_invalid, 153 [SCSPTR] = sci_reg_invalid, 154 [SCLSR] = sci_reg_invalid, 155 }, 156 157 /* 158 * Common definitions for legacy IrDA ports, dependent on 159 * regshift value. 160 */ 161 [SCIx_IRDA_REGTYPE] = { 162 [SCSMR] = { 0x00, 8 }, 163 [SCBRR] = { 0x01, 8 }, 164 [SCSCR] = { 0x02, 8 }, 165 [SCxTDR] = { 0x03, 8 }, 166 [SCxSR] = { 0x04, 8 }, 167 [SCxRDR] = { 0x05, 8 }, 168 [SCFCR] = { 0x06, 8 }, 169 [SCFDR] = { 0x07, 16 }, 170 [SCTFDR] = sci_reg_invalid, 171 [SCRFDR] = sci_reg_invalid, 172 [SCSPTR] = sci_reg_invalid, 173 [SCLSR] = sci_reg_invalid, 174 }, 175 176 /* 177 * Common SCIFA definitions. 178 */ 179 [SCIx_SCIFA_REGTYPE] = { 180 [SCSMR] = { 0x00, 16 }, 181 [SCBRR] = { 0x04, 8 }, 182 [SCSCR] = { 0x08, 16 }, 183 [SCxTDR] = { 0x20, 8 }, 184 [SCxSR] = { 0x14, 16 }, 185 [SCxRDR] = { 0x24, 8 }, 186 [SCFCR] = { 0x18, 16 }, 187 [SCFDR] = { 0x1c, 16 }, 188 [SCTFDR] = sci_reg_invalid, 189 [SCRFDR] = sci_reg_invalid, 190 [SCSPTR] = sci_reg_invalid, 191 [SCLSR] = sci_reg_invalid, 192 }, 193 194 /* 195 * Common SCIFB definitions. 196 */ 197 [SCIx_SCIFB_REGTYPE] = { 198 [SCSMR] = { 0x00, 16 }, 199 [SCBRR] = { 0x04, 8 }, 200 [SCSCR] = { 0x08, 16 }, 201 [SCxTDR] = { 0x40, 8 }, 202 [SCxSR] = { 0x14, 16 }, 203 [SCxRDR] = { 0x60, 8 }, 204 [SCFCR] = { 0x18, 16 }, 205 [SCFDR] = { 0x1c, 16 }, 206 [SCTFDR] = sci_reg_invalid, 207 [SCRFDR] = sci_reg_invalid, 208 [SCSPTR] = sci_reg_invalid, 209 [SCLSR] = sci_reg_invalid, 210 }, 211 212 /* 213 * Common SH-2(A) SCIF definitions for ports with FIFO data 214 * count registers. 215 */ 216 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 217 [SCSMR] = { 0x00, 16 }, 218 [SCBRR] = { 0x04, 8 }, 219 [SCSCR] = { 0x08, 16 }, 220 [SCxTDR] = { 0x0c, 8 }, 221 [SCxSR] = { 0x10, 16 }, 222 [SCxRDR] = { 0x14, 8 }, 223 [SCFCR] = { 0x18, 16 }, 224 [SCFDR] = { 0x1c, 16 }, 225 [SCTFDR] = sci_reg_invalid, 226 [SCRFDR] = sci_reg_invalid, 227 [SCSPTR] = { 0x20, 16 }, 228 [SCLSR] = { 0x24, 16 }, 229 }, 230 231 /* 232 * Common SH-3 SCIF definitions. 233 */ 234 [SCIx_SH3_SCIF_REGTYPE] = { 235 [SCSMR] = { 0x00, 8 }, 236 [SCBRR] = { 0x02, 8 }, 237 [SCSCR] = { 0x04, 8 }, 238 [SCxTDR] = { 0x06, 8 }, 239 [SCxSR] = { 0x08, 16 }, 240 [SCxRDR] = { 0x0a, 8 }, 241 [SCFCR] = { 0x0c, 8 }, 242 [SCFDR] = { 0x0e, 16 }, 243 [SCTFDR] = sci_reg_invalid, 244 [SCRFDR] = sci_reg_invalid, 245 [SCSPTR] = sci_reg_invalid, 246 [SCLSR] = sci_reg_invalid, 247 }, 248 249 /* 250 * Common SH-4(A) SCIF(B) definitions. 251 */ 252 [SCIx_SH4_SCIF_REGTYPE] = { 253 [SCSMR] = { 0x00, 16 }, 254 [SCBRR] = { 0x04, 8 }, 255 [SCSCR] = { 0x08, 16 }, 256 [SCxTDR] = { 0x0c, 8 }, 257 [SCxSR] = { 0x10, 16 }, 258 [SCxRDR] = { 0x14, 8 }, 259 [SCFCR] = { 0x18, 16 }, 260 [SCFDR] = { 0x1c, 16 }, 261 [SCTFDR] = sci_reg_invalid, 262 [SCRFDR] = sci_reg_invalid, 263 [SCSPTR] = { 0x20, 16 }, 264 [SCLSR] = { 0x24, 16 }, 265 }, 266 267 /* 268 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 269 * register. 270 */ 271 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 272 [SCSMR] = { 0x00, 16 }, 273 [SCBRR] = { 0x04, 8 }, 274 [SCSCR] = { 0x08, 16 }, 275 [SCxTDR] = { 0x0c, 8 }, 276 [SCxSR] = { 0x10, 16 }, 277 [SCxRDR] = { 0x14, 8 }, 278 [SCFCR] = { 0x18, 16 }, 279 [SCFDR] = { 0x1c, 16 }, 280 [SCTFDR] = sci_reg_invalid, 281 [SCRFDR] = sci_reg_invalid, 282 [SCSPTR] = sci_reg_invalid, 283 [SCLSR] = { 0x24, 16 }, 284 }, 285 286 /* 287 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 288 * count registers. 289 */ 290 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 291 [SCSMR] = { 0x00, 16 }, 292 [SCBRR] = { 0x04, 8 }, 293 [SCSCR] = { 0x08, 16 }, 294 [SCxTDR] = { 0x0c, 8 }, 295 [SCxSR] = { 0x10, 16 }, 296 [SCxRDR] = { 0x14, 8 }, 297 [SCFCR] = { 0x18, 16 }, 298 [SCFDR] = { 0x1c, 16 }, 299 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 300 [SCRFDR] = { 0x20, 16 }, 301 [SCSPTR] = { 0x24, 16 }, 302 [SCLSR] = { 0x28, 16 }, 303 }, 304 305 /* 306 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 307 * registers. 308 */ 309 [SCIx_SH7705_SCIF_REGTYPE] = { 310 [SCSMR] = { 0x00, 16 }, 311 [SCBRR] = { 0x04, 8 }, 312 [SCSCR] = { 0x08, 16 }, 313 [SCxTDR] = { 0x20, 8 }, 314 [SCxSR] = { 0x14, 16 }, 315 [SCxRDR] = { 0x24, 8 }, 316 [SCFCR] = { 0x18, 16 }, 317 [SCFDR] = { 0x1c, 16 }, 318 [SCTFDR] = sci_reg_invalid, 319 [SCRFDR] = sci_reg_invalid, 320 [SCSPTR] = sci_reg_invalid, 321 [SCLSR] = sci_reg_invalid, 322 }, 323 }; 324 325 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 326 327 /* 328 * The "offset" here is rather misleading, in that it refers to an enum 329 * value relative to the port mapping rather than the fixed offset 330 * itself, which needs to be manually retrieved from the platform's 331 * register map for the given port. 332 */ 333 static unsigned int sci_serial_in(struct uart_port *p, int offset) 334 { 335 struct plat_sci_reg *reg = sci_getreg(p, offset); 336 337 if (reg->size == 8) 338 return ioread8(p->membase + (reg->offset << p->regshift)); 339 else if (reg->size == 16) 340 return ioread16(p->membase + (reg->offset << p->regshift)); 341 else 342 WARN(1, "Invalid register access\n"); 343 344 return 0; 345 } 346 347 static void sci_serial_out(struct uart_port *p, int offset, int value) 348 { 349 struct plat_sci_reg *reg = sci_getreg(p, offset); 350 351 if (reg->size == 8) 352 iowrite8(value, p->membase + (reg->offset << p->regshift)); 353 else if (reg->size == 16) 354 iowrite16(value, p->membase + (reg->offset << p->regshift)); 355 else 356 WARN(1, "Invalid register access\n"); 357 } 358 359 static int sci_probe_regmap(struct plat_sci_port *cfg) 360 { 361 switch (cfg->type) { 362 case PORT_SCI: 363 cfg->regtype = SCIx_SCI_REGTYPE; 364 break; 365 case PORT_IRDA: 366 cfg->regtype = SCIx_IRDA_REGTYPE; 367 break; 368 case PORT_SCIFA: 369 cfg->regtype = SCIx_SCIFA_REGTYPE; 370 break; 371 case PORT_SCIFB: 372 cfg->regtype = SCIx_SCIFB_REGTYPE; 373 break; 374 case PORT_SCIF: 375 /* 376 * The SH-4 is a bit of a misnomer here, although that's 377 * where this particular port layout originated. This 378 * configuration (or some slight variation thereof) 379 * remains the dominant model for all SCIFs. 380 */ 381 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 382 break; 383 default: 384 printk(KERN_ERR "Can't probe register map for given port\n"); 385 return -EINVAL; 386 } 387 388 return 0; 389 } 390 391 static void sci_port_enable(struct sci_port *sci_port) 392 { 393 if (!sci_port->port.dev) 394 return; 395 396 pm_runtime_get_sync(sci_port->port.dev); 397 398 clk_enable(sci_port->iclk); 399 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 400 clk_enable(sci_port->fclk); 401 } 402 403 static void sci_port_disable(struct sci_port *sci_port) 404 { 405 if (!sci_port->port.dev) 406 return; 407 408 clk_disable(sci_port->fclk); 409 clk_disable(sci_port->iclk); 410 411 pm_runtime_put_sync(sci_port->port.dev); 412 } 413 414 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 415 416 #ifdef CONFIG_CONSOLE_POLL 417 static int sci_poll_get_char(struct uart_port *port) 418 { 419 unsigned short status; 420 int c; 421 422 do { 423 status = serial_port_in(port, SCxSR); 424 if (status & SCxSR_ERRORS(port)) { 425 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 426 continue; 427 } 428 break; 429 } while (1); 430 431 if (!(status & SCxSR_RDxF(port))) 432 return NO_POLL_CHAR; 433 434 c = serial_port_in(port, SCxRDR); 435 436 /* Dummy read */ 437 serial_port_in(port, SCxSR); 438 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 439 440 return c; 441 } 442 #endif 443 444 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 445 { 446 unsigned short status; 447 448 do { 449 status = serial_port_in(port, SCxSR); 450 } while (!(status & SCxSR_TDxE(port))); 451 452 serial_port_out(port, SCxTDR, c); 453 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 454 } 455 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 456 457 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 458 { 459 struct sci_port *s = to_sci_port(port); 460 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 461 462 /* 463 * Use port-specific handler if provided. 464 */ 465 if (s->cfg->ops && s->cfg->ops->init_pins) { 466 s->cfg->ops->init_pins(port, cflag); 467 return; 468 } 469 470 /* 471 * For the generic path SCSPTR is necessary. Bail out if that's 472 * unavailable, too. 473 */ 474 if (!reg->size) 475 return; 476 477 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && 478 ((!(cflag & CRTSCTS)))) { 479 unsigned short status; 480 481 status = serial_port_in(port, SCSPTR); 482 status &= ~SCSPTR_CTSIO; 483 status |= SCSPTR_RTSIO; 484 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ 485 } 486 } 487 488 static int sci_txfill(struct uart_port *port) 489 { 490 struct plat_sci_reg *reg; 491 492 reg = sci_getreg(port, SCTFDR); 493 if (reg->size) 494 return serial_port_in(port, SCTFDR) & 0xff; 495 496 reg = sci_getreg(port, SCFDR); 497 if (reg->size) 498 return serial_port_in(port, SCFDR) >> 8; 499 500 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 501 } 502 503 static int sci_txroom(struct uart_port *port) 504 { 505 return port->fifosize - sci_txfill(port); 506 } 507 508 static int sci_rxfill(struct uart_port *port) 509 { 510 struct plat_sci_reg *reg; 511 512 reg = sci_getreg(port, SCRFDR); 513 if (reg->size) 514 return serial_port_in(port, SCRFDR) & 0xff; 515 516 reg = sci_getreg(port, SCFDR); 517 if (reg->size) 518 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); 519 520 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 521 } 522 523 /* 524 * SCI helper for checking the state of the muxed port/RXD pins. 525 */ 526 static inline int sci_rxd_in(struct uart_port *port) 527 { 528 struct sci_port *s = to_sci_port(port); 529 530 if (s->cfg->port_reg <= 0) 531 return 1; 532 533 /* Cast for ARM damage */ 534 return !!__raw_readb((void __iomem *)s->cfg->port_reg); 535 } 536 537 /* ********************************************************************** * 538 * the interrupt related routines * 539 * ********************************************************************** */ 540 541 static void sci_transmit_chars(struct uart_port *port) 542 { 543 struct circ_buf *xmit = &port->state->xmit; 544 unsigned int stopped = uart_tx_stopped(port); 545 unsigned short status; 546 unsigned short ctrl; 547 int count; 548 549 status = serial_port_in(port, SCxSR); 550 if (!(status & SCxSR_TDxE(port))) { 551 ctrl = serial_port_in(port, SCSCR); 552 if (uart_circ_empty(xmit)) 553 ctrl &= ~SCSCR_TIE; 554 else 555 ctrl |= SCSCR_TIE; 556 serial_port_out(port, SCSCR, ctrl); 557 return; 558 } 559 560 count = sci_txroom(port); 561 562 do { 563 unsigned char c; 564 565 if (port->x_char) { 566 c = port->x_char; 567 port->x_char = 0; 568 } else if (!uart_circ_empty(xmit) && !stopped) { 569 c = xmit->buf[xmit->tail]; 570 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 571 } else { 572 break; 573 } 574 575 serial_port_out(port, SCxTDR, c); 576 577 port->icount.tx++; 578 } while (--count > 0); 579 580 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 581 582 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 583 uart_write_wakeup(port); 584 if (uart_circ_empty(xmit)) { 585 sci_stop_tx(port); 586 } else { 587 ctrl = serial_port_in(port, SCSCR); 588 589 if (port->type != PORT_SCI) { 590 serial_port_in(port, SCxSR); /* Dummy read */ 591 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 592 } 593 594 ctrl |= SCSCR_TIE; 595 serial_port_out(port, SCSCR, ctrl); 596 } 597 } 598 599 /* On SH3, SCIF may read end-of-break as a space->mark char */ 600 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 601 602 static void sci_receive_chars(struct uart_port *port) 603 { 604 struct sci_port *sci_port = to_sci_port(port); 605 struct tty_struct *tty = port->state->port.tty; 606 int i, count, copied = 0; 607 unsigned short status; 608 unsigned char flag; 609 610 status = serial_port_in(port, SCxSR); 611 if (!(status & SCxSR_RDxF(port))) 612 return; 613 614 while (1) { 615 /* Don't copy more bytes than there is room for in the buffer */ 616 count = tty_buffer_request_room(tty, sci_rxfill(port)); 617 618 /* If for any reason we can't copy more data, we're done! */ 619 if (count == 0) 620 break; 621 622 if (port->type == PORT_SCI) { 623 char c = serial_port_in(port, SCxRDR); 624 if (uart_handle_sysrq_char(port, c) || 625 sci_port->break_flag) 626 count = 0; 627 else 628 tty_insert_flip_char(tty, c, TTY_NORMAL); 629 } else { 630 for (i = 0; i < count; i++) { 631 char c = serial_port_in(port, SCxRDR); 632 633 status = serial_port_in(port, SCxSR); 634 #if defined(CONFIG_CPU_SH3) 635 /* Skip "chars" during break */ 636 if (sci_port->break_flag) { 637 if ((c == 0) && 638 (status & SCxSR_FER(port))) { 639 count--; i--; 640 continue; 641 } 642 643 /* Nonzero => end-of-break */ 644 dev_dbg(port->dev, "debounce<%02x>\n", c); 645 sci_port->break_flag = 0; 646 647 if (STEPFN(c)) { 648 count--; i--; 649 continue; 650 } 651 } 652 #endif /* CONFIG_CPU_SH3 */ 653 if (uart_handle_sysrq_char(port, c)) { 654 count--; i--; 655 continue; 656 } 657 658 /* Store data and status */ 659 if (status & SCxSR_FER(port)) { 660 flag = TTY_FRAME; 661 port->icount.frame++; 662 dev_notice(port->dev, "frame error\n"); 663 } else if (status & SCxSR_PER(port)) { 664 flag = TTY_PARITY; 665 port->icount.parity++; 666 dev_notice(port->dev, "parity error\n"); 667 } else 668 flag = TTY_NORMAL; 669 670 tty_insert_flip_char(tty, c, flag); 671 } 672 } 673 674 serial_port_in(port, SCxSR); /* dummy read */ 675 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 676 677 copied += count; 678 port->icount.rx += count; 679 } 680 681 if (copied) { 682 /* Tell the rest of the system the news. New characters! */ 683 tty_flip_buffer_push(tty); 684 } else { 685 serial_port_in(port, SCxSR); /* dummy read */ 686 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 687 } 688 } 689 690 #define SCI_BREAK_JIFFIES (HZ/20) 691 692 /* 693 * The sci generates interrupts during the break, 694 * 1 per millisecond or so during the break period, for 9600 baud. 695 * So dont bother disabling interrupts. 696 * But dont want more than 1 break event. 697 * Use a kernel timer to periodically poll the rx line until 698 * the break is finished. 699 */ 700 static inline void sci_schedule_break_timer(struct sci_port *port) 701 { 702 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 703 } 704 705 /* Ensure that two consecutive samples find the break over. */ 706 static void sci_break_timer(unsigned long data) 707 { 708 struct sci_port *port = (struct sci_port *)data; 709 710 sci_port_enable(port); 711 712 if (sci_rxd_in(&port->port) == 0) { 713 port->break_flag = 1; 714 sci_schedule_break_timer(port); 715 } else if (port->break_flag == 1) { 716 /* break is over. */ 717 port->break_flag = 2; 718 sci_schedule_break_timer(port); 719 } else 720 port->break_flag = 0; 721 722 sci_port_disable(port); 723 } 724 725 static int sci_handle_errors(struct uart_port *port) 726 { 727 int copied = 0; 728 unsigned short status = serial_port_in(port, SCxSR); 729 struct tty_struct *tty = port->state->port.tty; 730 struct sci_port *s = to_sci_port(port); 731 732 /* 733 * Handle overruns, if supported. 734 */ 735 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 736 if (status & (1 << s->cfg->overrun_bit)) { 737 port->icount.overrun++; 738 739 /* overrun error */ 740 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 741 copied++; 742 743 dev_notice(port->dev, "overrun error"); 744 } 745 } 746 747 if (status & SCxSR_FER(port)) { 748 if (sci_rxd_in(port) == 0) { 749 /* Notify of BREAK */ 750 struct sci_port *sci_port = to_sci_port(port); 751 752 if (!sci_port->break_flag) { 753 port->icount.brk++; 754 755 sci_port->break_flag = 1; 756 sci_schedule_break_timer(sci_port); 757 758 /* Do sysrq handling. */ 759 if (uart_handle_break(port)) 760 return 0; 761 762 dev_dbg(port->dev, "BREAK detected\n"); 763 764 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 765 copied++; 766 } 767 768 } else { 769 /* frame error */ 770 port->icount.frame++; 771 772 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 773 copied++; 774 775 dev_notice(port->dev, "frame error\n"); 776 } 777 } 778 779 if (status & SCxSR_PER(port)) { 780 /* parity error */ 781 port->icount.parity++; 782 783 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 784 copied++; 785 786 dev_notice(port->dev, "parity error"); 787 } 788 789 if (copied) 790 tty_flip_buffer_push(tty); 791 792 return copied; 793 } 794 795 static int sci_handle_fifo_overrun(struct uart_port *port) 796 { 797 struct tty_struct *tty = port->state->port.tty; 798 struct sci_port *s = to_sci_port(port); 799 struct plat_sci_reg *reg; 800 int copied = 0; 801 802 reg = sci_getreg(port, SCLSR); 803 if (!reg->size) 804 return 0; 805 806 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 807 serial_port_out(port, SCLSR, 0); 808 809 port->icount.overrun++; 810 811 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 812 tty_flip_buffer_push(tty); 813 814 dev_notice(port->dev, "overrun error\n"); 815 copied++; 816 } 817 818 return copied; 819 } 820 821 static int sci_handle_breaks(struct uart_port *port) 822 { 823 int copied = 0; 824 unsigned short status = serial_port_in(port, SCxSR); 825 struct tty_struct *tty = port->state->port.tty; 826 struct sci_port *s = to_sci_port(port); 827 828 if (uart_handle_break(port)) 829 return 0; 830 831 if (!s->break_flag && status & SCxSR_BRK(port)) { 832 #if defined(CONFIG_CPU_SH3) 833 /* Debounce break */ 834 s->break_flag = 1; 835 #endif 836 837 port->icount.brk++; 838 839 /* Notify of BREAK */ 840 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 841 copied++; 842 843 dev_dbg(port->dev, "BREAK detected\n"); 844 } 845 846 if (copied) 847 tty_flip_buffer_push(tty); 848 849 copied += sci_handle_fifo_overrun(port); 850 851 return copied; 852 } 853 854 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 855 { 856 #ifdef CONFIG_SERIAL_SH_SCI_DMA 857 struct uart_port *port = ptr; 858 struct sci_port *s = to_sci_port(port); 859 860 if (s->chan_rx) { 861 u16 scr = serial_port_in(port, SCSCR); 862 u16 ssr = serial_port_in(port, SCxSR); 863 864 /* Disable future Rx interrupts */ 865 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 866 disable_irq_nosync(irq); 867 scr |= 0x4000; 868 } else { 869 scr &= ~SCSCR_RIE; 870 } 871 serial_port_out(port, SCSCR, scr); 872 /* Clear current interrupt */ 873 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 874 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 875 jiffies, s->rx_timeout); 876 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 877 878 return IRQ_HANDLED; 879 } 880 #endif 881 882 /* I think sci_receive_chars has to be called irrespective 883 * of whether the I_IXOFF is set, otherwise, how is the interrupt 884 * to be disabled? 885 */ 886 sci_receive_chars(ptr); 887 888 return IRQ_HANDLED; 889 } 890 891 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 892 { 893 struct uart_port *port = ptr; 894 unsigned long flags; 895 896 spin_lock_irqsave(&port->lock, flags); 897 sci_transmit_chars(port); 898 spin_unlock_irqrestore(&port->lock, flags); 899 900 return IRQ_HANDLED; 901 } 902 903 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 904 { 905 struct uart_port *port = ptr; 906 907 /* Handle errors */ 908 if (port->type == PORT_SCI) { 909 if (sci_handle_errors(port)) { 910 /* discard character in rx buffer */ 911 serial_port_in(port, SCxSR); 912 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 913 } 914 } else { 915 sci_handle_fifo_overrun(port); 916 sci_rx_interrupt(irq, ptr); 917 } 918 919 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 920 921 /* Kick the transmission */ 922 sci_tx_interrupt(irq, ptr); 923 924 return IRQ_HANDLED; 925 } 926 927 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 928 { 929 struct uart_port *port = ptr; 930 931 /* Handle BREAKs */ 932 sci_handle_breaks(port); 933 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 934 935 return IRQ_HANDLED; 936 } 937 938 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 939 { 940 /* 941 * Not all ports (such as SCIFA) will support REIE. Rather than 942 * special-casing the port type, we check the port initialization 943 * IRQ enable mask to see whether the IRQ is desired at all. If 944 * it's unset, it's logically inferred that there's no point in 945 * testing for it. 946 */ 947 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 948 } 949 950 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 951 { 952 unsigned short ssr_status, scr_status, err_enabled; 953 struct uart_port *port = ptr; 954 struct sci_port *s = to_sci_port(port); 955 irqreturn_t ret = IRQ_NONE; 956 957 ssr_status = serial_port_in(port, SCxSR); 958 scr_status = serial_port_in(port, SCSCR); 959 err_enabled = scr_status & port_rx_irq_mask(port); 960 961 /* Tx Interrupt */ 962 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 963 !s->chan_tx) 964 ret = sci_tx_interrupt(irq, ptr); 965 966 /* 967 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 968 * DR flags 969 */ 970 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 971 (scr_status & SCSCR_RIE)) 972 ret = sci_rx_interrupt(irq, ptr); 973 974 /* Error Interrupt */ 975 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 976 ret = sci_er_interrupt(irq, ptr); 977 978 /* Break Interrupt */ 979 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 980 ret = sci_br_interrupt(irq, ptr); 981 982 return ret; 983 } 984 985 /* 986 * Here we define a transition notifier so that we can update all of our 987 * ports' baud rate when the peripheral clock changes. 988 */ 989 static int sci_notifier(struct notifier_block *self, 990 unsigned long phase, void *p) 991 { 992 struct sci_port *sci_port; 993 unsigned long flags; 994 995 sci_port = container_of(self, struct sci_port, freq_transition); 996 997 if ((phase == CPUFREQ_POSTCHANGE) || 998 (phase == CPUFREQ_RESUMECHANGE)) { 999 struct uart_port *port = &sci_port->port; 1000 1001 spin_lock_irqsave(&port->lock, flags); 1002 port->uartclk = clk_get_rate(sci_port->iclk); 1003 spin_unlock_irqrestore(&port->lock, flags); 1004 } 1005 1006 return NOTIFY_OK; 1007 } 1008 1009 static struct sci_irq_desc { 1010 const char *desc; 1011 irq_handler_t handler; 1012 } sci_irq_desc[] = { 1013 /* 1014 * Split out handlers, the default case. 1015 */ 1016 [SCIx_ERI_IRQ] = { 1017 .desc = "rx err", 1018 .handler = sci_er_interrupt, 1019 }, 1020 1021 [SCIx_RXI_IRQ] = { 1022 .desc = "rx full", 1023 .handler = sci_rx_interrupt, 1024 }, 1025 1026 [SCIx_TXI_IRQ] = { 1027 .desc = "tx empty", 1028 .handler = sci_tx_interrupt, 1029 }, 1030 1031 [SCIx_BRI_IRQ] = { 1032 .desc = "break", 1033 .handler = sci_br_interrupt, 1034 }, 1035 1036 /* 1037 * Special muxed handler. 1038 */ 1039 [SCIx_MUX_IRQ] = { 1040 .desc = "mux", 1041 .handler = sci_mpxed_interrupt, 1042 }, 1043 }; 1044 1045 static int sci_request_irq(struct sci_port *port) 1046 { 1047 struct uart_port *up = &port->port; 1048 int i, j, ret = 0; 1049 1050 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1051 struct sci_irq_desc *desc; 1052 unsigned int irq; 1053 1054 if (SCIx_IRQ_IS_MUXED(port)) { 1055 i = SCIx_MUX_IRQ; 1056 irq = up->irq; 1057 } else { 1058 irq = port->cfg->irqs[i]; 1059 1060 /* 1061 * Certain port types won't support all of the 1062 * available interrupt sources. 1063 */ 1064 if (unlikely(!irq)) 1065 continue; 1066 } 1067 1068 desc = sci_irq_desc + i; 1069 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1070 dev_name(up->dev), desc->desc); 1071 if (!port->irqstr[j]) { 1072 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1073 desc->desc); 1074 goto out_nomem; 1075 } 1076 1077 ret = request_irq(irq, desc->handler, up->irqflags, 1078 port->irqstr[j], port); 1079 if (unlikely(ret)) { 1080 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1081 goto out_noirq; 1082 } 1083 } 1084 1085 return 0; 1086 1087 out_noirq: 1088 while (--i >= 0) 1089 free_irq(port->cfg->irqs[i], port); 1090 1091 out_nomem: 1092 while (--j >= 0) 1093 kfree(port->irqstr[j]); 1094 1095 return ret; 1096 } 1097 1098 static void sci_free_irq(struct sci_port *port) 1099 { 1100 int i; 1101 1102 /* 1103 * Intentionally in reverse order so we iterate over the muxed 1104 * IRQ first. 1105 */ 1106 for (i = 0; i < SCIx_NR_IRQS; i++) { 1107 unsigned int irq = port->cfg->irqs[i]; 1108 1109 /* 1110 * Certain port types won't support all of the available 1111 * interrupt sources. 1112 */ 1113 if (unlikely(!irq)) 1114 continue; 1115 1116 free_irq(port->cfg->irqs[i], port); 1117 kfree(port->irqstr[i]); 1118 1119 if (SCIx_IRQ_IS_MUXED(port)) { 1120 /* If there's only one IRQ, we're done. */ 1121 return; 1122 } 1123 } 1124 } 1125 1126 static const char *sci_gpio_names[SCIx_NR_FNS] = { 1127 "sck", "rxd", "txd", "cts", "rts", 1128 }; 1129 1130 static const char *sci_gpio_str(unsigned int index) 1131 { 1132 return sci_gpio_names[index]; 1133 } 1134 1135 static void __devinit sci_init_gpios(struct sci_port *port) 1136 { 1137 struct uart_port *up = &port->port; 1138 int i; 1139 1140 if (!port->cfg) 1141 return; 1142 1143 for (i = 0; i < SCIx_NR_FNS; i++) { 1144 const char *desc; 1145 int ret; 1146 1147 if (!port->cfg->gpios[i]) 1148 continue; 1149 1150 desc = sci_gpio_str(i); 1151 1152 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s", 1153 dev_name(up->dev), desc); 1154 1155 /* 1156 * If we've failed the allocation, we can still continue 1157 * on with a NULL string. 1158 */ 1159 if (!port->gpiostr[i]) 1160 dev_notice(up->dev, "%s string allocation failure\n", 1161 desc); 1162 1163 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]); 1164 if (unlikely(ret != 0)) { 1165 dev_notice(up->dev, "failed %s gpio request\n", desc); 1166 1167 /* 1168 * If we can't get the GPIO for whatever reason, 1169 * no point in keeping the verbose string around. 1170 */ 1171 kfree(port->gpiostr[i]); 1172 } 1173 } 1174 } 1175 1176 static void sci_free_gpios(struct sci_port *port) 1177 { 1178 int i; 1179 1180 for (i = 0; i < SCIx_NR_FNS; i++) 1181 if (port->cfg->gpios[i]) { 1182 gpio_free(port->cfg->gpios[i]); 1183 kfree(port->gpiostr[i]); 1184 } 1185 } 1186 1187 static unsigned int sci_tx_empty(struct uart_port *port) 1188 { 1189 unsigned short status = serial_port_in(port, SCxSR); 1190 unsigned short in_tx_fifo = sci_txfill(port); 1191 1192 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1193 } 1194 1195 /* 1196 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1197 * CTS/RTS is supported in hardware by at least one port and controlled 1198 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1199 * handled via the ->init_pins() op, which is a bit of a one-way street, 1200 * lacking any ability to defer pin control -- this will later be 1201 * converted over to the GPIO framework). 1202 * 1203 * Other modes (such as loopback) are supported generically on certain 1204 * port types, but not others. For these it's sufficient to test for the 1205 * existence of the support register and simply ignore the port type. 1206 */ 1207 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1208 { 1209 if (mctrl & TIOCM_LOOP) { 1210 struct plat_sci_reg *reg; 1211 1212 /* 1213 * Standard loopback mode for SCFCR ports. 1214 */ 1215 reg = sci_getreg(port, SCFCR); 1216 if (reg->size) 1217 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1); 1218 } 1219 } 1220 1221 static unsigned int sci_get_mctrl(struct uart_port *port) 1222 { 1223 /* 1224 * CTS/RTS is handled in hardware when supported, while nothing 1225 * else is wired up. Keep it simple and simply assert DSR/CAR. 1226 */ 1227 return TIOCM_DSR | TIOCM_CAR; 1228 } 1229 1230 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1231 static void sci_dma_tx_complete(void *arg) 1232 { 1233 struct sci_port *s = arg; 1234 struct uart_port *port = &s->port; 1235 struct circ_buf *xmit = &port->state->xmit; 1236 unsigned long flags; 1237 1238 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1239 1240 spin_lock_irqsave(&port->lock, flags); 1241 1242 xmit->tail += sg_dma_len(&s->sg_tx); 1243 xmit->tail &= UART_XMIT_SIZE - 1; 1244 1245 port->icount.tx += sg_dma_len(&s->sg_tx); 1246 1247 async_tx_ack(s->desc_tx); 1248 s->desc_tx = NULL; 1249 1250 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1251 uart_write_wakeup(port); 1252 1253 if (!uart_circ_empty(xmit)) { 1254 s->cookie_tx = 0; 1255 schedule_work(&s->work_tx); 1256 } else { 1257 s->cookie_tx = -EINVAL; 1258 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1259 u16 ctrl = serial_port_in(port, SCSCR); 1260 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1261 } 1262 } 1263 1264 spin_unlock_irqrestore(&port->lock, flags); 1265 } 1266 1267 /* Locking: called with port lock held */ 1268 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, 1269 size_t count) 1270 { 1271 struct uart_port *port = &s->port; 1272 int i, active, room; 1273 1274 room = tty_buffer_request_room(tty, count); 1275 1276 if (s->active_rx == s->cookie_rx[0]) { 1277 active = 0; 1278 } else if (s->active_rx == s->cookie_rx[1]) { 1279 active = 1; 1280 } else { 1281 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1282 return 0; 1283 } 1284 1285 if (room < count) 1286 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 1287 count - room); 1288 if (!room) 1289 return room; 1290 1291 for (i = 0; i < room; i++) 1292 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1293 TTY_NORMAL); 1294 1295 port->icount.rx += room; 1296 1297 return room; 1298 } 1299 1300 static void sci_dma_rx_complete(void *arg) 1301 { 1302 struct sci_port *s = arg; 1303 struct uart_port *port = &s->port; 1304 struct tty_struct *tty = port->state->port.tty; 1305 unsigned long flags; 1306 int count; 1307 1308 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1309 1310 spin_lock_irqsave(&port->lock, flags); 1311 1312 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 1313 1314 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1315 1316 spin_unlock_irqrestore(&port->lock, flags); 1317 1318 if (count) 1319 tty_flip_buffer_push(tty); 1320 1321 schedule_work(&s->work_rx); 1322 } 1323 1324 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1325 { 1326 struct dma_chan *chan = s->chan_rx; 1327 struct uart_port *port = &s->port; 1328 1329 s->chan_rx = NULL; 1330 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1331 dma_release_channel(chan); 1332 if (sg_dma_address(&s->sg_rx[0])) 1333 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1334 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1335 if (enable_pio) 1336 sci_start_rx(port); 1337 } 1338 1339 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1340 { 1341 struct dma_chan *chan = s->chan_tx; 1342 struct uart_port *port = &s->port; 1343 1344 s->chan_tx = NULL; 1345 s->cookie_tx = -EINVAL; 1346 dma_release_channel(chan); 1347 if (enable_pio) 1348 sci_start_tx(port); 1349 } 1350 1351 static void sci_submit_rx(struct sci_port *s) 1352 { 1353 struct dma_chan *chan = s->chan_rx; 1354 int i; 1355 1356 for (i = 0; i < 2; i++) { 1357 struct scatterlist *sg = &s->sg_rx[i]; 1358 struct dma_async_tx_descriptor *desc; 1359 1360 desc = dmaengine_prep_slave_sg(chan, 1361 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1362 1363 if (desc) { 1364 s->desc_rx[i] = desc; 1365 desc->callback = sci_dma_rx_complete; 1366 desc->callback_param = s; 1367 s->cookie_rx[i] = desc->tx_submit(desc); 1368 } 1369 1370 if (!desc || s->cookie_rx[i] < 0) { 1371 if (i) { 1372 async_tx_ack(s->desc_rx[0]); 1373 s->cookie_rx[0] = -EINVAL; 1374 } 1375 if (desc) { 1376 async_tx_ack(desc); 1377 s->cookie_rx[i] = -EINVAL; 1378 } 1379 dev_warn(s->port.dev, 1380 "failed to re-start DMA, using PIO\n"); 1381 sci_rx_dma_release(s, true); 1382 return; 1383 } 1384 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1385 s->cookie_rx[i], i); 1386 } 1387 1388 s->active_rx = s->cookie_rx[0]; 1389 1390 dma_async_issue_pending(chan); 1391 } 1392 1393 static void work_fn_rx(struct work_struct *work) 1394 { 1395 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1396 struct uart_port *port = &s->port; 1397 struct dma_async_tx_descriptor *desc; 1398 int new; 1399 1400 if (s->active_rx == s->cookie_rx[0]) { 1401 new = 0; 1402 } else if (s->active_rx == s->cookie_rx[1]) { 1403 new = 1; 1404 } else { 1405 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1406 return; 1407 } 1408 desc = s->desc_rx[new]; 1409 1410 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1411 DMA_SUCCESS) { 1412 /* Handle incomplete DMA receive */ 1413 struct tty_struct *tty = port->state->port.tty; 1414 struct dma_chan *chan = s->chan_rx; 1415 struct shdma_desc *sh_desc = container_of(desc, 1416 struct shdma_desc, async_tx); 1417 unsigned long flags; 1418 int count; 1419 1420 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1421 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1422 sh_desc->partial, sh_desc->cookie); 1423 1424 spin_lock_irqsave(&port->lock, flags); 1425 count = sci_dma_rx_push(s, tty, sh_desc->partial); 1426 spin_unlock_irqrestore(&port->lock, flags); 1427 1428 if (count) 1429 tty_flip_buffer_push(tty); 1430 1431 sci_submit_rx(s); 1432 1433 return; 1434 } 1435 1436 s->cookie_rx[new] = desc->tx_submit(desc); 1437 if (s->cookie_rx[new] < 0) { 1438 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1439 sci_rx_dma_release(s, true); 1440 return; 1441 } 1442 1443 s->active_rx = s->cookie_rx[!new]; 1444 1445 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1446 s->cookie_rx[new], new, s->active_rx); 1447 } 1448 1449 static void work_fn_tx(struct work_struct *work) 1450 { 1451 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1452 struct dma_async_tx_descriptor *desc; 1453 struct dma_chan *chan = s->chan_tx; 1454 struct uart_port *port = &s->port; 1455 struct circ_buf *xmit = &port->state->xmit; 1456 struct scatterlist *sg = &s->sg_tx; 1457 1458 /* 1459 * DMA is idle now. 1460 * Port xmit buffer is already mapped, and it is one page... Just adjust 1461 * offsets and lengths. Since it is a circular buffer, we have to 1462 * transmit till the end, and then the rest. Take the port lock to get a 1463 * consistent xmit buffer state. 1464 */ 1465 spin_lock_irq(&port->lock); 1466 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1467 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1468 sg->offset; 1469 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1470 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1471 spin_unlock_irq(&port->lock); 1472 1473 BUG_ON(!sg_dma_len(sg)); 1474 1475 desc = dmaengine_prep_slave_sg(chan, 1476 sg, s->sg_len_tx, DMA_MEM_TO_DEV, 1477 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1478 if (!desc) { 1479 /* switch to PIO */ 1480 sci_tx_dma_release(s, true); 1481 return; 1482 } 1483 1484 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1485 1486 spin_lock_irq(&port->lock); 1487 s->desc_tx = desc; 1488 desc->callback = sci_dma_tx_complete; 1489 desc->callback_param = s; 1490 spin_unlock_irq(&port->lock); 1491 s->cookie_tx = desc->tx_submit(desc); 1492 if (s->cookie_tx < 0) { 1493 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1494 /* switch to PIO */ 1495 sci_tx_dma_release(s, true); 1496 return; 1497 } 1498 1499 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1500 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1501 1502 dma_async_issue_pending(chan); 1503 } 1504 #endif 1505 1506 static void sci_start_tx(struct uart_port *port) 1507 { 1508 struct sci_port *s = to_sci_port(port); 1509 unsigned short ctrl; 1510 1511 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1512 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1513 u16 new, scr = serial_port_in(port, SCSCR); 1514 if (s->chan_tx) 1515 new = scr | 0x8000; 1516 else 1517 new = scr & ~0x8000; 1518 if (new != scr) 1519 serial_port_out(port, SCSCR, new); 1520 } 1521 1522 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1523 s->cookie_tx < 0) { 1524 s->cookie_tx = 0; 1525 schedule_work(&s->work_tx); 1526 } 1527 #endif 1528 1529 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1530 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1531 ctrl = serial_port_in(port, SCSCR); 1532 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 1533 } 1534 } 1535 1536 static void sci_stop_tx(struct uart_port *port) 1537 { 1538 unsigned short ctrl; 1539 1540 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1541 ctrl = serial_port_in(port, SCSCR); 1542 1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1544 ctrl &= ~0x8000; 1545 1546 ctrl &= ~SCSCR_TIE; 1547 1548 serial_port_out(port, SCSCR, ctrl); 1549 } 1550 1551 static void sci_start_rx(struct uart_port *port) 1552 { 1553 unsigned short ctrl; 1554 1555 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 1556 1557 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1558 ctrl &= ~0x4000; 1559 1560 serial_port_out(port, SCSCR, ctrl); 1561 } 1562 1563 static void sci_stop_rx(struct uart_port *port) 1564 { 1565 unsigned short ctrl; 1566 1567 ctrl = serial_port_in(port, SCSCR); 1568 1569 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1570 ctrl &= ~0x4000; 1571 1572 ctrl &= ~port_rx_irq_mask(port); 1573 1574 serial_port_out(port, SCSCR, ctrl); 1575 } 1576 1577 static void sci_enable_ms(struct uart_port *port) 1578 { 1579 /* 1580 * Not supported by hardware, always a nop. 1581 */ 1582 } 1583 1584 static void sci_break_ctl(struct uart_port *port, int break_state) 1585 { 1586 struct sci_port *s = to_sci_port(port); 1587 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 1588 unsigned short scscr, scsptr; 1589 1590 /* check wheter the port has SCSPTR */ 1591 if (!reg->size) { 1592 /* 1593 * Not supported by hardware. Most parts couple break and rx 1594 * interrupts together, with break detection always enabled. 1595 */ 1596 return; 1597 } 1598 1599 scsptr = serial_port_in(port, SCSPTR); 1600 scscr = serial_port_in(port, SCSCR); 1601 1602 if (break_state == -1) { 1603 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1604 scscr &= ~SCSCR_TE; 1605 } else { 1606 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1607 scscr |= SCSCR_TE; 1608 } 1609 1610 serial_port_out(port, SCSPTR, scsptr); 1611 serial_port_out(port, SCSCR, scscr); 1612 } 1613 1614 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1615 static bool filter(struct dma_chan *chan, void *slave) 1616 { 1617 struct sh_dmae_slave *param = slave; 1618 1619 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1620 param->shdma_slave.slave_id); 1621 1622 chan->private = ¶m->shdma_slave; 1623 return true; 1624 } 1625 1626 static void rx_timer_fn(unsigned long arg) 1627 { 1628 struct sci_port *s = (struct sci_port *)arg; 1629 struct uart_port *port = &s->port; 1630 u16 scr = serial_port_in(port, SCSCR); 1631 1632 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1633 scr &= ~0x4000; 1634 enable_irq(s->cfg->irqs[1]); 1635 } 1636 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1637 dev_dbg(port->dev, "DMA Rx timed out\n"); 1638 schedule_work(&s->work_rx); 1639 } 1640 1641 static void sci_request_dma(struct uart_port *port) 1642 { 1643 struct sci_port *s = to_sci_port(port); 1644 struct sh_dmae_slave *param; 1645 struct dma_chan *chan; 1646 dma_cap_mask_t mask; 1647 int nent; 1648 1649 dev_dbg(port->dev, "%s: port %d\n", __func__, 1650 port->line); 1651 1652 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1653 return; 1654 1655 dma_cap_zero(mask); 1656 dma_cap_set(DMA_SLAVE, mask); 1657 1658 param = &s->param_tx; 1659 1660 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1661 param->shdma_slave.slave_id = s->cfg->dma_slave_tx; 1662 1663 s->cookie_tx = -EINVAL; 1664 chan = dma_request_channel(mask, filter, param); 1665 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1666 if (chan) { 1667 s->chan_tx = chan; 1668 sg_init_table(&s->sg_tx, 1); 1669 /* UART circular tx buffer is an aligned page. */ 1670 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1671 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1672 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1673 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1674 if (!nent) 1675 sci_tx_dma_release(s, false); 1676 else 1677 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1678 sg_dma_len(&s->sg_tx), 1679 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1680 1681 s->sg_len_tx = nent; 1682 1683 INIT_WORK(&s->work_tx, work_fn_tx); 1684 } 1685 1686 param = &s->param_rx; 1687 1688 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1689 param->shdma_slave.slave_id = s->cfg->dma_slave_rx; 1690 1691 chan = dma_request_channel(mask, filter, param); 1692 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1693 if (chan) { 1694 dma_addr_t dma[2]; 1695 void *buf[2]; 1696 int i; 1697 1698 s->chan_rx = chan; 1699 1700 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1701 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1702 &dma[0], GFP_KERNEL); 1703 1704 if (!buf[0]) { 1705 dev_warn(port->dev, 1706 "failed to allocate dma buffer, using PIO\n"); 1707 sci_rx_dma_release(s, true); 1708 return; 1709 } 1710 1711 buf[1] = buf[0] + s->buf_len_rx; 1712 dma[1] = dma[0] + s->buf_len_rx; 1713 1714 for (i = 0; i < 2; i++) { 1715 struct scatterlist *sg = &s->sg_rx[i]; 1716 1717 sg_init_table(sg, 1); 1718 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1719 (int)buf[i] & ~PAGE_MASK); 1720 sg_dma_address(sg) = dma[i]; 1721 } 1722 1723 INIT_WORK(&s->work_rx, work_fn_rx); 1724 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1725 1726 sci_submit_rx(s); 1727 } 1728 } 1729 1730 static void sci_free_dma(struct uart_port *port) 1731 { 1732 struct sci_port *s = to_sci_port(port); 1733 1734 if (s->chan_tx) 1735 sci_tx_dma_release(s, false); 1736 if (s->chan_rx) 1737 sci_rx_dma_release(s, false); 1738 } 1739 #else 1740 static inline void sci_request_dma(struct uart_port *port) 1741 { 1742 } 1743 1744 static inline void sci_free_dma(struct uart_port *port) 1745 { 1746 } 1747 #endif 1748 1749 static int sci_startup(struct uart_port *port) 1750 { 1751 struct sci_port *s = to_sci_port(port); 1752 int ret; 1753 1754 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1755 1756 pm_runtime_put_noidle(port->dev); 1757 1758 sci_port_enable(s); 1759 1760 ret = sci_request_irq(s); 1761 if (unlikely(ret < 0)) 1762 return ret; 1763 1764 sci_request_dma(port); 1765 1766 sci_start_tx(port); 1767 sci_start_rx(port); 1768 1769 return 0; 1770 } 1771 1772 static void sci_shutdown(struct uart_port *port) 1773 { 1774 struct sci_port *s = to_sci_port(port); 1775 1776 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1777 1778 sci_stop_rx(port); 1779 sci_stop_tx(port); 1780 1781 sci_free_dma(port); 1782 sci_free_irq(s); 1783 1784 sci_port_disable(s); 1785 1786 pm_runtime_get_noresume(port->dev); 1787 } 1788 1789 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1790 unsigned long freq) 1791 { 1792 switch (algo_id) { 1793 case SCBRR_ALGO_1: 1794 return ((freq + 16 * bps) / (16 * bps) - 1); 1795 case SCBRR_ALGO_2: 1796 return ((freq + 16 * bps) / (32 * bps) - 1); 1797 case SCBRR_ALGO_3: 1798 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1799 case SCBRR_ALGO_4: 1800 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1801 case SCBRR_ALGO_5: 1802 return (((freq * 1000 / 32) / bps) - 1); 1803 } 1804 1805 /* Warn, but use a safe default */ 1806 WARN_ON(1); 1807 1808 return ((freq + 16 * bps) / (32 * bps) - 1); 1809 } 1810 1811 static void sci_reset(struct uart_port *port) 1812 { 1813 struct plat_sci_reg *reg; 1814 unsigned int status; 1815 1816 do { 1817 status = serial_port_in(port, SCxSR); 1818 } while (!(status & SCxSR_TEND(port))); 1819 1820 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1821 1822 reg = sci_getreg(port, SCFCR); 1823 if (reg->size) 1824 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1825 } 1826 1827 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1828 struct ktermios *old) 1829 { 1830 struct sci_port *s = to_sci_port(port); 1831 struct plat_sci_reg *reg; 1832 unsigned int baud, smr_val, max_baud; 1833 int t = -1; 1834 1835 /* 1836 * earlyprintk comes here early on with port->uartclk set to zero. 1837 * the clock framework is not up and running at this point so here 1838 * we assume that 115200 is the maximum baud rate. please note that 1839 * the baud rate is not programmed during earlyprintk - it is assumed 1840 * that the previous boot loader has enabled required clocks and 1841 * setup the baud rate generator hardware for us already. 1842 */ 1843 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1844 1845 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1846 if (likely(baud && port->uartclk)) 1847 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1848 1849 sci_port_enable(s); 1850 1851 sci_reset(port); 1852 1853 smr_val = serial_port_in(port, SCSMR) & 3; 1854 1855 if ((termios->c_cflag & CSIZE) == CS7) 1856 smr_val |= 0x40; 1857 if (termios->c_cflag & PARENB) 1858 smr_val |= 0x20; 1859 if (termios->c_cflag & PARODD) 1860 smr_val |= 0x30; 1861 if (termios->c_cflag & CSTOPB) 1862 smr_val |= 0x08; 1863 1864 uart_update_timeout(port, termios->c_cflag, baud); 1865 1866 serial_port_out(port, SCSMR, smr_val); 1867 1868 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, 1869 s->cfg->scscr); 1870 1871 if (t > 0) { 1872 if (t >= 256) { 1873 serial_port_out(port, SCSMR, (serial_port_in(port, SCSMR) & ~3) | 1); 1874 t >>= 2; 1875 } else 1876 serial_port_out(port, SCSMR, serial_port_in(port, SCSMR) & ~3); 1877 1878 serial_port_out(port, SCBRR, t); 1879 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1880 } 1881 1882 sci_init_pins(port, termios->c_cflag); 1883 1884 reg = sci_getreg(port, SCFCR); 1885 if (reg->size) { 1886 unsigned short ctrl = serial_port_in(port, SCFCR); 1887 1888 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { 1889 if (termios->c_cflag & CRTSCTS) 1890 ctrl |= SCFCR_MCE; 1891 else 1892 ctrl &= ~SCFCR_MCE; 1893 } 1894 1895 /* 1896 * As we've done a sci_reset() above, ensure we don't 1897 * interfere with the FIFOs while toggling MCE. As the 1898 * reset values could still be set, simply mask them out. 1899 */ 1900 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 1901 1902 serial_port_out(port, SCFCR, ctrl); 1903 } 1904 1905 serial_port_out(port, SCSCR, s->cfg->scscr); 1906 1907 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1908 /* 1909 * Calculate delay for 1.5 DMA buffers: see 1910 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1911 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1912 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1913 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1914 * sizes), but it has been found out experimentally, that this is not 1915 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1916 * as a minimum seem to work perfectly. 1917 */ 1918 if (s->chan_rx) { 1919 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1920 port->fifosize / 2; 1921 dev_dbg(port->dev, 1922 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1923 s->rx_timeout * 1000 / HZ, port->timeout); 1924 if (s->rx_timeout < msecs_to_jiffies(20)) 1925 s->rx_timeout = msecs_to_jiffies(20); 1926 } 1927 #endif 1928 1929 if ((termios->c_cflag & CREAD) != 0) 1930 sci_start_rx(port); 1931 1932 sci_port_disable(s); 1933 } 1934 1935 static const char *sci_type(struct uart_port *port) 1936 { 1937 switch (port->type) { 1938 case PORT_IRDA: 1939 return "irda"; 1940 case PORT_SCI: 1941 return "sci"; 1942 case PORT_SCIF: 1943 return "scif"; 1944 case PORT_SCIFA: 1945 return "scifa"; 1946 case PORT_SCIFB: 1947 return "scifb"; 1948 } 1949 1950 return NULL; 1951 } 1952 1953 static inline unsigned long sci_port_size(struct uart_port *port) 1954 { 1955 /* 1956 * Pick an arbitrary size that encapsulates all of the base 1957 * registers by default. This can be optimized later, or derived 1958 * from platform resource data at such a time that ports begin to 1959 * behave more erratically. 1960 */ 1961 return 64; 1962 } 1963 1964 static int sci_remap_port(struct uart_port *port) 1965 { 1966 unsigned long size = sci_port_size(port); 1967 1968 /* 1969 * Nothing to do if there's already an established membase. 1970 */ 1971 if (port->membase) 1972 return 0; 1973 1974 if (port->flags & UPF_IOREMAP) { 1975 port->membase = ioremap_nocache(port->mapbase, size); 1976 if (unlikely(!port->membase)) { 1977 dev_err(port->dev, "can't remap port#%d\n", port->line); 1978 return -ENXIO; 1979 } 1980 } else { 1981 /* 1982 * For the simple (and majority of) cases where we don't 1983 * need to do any remapping, just cast the cookie 1984 * directly. 1985 */ 1986 port->membase = (void __iomem *)port->mapbase; 1987 } 1988 1989 return 0; 1990 } 1991 1992 static void sci_release_port(struct uart_port *port) 1993 { 1994 if (port->flags & UPF_IOREMAP) { 1995 iounmap(port->membase); 1996 port->membase = NULL; 1997 } 1998 1999 release_mem_region(port->mapbase, sci_port_size(port)); 2000 } 2001 2002 static int sci_request_port(struct uart_port *port) 2003 { 2004 unsigned long size = sci_port_size(port); 2005 struct resource *res; 2006 int ret; 2007 2008 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 2009 if (unlikely(res == NULL)) 2010 return -EBUSY; 2011 2012 ret = sci_remap_port(port); 2013 if (unlikely(ret != 0)) { 2014 release_resource(res); 2015 return ret; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static void sci_config_port(struct uart_port *port, int flags) 2022 { 2023 if (flags & UART_CONFIG_TYPE) { 2024 struct sci_port *sport = to_sci_port(port); 2025 2026 port->type = sport->cfg->type; 2027 sci_request_port(port); 2028 } 2029 } 2030 2031 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2032 { 2033 struct sci_port *s = to_sci_port(port); 2034 2035 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 2036 return -EINVAL; 2037 if (ser->baud_base < 2400) 2038 /* No paper tape reader for Mitch.. */ 2039 return -EINVAL; 2040 2041 return 0; 2042 } 2043 2044 static struct uart_ops sci_uart_ops = { 2045 .tx_empty = sci_tx_empty, 2046 .set_mctrl = sci_set_mctrl, 2047 .get_mctrl = sci_get_mctrl, 2048 .start_tx = sci_start_tx, 2049 .stop_tx = sci_stop_tx, 2050 .stop_rx = sci_stop_rx, 2051 .enable_ms = sci_enable_ms, 2052 .break_ctl = sci_break_ctl, 2053 .startup = sci_startup, 2054 .shutdown = sci_shutdown, 2055 .set_termios = sci_set_termios, 2056 .type = sci_type, 2057 .release_port = sci_release_port, 2058 .request_port = sci_request_port, 2059 .config_port = sci_config_port, 2060 .verify_port = sci_verify_port, 2061 #ifdef CONFIG_CONSOLE_POLL 2062 .poll_get_char = sci_poll_get_char, 2063 .poll_put_char = sci_poll_put_char, 2064 #endif 2065 }; 2066 2067 static int __devinit sci_init_single(struct platform_device *dev, 2068 struct sci_port *sci_port, 2069 unsigned int index, 2070 struct plat_sci_port *p) 2071 { 2072 struct uart_port *port = &sci_port->port; 2073 int ret; 2074 2075 sci_port->cfg = p; 2076 2077 port->ops = &sci_uart_ops; 2078 port->iotype = UPIO_MEM; 2079 port->line = index; 2080 2081 switch (p->type) { 2082 case PORT_SCIFB: 2083 port->fifosize = 256; 2084 break; 2085 case PORT_SCIFA: 2086 port->fifosize = 64; 2087 break; 2088 case PORT_SCIF: 2089 port->fifosize = 16; 2090 break; 2091 default: 2092 port->fifosize = 1; 2093 break; 2094 } 2095 2096 if (p->regtype == SCIx_PROBE_REGTYPE) { 2097 ret = sci_probe_regmap(p); 2098 if (unlikely(ret)) 2099 return ret; 2100 } 2101 2102 if (dev) { 2103 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2104 if (IS_ERR(sci_port->iclk)) { 2105 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 2106 if (IS_ERR(sci_port->iclk)) { 2107 dev_err(&dev->dev, "can't get iclk\n"); 2108 return PTR_ERR(sci_port->iclk); 2109 } 2110 } 2111 2112 /* 2113 * The function clock is optional, ignore it if we can't 2114 * find it. 2115 */ 2116 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 2117 if (IS_ERR(sci_port->fclk)) 2118 sci_port->fclk = NULL; 2119 2120 port->dev = &dev->dev; 2121 2122 sci_init_gpios(sci_port); 2123 2124 pm_runtime_irq_safe(&dev->dev); 2125 pm_runtime_get_noresume(&dev->dev); 2126 pm_runtime_enable(&dev->dev); 2127 } 2128 2129 sci_port->break_timer.data = (unsigned long)sci_port; 2130 sci_port->break_timer.function = sci_break_timer; 2131 init_timer(&sci_port->break_timer); 2132 2133 /* 2134 * Establish some sensible defaults for the error detection. 2135 */ 2136 if (!p->error_mask) 2137 p->error_mask = (p->type == PORT_SCI) ? 2138 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 2139 2140 /* 2141 * Establish sensible defaults for the overrun detection, unless 2142 * the part has explicitly disabled support for it. 2143 */ 2144 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 2145 if (p->type == PORT_SCI) 2146 p->overrun_bit = 5; 2147 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 2148 p->overrun_bit = 9; 2149 else 2150 p->overrun_bit = 0; 2151 2152 /* 2153 * Make the error mask inclusive of overrun detection, if 2154 * supported. 2155 */ 2156 p->error_mask |= (1 << p->overrun_bit); 2157 } 2158 2159 port->mapbase = p->mapbase; 2160 port->type = p->type; 2161 port->flags = p->flags; 2162 port->regshift = p->regshift; 2163 2164 /* 2165 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2166 * for the multi-IRQ ports, which is where we are primarily 2167 * concerned with the shutdown path synchronization. 2168 * 2169 * For the muxed case there's nothing more to do. 2170 */ 2171 port->irq = p->irqs[SCIx_RXI_IRQ]; 2172 port->irqflags = 0; 2173 2174 port->serial_in = sci_serial_in; 2175 port->serial_out = sci_serial_out; 2176 2177 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 2178 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 2179 p->dma_slave_tx, p->dma_slave_rx); 2180 2181 return 0; 2182 } 2183 2184 static void sci_cleanup_single(struct sci_port *port) 2185 { 2186 sci_free_gpios(port); 2187 2188 clk_put(port->iclk); 2189 clk_put(port->fclk); 2190 2191 pm_runtime_disable(port->port.dev); 2192 } 2193 2194 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2195 static void serial_console_putchar(struct uart_port *port, int ch) 2196 { 2197 sci_poll_put_char(port, ch); 2198 } 2199 2200 /* 2201 * Print a string to the serial port trying not to disturb 2202 * any possible real use of the port... 2203 */ 2204 static void serial_console_write(struct console *co, const char *s, 2205 unsigned count) 2206 { 2207 struct sci_port *sci_port = &sci_ports[co->index]; 2208 struct uart_port *port = &sci_port->port; 2209 unsigned short bits; 2210 2211 sci_port_enable(sci_port); 2212 2213 uart_console_write(port, s, count, serial_console_putchar); 2214 2215 /* wait until fifo is empty and last bit has been transmitted */ 2216 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2217 while ((serial_port_in(port, SCxSR) & bits) != bits) 2218 cpu_relax(); 2219 2220 sci_port_disable(sci_port); 2221 } 2222 2223 static int __devinit serial_console_setup(struct console *co, char *options) 2224 { 2225 struct sci_port *sci_port; 2226 struct uart_port *port; 2227 int baud = 115200; 2228 int bits = 8; 2229 int parity = 'n'; 2230 int flow = 'n'; 2231 int ret; 2232 2233 /* 2234 * Refuse to handle any bogus ports. 2235 */ 2236 if (co->index < 0 || co->index >= SCI_NPORTS) 2237 return -ENODEV; 2238 2239 sci_port = &sci_ports[co->index]; 2240 port = &sci_port->port; 2241 2242 /* 2243 * Refuse to handle uninitialized ports. 2244 */ 2245 if (!port->ops) 2246 return -ENODEV; 2247 2248 ret = sci_remap_port(port); 2249 if (unlikely(ret != 0)) 2250 return ret; 2251 2252 sci_port_enable(sci_port); 2253 2254 if (options) 2255 uart_parse_options(options, &baud, &parity, &bits, &flow); 2256 2257 sci_port_disable(sci_port); 2258 2259 return uart_set_options(port, co, baud, parity, bits, flow); 2260 } 2261 2262 static struct console serial_console = { 2263 .name = "ttySC", 2264 .device = uart_console_device, 2265 .write = serial_console_write, 2266 .setup = serial_console_setup, 2267 .flags = CON_PRINTBUFFER, 2268 .index = -1, 2269 .data = &sci_uart_driver, 2270 }; 2271 2272 static struct console early_serial_console = { 2273 .name = "early_ttySC", 2274 .write = serial_console_write, 2275 .flags = CON_PRINTBUFFER, 2276 .index = -1, 2277 }; 2278 2279 static char early_serial_buf[32]; 2280 2281 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2282 { 2283 struct plat_sci_port *cfg = pdev->dev.platform_data; 2284 2285 if (early_serial_console.data) 2286 return -EEXIST; 2287 2288 early_serial_console.index = pdev->id; 2289 2290 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2291 2292 serial_console_setup(&early_serial_console, early_serial_buf); 2293 2294 if (!strstr(early_serial_buf, "keep")) 2295 early_serial_console.flags |= CON_BOOT; 2296 2297 register_console(&early_serial_console); 2298 return 0; 2299 } 2300 2301 #define uart_console(port) ((port)->cons->index == (port)->line) 2302 2303 static int sci_runtime_suspend(struct device *dev) 2304 { 2305 struct sci_port *sci_port = dev_get_drvdata(dev); 2306 struct uart_port *port = &sci_port->port; 2307 2308 if (uart_console(port)) { 2309 struct plat_sci_reg *reg; 2310 2311 sci_port->saved_smr = serial_port_in(port, SCSMR); 2312 sci_port->saved_brr = serial_port_in(port, SCBRR); 2313 2314 reg = sci_getreg(port, SCFCR); 2315 if (reg->size) 2316 sci_port->saved_fcr = serial_port_in(port, SCFCR); 2317 else 2318 sci_port->saved_fcr = 0; 2319 } 2320 return 0; 2321 } 2322 2323 static int sci_runtime_resume(struct device *dev) 2324 { 2325 struct sci_port *sci_port = dev_get_drvdata(dev); 2326 struct uart_port *port = &sci_port->port; 2327 2328 if (uart_console(port)) { 2329 sci_reset(port); 2330 serial_port_out(port, SCSMR, sci_port->saved_smr); 2331 serial_port_out(port, SCBRR, sci_port->saved_brr); 2332 2333 if (sci_port->saved_fcr) 2334 serial_port_out(port, SCFCR, sci_port->saved_fcr); 2335 2336 serial_port_out(port, SCSCR, sci_port->cfg->scscr); 2337 } 2338 return 0; 2339 } 2340 2341 #define SCI_CONSOLE (&serial_console) 2342 2343 #else 2344 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2345 { 2346 return -EINVAL; 2347 } 2348 2349 #define SCI_CONSOLE NULL 2350 #define sci_runtime_suspend NULL 2351 #define sci_runtime_resume NULL 2352 2353 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2354 2355 static char banner[] __initdata = 2356 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2357 2358 static struct uart_driver sci_uart_driver = { 2359 .owner = THIS_MODULE, 2360 .driver_name = "sci", 2361 .dev_name = "ttySC", 2362 .major = SCI_MAJOR, 2363 .minor = SCI_MINOR_START, 2364 .nr = SCI_NPORTS, 2365 .cons = SCI_CONSOLE, 2366 }; 2367 2368 static int sci_remove(struct platform_device *dev) 2369 { 2370 struct sci_port *port = platform_get_drvdata(dev); 2371 2372 cpufreq_unregister_notifier(&port->freq_transition, 2373 CPUFREQ_TRANSITION_NOTIFIER); 2374 2375 uart_remove_one_port(&sci_uart_driver, &port->port); 2376 2377 sci_cleanup_single(port); 2378 2379 return 0; 2380 } 2381 2382 static int __devinit sci_probe_single(struct platform_device *dev, 2383 unsigned int index, 2384 struct plat_sci_port *p, 2385 struct sci_port *sciport) 2386 { 2387 int ret; 2388 2389 /* Sanity check */ 2390 if (unlikely(index >= SCI_NPORTS)) { 2391 dev_notice(&dev->dev, "Attempting to register port " 2392 "%d when only %d are available.\n", 2393 index+1, SCI_NPORTS); 2394 dev_notice(&dev->dev, "Consider bumping " 2395 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2396 return -EINVAL; 2397 } 2398 2399 ret = sci_init_single(dev, sciport, index, p); 2400 if (ret) 2401 return ret; 2402 2403 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 2404 if (ret) { 2405 sci_cleanup_single(sciport); 2406 return ret; 2407 } 2408 2409 return 0; 2410 } 2411 2412 static int __devinit sci_probe(struct platform_device *dev) 2413 { 2414 struct plat_sci_port *p = dev->dev.platform_data; 2415 struct sci_port *sp = &sci_ports[dev->id]; 2416 int ret; 2417 2418 /* 2419 * If we've come here via earlyprintk initialization, head off to 2420 * the special early probe. We don't have sufficient device state 2421 * to make it beyond this yet. 2422 */ 2423 if (is_early_platform_device(dev)) 2424 return sci_probe_earlyprintk(dev); 2425 2426 platform_set_drvdata(dev, sp); 2427 2428 ret = sci_probe_single(dev, dev->id, p, sp); 2429 if (ret) 2430 return ret; 2431 2432 sp->freq_transition.notifier_call = sci_notifier; 2433 2434 ret = cpufreq_register_notifier(&sp->freq_transition, 2435 CPUFREQ_TRANSITION_NOTIFIER); 2436 if (unlikely(ret < 0)) { 2437 sci_cleanup_single(sp); 2438 return ret; 2439 } 2440 2441 #ifdef CONFIG_SH_STANDARD_BIOS 2442 sh_bios_gdb_detach(); 2443 #endif 2444 2445 return 0; 2446 } 2447 2448 static int sci_suspend(struct device *dev) 2449 { 2450 struct sci_port *sport = dev_get_drvdata(dev); 2451 2452 if (sport) 2453 uart_suspend_port(&sci_uart_driver, &sport->port); 2454 2455 return 0; 2456 } 2457 2458 static int sci_resume(struct device *dev) 2459 { 2460 struct sci_port *sport = dev_get_drvdata(dev); 2461 2462 if (sport) 2463 uart_resume_port(&sci_uart_driver, &sport->port); 2464 2465 return 0; 2466 } 2467 2468 static const struct dev_pm_ops sci_dev_pm_ops = { 2469 .runtime_suspend = sci_runtime_suspend, 2470 .runtime_resume = sci_runtime_resume, 2471 .suspend = sci_suspend, 2472 .resume = sci_resume, 2473 }; 2474 2475 static struct platform_driver sci_driver = { 2476 .probe = sci_probe, 2477 .remove = sci_remove, 2478 .driver = { 2479 .name = "sh-sci", 2480 .owner = THIS_MODULE, 2481 .pm = &sci_dev_pm_ops, 2482 }, 2483 }; 2484 2485 static int __init sci_init(void) 2486 { 2487 int ret; 2488 2489 printk(banner); 2490 2491 ret = uart_register_driver(&sci_uart_driver); 2492 if (likely(ret == 0)) { 2493 ret = platform_driver_register(&sci_driver); 2494 if (unlikely(ret)) 2495 uart_unregister_driver(&sci_uart_driver); 2496 } 2497 2498 return ret; 2499 } 2500 2501 static void __exit sci_exit(void) 2502 { 2503 platform_driver_unregister(&sci_driver); 2504 uart_unregister_driver(&sci_uart_driver); 2505 } 2506 2507 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2508 early_platform_init_buffer("earlyprintk", &sci_driver, 2509 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2510 #endif 2511 module_init(sci_init); 2512 module_exit(sci_exit); 2513 2514 MODULE_LICENSE("GPL"); 2515 MODULE_ALIAS("platform:sh-sci"); 2516 MODULE_AUTHOR("Paul Mundt"); 2517 MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2518