1 /* 2 * serial_tegra.c 3 * 4 * High-speed serial driver for NVIDIA Tegra SoCs 5 * 6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/debugfs.h> 25 #include <linux/delay.h> 26 #include <linux/dmaengine.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/module.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/pagemap.h> 36 #include <linux/platform_device.h> 37 #include <linux/reset.h> 38 #include <linux/serial.h> 39 #include <linux/serial_8250.h> 40 #include <linux/serial_core.h> 41 #include <linux/serial_reg.h> 42 #include <linux/slab.h> 43 #include <linux/string.h> 44 #include <linux/termios.h> 45 #include <linux/tty.h> 46 #include <linux/tty_flip.h> 47 48 #define TEGRA_UART_TYPE "TEGRA_UART" 49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 51 52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 54 #define TEGRA_UART_IER_EORD 0x20 55 #define TEGRA_UART_MCR_RTS_EN 0x40 56 #define TEGRA_UART_MCR_CTS_EN 0x20 57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 58 UART_LSR_PE | UART_LSR_FE) 59 #define TEGRA_UART_IRDA_CSR 0x08 60 #define TEGRA_UART_SIR_ENABLED 0x80 61 62 #define TEGRA_UART_TX_PIO 1 63 #define TEGRA_UART_TX_DMA 2 64 #define TEGRA_UART_MIN_DMA 16 65 #define TEGRA_UART_FIFO_SIZE 32 66 67 /* 68 * Tx fifo trigger level setting in tegra uart is in 69 * reverse way then conventional uart. 70 */ 71 #define TEGRA_UART_TX_TRIG_16B 0x00 72 #define TEGRA_UART_TX_TRIG_8B 0x10 73 #define TEGRA_UART_TX_TRIG_4B 0x20 74 #define TEGRA_UART_TX_TRIG_1B 0x30 75 76 #define TEGRA_UART_MAXIMUM 5 77 78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 79 #define TEGRA_UART_DEFAULT_BAUD 115200 80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 81 82 /* Tx transfer mode */ 83 #define TEGRA_TX_PIO 1 84 #define TEGRA_TX_DMA 2 85 86 /** 87 * tegra_uart_chip_data: SOC specific data. 88 * 89 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 91 * Tegra30 does not allow this. 92 * @support_clk_src_div: Clock source support the clock divider. 93 */ 94 struct tegra_uart_chip_data { 95 bool tx_fifo_full_status; 96 bool allow_txfifo_reset_fifo_mode; 97 bool support_clk_src_div; 98 }; 99 100 struct tegra_uart_port { 101 struct uart_port uport; 102 const struct tegra_uart_chip_data *cdata; 103 104 struct clk *uart_clk; 105 struct reset_control *rst; 106 unsigned int current_baud; 107 108 /* Register shadow */ 109 unsigned long fcr_shadow; 110 unsigned long mcr_shadow; 111 unsigned long lcr_shadow; 112 unsigned long ier_shadow; 113 bool rts_active; 114 115 int tx_in_progress; 116 unsigned int tx_bytes; 117 118 bool enable_modem_interrupt; 119 120 bool rx_timeout; 121 int rx_in_progress; 122 int symb_bit; 123 124 struct dma_chan *rx_dma_chan; 125 struct dma_chan *tx_dma_chan; 126 dma_addr_t rx_dma_buf_phys; 127 dma_addr_t tx_dma_buf_phys; 128 unsigned char *rx_dma_buf_virt; 129 unsigned char *tx_dma_buf_virt; 130 struct dma_async_tx_descriptor *tx_dma_desc; 131 struct dma_async_tx_descriptor *rx_dma_desc; 132 dma_cookie_t tx_cookie; 133 dma_cookie_t rx_cookie; 134 int tx_bytes_requested; 135 int rx_bytes_requested; 136 }; 137 138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 140 141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 142 unsigned long reg) 143 { 144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 145 } 146 147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 148 unsigned long reg) 149 { 150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 151 } 152 153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 154 { 155 return container_of(u, struct tegra_uart_port, uport); 156 } 157 158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 159 { 160 struct tegra_uart_port *tup = to_tegra_uport(u); 161 162 /* 163 * RI - Ring detector is active 164 * CD/DCD/CAR - Carrier detect is always active. For some reason 165 * linux has different names for carrier detect. 166 * DSR - Data Set ready is active as the hardware doesn't support it. 167 * Don't know if the linux support this yet? 168 * CTS - Clear to send. Always set to active, as the hardware handles 169 * CTS automatically. 170 */ 171 if (tup->enable_modem_interrupt) 172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 173 return TIOCM_CTS; 174 } 175 176 static void set_rts(struct tegra_uart_port *tup, bool active) 177 { 178 unsigned long mcr; 179 180 mcr = tup->mcr_shadow; 181 if (active) 182 mcr |= TEGRA_UART_MCR_RTS_EN; 183 else 184 mcr &= ~TEGRA_UART_MCR_RTS_EN; 185 if (mcr != tup->mcr_shadow) { 186 tegra_uart_write(tup, mcr, UART_MCR); 187 tup->mcr_shadow = mcr; 188 } 189 return; 190 } 191 192 static void set_dtr(struct tegra_uart_port *tup, bool active) 193 { 194 unsigned long mcr; 195 196 mcr = tup->mcr_shadow; 197 if (active) 198 mcr |= UART_MCR_DTR; 199 else 200 mcr &= ~UART_MCR_DTR; 201 if (mcr != tup->mcr_shadow) { 202 tegra_uart_write(tup, mcr, UART_MCR); 203 tup->mcr_shadow = mcr; 204 } 205 return; 206 } 207 208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 209 { 210 struct tegra_uart_port *tup = to_tegra_uport(u); 211 unsigned long mcr; 212 int dtr_enable; 213 214 mcr = tup->mcr_shadow; 215 tup->rts_active = !!(mctrl & TIOCM_RTS); 216 set_rts(tup, tup->rts_active); 217 218 dtr_enable = !!(mctrl & TIOCM_DTR); 219 set_dtr(tup, dtr_enable); 220 return; 221 } 222 223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 224 { 225 struct tegra_uart_port *tup = to_tegra_uport(u); 226 unsigned long lcr; 227 228 lcr = tup->lcr_shadow; 229 if (break_ctl) 230 lcr |= UART_LCR_SBC; 231 else 232 lcr &= ~UART_LCR_SBC; 233 tegra_uart_write(tup, lcr, UART_LCR); 234 tup->lcr_shadow = lcr; 235 } 236 237 /* Wait for a symbol-time. */ 238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 239 unsigned int syms) 240 { 241 if (tup->current_baud) 242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 243 tup->current_baud)); 244 } 245 246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 247 { 248 unsigned long fcr = tup->fcr_shadow; 249 250 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 252 tegra_uart_write(tup, fcr, UART_FCR); 253 } else { 254 fcr &= ~UART_FCR_ENABLE_FIFO; 255 tegra_uart_write(tup, fcr, UART_FCR); 256 udelay(60); 257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 258 tegra_uart_write(tup, fcr, UART_FCR); 259 fcr |= UART_FCR_ENABLE_FIFO; 260 tegra_uart_write(tup, fcr, UART_FCR); 261 } 262 263 /* Dummy read to ensure the write is posted */ 264 tegra_uart_read(tup, UART_SCR); 265 266 /* Wait for the flush to propagate. */ 267 tegra_uart_wait_sym_time(tup, 1); 268 } 269 270 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 271 { 272 unsigned long rate; 273 unsigned int divisor; 274 unsigned long lcr; 275 int ret; 276 277 if (tup->current_baud == baud) 278 return 0; 279 280 if (tup->cdata->support_clk_src_div) { 281 rate = baud * 16; 282 ret = clk_set_rate(tup->uart_clk, rate); 283 if (ret < 0) { 284 dev_err(tup->uport.dev, 285 "clk_set_rate() failed for rate %lu\n", rate); 286 return ret; 287 } 288 divisor = 1; 289 } else { 290 rate = clk_get_rate(tup->uart_clk); 291 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 292 } 293 294 lcr = tup->lcr_shadow; 295 lcr |= UART_LCR_DLAB; 296 tegra_uart_write(tup, lcr, UART_LCR); 297 298 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 300 301 lcr &= ~UART_LCR_DLAB; 302 tegra_uart_write(tup, lcr, UART_LCR); 303 304 /* Dummy read to ensure the write is posted */ 305 tegra_uart_read(tup, UART_SCR); 306 307 tup->current_baud = baud; 308 309 /* wait two character intervals at new rate */ 310 tegra_uart_wait_sym_time(tup, 2); 311 return 0; 312 } 313 314 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 315 unsigned long lsr) 316 { 317 char flag = TTY_NORMAL; 318 319 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 320 if (lsr & UART_LSR_OE) { 321 /* Overrrun error */ 322 flag = TTY_OVERRUN; 323 tup->uport.icount.overrun++; 324 dev_err(tup->uport.dev, "Got overrun errors\n"); 325 } else if (lsr & UART_LSR_PE) { 326 /* Parity error */ 327 flag = TTY_PARITY; 328 tup->uport.icount.parity++; 329 dev_err(tup->uport.dev, "Got Parity errors\n"); 330 } else if (lsr & UART_LSR_FE) { 331 flag = TTY_FRAME; 332 tup->uport.icount.frame++; 333 dev_err(tup->uport.dev, "Got frame errors\n"); 334 } else if (lsr & UART_LSR_BI) { 335 dev_err(tup->uport.dev, "Got Break\n"); 336 tup->uport.icount.brk++; 337 /* If FIFO read error without any data, reset Rx FIFO */ 338 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 339 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 340 } 341 } 342 return flag; 343 } 344 345 static int tegra_uart_request_port(struct uart_port *u) 346 { 347 return 0; 348 } 349 350 static void tegra_uart_release_port(struct uart_port *u) 351 { 352 /* Nothing to do here */ 353 } 354 355 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 356 { 357 struct circ_buf *xmit = &tup->uport.state->xmit; 358 int i; 359 360 for (i = 0; i < max_bytes; i++) { 361 BUG_ON(uart_circ_empty(xmit)); 362 if (tup->cdata->tx_fifo_full_status) { 363 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 364 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 365 break; 366 } 367 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 368 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 369 tup->uport.icount.tx++; 370 } 371 } 372 373 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 374 unsigned int bytes) 375 { 376 if (bytes > TEGRA_UART_MIN_DMA) 377 bytes = TEGRA_UART_MIN_DMA; 378 379 tup->tx_in_progress = TEGRA_UART_TX_PIO; 380 tup->tx_bytes = bytes; 381 tup->ier_shadow |= UART_IER_THRI; 382 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 383 } 384 385 static void tegra_uart_tx_dma_complete(void *args) 386 { 387 struct tegra_uart_port *tup = args; 388 struct circ_buf *xmit = &tup->uport.state->xmit; 389 struct dma_tx_state state; 390 unsigned long flags; 391 int count; 392 393 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state); 394 count = tup->tx_bytes_requested - state.residue; 395 async_tx_ack(tup->tx_dma_desc); 396 spin_lock_irqsave(&tup->uport.lock, flags); 397 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 398 tup->tx_in_progress = 0; 399 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 400 uart_write_wakeup(&tup->uport); 401 tegra_uart_start_next_tx(tup); 402 spin_unlock_irqrestore(&tup->uport.lock, flags); 403 } 404 405 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 406 unsigned long count) 407 { 408 struct circ_buf *xmit = &tup->uport.state->xmit; 409 dma_addr_t tx_phys_addr; 410 411 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, 412 UART_XMIT_SIZE, DMA_TO_DEVICE); 413 414 tup->tx_bytes = count & ~(0xF); 415 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 416 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 417 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 418 DMA_PREP_INTERRUPT); 419 if (!tup->tx_dma_desc) { 420 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 421 return -EIO; 422 } 423 424 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 425 tup->tx_dma_desc->callback_param = tup; 426 tup->tx_in_progress = TEGRA_UART_TX_DMA; 427 tup->tx_bytes_requested = tup->tx_bytes; 428 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 429 dma_async_issue_pending(tup->tx_dma_chan); 430 return 0; 431 } 432 433 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 434 { 435 unsigned long tail; 436 unsigned long count; 437 struct circ_buf *xmit = &tup->uport.state->xmit; 438 439 tail = (unsigned long)&xmit->buf[xmit->tail]; 440 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 441 if (!count) 442 return; 443 444 if (count < TEGRA_UART_MIN_DMA) 445 tegra_uart_start_pio_tx(tup, count); 446 else if (BYTES_TO_ALIGN(tail) > 0) 447 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 448 else 449 tegra_uart_start_tx_dma(tup, count); 450 } 451 452 /* Called by serial core driver with u->lock taken. */ 453 static void tegra_uart_start_tx(struct uart_port *u) 454 { 455 struct tegra_uart_port *tup = to_tegra_uport(u); 456 struct circ_buf *xmit = &u->state->xmit; 457 458 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 459 tegra_uart_start_next_tx(tup); 460 } 461 462 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 463 { 464 struct tegra_uart_port *tup = to_tegra_uport(u); 465 unsigned int ret = 0; 466 unsigned long flags; 467 468 spin_lock_irqsave(&u->lock, flags); 469 if (!tup->tx_in_progress) { 470 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 471 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 472 ret = TIOCSER_TEMT; 473 } 474 spin_unlock_irqrestore(&u->lock, flags); 475 return ret; 476 } 477 478 static void tegra_uart_stop_tx(struct uart_port *u) 479 { 480 struct tegra_uart_port *tup = to_tegra_uport(u); 481 struct circ_buf *xmit = &tup->uport.state->xmit; 482 struct dma_tx_state state; 483 int count; 484 485 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) 486 return; 487 488 dmaengine_terminate_all(tup->tx_dma_chan); 489 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 490 count = tup->tx_bytes_requested - state.residue; 491 async_tx_ack(tup->tx_dma_desc); 492 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 493 tup->tx_in_progress = 0; 494 return; 495 } 496 497 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 498 { 499 struct circ_buf *xmit = &tup->uport.state->xmit; 500 501 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 502 tup->tx_in_progress = 0; 503 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 504 uart_write_wakeup(&tup->uport); 505 tegra_uart_start_next_tx(tup); 506 return; 507 } 508 509 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 510 struct tty_port *tty) 511 { 512 do { 513 char flag = TTY_NORMAL; 514 unsigned long lsr = 0; 515 unsigned char ch; 516 517 lsr = tegra_uart_read(tup, UART_LSR); 518 if (!(lsr & UART_LSR_DR)) 519 break; 520 521 flag = tegra_uart_decode_rx_error(tup, lsr); 522 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 523 tup->uport.icount.rx++; 524 525 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) 526 tty_insert_flip_char(tty, ch, flag); 527 } while (1); 528 529 return; 530 } 531 532 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 533 struct tty_port *tty, int count) 534 { 535 int copied; 536 537 tup->uport.icount.rx += count; 538 if (!tty) { 539 dev_err(tup->uport.dev, "No tty port\n"); 540 return; 541 } 542 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 543 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 544 copied = tty_insert_flip_string(tty, 545 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 546 if (copied != count) { 547 WARN_ON(1); 548 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 549 } 550 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 551 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 552 } 553 554 static void tegra_uart_rx_dma_complete(void *args) 555 { 556 struct tegra_uart_port *tup = args; 557 struct uart_port *u = &tup->uport; 558 int count = tup->rx_bytes_requested; 559 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 560 struct tty_port *port = &u->state->port; 561 unsigned long flags; 562 563 async_tx_ack(tup->rx_dma_desc); 564 spin_lock_irqsave(&u->lock, flags); 565 566 /* Deactivate flow control to stop sender */ 567 if (tup->rts_active) 568 set_rts(tup, false); 569 570 /* If we are here, DMA is stopped */ 571 if (count) 572 tegra_uart_copy_rx_to_tty(tup, port, count); 573 574 tegra_uart_handle_rx_pio(tup, port); 575 if (tty) { 576 spin_unlock_irqrestore(&u->lock, flags); 577 tty_flip_buffer_push(port); 578 spin_lock_irqsave(&u->lock, flags); 579 tty_kref_put(tty); 580 } 581 tegra_uart_start_rx_dma(tup); 582 583 /* Activate flow control to start transfer */ 584 if (tup->rts_active) 585 set_rts(tup, true); 586 587 spin_unlock_irqrestore(&u->lock, flags); 588 } 589 590 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup, 591 unsigned long *flags) 592 { 593 struct dma_tx_state state; 594 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 595 struct tty_port *port = &tup->uport.state->port; 596 struct uart_port *u = &tup->uport; 597 int count; 598 599 /* Deactivate flow control to stop sender */ 600 if (tup->rts_active) 601 set_rts(tup, false); 602 603 dmaengine_terminate_all(tup->rx_dma_chan); 604 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 605 async_tx_ack(tup->rx_dma_desc); 606 count = tup->rx_bytes_requested - state.residue; 607 608 /* If we are here, DMA is stopped */ 609 if (count) 610 tegra_uart_copy_rx_to_tty(tup, port, count); 611 612 tegra_uart_handle_rx_pio(tup, port); 613 if (tty) { 614 spin_unlock_irqrestore(&u->lock, *flags); 615 tty_flip_buffer_push(port); 616 spin_lock_irqsave(&u->lock, *flags); 617 tty_kref_put(tty); 618 } 619 tegra_uart_start_rx_dma(tup); 620 621 if (tup->rts_active) 622 set_rts(tup, true); 623 } 624 625 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 626 { 627 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 628 629 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 630 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 631 DMA_PREP_INTERRUPT); 632 if (!tup->rx_dma_desc) { 633 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 634 return -EIO; 635 } 636 637 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 638 tup->rx_dma_desc->callback_param = tup; 639 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 640 count, DMA_TO_DEVICE); 641 tup->rx_bytes_requested = count; 642 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 643 dma_async_issue_pending(tup->rx_dma_chan); 644 return 0; 645 } 646 647 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 648 { 649 struct tegra_uart_port *tup = to_tegra_uport(u); 650 unsigned long msr; 651 652 msr = tegra_uart_read(tup, UART_MSR); 653 if (!(msr & UART_MSR_ANY_DELTA)) 654 return; 655 656 if (msr & UART_MSR_TERI) 657 tup->uport.icount.rng++; 658 if (msr & UART_MSR_DDSR) 659 tup->uport.icount.dsr++; 660 /* We may only get DDCD when HW init and reset */ 661 if (msr & UART_MSR_DDCD) 662 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 663 /* Will start/stop_tx accordingly */ 664 if (msr & UART_MSR_DCTS) 665 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 666 return; 667 } 668 669 static irqreturn_t tegra_uart_isr(int irq, void *data) 670 { 671 struct tegra_uart_port *tup = data; 672 struct uart_port *u = &tup->uport; 673 unsigned long iir; 674 unsigned long ier; 675 bool is_rx_int = false; 676 unsigned long flags; 677 678 spin_lock_irqsave(&u->lock, flags); 679 while (1) { 680 iir = tegra_uart_read(tup, UART_IIR); 681 if (iir & UART_IIR_NO_INT) { 682 if (is_rx_int) { 683 tegra_uart_handle_rx_dma(tup, &flags); 684 if (tup->rx_in_progress) { 685 ier = tup->ier_shadow; 686 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 687 TEGRA_UART_IER_EORD); 688 tup->ier_shadow = ier; 689 tegra_uart_write(tup, ier, UART_IER); 690 } 691 } 692 spin_unlock_irqrestore(&u->lock, flags); 693 return IRQ_HANDLED; 694 } 695 696 switch ((iir >> 1) & 0x7) { 697 case 0: /* Modem signal change interrupt */ 698 tegra_uart_handle_modem_signal_change(u); 699 break; 700 701 case 1: /* Transmit interrupt only triggered when using PIO */ 702 tup->ier_shadow &= ~UART_IER_THRI; 703 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 704 tegra_uart_handle_tx_pio(tup); 705 break; 706 707 case 4: /* End of data */ 708 case 6: /* Rx timeout */ 709 case 2: /* Receive */ 710 if (!is_rx_int) { 711 is_rx_int = true; 712 /* Disable Rx interrupts */ 713 ier = tup->ier_shadow; 714 ier |= UART_IER_RDI; 715 tegra_uart_write(tup, ier, UART_IER); 716 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 717 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 718 tup->ier_shadow = ier; 719 tegra_uart_write(tup, ier, UART_IER); 720 } 721 break; 722 723 case 3: /* Receive error */ 724 tegra_uart_decode_rx_error(tup, 725 tegra_uart_read(tup, UART_LSR)); 726 break; 727 728 case 5: /* break nothing to handle */ 729 case 7: /* break nothing to handle */ 730 break; 731 } 732 } 733 } 734 735 static void tegra_uart_stop_rx(struct uart_port *u) 736 { 737 struct tegra_uart_port *tup = to_tegra_uport(u); 738 struct tty_struct *tty; 739 struct tty_port *port = &u->state->port; 740 struct dma_tx_state state; 741 unsigned long ier; 742 int count; 743 744 if (tup->rts_active) 745 set_rts(tup, false); 746 747 if (!tup->rx_in_progress) 748 return; 749 750 tty = tty_port_tty_get(&tup->uport.state->port); 751 752 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ 753 754 ier = tup->ier_shadow; 755 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 756 TEGRA_UART_IER_EORD); 757 tup->ier_shadow = ier; 758 tegra_uart_write(tup, ier, UART_IER); 759 tup->rx_in_progress = 0; 760 if (tup->rx_dma_chan) { 761 dmaengine_terminate_all(tup->rx_dma_chan); 762 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 763 async_tx_ack(tup->rx_dma_desc); 764 count = tup->rx_bytes_requested - state.residue; 765 tegra_uart_copy_rx_to_tty(tup, port, count); 766 tegra_uart_handle_rx_pio(tup, port); 767 } else { 768 tegra_uart_handle_rx_pio(tup, port); 769 } 770 if (tty) { 771 tty_flip_buffer_push(port); 772 tty_kref_put(tty); 773 } 774 return; 775 } 776 777 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 778 { 779 unsigned long flags; 780 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 781 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 782 unsigned long wait_time; 783 unsigned long lsr; 784 unsigned long msr; 785 unsigned long mcr; 786 787 /* Disable interrupts */ 788 tegra_uart_write(tup, 0, UART_IER); 789 790 lsr = tegra_uart_read(tup, UART_LSR); 791 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 792 msr = tegra_uart_read(tup, UART_MSR); 793 mcr = tegra_uart_read(tup, UART_MCR); 794 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 795 dev_err(tup->uport.dev, 796 "Tx Fifo not empty, CTS disabled, waiting\n"); 797 798 /* Wait for Tx fifo to be empty */ 799 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 800 wait_time = min(fifo_empty_time, 100lu); 801 udelay(wait_time); 802 fifo_empty_time -= wait_time; 803 if (!fifo_empty_time) { 804 msr = tegra_uart_read(tup, UART_MSR); 805 mcr = tegra_uart_read(tup, UART_MCR); 806 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 807 (msr & UART_MSR_CTS)) 808 dev_err(tup->uport.dev, 809 "Slave not ready\n"); 810 break; 811 } 812 lsr = tegra_uart_read(tup, UART_LSR); 813 } 814 } 815 816 spin_lock_irqsave(&tup->uport.lock, flags); 817 /* Reset the Rx and Tx FIFOs */ 818 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 819 tup->current_baud = 0; 820 spin_unlock_irqrestore(&tup->uport.lock, flags); 821 822 clk_disable_unprepare(tup->uart_clk); 823 } 824 825 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 826 { 827 int ret; 828 829 tup->fcr_shadow = 0; 830 tup->mcr_shadow = 0; 831 tup->lcr_shadow = 0; 832 tup->ier_shadow = 0; 833 tup->current_baud = 0; 834 835 clk_prepare_enable(tup->uart_clk); 836 837 /* Reset the UART controller to clear all previous status.*/ 838 reset_control_assert(tup->rst); 839 udelay(10); 840 reset_control_deassert(tup->rst); 841 842 tup->rx_in_progress = 0; 843 tup->tx_in_progress = 0; 844 845 /* 846 * Set the trigger level 847 * 848 * For PIO mode: 849 * 850 * For receive, this will interrupt the CPU after that many number of 851 * bytes are received, for the remaining bytes the receive timeout 852 * interrupt is received. Rx high watermark is set to 4. 853 * 854 * For transmit, if the trasnmit interrupt is enabled, this will 855 * interrupt the CPU when the number of entries in the FIFO reaches the 856 * low watermark. Tx low watermark is set to 16 bytes. 857 * 858 * For DMA mode: 859 * 860 * Set the Tx trigger to 16. This should match the DMA burst size that 861 * programmed in the DMA registers. 862 */ 863 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 864 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 865 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 866 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 867 868 /* 869 * Initialize the UART with default configuration 870 * (115200, N, 8, 1) so that the receive DMA buffer may be 871 * enqueued 872 */ 873 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 874 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 875 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 876 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 877 878 ret = tegra_uart_start_rx_dma(tup); 879 if (ret < 0) { 880 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); 881 return ret; 882 } 883 tup->rx_in_progress = 1; 884 885 /* 886 * Enable IE_RXS for the receive status interrupts like line errros. 887 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 888 * 889 * If using DMA mode, enable EORD instead of receive interrupt which 890 * will interrupt after the UART is done with the receive instead of 891 * the interrupt when the FIFO "threshold" is reached. 892 * 893 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 894 * the DATA is sitting in the FIFO and couldn't be transferred to the 895 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be 896 * triggered when there is a pause of the incomming data stream for 4 897 * characters long. 898 * 899 * For pauses in the data which is not aligned to 4 bytes, we get 900 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 901 * then the EORD. 902 */ 903 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; 904 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 905 return 0; 906 } 907 908 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 909 bool dma_to_memory) 910 { 911 struct dma_chan *dma_chan; 912 unsigned char *dma_buf; 913 dma_addr_t dma_phys; 914 int ret; 915 struct dma_slave_config dma_sconfig; 916 917 dma_chan = dma_request_slave_channel_reason(tup->uport.dev, 918 dma_to_memory ? "rx" : "tx"); 919 if (IS_ERR(dma_chan)) { 920 ret = PTR_ERR(dma_chan); 921 dev_err(tup->uport.dev, 922 "DMA channel alloc failed: %d\n", ret); 923 return ret; 924 } 925 926 if (dma_to_memory) { 927 dma_buf = dma_alloc_coherent(tup->uport.dev, 928 TEGRA_UART_RX_DMA_BUFFER_SIZE, 929 &dma_phys, GFP_KERNEL); 930 if (!dma_buf) { 931 dev_err(tup->uport.dev, 932 "Not able to allocate the dma buffer\n"); 933 dma_release_channel(dma_chan); 934 return -ENOMEM; 935 } 936 } else { 937 dma_phys = dma_map_single(tup->uport.dev, 938 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 939 DMA_TO_DEVICE); 940 dma_buf = tup->uport.state->xmit.buf; 941 } 942 943 if (dma_to_memory) { 944 dma_sconfig.src_addr = tup->uport.mapbase; 945 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 946 dma_sconfig.src_maxburst = 4; 947 } else { 948 dma_sconfig.dst_addr = tup->uport.mapbase; 949 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 950 dma_sconfig.dst_maxburst = 16; 951 } 952 953 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 954 if (ret < 0) { 955 dev_err(tup->uport.dev, 956 "Dma slave config failed, err = %d\n", ret); 957 goto scrub; 958 } 959 960 if (dma_to_memory) { 961 tup->rx_dma_chan = dma_chan; 962 tup->rx_dma_buf_virt = dma_buf; 963 tup->rx_dma_buf_phys = dma_phys; 964 } else { 965 tup->tx_dma_chan = dma_chan; 966 tup->tx_dma_buf_virt = dma_buf; 967 tup->tx_dma_buf_phys = dma_phys; 968 } 969 return 0; 970 971 scrub: 972 dma_release_channel(dma_chan); 973 return ret; 974 } 975 976 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 977 bool dma_to_memory) 978 { 979 struct dma_chan *dma_chan; 980 981 if (dma_to_memory) { 982 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 983 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 984 dma_chan = tup->rx_dma_chan; 985 tup->rx_dma_chan = NULL; 986 tup->rx_dma_buf_phys = 0; 987 tup->rx_dma_buf_virt = NULL; 988 } else { 989 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 990 UART_XMIT_SIZE, DMA_TO_DEVICE); 991 dma_chan = tup->tx_dma_chan; 992 tup->tx_dma_chan = NULL; 993 tup->tx_dma_buf_phys = 0; 994 tup->tx_dma_buf_virt = NULL; 995 } 996 dma_release_channel(dma_chan); 997 } 998 999 static int tegra_uart_startup(struct uart_port *u) 1000 { 1001 struct tegra_uart_port *tup = to_tegra_uport(u); 1002 int ret; 1003 1004 ret = tegra_uart_dma_channel_allocate(tup, false); 1005 if (ret < 0) { 1006 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret); 1007 return ret; 1008 } 1009 1010 ret = tegra_uart_dma_channel_allocate(tup, true); 1011 if (ret < 0) { 1012 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret); 1013 goto fail_rx_dma; 1014 } 1015 1016 ret = tegra_uart_hw_init(tup); 1017 if (ret < 0) { 1018 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1019 goto fail_hw_init; 1020 } 1021 1022 ret = request_irq(u->irq, tegra_uart_isr, 0, 1023 dev_name(u->dev), tup); 1024 if (ret < 0) { 1025 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1026 goto fail_hw_init; 1027 } 1028 return 0; 1029 1030 fail_hw_init: 1031 tegra_uart_dma_channel_free(tup, true); 1032 fail_rx_dma: 1033 tegra_uart_dma_channel_free(tup, false); 1034 return ret; 1035 } 1036 1037 /* 1038 * Flush any TX data submitted for DMA and PIO. Called when the 1039 * TX circular buffer is reset. 1040 */ 1041 static void tegra_uart_flush_buffer(struct uart_port *u) 1042 { 1043 struct tegra_uart_port *tup = to_tegra_uport(u); 1044 1045 tup->tx_bytes = 0; 1046 if (tup->tx_dma_chan) 1047 dmaengine_terminate_all(tup->tx_dma_chan); 1048 return; 1049 } 1050 1051 static void tegra_uart_shutdown(struct uart_port *u) 1052 { 1053 struct tegra_uart_port *tup = to_tegra_uport(u); 1054 1055 tegra_uart_hw_deinit(tup); 1056 1057 tup->rx_in_progress = 0; 1058 tup->tx_in_progress = 0; 1059 1060 tegra_uart_dma_channel_free(tup, true); 1061 tegra_uart_dma_channel_free(tup, false); 1062 free_irq(u->irq, tup); 1063 1064 tegra_uart_flush_buffer(u); 1065 } 1066 1067 static void tegra_uart_enable_ms(struct uart_port *u) 1068 { 1069 struct tegra_uart_port *tup = to_tegra_uport(u); 1070 1071 if (tup->enable_modem_interrupt) { 1072 tup->ier_shadow |= UART_IER_MSI; 1073 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1074 } 1075 } 1076 1077 static void tegra_uart_set_termios(struct uart_port *u, 1078 struct ktermios *termios, struct ktermios *oldtermios) 1079 { 1080 struct tegra_uart_port *tup = to_tegra_uport(u); 1081 unsigned int baud; 1082 unsigned long flags; 1083 unsigned int lcr; 1084 int symb_bit = 1; 1085 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1086 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1087 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1088 1089 max_divider *= 16; 1090 spin_lock_irqsave(&u->lock, flags); 1091 1092 /* Changing configuration, it is safe to stop any rx now */ 1093 if (tup->rts_active) 1094 set_rts(tup, false); 1095 1096 /* Clear all interrupts as configuration is going to be change */ 1097 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1098 tegra_uart_read(tup, UART_IER); 1099 tegra_uart_write(tup, 0, UART_IER); 1100 tegra_uart_read(tup, UART_IER); 1101 1102 /* Parity */ 1103 lcr = tup->lcr_shadow; 1104 lcr &= ~UART_LCR_PARITY; 1105 1106 /* CMSPAR isn't supported by this driver */ 1107 termios->c_cflag &= ~CMSPAR; 1108 1109 if ((termios->c_cflag & PARENB) == PARENB) { 1110 symb_bit++; 1111 if (termios->c_cflag & PARODD) { 1112 lcr |= UART_LCR_PARITY; 1113 lcr &= ~UART_LCR_EPAR; 1114 lcr &= ~UART_LCR_SPAR; 1115 } else { 1116 lcr |= UART_LCR_PARITY; 1117 lcr |= UART_LCR_EPAR; 1118 lcr &= ~UART_LCR_SPAR; 1119 } 1120 } 1121 1122 lcr &= ~UART_LCR_WLEN8; 1123 switch (termios->c_cflag & CSIZE) { 1124 case CS5: 1125 lcr |= UART_LCR_WLEN5; 1126 symb_bit += 5; 1127 break; 1128 case CS6: 1129 lcr |= UART_LCR_WLEN6; 1130 symb_bit += 6; 1131 break; 1132 case CS7: 1133 lcr |= UART_LCR_WLEN7; 1134 symb_bit += 7; 1135 break; 1136 default: 1137 lcr |= UART_LCR_WLEN8; 1138 symb_bit += 8; 1139 break; 1140 } 1141 1142 /* Stop bits */ 1143 if (termios->c_cflag & CSTOPB) { 1144 lcr |= UART_LCR_STOP; 1145 symb_bit += 2; 1146 } else { 1147 lcr &= ~UART_LCR_STOP; 1148 symb_bit++; 1149 } 1150 1151 tegra_uart_write(tup, lcr, UART_LCR); 1152 tup->lcr_shadow = lcr; 1153 tup->symb_bit = symb_bit; 1154 1155 /* Baud rate. */ 1156 baud = uart_get_baud_rate(u, termios, oldtermios, 1157 parent_clk_rate/max_divider, 1158 parent_clk_rate/16); 1159 spin_unlock_irqrestore(&u->lock, flags); 1160 tegra_set_baudrate(tup, baud); 1161 if (tty_termios_baud_rate(termios)) 1162 tty_termios_encode_baud_rate(termios, baud, baud); 1163 spin_lock_irqsave(&u->lock, flags); 1164 1165 /* Flow control */ 1166 if (termios->c_cflag & CRTSCTS) { 1167 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1168 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1169 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1170 /* if top layer has asked to set rts active then do so here */ 1171 if (tup->rts_active) 1172 set_rts(tup, true); 1173 } else { 1174 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1175 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1176 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1177 } 1178 1179 /* update the port timeout based on new settings */ 1180 uart_update_timeout(u, termios->c_cflag, baud); 1181 1182 /* Make sure all write has completed */ 1183 tegra_uart_read(tup, UART_IER); 1184 1185 /* Reenable interrupt */ 1186 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1187 tegra_uart_read(tup, UART_IER); 1188 1189 spin_unlock_irqrestore(&u->lock, flags); 1190 return; 1191 } 1192 1193 static const char *tegra_uart_type(struct uart_port *u) 1194 { 1195 return TEGRA_UART_TYPE; 1196 } 1197 1198 static struct uart_ops tegra_uart_ops = { 1199 .tx_empty = tegra_uart_tx_empty, 1200 .set_mctrl = tegra_uart_set_mctrl, 1201 .get_mctrl = tegra_uart_get_mctrl, 1202 .stop_tx = tegra_uart_stop_tx, 1203 .start_tx = tegra_uart_start_tx, 1204 .stop_rx = tegra_uart_stop_rx, 1205 .flush_buffer = tegra_uart_flush_buffer, 1206 .enable_ms = tegra_uart_enable_ms, 1207 .break_ctl = tegra_uart_break_ctl, 1208 .startup = tegra_uart_startup, 1209 .shutdown = tegra_uart_shutdown, 1210 .set_termios = tegra_uart_set_termios, 1211 .type = tegra_uart_type, 1212 .request_port = tegra_uart_request_port, 1213 .release_port = tegra_uart_release_port, 1214 }; 1215 1216 static struct uart_driver tegra_uart_driver = { 1217 .owner = THIS_MODULE, 1218 .driver_name = "tegra_hsuart", 1219 .dev_name = "ttyTHS", 1220 .cons = NULL, 1221 .nr = TEGRA_UART_MAXIMUM, 1222 }; 1223 1224 static int tegra_uart_parse_dt(struct platform_device *pdev, 1225 struct tegra_uart_port *tup) 1226 { 1227 struct device_node *np = pdev->dev.of_node; 1228 int port; 1229 1230 port = of_alias_get_id(np, "serial"); 1231 if (port < 0) { 1232 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1233 return port; 1234 } 1235 tup->uport.line = port; 1236 1237 tup->enable_modem_interrupt = of_property_read_bool(np, 1238 "nvidia,enable-modem-interrupt"); 1239 return 0; 1240 } 1241 1242 static struct tegra_uart_chip_data tegra20_uart_chip_data = { 1243 .tx_fifo_full_status = false, 1244 .allow_txfifo_reset_fifo_mode = true, 1245 .support_clk_src_div = false, 1246 }; 1247 1248 static struct tegra_uart_chip_data tegra30_uart_chip_data = { 1249 .tx_fifo_full_status = true, 1250 .allow_txfifo_reset_fifo_mode = false, 1251 .support_clk_src_div = true, 1252 }; 1253 1254 static struct of_device_id tegra_uart_of_match[] = { 1255 { 1256 .compatible = "nvidia,tegra30-hsuart", 1257 .data = &tegra30_uart_chip_data, 1258 }, { 1259 .compatible = "nvidia,tegra20-hsuart", 1260 .data = &tegra20_uart_chip_data, 1261 }, { 1262 }, 1263 }; 1264 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1265 1266 static int tegra_uart_probe(struct platform_device *pdev) 1267 { 1268 struct tegra_uart_port *tup; 1269 struct uart_port *u; 1270 struct resource *resource; 1271 int ret; 1272 const struct tegra_uart_chip_data *cdata; 1273 const struct of_device_id *match; 1274 1275 match = of_match_device(tegra_uart_of_match, &pdev->dev); 1276 if (!match) { 1277 dev_err(&pdev->dev, "Error: No device match found\n"); 1278 return -ENODEV; 1279 } 1280 cdata = match->data; 1281 1282 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1283 if (!tup) { 1284 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1285 return -ENOMEM; 1286 } 1287 1288 ret = tegra_uart_parse_dt(pdev, tup); 1289 if (ret < 0) 1290 return ret; 1291 1292 u = &tup->uport; 1293 u->dev = &pdev->dev; 1294 u->ops = &tegra_uart_ops; 1295 u->type = PORT_TEGRA; 1296 u->fifosize = 32; 1297 tup->cdata = cdata; 1298 1299 platform_set_drvdata(pdev, tup); 1300 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1301 if (!resource) { 1302 dev_err(&pdev->dev, "No IO memory resource\n"); 1303 return -ENODEV; 1304 } 1305 1306 u->mapbase = resource->start; 1307 u->membase = devm_ioremap_resource(&pdev->dev, resource); 1308 if (IS_ERR(u->membase)) 1309 return PTR_ERR(u->membase); 1310 1311 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1312 if (IS_ERR(tup->uart_clk)) { 1313 dev_err(&pdev->dev, "Couldn't get the clock\n"); 1314 return PTR_ERR(tup->uart_clk); 1315 } 1316 1317 tup->rst = devm_reset_control_get(&pdev->dev, "serial"); 1318 if (IS_ERR(tup->rst)) { 1319 dev_err(&pdev->dev, "Couldn't get the reset\n"); 1320 return PTR_ERR(tup->rst); 1321 } 1322 1323 u->iotype = UPIO_MEM32; 1324 u->irq = platform_get_irq(pdev, 0); 1325 u->regshift = 2; 1326 ret = uart_add_one_port(&tegra_uart_driver, u); 1327 if (ret < 0) { 1328 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1329 return ret; 1330 } 1331 return ret; 1332 } 1333 1334 static int tegra_uart_remove(struct platform_device *pdev) 1335 { 1336 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1337 struct uart_port *u = &tup->uport; 1338 1339 uart_remove_one_port(&tegra_uart_driver, u); 1340 return 0; 1341 } 1342 1343 #ifdef CONFIG_PM_SLEEP 1344 static int tegra_uart_suspend(struct device *dev) 1345 { 1346 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1347 struct uart_port *u = &tup->uport; 1348 1349 return uart_suspend_port(&tegra_uart_driver, u); 1350 } 1351 1352 static int tegra_uart_resume(struct device *dev) 1353 { 1354 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1355 struct uart_port *u = &tup->uport; 1356 1357 return uart_resume_port(&tegra_uart_driver, u); 1358 } 1359 #endif 1360 1361 static const struct dev_pm_ops tegra_uart_pm_ops = { 1362 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1363 }; 1364 1365 static struct platform_driver tegra_uart_platform_driver = { 1366 .probe = tegra_uart_probe, 1367 .remove = tegra_uart_remove, 1368 .driver = { 1369 .name = "serial-tegra", 1370 .of_match_table = tegra_uart_of_match, 1371 .pm = &tegra_uart_pm_ops, 1372 }, 1373 }; 1374 1375 static int __init tegra_uart_init(void) 1376 { 1377 int ret; 1378 1379 ret = uart_register_driver(&tegra_uart_driver); 1380 if (ret < 0) { 1381 pr_err("Could not register %s driver\n", 1382 tegra_uart_driver.driver_name); 1383 return ret; 1384 } 1385 1386 ret = platform_driver_register(&tegra_uart_platform_driver); 1387 if (ret < 0) { 1388 pr_err("Uart platform driver register failed, e = %d\n", ret); 1389 uart_unregister_driver(&tegra_uart_driver); 1390 return ret; 1391 } 1392 return 0; 1393 } 1394 1395 static void __exit tegra_uart_exit(void) 1396 { 1397 pr_info("Unloading tegra uart driver\n"); 1398 platform_driver_unregister(&tegra_uart_platform_driver); 1399 uart_unregister_driver(&tegra_uart_driver); 1400 } 1401 1402 module_init(tegra_uart_init); 1403 module_exit(tegra_uart_exit); 1404 1405 MODULE_ALIAS("platform:serial-tegra"); 1406 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1407 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1408 MODULE_LICENSE("GPL v2"); 1409