1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * serial_tegra.c 4 * 5 * High-speed serial driver for NVIDIA Tegra SoCs 6 * 7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved. 8 * 9 * Author: Laxman Dewangan <ldewangan@nvidia.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/pagemap.h> 25 #include <linux/platform_device.h> 26 #include <linux/reset.h> 27 #include <linux/serial.h> 28 #include <linux/serial_8250.h> 29 #include <linux/serial_core.h> 30 #include <linux/serial_reg.h> 31 #include <linux/slab.h> 32 #include <linux/string.h> 33 #include <linux/termios.h> 34 #include <linux/tty.h> 35 #include <linux/tty_flip.h> 36 37 #define TEGRA_UART_TYPE "TEGRA_UART" 38 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 39 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 40 41 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 42 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 43 #define TEGRA_UART_IER_EORD 0x20 44 #define TEGRA_UART_MCR_RTS_EN 0x40 45 #define TEGRA_UART_MCR_CTS_EN 0x20 46 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 47 UART_LSR_PE | UART_LSR_FE) 48 #define TEGRA_UART_IRDA_CSR 0x08 49 #define TEGRA_UART_SIR_ENABLED 0x80 50 51 #define TEGRA_UART_TX_PIO 1 52 #define TEGRA_UART_TX_DMA 2 53 #define TEGRA_UART_MIN_DMA 16 54 #define TEGRA_UART_FIFO_SIZE 32 55 56 /* 57 * Tx fifo trigger level setting in tegra uart is in 58 * reverse way then conventional uart. 59 */ 60 #define TEGRA_UART_TX_TRIG_16B 0x00 61 #define TEGRA_UART_TX_TRIG_8B 0x10 62 #define TEGRA_UART_TX_TRIG_4B 0x20 63 #define TEGRA_UART_TX_TRIG_1B 0x30 64 65 #define TEGRA_UART_MAXIMUM 8 66 67 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 68 #define TEGRA_UART_DEFAULT_BAUD 115200 69 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 70 71 /* Tx transfer mode */ 72 #define TEGRA_TX_PIO 1 73 #define TEGRA_TX_DMA 2 74 75 #define TEGRA_UART_FCR_IIR_FIFO_EN 0x40 76 77 /** 78 * tegra_uart_chip_data: SOC specific data. 79 * 80 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 82 * Tegra30 does not allow this. 83 * @support_clk_src_div: Clock source support the clock divider. 84 */ 85 struct tegra_uart_chip_data { 86 bool tx_fifo_full_status; 87 bool allow_txfifo_reset_fifo_mode; 88 bool support_clk_src_div; 89 bool fifo_mode_enable_status; 90 int uart_max_port; 91 int max_dma_burst_bytes; 92 int error_tolerance_low_range; 93 int error_tolerance_high_range; 94 }; 95 96 struct tegra_baud_tolerance { 97 u32 lower_range_baud; 98 u32 upper_range_baud; 99 s32 tolerance; 100 }; 101 102 struct tegra_uart_port { 103 struct uart_port uport; 104 const struct tegra_uart_chip_data *cdata; 105 106 struct clk *uart_clk; 107 struct reset_control *rst; 108 unsigned int current_baud; 109 110 /* Register shadow */ 111 unsigned long fcr_shadow; 112 unsigned long mcr_shadow; 113 unsigned long lcr_shadow; 114 unsigned long ier_shadow; 115 bool rts_active; 116 117 int tx_in_progress; 118 unsigned int tx_bytes; 119 120 bool enable_modem_interrupt; 121 122 bool rx_timeout; 123 int rx_in_progress; 124 int symb_bit; 125 126 struct dma_chan *rx_dma_chan; 127 struct dma_chan *tx_dma_chan; 128 dma_addr_t rx_dma_buf_phys; 129 dma_addr_t tx_dma_buf_phys; 130 unsigned char *rx_dma_buf_virt; 131 unsigned char *tx_dma_buf_virt; 132 struct dma_async_tx_descriptor *tx_dma_desc; 133 struct dma_async_tx_descriptor *rx_dma_desc; 134 dma_cookie_t tx_cookie; 135 dma_cookie_t rx_cookie; 136 unsigned int tx_bytes_requested; 137 unsigned int rx_bytes_requested; 138 struct tegra_baud_tolerance *baud_tolerance; 139 int n_adjustable_baud_rates; 140 int required_rate; 141 int configured_rate; 142 bool use_rx_pio; 143 bool use_tx_pio; 144 bool rx_dma_active; 145 }; 146 147 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 148 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 149 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 150 bool dma_to_memory); 151 152 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 153 unsigned long reg) 154 { 155 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 156 } 157 158 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 159 unsigned long reg) 160 { 161 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 162 } 163 164 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 165 { 166 return container_of(u, struct tegra_uart_port, uport); 167 } 168 169 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 170 { 171 struct tegra_uart_port *tup = to_tegra_uport(u); 172 173 /* 174 * RI - Ring detector is active 175 * CD/DCD/CAR - Carrier detect is always active. For some reason 176 * linux has different names for carrier detect. 177 * DSR - Data Set ready is active as the hardware doesn't support it. 178 * Don't know if the linux support this yet? 179 * CTS - Clear to send. Always set to active, as the hardware handles 180 * CTS automatically. 181 */ 182 if (tup->enable_modem_interrupt) 183 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 184 return TIOCM_CTS; 185 } 186 187 static void set_rts(struct tegra_uart_port *tup, bool active) 188 { 189 unsigned long mcr; 190 191 mcr = tup->mcr_shadow; 192 if (active) 193 mcr |= TEGRA_UART_MCR_RTS_EN; 194 else 195 mcr &= ~TEGRA_UART_MCR_RTS_EN; 196 if (mcr != tup->mcr_shadow) { 197 tegra_uart_write(tup, mcr, UART_MCR); 198 tup->mcr_shadow = mcr; 199 } 200 } 201 202 static void set_dtr(struct tegra_uart_port *tup, bool active) 203 { 204 unsigned long mcr; 205 206 mcr = tup->mcr_shadow; 207 if (active) 208 mcr |= UART_MCR_DTR; 209 else 210 mcr &= ~UART_MCR_DTR; 211 if (mcr != tup->mcr_shadow) { 212 tegra_uart_write(tup, mcr, UART_MCR); 213 tup->mcr_shadow = mcr; 214 } 215 } 216 217 static void set_loopbk(struct tegra_uart_port *tup, bool active) 218 { 219 unsigned long mcr = tup->mcr_shadow; 220 221 if (active) 222 mcr |= UART_MCR_LOOP; 223 else 224 mcr &= ~UART_MCR_LOOP; 225 226 if (mcr != tup->mcr_shadow) { 227 tegra_uart_write(tup, mcr, UART_MCR); 228 tup->mcr_shadow = mcr; 229 } 230 } 231 232 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 233 { 234 struct tegra_uart_port *tup = to_tegra_uport(u); 235 int enable; 236 237 tup->rts_active = !!(mctrl & TIOCM_RTS); 238 set_rts(tup, tup->rts_active); 239 240 enable = !!(mctrl & TIOCM_DTR); 241 set_dtr(tup, enable); 242 243 enable = !!(mctrl & TIOCM_LOOP); 244 set_loopbk(tup, enable); 245 } 246 247 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 248 { 249 struct tegra_uart_port *tup = to_tegra_uport(u); 250 unsigned long lcr; 251 252 lcr = tup->lcr_shadow; 253 if (break_ctl) 254 lcr |= UART_LCR_SBC; 255 else 256 lcr &= ~UART_LCR_SBC; 257 tegra_uart_write(tup, lcr, UART_LCR); 258 tup->lcr_shadow = lcr; 259 } 260 261 /** 262 * tegra_uart_wait_cycle_time: Wait for N UART clock periods 263 * 264 * @tup: Tegra serial port data structure. 265 * @cycles: Number of clock periods to wait. 266 * 267 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART 268 * clock speed is 16X the current baud rate. 269 */ 270 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, 271 unsigned int cycles) 272 { 273 if (tup->current_baud) 274 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); 275 } 276 277 /* Wait for a symbol-time. */ 278 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 279 unsigned int syms) 280 { 281 if (tup->current_baud) 282 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 283 tup->current_baud)); 284 } 285 286 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup) 287 { 288 unsigned long iir; 289 unsigned int tmout = 100; 290 291 do { 292 iir = tegra_uart_read(tup, UART_IIR); 293 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN) 294 return 0; 295 udelay(1); 296 } while (--tmout); 297 298 return -ETIMEDOUT; 299 } 300 301 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 302 { 303 unsigned long fcr = tup->fcr_shadow; 304 unsigned int lsr, tmout = 10000; 305 306 if (tup->rts_active) 307 set_rts(tup, false); 308 309 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 310 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 311 tegra_uart_write(tup, fcr, UART_FCR); 312 } else { 313 fcr &= ~UART_FCR_ENABLE_FIFO; 314 tegra_uart_write(tup, fcr, UART_FCR); 315 udelay(60); 316 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 317 tegra_uart_write(tup, fcr, UART_FCR); 318 fcr |= UART_FCR_ENABLE_FIFO; 319 tegra_uart_write(tup, fcr, UART_FCR); 320 if (tup->cdata->fifo_mode_enable_status) 321 tegra_uart_wait_fifo_mode_enabled(tup); 322 } 323 324 /* Dummy read to ensure the write is posted */ 325 tegra_uart_read(tup, UART_SCR); 326 327 /* 328 * For all tegra devices (up to t210), there is a hardware issue that 329 * requires software to wait for 32 UART clock periods for the flush 330 * to propagate, otherwise data could be lost. 331 */ 332 tegra_uart_wait_cycle_time(tup, 32); 333 334 do { 335 lsr = tegra_uart_read(tup, UART_LSR); 336 if ((lsr | UART_LSR_TEMT) && !(lsr & UART_LSR_DR)) 337 break; 338 udelay(1); 339 } while (--tmout); 340 341 if (tup->rts_active) 342 set_rts(tup, true); 343 } 344 345 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup, 346 unsigned int baud, long rate) 347 { 348 int i; 349 350 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { 351 if (baud >= tup->baud_tolerance[i].lower_range_baud && 352 baud <= tup->baud_tolerance[i].upper_range_baud) 353 return (rate + (rate * 354 tup->baud_tolerance[i].tolerance) / 10000); 355 } 356 357 return rate; 358 } 359 360 static int tegra_check_rate_in_range(struct tegra_uart_port *tup) 361 { 362 long diff; 363 364 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) 365 / tup->required_rate; 366 if (diff < (tup->cdata->error_tolerance_low_range * 100) || 367 diff > (tup->cdata->error_tolerance_high_range * 100)) { 368 dev_err(tup->uport.dev, 369 "configured baud rate is out of range by %ld", diff); 370 return -EIO; 371 } 372 373 return 0; 374 } 375 376 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 377 { 378 unsigned long rate; 379 unsigned int divisor; 380 unsigned long lcr; 381 unsigned long flags; 382 int ret; 383 384 if (tup->current_baud == baud) 385 return 0; 386 387 if (tup->cdata->support_clk_src_div) { 388 rate = baud * 16; 389 tup->required_rate = rate; 390 391 if (tup->n_adjustable_baud_rates) 392 rate = tegra_get_tolerance_rate(tup, baud, rate); 393 394 ret = clk_set_rate(tup->uart_clk, rate); 395 if (ret < 0) { 396 dev_err(tup->uport.dev, 397 "clk_set_rate() failed for rate %lu\n", rate); 398 return ret; 399 } 400 tup->configured_rate = clk_get_rate(tup->uart_clk); 401 divisor = 1; 402 ret = tegra_check_rate_in_range(tup); 403 if (ret < 0) 404 return ret; 405 } else { 406 rate = clk_get_rate(tup->uart_clk); 407 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 408 } 409 410 spin_lock_irqsave(&tup->uport.lock, flags); 411 lcr = tup->lcr_shadow; 412 lcr |= UART_LCR_DLAB; 413 tegra_uart_write(tup, lcr, UART_LCR); 414 415 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 416 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 417 418 lcr &= ~UART_LCR_DLAB; 419 tegra_uart_write(tup, lcr, UART_LCR); 420 421 /* Dummy read to ensure the write is posted */ 422 tegra_uart_read(tup, UART_SCR); 423 spin_unlock_irqrestore(&tup->uport.lock, flags); 424 425 tup->current_baud = baud; 426 427 /* wait two character intervals at new rate */ 428 tegra_uart_wait_sym_time(tup, 2); 429 return 0; 430 } 431 432 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 433 unsigned long lsr) 434 { 435 char flag = TTY_NORMAL; 436 437 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 438 if (lsr & UART_LSR_OE) { 439 /* Overrrun error */ 440 flag = TTY_OVERRUN; 441 tup->uport.icount.overrun++; 442 dev_err(tup->uport.dev, "Got overrun errors\n"); 443 } else if (lsr & UART_LSR_PE) { 444 /* Parity error */ 445 flag = TTY_PARITY; 446 tup->uport.icount.parity++; 447 dev_err(tup->uport.dev, "Got Parity errors\n"); 448 } else if (lsr & UART_LSR_FE) { 449 flag = TTY_FRAME; 450 tup->uport.icount.frame++; 451 dev_err(tup->uport.dev, "Got frame errors\n"); 452 } else if (lsr & UART_LSR_BI) { 453 /* 454 * Break error 455 * If FIFO read error without any data, reset Rx FIFO 456 */ 457 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 458 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 459 if (tup->uport.ignore_status_mask & UART_LSR_BI) 460 return TTY_BREAK; 461 flag = TTY_BREAK; 462 tup->uport.icount.brk++; 463 dev_dbg(tup->uport.dev, "Got Break\n"); 464 } 465 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); 466 } 467 468 return flag; 469 } 470 471 static int tegra_uart_request_port(struct uart_port *u) 472 { 473 return 0; 474 } 475 476 static void tegra_uart_release_port(struct uart_port *u) 477 { 478 /* Nothing to do here */ 479 } 480 481 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 482 { 483 struct circ_buf *xmit = &tup->uport.state->xmit; 484 int i; 485 486 for (i = 0; i < max_bytes; i++) { 487 BUG_ON(uart_circ_empty(xmit)); 488 if (tup->cdata->tx_fifo_full_status) { 489 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 490 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 491 break; 492 } 493 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 494 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 495 tup->uport.icount.tx++; 496 } 497 } 498 499 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 500 unsigned int bytes) 501 { 502 if (bytes > TEGRA_UART_MIN_DMA) 503 bytes = TEGRA_UART_MIN_DMA; 504 505 tup->tx_in_progress = TEGRA_UART_TX_PIO; 506 tup->tx_bytes = bytes; 507 tup->ier_shadow |= UART_IER_THRI; 508 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 509 } 510 511 static void tegra_uart_tx_dma_complete(void *args) 512 { 513 struct tegra_uart_port *tup = args; 514 struct circ_buf *xmit = &tup->uport.state->xmit; 515 struct dma_tx_state state; 516 unsigned long flags; 517 unsigned int count; 518 519 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 520 count = tup->tx_bytes_requested - state.residue; 521 async_tx_ack(tup->tx_dma_desc); 522 spin_lock_irqsave(&tup->uport.lock, flags); 523 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 524 tup->tx_in_progress = 0; 525 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 526 uart_write_wakeup(&tup->uport); 527 tegra_uart_start_next_tx(tup); 528 spin_unlock_irqrestore(&tup->uport.lock, flags); 529 } 530 531 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 532 unsigned long count) 533 { 534 struct circ_buf *xmit = &tup->uport.state->xmit; 535 dma_addr_t tx_phys_addr; 536 537 tup->tx_bytes = count & ~(0xF); 538 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 539 540 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, 541 tup->tx_bytes, DMA_TO_DEVICE); 542 543 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 544 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 545 DMA_PREP_INTERRUPT); 546 if (!tup->tx_dma_desc) { 547 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 548 return -EIO; 549 } 550 551 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 552 tup->tx_dma_desc->callback_param = tup; 553 tup->tx_in_progress = TEGRA_UART_TX_DMA; 554 tup->tx_bytes_requested = tup->tx_bytes; 555 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 556 dma_async_issue_pending(tup->tx_dma_chan); 557 return 0; 558 } 559 560 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 561 { 562 unsigned long tail; 563 unsigned long count; 564 struct circ_buf *xmit = &tup->uport.state->xmit; 565 566 if (!tup->current_baud) 567 return; 568 569 tail = (unsigned long)&xmit->buf[xmit->tail]; 570 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 571 if (!count) 572 return; 573 574 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) 575 tegra_uart_start_pio_tx(tup, count); 576 else if (BYTES_TO_ALIGN(tail) > 0) 577 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 578 else 579 tegra_uart_start_tx_dma(tup, count); 580 } 581 582 /* Called by serial core driver with u->lock taken. */ 583 static void tegra_uart_start_tx(struct uart_port *u) 584 { 585 struct tegra_uart_port *tup = to_tegra_uport(u); 586 struct circ_buf *xmit = &u->state->xmit; 587 588 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 589 tegra_uart_start_next_tx(tup); 590 } 591 592 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 593 { 594 struct tegra_uart_port *tup = to_tegra_uport(u); 595 unsigned int ret = 0; 596 unsigned long flags; 597 598 spin_lock_irqsave(&u->lock, flags); 599 if (!tup->tx_in_progress) { 600 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 601 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 602 ret = TIOCSER_TEMT; 603 } 604 spin_unlock_irqrestore(&u->lock, flags); 605 return ret; 606 } 607 608 static void tegra_uart_stop_tx(struct uart_port *u) 609 { 610 struct tegra_uart_port *tup = to_tegra_uport(u); 611 struct circ_buf *xmit = &tup->uport.state->xmit; 612 struct dma_tx_state state; 613 unsigned int count; 614 615 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) 616 return; 617 618 dmaengine_terminate_all(tup->tx_dma_chan); 619 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 620 count = tup->tx_bytes_requested - state.residue; 621 async_tx_ack(tup->tx_dma_desc); 622 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 623 tup->tx_in_progress = 0; 624 } 625 626 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 627 { 628 struct circ_buf *xmit = &tup->uport.state->xmit; 629 630 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 631 tup->tx_in_progress = 0; 632 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 633 uart_write_wakeup(&tup->uport); 634 tegra_uart_start_next_tx(tup); 635 } 636 637 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 638 struct tty_port *tty) 639 { 640 do { 641 char flag = TTY_NORMAL; 642 unsigned long lsr = 0; 643 unsigned char ch; 644 645 lsr = tegra_uart_read(tup, UART_LSR); 646 if (!(lsr & UART_LSR_DR)) 647 break; 648 649 flag = tegra_uart_decode_rx_error(tup, lsr); 650 if (flag != TTY_NORMAL) 651 continue; 652 653 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 654 tup->uport.icount.rx++; 655 656 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) 657 tty_insert_flip_char(tty, ch, flag); 658 659 if (tup->uport.ignore_status_mask & UART_LSR_DR) 660 continue; 661 } while (1); 662 } 663 664 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 665 struct tty_port *tty, 666 unsigned int count) 667 { 668 int copied; 669 670 /* If count is zero, then there is no data to be copied */ 671 if (!count) 672 return; 673 674 tup->uport.icount.rx += count; 675 if (!tty) { 676 dev_err(tup->uport.dev, "No tty port\n"); 677 return; 678 } 679 680 if (tup->uport.ignore_status_mask & UART_LSR_DR) 681 return; 682 683 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 684 count, DMA_FROM_DEVICE); 685 copied = tty_insert_flip_string(tty, 686 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 687 if (copied != count) { 688 WARN_ON(1); 689 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 690 } 691 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 692 count, DMA_TO_DEVICE); 693 } 694 695 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, 696 unsigned int residue) 697 { 698 struct tty_port *port = &tup->uport.state->port; 699 struct tty_struct *tty = tty_port_tty_get(port); 700 unsigned int count; 701 702 async_tx_ack(tup->rx_dma_desc); 703 count = tup->rx_bytes_requested - residue; 704 705 /* If we are here, DMA is stopped */ 706 tegra_uart_copy_rx_to_tty(tup, port, count); 707 708 tegra_uart_handle_rx_pio(tup, port); 709 if (tty) { 710 tty_flip_buffer_push(port); 711 tty_kref_put(tty); 712 } 713 } 714 715 static void tegra_uart_rx_dma_complete(void *args) 716 { 717 struct tegra_uart_port *tup = args; 718 struct uart_port *u = &tup->uport; 719 unsigned long flags; 720 struct dma_tx_state state; 721 enum dma_status status; 722 723 spin_lock_irqsave(&u->lock, flags); 724 725 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 726 727 if (status == DMA_IN_PROGRESS) { 728 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); 729 goto done; 730 } 731 732 /* Deactivate flow control to stop sender */ 733 if (tup->rts_active) 734 set_rts(tup, false); 735 736 tup->rx_dma_active = false; 737 tegra_uart_rx_buffer_push(tup, 0); 738 tegra_uart_start_rx_dma(tup); 739 740 /* Activate flow control to start transfer */ 741 if (tup->rts_active) 742 set_rts(tup, true); 743 744 done: 745 spin_unlock_irqrestore(&u->lock, flags); 746 } 747 748 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) 749 { 750 struct dma_tx_state state; 751 752 if (!tup->rx_dma_active) 753 return; 754 755 dmaengine_terminate_all(tup->rx_dma_chan); 756 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 757 758 tegra_uart_rx_buffer_push(tup, state.residue); 759 tup->rx_dma_active = false; 760 } 761 762 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) 763 { 764 /* Deactivate flow control to stop sender */ 765 if (tup->rts_active) 766 set_rts(tup, false); 767 768 tegra_uart_terminate_rx_dma(tup); 769 770 if (tup->rts_active) 771 set_rts(tup, true); 772 } 773 774 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 775 { 776 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 777 778 if (tup->rx_dma_active) 779 return 0; 780 781 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 782 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 783 DMA_PREP_INTERRUPT); 784 if (!tup->rx_dma_desc) { 785 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 786 return -EIO; 787 } 788 789 tup->rx_dma_active = true; 790 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 791 tup->rx_dma_desc->callback_param = tup; 792 tup->rx_bytes_requested = count; 793 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 794 dma_async_issue_pending(tup->rx_dma_chan); 795 return 0; 796 } 797 798 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 799 { 800 struct tegra_uart_port *tup = to_tegra_uport(u); 801 unsigned long msr; 802 803 msr = tegra_uart_read(tup, UART_MSR); 804 if (!(msr & UART_MSR_ANY_DELTA)) 805 return; 806 807 if (msr & UART_MSR_TERI) 808 tup->uport.icount.rng++; 809 if (msr & UART_MSR_DDSR) 810 tup->uport.icount.dsr++; 811 /* We may only get DDCD when HW init and reset */ 812 if (msr & UART_MSR_DDCD) 813 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 814 /* Will start/stop_tx accordingly */ 815 if (msr & UART_MSR_DCTS) 816 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 817 } 818 819 static void do_handle_rx_pio(struct tegra_uart_port *tup) 820 { 821 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 822 struct tty_port *port = &tup->uport.state->port; 823 824 tegra_uart_handle_rx_pio(tup, port); 825 if (tty) { 826 tty_flip_buffer_push(port); 827 tty_kref_put(tty); 828 } 829 } 830 831 static irqreturn_t tegra_uart_isr(int irq, void *data) 832 { 833 struct tegra_uart_port *tup = data; 834 struct uart_port *u = &tup->uport; 835 unsigned long iir; 836 unsigned long ier; 837 bool is_rx_start = false; 838 bool is_rx_int = false; 839 unsigned long flags; 840 841 spin_lock_irqsave(&u->lock, flags); 842 while (1) { 843 iir = tegra_uart_read(tup, UART_IIR); 844 if (iir & UART_IIR_NO_INT) { 845 if (!tup->use_rx_pio && is_rx_int) { 846 tegra_uart_handle_rx_dma(tup); 847 if (tup->rx_in_progress) { 848 ier = tup->ier_shadow; 849 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 850 TEGRA_UART_IER_EORD | UART_IER_RDI); 851 tup->ier_shadow = ier; 852 tegra_uart_write(tup, ier, UART_IER); 853 } 854 } else if (is_rx_start) { 855 tegra_uart_start_rx_dma(tup); 856 } 857 spin_unlock_irqrestore(&u->lock, flags); 858 return IRQ_HANDLED; 859 } 860 861 switch ((iir >> 1) & 0x7) { 862 case 0: /* Modem signal change interrupt */ 863 tegra_uart_handle_modem_signal_change(u); 864 break; 865 866 case 1: /* Transmit interrupt only triggered when using PIO */ 867 tup->ier_shadow &= ~UART_IER_THRI; 868 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 869 tegra_uart_handle_tx_pio(tup); 870 break; 871 872 case 4: /* End of data */ 873 case 6: /* Rx timeout */ 874 if (!tup->use_rx_pio) { 875 is_rx_int = tup->rx_in_progress; 876 /* Disable Rx interrupts */ 877 ier = tup->ier_shadow; 878 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 879 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 880 tup->ier_shadow = ier; 881 tegra_uart_write(tup, ier, UART_IER); 882 break; 883 } 884 /* Fall through */ 885 case 2: /* Receive */ 886 if (!tup->use_rx_pio) { 887 is_rx_start = tup->rx_in_progress; 888 tup->ier_shadow &= ~UART_IER_RDI; 889 tegra_uart_write(tup, tup->ier_shadow, 890 UART_IER); 891 } else { 892 do_handle_rx_pio(tup); 893 } 894 break; 895 896 case 3: /* Receive error */ 897 tegra_uart_decode_rx_error(tup, 898 tegra_uart_read(tup, UART_LSR)); 899 break; 900 901 case 5: /* break nothing to handle */ 902 case 7: /* break nothing to handle */ 903 break; 904 } 905 } 906 } 907 908 static void tegra_uart_stop_rx(struct uart_port *u) 909 { 910 struct tegra_uart_port *tup = to_tegra_uport(u); 911 struct tty_port *port = &tup->uport.state->port; 912 unsigned long ier; 913 914 if (tup->rts_active) 915 set_rts(tup, false); 916 917 if (!tup->rx_in_progress) 918 return; 919 920 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */ 921 922 ier = tup->ier_shadow; 923 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 924 TEGRA_UART_IER_EORD); 925 tup->ier_shadow = ier; 926 tegra_uart_write(tup, ier, UART_IER); 927 tup->rx_in_progress = 0; 928 929 if (!tup->use_rx_pio) 930 tegra_uart_terminate_rx_dma(tup); 931 else 932 tegra_uart_handle_rx_pio(tup, port); 933 } 934 935 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 936 { 937 unsigned long flags; 938 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 939 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 940 unsigned long wait_time; 941 unsigned long lsr; 942 unsigned long msr; 943 unsigned long mcr; 944 945 /* Disable interrupts */ 946 tegra_uart_write(tup, 0, UART_IER); 947 948 lsr = tegra_uart_read(tup, UART_LSR); 949 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 950 msr = tegra_uart_read(tup, UART_MSR); 951 mcr = tegra_uart_read(tup, UART_MCR); 952 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 953 dev_err(tup->uport.dev, 954 "Tx Fifo not empty, CTS disabled, waiting\n"); 955 956 /* Wait for Tx fifo to be empty */ 957 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 958 wait_time = min(fifo_empty_time, 100lu); 959 udelay(wait_time); 960 fifo_empty_time -= wait_time; 961 if (!fifo_empty_time) { 962 msr = tegra_uart_read(tup, UART_MSR); 963 mcr = tegra_uart_read(tup, UART_MCR); 964 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 965 (msr & UART_MSR_CTS)) 966 dev_err(tup->uport.dev, 967 "Slave not ready\n"); 968 break; 969 } 970 lsr = tegra_uart_read(tup, UART_LSR); 971 } 972 } 973 974 spin_lock_irqsave(&tup->uport.lock, flags); 975 /* Reset the Rx and Tx FIFOs */ 976 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 977 tup->current_baud = 0; 978 spin_unlock_irqrestore(&tup->uport.lock, flags); 979 980 tup->rx_in_progress = 0; 981 tup->tx_in_progress = 0; 982 983 if (!tup->use_rx_pio) 984 tegra_uart_dma_channel_free(tup, true); 985 if (!tup->use_tx_pio) 986 tegra_uart_dma_channel_free(tup, false); 987 988 clk_disable_unprepare(tup->uart_clk); 989 } 990 991 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 992 { 993 int ret; 994 995 tup->fcr_shadow = 0; 996 tup->mcr_shadow = 0; 997 tup->lcr_shadow = 0; 998 tup->ier_shadow = 0; 999 tup->current_baud = 0; 1000 1001 clk_prepare_enable(tup->uart_clk); 1002 1003 /* Reset the UART controller to clear all previous status.*/ 1004 reset_control_assert(tup->rst); 1005 udelay(10); 1006 reset_control_deassert(tup->rst); 1007 1008 tup->rx_in_progress = 0; 1009 tup->tx_in_progress = 0; 1010 1011 /* 1012 * Set the trigger level 1013 * 1014 * For PIO mode: 1015 * 1016 * For receive, this will interrupt the CPU after that many number of 1017 * bytes are received, for the remaining bytes the receive timeout 1018 * interrupt is received. Rx high watermark is set to 4. 1019 * 1020 * For transmit, if the trasnmit interrupt is enabled, this will 1021 * interrupt the CPU when the number of entries in the FIFO reaches the 1022 * low watermark. Tx low watermark is set to 16 bytes. 1023 * 1024 * For DMA mode: 1025 * 1026 * Set the Tx trigger to 16. This should match the DMA burst size that 1027 * programmed in the DMA registers. 1028 */ 1029 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 1030 1031 if (tup->use_rx_pio) { 1032 tup->fcr_shadow |= UART_FCR_R_TRIG_11; 1033 } else { 1034 if (tup->cdata->max_dma_burst_bytes == 8) 1035 tup->fcr_shadow |= UART_FCR_R_TRIG_10; 1036 else 1037 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 1038 } 1039 1040 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 1041 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 1042 1043 /* Dummy read to ensure the write is posted */ 1044 tegra_uart_read(tup, UART_SCR); 1045 1046 if (tup->cdata->fifo_mode_enable_status) { 1047 ret = tegra_uart_wait_fifo_mode_enabled(tup); 1048 dev_err(tup->uport.dev, "FIFO mode not enabled\n"); 1049 if (ret < 0) 1050 return ret; 1051 } else { 1052 /* 1053 * For all tegra devices (up to t210), there is a hardware 1054 * issue that requires software to wait for 3 UART clock 1055 * periods after enabling the TX fifo, otherwise data could 1056 * be lost. 1057 */ 1058 tegra_uart_wait_cycle_time(tup, 3); 1059 } 1060 1061 /* 1062 * Initialize the UART with default configuration 1063 * (115200, N, 8, 1) so that the receive DMA buffer may be 1064 * enqueued 1065 */ 1066 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 1067 if (ret < 0) { 1068 dev_err(tup->uport.dev, "Failed to set baud rate\n"); 1069 return ret; 1070 } 1071 if (!tup->use_rx_pio) { 1072 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 1073 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 1074 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 1075 } else { 1076 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 1077 } 1078 tup->rx_in_progress = 1; 1079 1080 /* 1081 * Enable IE_RXS for the receive status interrupts like line errros. 1082 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 1083 * 1084 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 1085 * the DATA is sitting in the FIFO and couldn't be transferred to the 1086 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be 1087 * triggered when there is a pause of the incomming data stream for 4 1088 * characters long. 1089 * 1090 * For pauses in the data which is not aligned to 4 bytes, we get 1091 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 1092 * then the EORD. 1093 */ 1094 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; 1095 1096 /* 1097 * If using DMA mode, enable EORD interrupt to notify about RX 1098 * completion. 1099 */ 1100 if (!tup->use_rx_pio) 1101 tup->ier_shadow |= TEGRA_UART_IER_EORD; 1102 1103 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1104 return 0; 1105 } 1106 1107 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 1108 bool dma_to_memory) 1109 { 1110 if (dma_to_memory) { 1111 dmaengine_terminate_all(tup->rx_dma_chan); 1112 dma_release_channel(tup->rx_dma_chan); 1113 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 1114 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 1115 tup->rx_dma_chan = NULL; 1116 tup->rx_dma_buf_phys = 0; 1117 tup->rx_dma_buf_virt = NULL; 1118 } else { 1119 dmaengine_terminate_all(tup->tx_dma_chan); 1120 dma_release_channel(tup->tx_dma_chan); 1121 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 1122 UART_XMIT_SIZE, DMA_TO_DEVICE); 1123 tup->tx_dma_chan = NULL; 1124 tup->tx_dma_buf_phys = 0; 1125 tup->tx_dma_buf_virt = NULL; 1126 } 1127 } 1128 1129 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 1130 bool dma_to_memory) 1131 { 1132 struct dma_chan *dma_chan; 1133 unsigned char *dma_buf; 1134 dma_addr_t dma_phys; 1135 int ret; 1136 struct dma_slave_config dma_sconfig; 1137 1138 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); 1139 if (IS_ERR(dma_chan)) { 1140 ret = PTR_ERR(dma_chan); 1141 dev_err(tup->uport.dev, 1142 "DMA channel alloc failed: %d\n", ret); 1143 return ret; 1144 } 1145 1146 if (dma_to_memory) { 1147 dma_buf = dma_alloc_coherent(tup->uport.dev, 1148 TEGRA_UART_RX_DMA_BUFFER_SIZE, 1149 &dma_phys, GFP_KERNEL); 1150 if (!dma_buf) { 1151 dev_err(tup->uport.dev, 1152 "Not able to allocate the dma buffer\n"); 1153 dma_release_channel(dma_chan); 1154 return -ENOMEM; 1155 } 1156 dma_sync_single_for_device(tup->uport.dev, dma_phys, 1157 TEGRA_UART_RX_DMA_BUFFER_SIZE, 1158 DMA_TO_DEVICE); 1159 dma_sconfig.src_addr = tup->uport.mapbase; 1160 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1161 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; 1162 tup->rx_dma_chan = dma_chan; 1163 tup->rx_dma_buf_virt = dma_buf; 1164 tup->rx_dma_buf_phys = dma_phys; 1165 } else { 1166 dma_phys = dma_map_single(tup->uport.dev, 1167 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 1168 DMA_TO_DEVICE); 1169 if (dma_mapping_error(tup->uport.dev, dma_phys)) { 1170 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); 1171 dma_release_channel(dma_chan); 1172 return -ENOMEM; 1173 } 1174 dma_buf = tup->uport.state->xmit.buf; 1175 dma_sconfig.dst_addr = tup->uport.mapbase; 1176 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1177 dma_sconfig.dst_maxburst = 16; 1178 tup->tx_dma_chan = dma_chan; 1179 tup->tx_dma_buf_virt = dma_buf; 1180 tup->tx_dma_buf_phys = dma_phys; 1181 } 1182 1183 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 1184 if (ret < 0) { 1185 dev_err(tup->uport.dev, 1186 "Dma slave config failed, err = %d\n", ret); 1187 tegra_uart_dma_channel_free(tup, dma_to_memory); 1188 return ret; 1189 } 1190 1191 return 0; 1192 } 1193 1194 static int tegra_uart_startup(struct uart_port *u) 1195 { 1196 struct tegra_uart_port *tup = to_tegra_uport(u); 1197 int ret; 1198 1199 if (!tup->use_tx_pio) { 1200 ret = tegra_uart_dma_channel_allocate(tup, false); 1201 if (ret < 0) { 1202 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", 1203 ret); 1204 return ret; 1205 } 1206 } 1207 1208 if (!tup->use_rx_pio) { 1209 ret = tegra_uart_dma_channel_allocate(tup, true); 1210 if (ret < 0) { 1211 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", 1212 ret); 1213 goto fail_rx_dma; 1214 } 1215 } 1216 1217 ret = tegra_uart_hw_init(tup); 1218 if (ret < 0) { 1219 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1220 goto fail_hw_init; 1221 } 1222 1223 ret = request_irq(u->irq, tegra_uart_isr, 0, 1224 dev_name(u->dev), tup); 1225 if (ret < 0) { 1226 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1227 goto fail_hw_init; 1228 } 1229 return 0; 1230 1231 fail_hw_init: 1232 if (!tup->use_rx_pio) 1233 tegra_uart_dma_channel_free(tup, true); 1234 fail_rx_dma: 1235 if (!tup->use_tx_pio) 1236 tegra_uart_dma_channel_free(tup, false); 1237 return ret; 1238 } 1239 1240 /* 1241 * Flush any TX data submitted for DMA and PIO. Called when the 1242 * TX circular buffer is reset. 1243 */ 1244 static void tegra_uart_flush_buffer(struct uart_port *u) 1245 { 1246 struct tegra_uart_port *tup = to_tegra_uport(u); 1247 1248 tup->tx_bytes = 0; 1249 if (tup->tx_dma_chan) 1250 dmaengine_terminate_all(tup->tx_dma_chan); 1251 } 1252 1253 static void tegra_uart_shutdown(struct uart_port *u) 1254 { 1255 struct tegra_uart_port *tup = to_tegra_uport(u); 1256 1257 tegra_uart_hw_deinit(tup); 1258 free_irq(u->irq, tup); 1259 } 1260 1261 static void tegra_uart_enable_ms(struct uart_port *u) 1262 { 1263 struct tegra_uart_port *tup = to_tegra_uport(u); 1264 1265 if (tup->enable_modem_interrupt) { 1266 tup->ier_shadow |= UART_IER_MSI; 1267 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1268 } 1269 } 1270 1271 static void tegra_uart_set_termios(struct uart_port *u, 1272 struct ktermios *termios, struct ktermios *oldtermios) 1273 { 1274 struct tegra_uart_port *tup = to_tegra_uport(u); 1275 unsigned int baud; 1276 unsigned long flags; 1277 unsigned int lcr; 1278 int symb_bit = 1; 1279 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1280 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1281 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1282 int ret; 1283 1284 max_divider *= 16; 1285 spin_lock_irqsave(&u->lock, flags); 1286 1287 /* Changing configuration, it is safe to stop any rx now */ 1288 if (tup->rts_active) 1289 set_rts(tup, false); 1290 1291 /* Clear all interrupts as configuration is going to be changed */ 1292 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1293 tegra_uart_read(tup, UART_IER); 1294 tegra_uart_write(tup, 0, UART_IER); 1295 tegra_uart_read(tup, UART_IER); 1296 1297 /* Parity */ 1298 lcr = tup->lcr_shadow; 1299 lcr &= ~UART_LCR_PARITY; 1300 1301 /* CMSPAR isn't supported by this driver */ 1302 termios->c_cflag &= ~CMSPAR; 1303 1304 if ((termios->c_cflag & PARENB) == PARENB) { 1305 symb_bit++; 1306 if (termios->c_cflag & PARODD) { 1307 lcr |= UART_LCR_PARITY; 1308 lcr &= ~UART_LCR_EPAR; 1309 lcr &= ~UART_LCR_SPAR; 1310 } else { 1311 lcr |= UART_LCR_PARITY; 1312 lcr |= UART_LCR_EPAR; 1313 lcr &= ~UART_LCR_SPAR; 1314 } 1315 } 1316 1317 lcr &= ~UART_LCR_WLEN8; 1318 switch (termios->c_cflag & CSIZE) { 1319 case CS5: 1320 lcr |= UART_LCR_WLEN5; 1321 symb_bit += 5; 1322 break; 1323 case CS6: 1324 lcr |= UART_LCR_WLEN6; 1325 symb_bit += 6; 1326 break; 1327 case CS7: 1328 lcr |= UART_LCR_WLEN7; 1329 symb_bit += 7; 1330 break; 1331 default: 1332 lcr |= UART_LCR_WLEN8; 1333 symb_bit += 8; 1334 break; 1335 } 1336 1337 /* Stop bits */ 1338 if (termios->c_cflag & CSTOPB) { 1339 lcr |= UART_LCR_STOP; 1340 symb_bit += 2; 1341 } else { 1342 lcr &= ~UART_LCR_STOP; 1343 symb_bit++; 1344 } 1345 1346 tegra_uart_write(tup, lcr, UART_LCR); 1347 tup->lcr_shadow = lcr; 1348 tup->symb_bit = symb_bit; 1349 1350 /* Baud rate. */ 1351 baud = uart_get_baud_rate(u, termios, oldtermios, 1352 parent_clk_rate/max_divider, 1353 parent_clk_rate/16); 1354 spin_unlock_irqrestore(&u->lock, flags); 1355 ret = tegra_set_baudrate(tup, baud); 1356 if (ret < 0) { 1357 dev_err(tup->uport.dev, "Failed to set baud rate\n"); 1358 return; 1359 } 1360 if (tty_termios_baud_rate(termios)) 1361 tty_termios_encode_baud_rate(termios, baud, baud); 1362 spin_lock_irqsave(&u->lock, flags); 1363 1364 /* Flow control */ 1365 if (termios->c_cflag & CRTSCTS) { 1366 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1367 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1368 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1369 /* if top layer has asked to set rts active then do so here */ 1370 if (tup->rts_active) 1371 set_rts(tup, true); 1372 } else { 1373 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1374 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1375 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1376 } 1377 1378 /* update the port timeout based on new settings */ 1379 uart_update_timeout(u, termios->c_cflag, baud); 1380 1381 /* Make sure all writes have completed */ 1382 tegra_uart_read(tup, UART_IER); 1383 1384 /* Re-enable interrupt */ 1385 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1386 tegra_uart_read(tup, UART_IER); 1387 1388 tup->uport.ignore_status_mask = 0; 1389 /* Ignore all characters if CREAD is not set */ 1390 if ((termios->c_cflag & CREAD) == 0) 1391 tup->uport.ignore_status_mask |= UART_LSR_DR; 1392 if (termios->c_iflag & IGNBRK) 1393 tup->uport.ignore_status_mask |= UART_LSR_BI; 1394 1395 spin_unlock_irqrestore(&u->lock, flags); 1396 } 1397 1398 static const char *tegra_uart_type(struct uart_port *u) 1399 { 1400 return TEGRA_UART_TYPE; 1401 } 1402 1403 static const struct uart_ops tegra_uart_ops = { 1404 .tx_empty = tegra_uart_tx_empty, 1405 .set_mctrl = tegra_uart_set_mctrl, 1406 .get_mctrl = tegra_uart_get_mctrl, 1407 .stop_tx = tegra_uart_stop_tx, 1408 .start_tx = tegra_uart_start_tx, 1409 .stop_rx = tegra_uart_stop_rx, 1410 .flush_buffer = tegra_uart_flush_buffer, 1411 .enable_ms = tegra_uart_enable_ms, 1412 .break_ctl = tegra_uart_break_ctl, 1413 .startup = tegra_uart_startup, 1414 .shutdown = tegra_uart_shutdown, 1415 .set_termios = tegra_uart_set_termios, 1416 .type = tegra_uart_type, 1417 .request_port = tegra_uart_request_port, 1418 .release_port = tegra_uart_release_port, 1419 }; 1420 1421 static struct uart_driver tegra_uart_driver = { 1422 .owner = THIS_MODULE, 1423 .driver_name = "tegra_hsuart", 1424 .dev_name = "ttyTHS", 1425 .cons = NULL, 1426 .nr = TEGRA_UART_MAXIMUM, 1427 }; 1428 1429 static int tegra_uart_parse_dt(struct platform_device *pdev, 1430 struct tegra_uart_port *tup) 1431 { 1432 struct device_node *np = pdev->dev.of_node; 1433 int port; 1434 int ret; 1435 int index; 1436 u32 pval; 1437 int count; 1438 int n_entries; 1439 1440 port = of_alias_get_id(np, "serial"); 1441 if (port < 0) { 1442 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1443 return port; 1444 } 1445 tup->uport.line = port; 1446 1447 tup->enable_modem_interrupt = of_property_read_bool(np, 1448 "nvidia,enable-modem-interrupt"); 1449 1450 index = of_property_match_string(np, "dma-names", "rx"); 1451 if (index < 0) { 1452 tup->use_rx_pio = true; 1453 dev_info(&pdev->dev, "RX in PIO mode\n"); 1454 } 1455 index = of_property_match_string(np, "dma-names", "tx"); 1456 if (index < 0) { 1457 tup->use_tx_pio = true; 1458 dev_info(&pdev->dev, "TX in PIO mode\n"); 1459 } 1460 1461 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates"); 1462 if (n_entries > 0) { 1463 tup->n_adjustable_baud_rates = n_entries / 3; 1464 tup->baud_tolerance = 1465 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * 1466 sizeof(*tup->baud_tolerance), GFP_KERNEL); 1467 if (!tup->baud_tolerance) 1468 return -ENOMEM; 1469 for (count = 0, index = 0; count < n_entries; count += 3, 1470 index++) { 1471 ret = 1472 of_property_read_u32_index(np, 1473 "nvidia,adjust-baud-rates", 1474 count, &pval); 1475 if (!ret) 1476 tup->baud_tolerance[index].lower_range_baud = 1477 pval; 1478 ret = 1479 of_property_read_u32_index(np, 1480 "nvidia,adjust-baud-rates", 1481 count + 1, &pval); 1482 if (!ret) 1483 tup->baud_tolerance[index].upper_range_baud = 1484 pval; 1485 ret = 1486 of_property_read_u32_index(np, 1487 "nvidia,adjust-baud-rates", 1488 count + 2, &pval); 1489 if (!ret) 1490 tup->baud_tolerance[index].tolerance = 1491 (s32)pval; 1492 } 1493 } else { 1494 tup->n_adjustable_baud_rates = 0; 1495 } 1496 1497 return 0; 1498 } 1499 1500 static struct tegra_uart_chip_data tegra20_uart_chip_data = { 1501 .tx_fifo_full_status = false, 1502 .allow_txfifo_reset_fifo_mode = true, 1503 .support_clk_src_div = false, 1504 .fifo_mode_enable_status = false, 1505 .uart_max_port = 5, 1506 .max_dma_burst_bytes = 4, 1507 .error_tolerance_low_range = 0, 1508 .error_tolerance_high_range = 4, 1509 }; 1510 1511 static struct tegra_uart_chip_data tegra30_uart_chip_data = { 1512 .tx_fifo_full_status = true, 1513 .allow_txfifo_reset_fifo_mode = false, 1514 .support_clk_src_div = true, 1515 .fifo_mode_enable_status = false, 1516 .uart_max_port = 5, 1517 .max_dma_burst_bytes = 4, 1518 .error_tolerance_low_range = 0, 1519 .error_tolerance_high_range = 4, 1520 }; 1521 1522 static struct tegra_uart_chip_data tegra186_uart_chip_data = { 1523 .tx_fifo_full_status = true, 1524 .allow_txfifo_reset_fifo_mode = false, 1525 .support_clk_src_div = true, 1526 .fifo_mode_enable_status = true, 1527 .uart_max_port = 8, 1528 .max_dma_burst_bytes = 8, 1529 .error_tolerance_low_range = 0, 1530 .error_tolerance_high_range = 4, 1531 }; 1532 1533 static struct tegra_uart_chip_data tegra194_uart_chip_data = { 1534 .tx_fifo_full_status = true, 1535 .allow_txfifo_reset_fifo_mode = false, 1536 .support_clk_src_div = true, 1537 .fifo_mode_enable_status = true, 1538 .uart_max_port = 8, 1539 .max_dma_burst_bytes = 8, 1540 .error_tolerance_low_range = -2, 1541 .error_tolerance_high_range = 2, 1542 }; 1543 1544 static const struct of_device_id tegra_uart_of_match[] = { 1545 { 1546 .compatible = "nvidia,tegra30-hsuart", 1547 .data = &tegra30_uart_chip_data, 1548 }, { 1549 .compatible = "nvidia,tegra20-hsuart", 1550 .data = &tegra20_uart_chip_data, 1551 }, { 1552 .compatible = "nvidia,tegra186-hsuart", 1553 .data = &tegra186_uart_chip_data, 1554 }, { 1555 .compatible = "nvidia,tegra194-hsuart", 1556 .data = &tegra194_uart_chip_data, 1557 }, { 1558 }, 1559 }; 1560 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1561 1562 static int tegra_uart_probe(struct platform_device *pdev) 1563 { 1564 struct tegra_uart_port *tup; 1565 struct uart_port *u; 1566 struct resource *resource; 1567 int ret; 1568 const struct tegra_uart_chip_data *cdata; 1569 const struct of_device_id *match; 1570 1571 match = of_match_device(tegra_uart_of_match, &pdev->dev); 1572 if (!match) { 1573 dev_err(&pdev->dev, "Error: No device match found\n"); 1574 return -ENODEV; 1575 } 1576 cdata = match->data; 1577 1578 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1579 if (!tup) { 1580 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1581 return -ENOMEM; 1582 } 1583 1584 ret = tegra_uart_parse_dt(pdev, tup); 1585 if (ret < 0) 1586 return ret; 1587 1588 u = &tup->uport; 1589 u->dev = &pdev->dev; 1590 u->ops = &tegra_uart_ops; 1591 u->type = PORT_TEGRA; 1592 u->fifosize = 32; 1593 tup->cdata = cdata; 1594 1595 platform_set_drvdata(pdev, tup); 1596 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1597 if (!resource) { 1598 dev_err(&pdev->dev, "No IO memory resource\n"); 1599 return -ENODEV; 1600 } 1601 1602 u->mapbase = resource->start; 1603 u->membase = devm_ioremap_resource(&pdev->dev, resource); 1604 if (IS_ERR(u->membase)) 1605 return PTR_ERR(u->membase); 1606 1607 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1608 if (IS_ERR(tup->uart_clk)) { 1609 dev_err(&pdev->dev, "Couldn't get the clock\n"); 1610 return PTR_ERR(tup->uart_clk); 1611 } 1612 1613 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); 1614 if (IS_ERR(tup->rst)) { 1615 dev_err(&pdev->dev, "Couldn't get the reset\n"); 1616 return PTR_ERR(tup->rst); 1617 } 1618 1619 u->iotype = UPIO_MEM32; 1620 ret = platform_get_irq(pdev, 0); 1621 if (ret < 0) 1622 return ret; 1623 u->irq = ret; 1624 u->regshift = 2; 1625 ret = uart_add_one_port(&tegra_uart_driver, u); 1626 if (ret < 0) { 1627 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1628 return ret; 1629 } 1630 return ret; 1631 } 1632 1633 static int tegra_uart_remove(struct platform_device *pdev) 1634 { 1635 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1636 struct uart_port *u = &tup->uport; 1637 1638 uart_remove_one_port(&tegra_uart_driver, u); 1639 return 0; 1640 } 1641 1642 #ifdef CONFIG_PM_SLEEP 1643 static int tegra_uart_suspend(struct device *dev) 1644 { 1645 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1646 struct uart_port *u = &tup->uport; 1647 1648 return uart_suspend_port(&tegra_uart_driver, u); 1649 } 1650 1651 static int tegra_uart_resume(struct device *dev) 1652 { 1653 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1654 struct uart_port *u = &tup->uport; 1655 1656 return uart_resume_port(&tegra_uart_driver, u); 1657 } 1658 #endif 1659 1660 static const struct dev_pm_ops tegra_uart_pm_ops = { 1661 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1662 }; 1663 1664 static struct platform_driver tegra_uart_platform_driver = { 1665 .probe = tegra_uart_probe, 1666 .remove = tegra_uart_remove, 1667 .driver = { 1668 .name = "serial-tegra", 1669 .of_match_table = tegra_uart_of_match, 1670 .pm = &tegra_uart_pm_ops, 1671 }, 1672 }; 1673 1674 static int __init tegra_uart_init(void) 1675 { 1676 int ret; 1677 struct device_node *node; 1678 const struct of_device_id *match = NULL; 1679 const struct tegra_uart_chip_data *cdata = NULL; 1680 1681 node = of_find_matching_node(NULL, tegra_uart_of_match); 1682 if (node) 1683 match = of_match_node(tegra_uart_of_match, node); 1684 if (match) 1685 cdata = match->data; 1686 if (cdata) 1687 tegra_uart_driver.nr = cdata->uart_max_port; 1688 1689 ret = uart_register_driver(&tegra_uart_driver); 1690 if (ret < 0) { 1691 pr_err("Could not register %s driver\n", 1692 tegra_uart_driver.driver_name); 1693 return ret; 1694 } 1695 1696 ret = platform_driver_register(&tegra_uart_platform_driver); 1697 if (ret < 0) { 1698 pr_err("Uart platform driver register failed, e = %d\n", ret); 1699 uart_unregister_driver(&tegra_uart_driver); 1700 return ret; 1701 } 1702 return 0; 1703 } 1704 1705 static void __exit tegra_uart_exit(void) 1706 { 1707 pr_info("Unloading tegra uart driver\n"); 1708 platform_driver_unregister(&tegra_uart_platform_driver); 1709 uart_unregister_driver(&tegra_uart_driver); 1710 } 1711 1712 module_init(tegra_uart_init); 1713 module_exit(tegra_uart_exit); 1714 1715 MODULE_ALIAS("platform:serial-tegra"); 1716 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1717 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1718 MODULE_LICENSE("GPL v2"); 1719