1 /* 2 * serial_tegra.c 3 * 4 * High-speed serial driver for NVIDIA Tegra SoCs 5 * 6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/debugfs.h> 25 #include <linux/delay.h> 26 #include <linux/dmaengine.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/module.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/pagemap.h> 36 #include <linux/platform_device.h> 37 #include <linux/reset.h> 38 #include <linux/serial.h> 39 #include <linux/serial_8250.h> 40 #include <linux/serial_core.h> 41 #include <linux/serial_reg.h> 42 #include <linux/slab.h> 43 #include <linux/string.h> 44 #include <linux/termios.h> 45 #include <linux/tty.h> 46 #include <linux/tty_flip.h> 47 48 #define TEGRA_UART_TYPE "TEGRA_UART" 49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 51 52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 54 #define TEGRA_UART_IER_EORD 0x20 55 #define TEGRA_UART_MCR_RTS_EN 0x40 56 #define TEGRA_UART_MCR_CTS_EN 0x20 57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 58 UART_LSR_PE | UART_LSR_FE) 59 #define TEGRA_UART_IRDA_CSR 0x08 60 #define TEGRA_UART_SIR_ENABLED 0x80 61 62 #define TEGRA_UART_TX_PIO 1 63 #define TEGRA_UART_TX_DMA 2 64 #define TEGRA_UART_MIN_DMA 16 65 #define TEGRA_UART_FIFO_SIZE 32 66 67 /* 68 * Tx fifo trigger level setting in tegra uart is in 69 * reverse way then conventional uart. 70 */ 71 #define TEGRA_UART_TX_TRIG_16B 0x00 72 #define TEGRA_UART_TX_TRIG_8B 0x10 73 #define TEGRA_UART_TX_TRIG_4B 0x20 74 #define TEGRA_UART_TX_TRIG_1B 0x30 75 76 #define TEGRA_UART_MAXIMUM 5 77 78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 79 #define TEGRA_UART_DEFAULT_BAUD 115200 80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 81 82 /* Tx transfer mode */ 83 #define TEGRA_TX_PIO 1 84 #define TEGRA_TX_DMA 2 85 86 /** 87 * tegra_uart_chip_data: SOC specific data. 88 * 89 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 91 * Tegra30 does not allow this. 92 * @support_clk_src_div: Clock source support the clock divider. 93 */ 94 struct tegra_uart_chip_data { 95 bool tx_fifo_full_status; 96 bool allow_txfifo_reset_fifo_mode; 97 bool support_clk_src_div; 98 }; 99 100 struct tegra_uart_port { 101 struct uart_port uport; 102 const struct tegra_uart_chip_data *cdata; 103 104 struct clk *uart_clk; 105 struct reset_control *rst; 106 unsigned int current_baud; 107 108 /* Register shadow */ 109 unsigned long fcr_shadow; 110 unsigned long mcr_shadow; 111 unsigned long lcr_shadow; 112 unsigned long ier_shadow; 113 bool rts_active; 114 115 int tx_in_progress; 116 unsigned int tx_bytes; 117 118 bool enable_modem_interrupt; 119 120 bool rx_timeout; 121 int rx_in_progress; 122 int symb_bit; 123 124 struct dma_chan *rx_dma_chan; 125 struct dma_chan *tx_dma_chan; 126 dma_addr_t rx_dma_buf_phys; 127 dma_addr_t tx_dma_buf_phys; 128 unsigned char *rx_dma_buf_virt; 129 unsigned char *tx_dma_buf_virt; 130 struct dma_async_tx_descriptor *tx_dma_desc; 131 struct dma_async_tx_descriptor *rx_dma_desc; 132 dma_cookie_t tx_cookie; 133 dma_cookie_t rx_cookie; 134 unsigned int tx_bytes_requested; 135 unsigned int rx_bytes_requested; 136 }; 137 138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 140 141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 142 unsigned long reg) 143 { 144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 145 } 146 147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 148 unsigned long reg) 149 { 150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 151 } 152 153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 154 { 155 return container_of(u, struct tegra_uart_port, uport); 156 } 157 158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 159 { 160 struct tegra_uart_port *tup = to_tegra_uport(u); 161 162 /* 163 * RI - Ring detector is active 164 * CD/DCD/CAR - Carrier detect is always active. For some reason 165 * linux has different names for carrier detect. 166 * DSR - Data Set ready is active as the hardware doesn't support it. 167 * Don't know if the linux support this yet? 168 * CTS - Clear to send. Always set to active, as the hardware handles 169 * CTS automatically. 170 */ 171 if (tup->enable_modem_interrupt) 172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 173 return TIOCM_CTS; 174 } 175 176 static void set_rts(struct tegra_uart_port *tup, bool active) 177 { 178 unsigned long mcr; 179 180 mcr = tup->mcr_shadow; 181 if (active) 182 mcr |= TEGRA_UART_MCR_RTS_EN; 183 else 184 mcr &= ~TEGRA_UART_MCR_RTS_EN; 185 if (mcr != tup->mcr_shadow) { 186 tegra_uart_write(tup, mcr, UART_MCR); 187 tup->mcr_shadow = mcr; 188 } 189 } 190 191 static void set_dtr(struct tegra_uart_port *tup, bool active) 192 { 193 unsigned long mcr; 194 195 mcr = tup->mcr_shadow; 196 if (active) 197 mcr |= UART_MCR_DTR; 198 else 199 mcr &= ~UART_MCR_DTR; 200 if (mcr != tup->mcr_shadow) { 201 tegra_uart_write(tup, mcr, UART_MCR); 202 tup->mcr_shadow = mcr; 203 } 204 } 205 206 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 207 { 208 struct tegra_uart_port *tup = to_tegra_uport(u); 209 unsigned long mcr; 210 int dtr_enable; 211 212 mcr = tup->mcr_shadow; 213 tup->rts_active = !!(mctrl & TIOCM_RTS); 214 set_rts(tup, tup->rts_active); 215 216 dtr_enable = !!(mctrl & TIOCM_DTR); 217 set_dtr(tup, dtr_enable); 218 } 219 220 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 221 { 222 struct tegra_uart_port *tup = to_tegra_uport(u); 223 unsigned long lcr; 224 225 lcr = tup->lcr_shadow; 226 if (break_ctl) 227 lcr |= UART_LCR_SBC; 228 else 229 lcr &= ~UART_LCR_SBC; 230 tegra_uart_write(tup, lcr, UART_LCR); 231 tup->lcr_shadow = lcr; 232 } 233 234 /** 235 * tegra_uart_wait_cycle_time: Wait for N UART clock periods 236 * 237 * @tup: Tegra serial port data structure. 238 * @cycles: Number of clock periods to wait. 239 * 240 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART 241 * clock speed is 16X the current baud rate. 242 */ 243 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, 244 unsigned int cycles) 245 { 246 if (tup->current_baud) 247 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); 248 } 249 250 /* Wait for a symbol-time. */ 251 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 252 unsigned int syms) 253 { 254 if (tup->current_baud) 255 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 256 tup->current_baud)); 257 } 258 259 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 260 { 261 unsigned long fcr = tup->fcr_shadow; 262 263 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 264 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 265 tegra_uart_write(tup, fcr, UART_FCR); 266 } else { 267 fcr &= ~UART_FCR_ENABLE_FIFO; 268 tegra_uart_write(tup, fcr, UART_FCR); 269 udelay(60); 270 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 271 tegra_uart_write(tup, fcr, UART_FCR); 272 fcr |= UART_FCR_ENABLE_FIFO; 273 tegra_uart_write(tup, fcr, UART_FCR); 274 } 275 276 /* Dummy read to ensure the write is posted */ 277 tegra_uart_read(tup, UART_SCR); 278 279 /* 280 * For all tegra devices (up to t210), there is a hardware issue that 281 * requires software to wait for 32 UART clock periods for the flush 282 * to propagate, otherwise data could be lost. 283 */ 284 tegra_uart_wait_cycle_time(tup, 32); 285 } 286 287 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 288 { 289 unsigned long rate; 290 unsigned int divisor; 291 unsigned long lcr; 292 int ret; 293 294 if (tup->current_baud == baud) 295 return 0; 296 297 if (tup->cdata->support_clk_src_div) { 298 rate = baud * 16; 299 ret = clk_set_rate(tup->uart_clk, rate); 300 if (ret < 0) { 301 dev_err(tup->uport.dev, 302 "clk_set_rate() failed for rate %lu\n", rate); 303 return ret; 304 } 305 divisor = 1; 306 } else { 307 rate = clk_get_rate(tup->uart_clk); 308 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 309 } 310 311 lcr = tup->lcr_shadow; 312 lcr |= UART_LCR_DLAB; 313 tegra_uart_write(tup, lcr, UART_LCR); 314 315 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 316 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 317 318 lcr &= ~UART_LCR_DLAB; 319 tegra_uart_write(tup, lcr, UART_LCR); 320 321 /* Dummy read to ensure the write is posted */ 322 tegra_uart_read(tup, UART_SCR); 323 324 tup->current_baud = baud; 325 326 /* wait two character intervals at new rate */ 327 tegra_uart_wait_sym_time(tup, 2); 328 return 0; 329 } 330 331 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 332 unsigned long lsr) 333 { 334 char flag = TTY_NORMAL; 335 336 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 337 if (lsr & UART_LSR_OE) { 338 /* Overrrun error */ 339 flag = TTY_OVERRUN; 340 tup->uport.icount.overrun++; 341 dev_err(tup->uport.dev, "Got overrun errors\n"); 342 } else if (lsr & UART_LSR_PE) { 343 /* Parity error */ 344 flag = TTY_PARITY; 345 tup->uport.icount.parity++; 346 dev_err(tup->uport.dev, "Got Parity errors\n"); 347 } else if (lsr & UART_LSR_FE) { 348 flag = TTY_FRAME; 349 tup->uport.icount.frame++; 350 dev_err(tup->uport.dev, "Got frame errors\n"); 351 } else if (lsr & UART_LSR_BI) { 352 dev_err(tup->uport.dev, "Got Break\n"); 353 tup->uport.icount.brk++; 354 /* If FIFO read error without any data, reset Rx FIFO */ 355 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 356 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 357 } 358 } 359 return flag; 360 } 361 362 static int tegra_uart_request_port(struct uart_port *u) 363 { 364 return 0; 365 } 366 367 static void tegra_uart_release_port(struct uart_port *u) 368 { 369 /* Nothing to do here */ 370 } 371 372 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 373 { 374 struct circ_buf *xmit = &tup->uport.state->xmit; 375 int i; 376 377 for (i = 0; i < max_bytes; i++) { 378 BUG_ON(uart_circ_empty(xmit)); 379 if (tup->cdata->tx_fifo_full_status) { 380 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 381 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 382 break; 383 } 384 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 385 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 386 tup->uport.icount.tx++; 387 } 388 } 389 390 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 391 unsigned int bytes) 392 { 393 if (bytes > TEGRA_UART_MIN_DMA) 394 bytes = TEGRA_UART_MIN_DMA; 395 396 tup->tx_in_progress = TEGRA_UART_TX_PIO; 397 tup->tx_bytes = bytes; 398 tup->ier_shadow |= UART_IER_THRI; 399 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 400 } 401 402 static void tegra_uart_tx_dma_complete(void *args) 403 { 404 struct tegra_uart_port *tup = args; 405 struct circ_buf *xmit = &tup->uport.state->xmit; 406 struct dma_tx_state state; 407 unsigned long flags; 408 unsigned int count; 409 410 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 411 count = tup->tx_bytes_requested - state.residue; 412 async_tx_ack(tup->tx_dma_desc); 413 spin_lock_irqsave(&tup->uport.lock, flags); 414 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 415 tup->tx_in_progress = 0; 416 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 417 uart_write_wakeup(&tup->uport); 418 tegra_uart_start_next_tx(tup); 419 spin_unlock_irqrestore(&tup->uport.lock, flags); 420 } 421 422 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 423 unsigned long count) 424 { 425 struct circ_buf *xmit = &tup->uport.state->xmit; 426 dma_addr_t tx_phys_addr; 427 428 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, 429 UART_XMIT_SIZE, DMA_TO_DEVICE); 430 431 tup->tx_bytes = count & ~(0xF); 432 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 433 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 434 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 435 DMA_PREP_INTERRUPT); 436 if (!tup->tx_dma_desc) { 437 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 438 return -EIO; 439 } 440 441 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 442 tup->tx_dma_desc->callback_param = tup; 443 tup->tx_in_progress = TEGRA_UART_TX_DMA; 444 tup->tx_bytes_requested = tup->tx_bytes; 445 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 446 dma_async_issue_pending(tup->tx_dma_chan); 447 return 0; 448 } 449 450 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 451 { 452 unsigned long tail; 453 unsigned long count; 454 struct circ_buf *xmit = &tup->uport.state->xmit; 455 456 tail = (unsigned long)&xmit->buf[xmit->tail]; 457 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 458 if (!count) 459 return; 460 461 if (count < TEGRA_UART_MIN_DMA) 462 tegra_uart_start_pio_tx(tup, count); 463 else if (BYTES_TO_ALIGN(tail) > 0) 464 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 465 else 466 tegra_uart_start_tx_dma(tup, count); 467 } 468 469 /* Called by serial core driver with u->lock taken. */ 470 static void tegra_uart_start_tx(struct uart_port *u) 471 { 472 struct tegra_uart_port *tup = to_tegra_uport(u); 473 struct circ_buf *xmit = &u->state->xmit; 474 475 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 476 tegra_uart_start_next_tx(tup); 477 } 478 479 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 480 { 481 struct tegra_uart_port *tup = to_tegra_uport(u); 482 unsigned int ret = 0; 483 unsigned long flags; 484 485 spin_lock_irqsave(&u->lock, flags); 486 if (!tup->tx_in_progress) { 487 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 488 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 489 ret = TIOCSER_TEMT; 490 } 491 spin_unlock_irqrestore(&u->lock, flags); 492 return ret; 493 } 494 495 static void tegra_uart_stop_tx(struct uart_port *u) 496 { 497 struct tegra_uart_port *tup = to_tegra_uport(u); 498 struct circ_buf *xmit = &tup->uport.state->xmit; 499 struct dma_tx_state state; 500 unsigned int count; 501 502 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) 503 return; 504 505 dmaengine_terminate_all(tup->tx_dma_chan); 506 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 507 count = tup->tx_bytes_requested - state.residue; 508 async_tx_ack(tup->tx_dma_desc); 509 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 510 tup->tx_in_progress = 0; 511 } 512 513 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 514 { 515 struct circ_buf *xmit = &tup->uport.state->xmit; 516 517 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 518 tup->tx_in_progress = 0; 519 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 520 uart_write_wakeup(&tup->uport); 521 tegra_uart_start_next_tx(tup); 522 } 523 524 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 525 struct tty_port *tty) 526 { 527 do { 528 char flag = TTY_NORMAL; 529 unsigned long lsr = 0; 530 unsigned char ch; 531 532 lsr = tegra_uart_read(tup, UART_LSR); 533 if (!(lsr & UART_LSR_DR)) 534 break; 535 536 flag = tegra_uart_decode_rx_error(tup, lsr); 537 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 538 tup->uport.icount.rx++; 539 540 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) 541 tty_insert_flip_char(tty, ch, flag); 542 } while (1); 543 } 544 545 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 546 struct tty_port *tty, 547 unsigned int count) 548 { 549 int copied; 550 551 /* If count is zero, then there is no data to be copied */ 552 if (!count) 553 return; 554 555 tup->uport.icount.rx += count; 556 if (!tty) { 557 dev_err(tup->uport.dev, "No tty port\n"); 558 return; 559 } 560 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 561 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 562 copied = tty_insert_flip_string(tty, 563 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 564 if (copied != count) { 565 WARN_ON(1); 566 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 567 } 568 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 569 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 570 } 571 572 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, 573 unsigned int residue) 574 { 575 struct tty_port *port = &tup->uport.state->port; 576 struct tty_struct *tty = tty_port_tty_get(port); 577 unsigned int count; 578 579 async_tx_ack(tup->rx_dma_desc); 580 count = tup->rx_bytes_requested - residue; 581 582 /* If we are here, DMA is stopped */ 583 tegra_uart_copy_rx_to_tty(tup, port, count); 584 585 tegra_uart_handle_rx_pio(tup, port); 586 if (tty) { 587 tty_flip_buffer_push(port); 588 tty_kref_put(tty); 589 } 590 } 591 592 static void tegra_uart_rx_dma_complete(void *args) 593 { 594 struct tegra_uart_port *tup = args; 595 struct uart_port *u = &tup->uport; 596 unsigned long flags; 597 struct dma_tx_state state; 598 enum dma_status status; 599 600 spin_lock_irqsave(&u->lock, flags); 601 602 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 603 604 if (status == DMA_IN_PROGRESS) { 605 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); 606 goto done; 607 } 608 609 /* Deactivate flow control to stop sender */ 610 if (tup->rts_active) 611 set_rts(tup, false); 612 613 tegra_uart_rx_buffer_push(tup, 0); 614 tegra_uart_start_rx_dma(tup); 615 616 /* Activate flow control to start transfer */ 617 if (tup->rts_active) 618 set_rts(tup, true); 619 620 done: 621 spin_unlock_irqrestore(&u->lock, flags); 622 } 623 624 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) 625 { 626 struct dma_tx_state state; 627 628 /* Deactivate flow control to stop sender */ 629 if (tup->rts_active) 630 set_rts(tup, false); 631 632 dmaengine_terminate_all(tup->rx_dma_chan); 633 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 634 tegra_uart_rx_buffer_push(tup, state.residue); 635 tegra_uart_start_rx_dma(tup); 636 637 if (tup->rts_active) 638 set_rts(tup, true); 639 } 640 641 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 642 { 643 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 644 645 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 646 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 647 DMA_PREP_INTERRUPT); 648 if (!tup->rx_dma_desc) { 649 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 650 return -EIO; 651 } 652 653 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 654 tup->rx_dma_desc->callback_param = tup; 655 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 656 count, DMA_TO_DEVICE); 657 tup->rx_bytes_requested = count; 658 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 659 dma_async_issue_pending(tup->rx_dma_chan); 660 return 0; 661 } 662 663 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 664 { 665 struct tegra_uart_port *tup = to_tegra_uport(u); 666 unsigned long msr; 667 668 msr = tegra_uart_read(tup, UART_MSR); 669 if (!(msr & UART_MSR_ANY_DELTA)) 670 return; 671 672 if (msr & UART_MSR_TERI) 673 tup->uport.icount.rng++; 674 if (msr & UART_MSR_DDSR) 675 tup->uport.icount.dsr++; 676 /* We may only get DDCD when HW init and reset */ 677 if (msr & UART_MSR_DDCD) 678 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 679 /* Will start/stop_tx accordingly */ 680 if (msr & UART_MSR_DCTS) 681 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 682 } 683 684 static irqreturn_t tegra_uart_isr(int irq, void *data) 685 { 686 struct tegra_uart_port *tup = data; 687 struct uart_port *u = &tup->uport; 688 unsigned long iir; 689 unsigned long ier; 690 bool is_rx_int = false; 691 unsigned long flags; 692 693 spin_lock_irqsave(&u->lock, flags); 694 while (1) { 695 iir = tegra_uart_read(tup, UART_IIR); 696 if (iir & UART_IIR_NO_INT) { 697 if (is_rx_int) { 698 tegra_uart_handle_rx_dma(tup); 699 if (tup->rx_in_progress) { 700 ier = tup->ier_shadow; 701 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 702 TEGRA_UART_IER_EORD); 703 tup->ier_shadow = ier; 704 tegra_uart_write(tup, ier, UART_IER); 705 } 706 } 707 spin_unlock_irqrestore(&u->lock, flags); 708 return IRQ_HANDLED; 709 } 710 711 switch ((iir >> 1) & 0x7) { 712 case 0: /* Modem signal change interrupt */ 713 tegra_uart_handle_modem_signal_change(u); 714 break; 715 716 case 1: /* Transmit interrupt only triggered when using PIO */ 717 tup->ier_shadow &= ~UART_IER_THRI; 718 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 719 tegra_uart_handle_tx_pio(tup); 720 break; 721 722 case 4: /* End of data */ 723 case 6: /* Rx timeout */ 724 case 2: /* Receive */ 725 if (!is_rx_int) { 726 is_rx_int = true; 727 /* Disable Rx interrupts */ 728 ier = tup->ier_shadow; 729 ier |= UART_IER_RDI; 730 tegra_uart_write(tup, ier, UART_IER); 731 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 732 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 733 tup->ier_shadow = ier; 734 tegra_uart_write(tup, ier, UART_IER); 735 } 736 break; 737 738 case 3: /* Receive error */ 739 tegra_uart_decode_rx_error(tup, 740 tegra_uart_read(tup, UART_LSR)); 741 break; 742 743 case 5: /* break nothing to handle */ 744 case 7: /* break nothing to handle */ 745 break; 746 } 747 } 748 } 749 750 static void tegra_uart_stop_rx(struct uart_port *u) 751 { 752 struct tegra_uart_port *tup = to_tegra_uport(u); 753 struct dma_tx_state state; 754 unsigned long ier; 755 756 if (tup->rts_active) 757 set_rts(tup, false); 758 759 if (!tup->rx_in_progress) 760 return; 761 762 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ 763 764 ier = tup->ier_shadow; 765 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 766 TEGRA_UART_IER_EORD); 767 tup->ier_shadow = ier; 768 tegra_uart_write(tup, ier, UART_IER); 769 tup->rx_in_progress = 0; 770 dmaengine_terminate_all(tup->rx_dma_chan); 771 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 772 tegra_uart_rx_buffer_push(tup, state.residue); 773 } 774 775 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 776 { 777 unsigned long flags; 778 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 779 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 780 unsigned long wait_time; 781 unsigned long lsr; 782 unsigned long msr; 783 unsigned long mcr; 784 785 /* Disable interrupts */ 786 tegra_uart_write(tup, 0, UART_IER); 787 788 lsr = tegra_uart_read(tup, UART_LSR); 789 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 790 msr = tegra_uart_read(tup, UART_MSR); 791 mcr = tegra_uart_read(tup, UART_MCR); 792 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 793 dev_err(tup->uport.dev, 794 "Tx Fifo not empty, CTS disabled, waiting\n"); 795 796 /* Wait for Tx fifo to be empty */ 797 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 798 wait_time = min(fifo_empty_time, 100lu); 799 udelay(wait_time); 800 fifo_empty_time -= wait_time; 801 if (!fifo_empty_time) { 802 msr = tegra_uart_read(tup, UART_MSR); 803 mcr = tegra_uart_read(tup, UART_MCR); 804 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 805 (msr & UART_MSR_CTS)) 806 dev_err(tup->uport.dev, 807 "Slave not ready\n"); 808 break; 809 } 810 lsr = tegra_uart_read(tup, UART_LSR); 811 } 812 } 813 814 spin_lock_irqsave(&tup->uport.lock, flags); 815 /* Reset the Rx and Tx FIFOs */ 816 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 817 tup->current_baud = 0; 818 spin_unlock_irqrestore(&tup->uport.lock, flags); 819 820 clk_disable_unprepare(tup->uart_clk); 821 } 822 823 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 824 { 825 int ret; 826 827 tup->fcr_shadow = 0; 828 tup->mcr_shadow = 0; 829 tup->lcr_shadow = 0; 830 tup->ier_shadow = 0; 831 tup->current_baud = 0; 832 833 clk_prepare_enable(tup->uart_clk); 834 835 /* Reset the UART controller to clear all previous status.*/ 836 reset_control_assert(tup->rst); 837 udelay(10); 838 reset_control_deassert(tup->rst); 839 840 tup->rx_in_progress = 0; 841 tup->tx_in_progress = 0; 842 843 /* 844 * Set the trigger level 845 * 846 * For PIO mode: 847 * 848 * For receive, this will interrupt the CPU after that many number of 849 * bytes are received, for the remaining bytes the receive timeout 850 * interrupt is received. Rx high watermark is set to 4. 851 * 852 * For transmit, if the trasnmit interrupt is enabled, this will 853 * interrupt the CPU when the number of entries in the FIFO reaches the 854 * low watermark. Tx low watermark is set to 16 bytes. 855 * 856 * For DMA mode: 857 * 858 * Set the Tx trigger to 16. This should match the DMA burst size that 859 * programmed in the DMA registers. 860 */ 861 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 862 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 863 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 864 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 865 866 /* Dummy read to ensure the write is posted */ 867 tegra_uart_read(tup, UART_SCR); 868 869 /* 870 * For all tegra devices (up to t210), there is a hardware issue that 871 * requires software to wait for 3 UART clock periods after enabling 872 * the TX fifo, otherwise data could be lost. 873 */ 874 tegra_uart_wait_cycle_time(tup, 3); 875 876 /* 877 * Initialize the UART with default configuration 878 * (115200, N, 8, 1) so that the receive DMA buffer may be 879 * enqueued 880 */ 881 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 882 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 883 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 884 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 885 886 ret = tegra_uart_start_rx_dma(tup); 887 if (ret < 0) { 888 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); 889 return ret; 890 } 891 tup->rx_in_progress = 1; 892 893 /* 894 * Enable IE_RXS for the receive status interrupts like line errros. 895 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 896 * 897 * If using DMA mode, enable EORD instead of receive interrupt which 898 * will interrupt after the UART is done with the receive instead of 899 * the interrupt when the FIFO "threshold" is reached. 900 * 901 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 902 * the DATA is sitting in the FIFO and couldn't be transferred to the 903 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be 904 * triggered when there is a pause of the incomming data stream for 4 905 * characters long. 906 * 907 * For pauses in the data which is not aligned to 4 bytes, we get 908 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 909 * then the EORD. 910 */ 911 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; 912 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 913 return 0; 914 } 915 916 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 917 bool dma_to_memory) 918 { 919 if (dma_to_memory) { 920 dmaengine_terminate_all(tup->rx_dma_chan); 921 dma_release_channel(tup->rx_dma_chan); 922 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 923 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 924 tup->rx_dma_chan = NULL; 925 tup->rx_dma_buf_phys = 0; 926 tup->rx_dma_buf_virt = NULL; 927 } else { 928 dmaengine_terminate_all(tup->tx_dma_chan); 929 dma_release_channel(tup->tx_dma_chan); 930 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 931 UART_XMIT_SIZE, DMA_TO_DEVICE); 932 tup->tx_dma_chan = NULL; 933 tup->tx_dma_buf_phys = 0; 934 tup->tx_dma_buf_virt = NULL; 935 } 936 } 937 938 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 939 bool dma_to_memory) 940 { 941 struct dma_chan *dma_chan; 942 unsigned char *dma_buf; 943 dma_addr_t dma_phys; 944 int ret; 945 struct dma_slave_config dma_sconfig; 946 947 dma_chan = dma_request_slave_channel_reason(tup->uport.dev, 948 dma_to_memory ? "rx" : "tx"); 949 if (IS_ERR(dma_chan)) { 950 ret = PTR_ERR(dma_chan); 951 dev_err(tup->uport.dev, 952 "DMA channel alloc failed: %d\n", ret); 953 return ret; 954 } 955 956 if (dma_to_memory) { 957 dma_buf = dma_alloc_coherent(tup->uport.dev, 958 TEGRA_UART_RX_DMA_BUFFER_SIZE, 959 &dma_phys, GFP_KERNEL); 960 if (!dma_buf) { 961 dev_err(tup->uport.dev, 962 "Not able to allocate the dma buffer\n"); 963 dma_release_channel(dma_chan); 964 return -ENOMEM; 965 } 966 dma_sconfig.src_addr = tup->uport.mapbase; 967 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 968 dma_sconfig.src_maxburst = 4; 969 tup->rx_dma_chan = dma_chan; 970 tup->rx_dma_buf_virt = dma_buf; 971 tup->rx_dma_buf_phys = dma_phys; 972 } else { 973 dma_phys = dma_map_single(tup->uport.dev, 974 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 975 DMA_TO_DEVICE); 976 if (dma_mapping_error(tup->uport.dev, dma_phys)) { 977 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); 978 dma_release_channel(dma_chan); 979 return -ENOMEM; 980 } 981 dma_buf = tup->uport.state->xmit.buf; 982 dma_sconfig.dst_addr = tup->uport.mapbase; 983 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 984 dma_sconfig.dst_maxburst = 16; 985 tup->tx_dma_chan = dma_chan; 986 tup->tx_dma_buf_virt = dma_buf; 987 tup->tx_dma_buf_phys = dma_phys; 988 } 989 990 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 991 if (ret < 0) { 992 dev_err(tup->uport.dev, 993 "Dma slave config failed, err = %d\n", ret); 994 tegra_uart_dma_channel_free(tup, dma_to_memory); 995 return ret; 996 } 997 998 return 0; 999 } 1000 1001 static int tegra_uart_startup(struct uart_port *u) 1002 { 1003 struct tegra_uart_port *tup = to_tegra_uport(u); 1004 int ret; 1005 1006 ret = tegra_uart_dma_channel_allocate(tup, false); 1007 if (ret < 0) { 1008 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret); 1009 return ret; 1010 } 1011 1012 ret = tegra_uart_dma_channel_allocate(tup, true); 1013 if (ret < 0) { 1014 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret); 1015 goto fail_rx_dma; 1016 } 1017 1018 ret = tegra_uart_hw_init(tup); 1019 if (ret < 0) { 1020 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1021 goto fail_hw_init; 1022 } 1023 1024 ret = request_irq(u->irq, tegra_uart_isr, 0, 1025 dev_name(u->dev), tup); 1026 if (ret < 0) { 1027 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1028 goto fail_hw_init; 1029 } 1030 return 0; 1031 1032 fail_hw_init: 1033 tegra_uart_dma_channel_free(tup, true); 1034 fail_rx_dma: 1035 tegra_uart_dma_channel_free(tup, false); 1036 return ret; 1037 } 1038 1039 /* 1040 * Flush any TX data submitted for DMA and PIO. Called when the 1041 * TX circular buffer is reset. 1042 */ 1043 static void tegra_uart_flush_buffer(struct uart_port *u) 1044 { 1045 struct tegra_uart_port *tup = to_tegra_uport(u); 1046 1047 tup->tx_bytes = 0; 1048 if (tup->tx_dma_chan) 1049 dmaengine_terminate_all(tup->tx_dma_chan); 1050 } 1051 1052 static void tegra_uart_shutdown(struct uart_port *u) 1053 { 1054 struct tegra_uart_port *tup = to_tegra_uport(u); 1055 1056 tegra_uart_hw_deinit(tup); 1057 1058 tup->rx_in_progress = 0; 1059 tup->tx_in_progress = 0; 1060 1061 tegra_uart_dma_channel_free(tup, true); 1062 tegra_uart_dma_channel_free(tup, false); 1063 free_irq(u->irq, tup); 1064 } 1065 1066 static void tegra_uart_enable_ms(struct uart_port *u) 1067 { 1068 struct tegra_uart_port *tup = to_tegra_uport(u); 1069 1070 if (tup->enable_modem_interrupt) { 1071 tup->ier_shadow |= UART_IER_MSI; 1072 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1073 } 1074 } 1075 1076 static void tegra_uart_set_termios(struct uart_port *u, 1077 struct ktermios *termios, struct ktermios *oldtermios) 1078 { 1079 struct tegra_uart_port *tup = to_tegra_uport(u); 1080 unsigned int baud; 1081 unsigned long flags; 1082 unsigned int lcr; 1083 int symb_bit = 1; 1084 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1085 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1086 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1087 1088 max_divider *= 16; 1089 spin_lock_irqsave(&u->lock, flags); 1090 1091 /* Changing configuration, it is safe to stop any rx now */ 1092 if (tup->rts_active) 1093 set_rts(tup, false); 1094 1095 /* Clear all interrupts as configuration is going to be change */ 1096 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1097 tegra_uart_read(tup, UART_IER); 1098 tegra_uart_write(tup, 0, UART_IER); 1099 tegra_uart_read(tup, UART_IER); 1100 1101 /* Parity */ 1102 lcr = tup->lcr_shadow; 1103 lcr &= ~UART_LCR_PARITY; 1104 1105 /* CMSPAR isn't supported by this driver */ 1106 termios->c_cflag &= ~CMSPAR; 1107 1108 if ((termios->c_cflag & PARENB) == PARENB) { 1109 symb_bit++; 1110 if (termios->c_cflag & PARODD) { 1111 lcr |= UART_LCR_PARITY; 1112 lcr &= ~UART_LCR_EPAR; 1113 lcr &= ~UART_LCR_SPAR; 1114 } else { 1115 lcr |= UART_LCR_PARITY; 1116 lcr |= UART_LCR_EPAR; 1117 lcr &= ~UART_LCR_SPAR; 1118 } 1119 } 1120 1121 lcr &= ~UART_LCR_WLEN8; 1122 switch (termios->c_cflag & CSIZE) { 1123 case CS5: 1124 lcr |= UART_LCR_WLEN5; 1125 symb_bit += 5; 1126 break; 1127 case CS6: 1128 lcr |= UART_LCR_WLEN6; 1129 symb_bit += 6; 1130 break; 1131 case CS7: 1132 lcr |= UART_LCR_WLEN7; 1133 symb_bit += 7; 1134 break; 1135 default: 1136 lcr |= UART_LCR_WLEN8; 1137 symb_bit += 8; 1138 break; 1139 } 1140 1141 /* Stop bits */ 1142 if (termios->c_cflag & CSTOPB) { 1143 lcr |= UART_LCR_STOP; 1144 symb_bit += 2; 1145 } else { 1146 lcr &= ~UART_LCR_STOP; 1147 symb_bit++; 1148 } 1149 1150 tegra_uart_write(tup, lcr, UART_LCR); 1151 tup->lcr_shadow = lcr; 1152 tup->symb_bit = symb_bit; 1153 1154 /* Baud rate. */ 1155 baud = uart_get_baud_rate(u, termios, oldtermios, 1156 parent_clk_rate/max_divider, 1157 parent_clk_rate/16); 1158 spin_unlock_irqrestore(&u->lock, flags); 1159 tegra_set_baudrate(tup, baud); 1160 if (tty_termios_baud_rate(termios)) 1161 tty_termios_encode_baud_rate(termios, baud, baud); 1162 spin_lock_irqsave(&u->lock, flags); 1163 1164 /* Flow control */ 1165 if (termios->c_cflag & CRTSCTS) { 1166 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1167 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1168 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1169 /* if top layer has asked to set rts active then do so here */ 1170 if (tup->rts_active) 1171 set_rts(tup, true); 1172 } else { 1173 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1174 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1175 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1176 } 1177 1178 /* update the port timeout based on new settings */ 1179 uart_update_timeout(u, termios->c_cflag, baud); 1180 1181 /* Make sure all write has completed */ 1182 tegra_uart_read(tup, UART_IER); 1183 1184 /* Reenable interrupt */ 1185 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1186 tegra_uart_read(tup, UART_IER); 1187 1188 spin_unlock_irqrestore(&u->lock, flags); 1189 } 1190 1191 static const char *tegra_uart_type(struct uart_port *u) 1192 { 1193 return TEGRA_UART_TYPE; 1194 } 1195 1196 static struct uart_ops tegra_uart_ops = { 1197 .tx_empty = tegra_uart_tx_empty, 1198 .set_mctrl = tegra_uart_set_mctrl, 1199 .get_mctrl = tegra_uart_get_mctrl, 1200 .stop_tx = tegra_uart_stop_tx, 1201 .start_tx = tegra_uart_start_tx, 1202 .stop_rx = tegra_uart_stop_rx, 1203 .flush_buffer = tegra_uart_flush_buffer, 1204 .enable_ms = tegra_uart_enable_ms, 1205 .break_ctl = tegra_uart_break_ctl, 1206 .startup = tegra_uart_startup, 1207 .shutdown = tegra_uart_shutdown, 1208 .set_termios = tegra_uart_set_termios, 1209 .type = tegra_uart_type, 1210 .request_port = tegra_uart_request_port, 1211 .release_port = tegra_uart_release_port, 1212 }; 1213 1214 static struct uart_driver tegra_uart_driver = { 1215 .owner = THIS_MODULE, 1216 .driver_name = "tegra_hsuart", 1217 .dev_name = "ttyTHS", 1218 .cons = NULL, 1219 .nr = TEGRA_UART_MAXIMUM, 1220 }; 1221 1222 static int tegra_uart_parse_dt(struct platform_device *pdev, 1223 struct tegra_uart_port *tup) 1224 { 1225 struct device_node *np = pdev->dev.of_node; 1226 int port; 1227 1228 port = of_alias_get_id(np, "serial"); 1229 if (port < 0) { 1230 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1231 return port; 1232 } 1233 tup->uport.line = port; 1234 1235 tup->enable_modem_interrupt = of_property_read_bool(np, 1236 "nvidia,enable-modem-interrupt"); 1237 return 0; 1238 } 1239 1240 static struct tegra_uart_chip_data tegra20_uart_chip_data = { 1241 .tx_fifo_full_status = false, 1242 .allow_txfifo_reset_fifo_mode = true, 1243 .support_clk_src_div = false, 1244 }; 1245 1246 static struct tegra_uart_chip_data tegra30_uart_chip_data = { 1247 .tx_fifo_full_status = true, 1248 .allow_txfifo_reset_fifo_mode = false, 1249 .support_clk_src_div = true, 1250 }; 1251 1252 static const struct of_device_id tegra_uart_of_match[] = { 1253 { 1254 .compatible = "nvidia,tegra30-hsuart", 1255 .data = &tegra30_uart_chip_data, 1256 }, { 1257 .compatible = "nvidia,tegra20-hsuart", 1258 .data = &tegra20_uart_chip_data, 1259 }, { 1260 }, 1261 }; 1262 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1263 1264 static int tegra_uart_probe(struct platform_device *pdev) 1265 { 1266 struct tegra_uart_port *tup; 1267 struct uart_port *u; 1268 struct resource *resource; 1269 int ret; 1270 const struct tegra_uart_chip_data *cdata; 1271 const struct of_device_id *match; 1272 1273 match = of_match_device(tegra_uart_of_match, &pdev->dev); 1274 if (!match) { 1275 dev_err(&pdev->dev, "Error: No device match found\n"); 1276 return -ENODEV; 1277 } 1278 cdata = match->data; 1279 1280 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1281 if (!tup) { 1282 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1283 return -ENOMEM; 1284 } 1285 1286 ret = tegra_uart_parse_dt(pdev, tup); 1287 if (ret < 0) 1288 return ret; 1289 1290 u = &tup->uport; 1291 u->dev = &pdev->dev; 1292 u->ops = &tegra_uart_ops; 1293 u->type = PORT_TEGRA; 1294 u->fifosize = 32; 1295 tup->cdata = cdata; 1296 1297 platform_set_drvdata(pdev, tup); 1298 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1299 if (!resource) { 1300 dev_err(&pdev->dev, "No IO memory resource\n"); 1301 return -ENODEV; 1302 } 1303 1304 u->mapbase = resource->start; 1305 u->membase = devm_ioremap_resource(&pdev->dev, resource); 1306 if (IS_ERR(u->membase)) 1307 return PTR_ERR(u->membase); 1308 1309 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1310 if (IS_ERR(tup->uart_clk)) { 1311 dev_err(&pdev->dev, "Couldn't get the clock\n"); 1312 return PTR_ERR(tup->uart_clk); 1313 } 1314 1315 tup->rst = devm_reset_control_get(&pdev->dev, "serial"); 1316 if (IS_ERR(tup->rst)) { 1317 dev_err(&pdev->dev, "Couldn't get the reset\n"); 1318 return PTR_ERR(tup->rst); 1319 } 1320 1321 u->iotype = UPIO_MEM32; 1322 u->irq = platform_get_irq(pdev, 0); 1323 u->regshift = 2; 1324 ret = uart_add_one_port(&tegra_uart_driver, u); 1325 if (ret < 0) { 1326 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1327 return ret; 1328 } 1329 return ret; 1330 } 1331 1332 static int tegra_uart_remove(struct platform_device *pdev) 1333 { 1334 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1335 struct uart_port *u = &tup->uport; 1336 1337 uart_remove_one_port(&tegra_uart_driver, u); 1338 return 0; 1339 } 1340 1341 #ifdef CONFIG_PM_SLEEP 1342 static int tegra_uart_suspend(struct device *dev) 1343 { 1344 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1345 struct uart_port *u = &tup->uport; 1346 1347 return uart_suspend_port(&tegra_uart_driver, u); 1348 } 1349 1350 static int tegra_uart_resume(struct device *dev) 1351 { 1352 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1353 struct uart_port *u = &tup->uport; 1354 1355 return uart_resume_port(&tegra_uart_driver, u); 1356 } 1357 #endif 1358 1359 static const struct dev_pm_ops tegra_uart_pm_ops = { 1360 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1361 }; 1362 1363 static struct platform_driver tegra_uart_platform_driver = { 1364 .probe = tegra_uart_probe, 1365 .remove = tegra_uart_remove, 1366 .driver = { 1367 .name = "serial-tegra", 1368 .of_match_table = tegra_uart_of_match, 1369 .pm = &tegra_uart_pm_ops, 1370 }, 1371 }; 1372 1373 static int __init tegra_uart_init(void) 1374 { 1375 int ret; 1376 1377 ret = uart_register_driver(&tegra_uart_driver); 1378 if (ret < 0) { 1379 pr_err("Could not register %s driver\n", 1380 tegra_uart_driver.driver_name); 1381 return ret; 1382 } 1383 1384 ret = platform_driver_register(&tegra_uart_platform_driver); 1385 if (ret < 0) { 1386 pr_err("Uart platform driver register failed, e = %d\n", ret); 1387 uart_unregister_driver(&tegra_uart_driver); 1388 return ret; 1389 } 1390 return 0; 1391 } 1392 1393 static void __exit tegra_uart_exit(void) 1394 { 1395 pr_info("Unloading tegra uart driver\n"); 1396 platform_driver_unregister(&tegra_uart_platform_driver); 1397 uart_unregister_driver(&tegra_uart_driver); 1398 } 1399 1400 module_init(tegra_uart_init); 1401 module_exit(tegra_uart_exit); 1402 1403 MODULE_ALIAS("platform:serial-tegra"); 1404 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1405 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1406 MODULE_LICENSE("GPL v2"); 1407