1 /* 2 * serial_tegra.c 3 * 4 * High-speed serial driver for NVIDIA Tegra SoCs 5 * 6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/debugfs.h> 25 #include <linux/delay.h> 26 #include <linux/dmaengine.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmapool.h> 29 #include <linux/io.h> 30 #include <linux/irq.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/pagemap.h> 35 #include <linux/platform_device.h> 36 #include <linux/serial.h> 37 #include <linux/serial_8250.h> 38 #include <linux/serial_core.h> 39 #include <linux/serial_reg.h> 40 #include <linux/slab.h> 41 #include <linux/string.h> 42 #include <linux/termios.h> 43 #include <linux/tty.h> 44 #include <linux/tty_flip.h> 45 46 #include <linux/clk/tegra.h> 47 48 #define TEGRA_UART_TYPE "TEGRA_UART" 49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 51 52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 54 #define TEGRA_UART_IER_EORD 0x20 55 #define TEGRA_UART_MCR_RTS_EN 0x40 56 #define TEGRA_UART_MCR_CTS_EN 0x20 57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 58 UART_LSR_PE | UART_LSR_FE) 59 #define TEGRA_UART_IRDA_CSR 0x08 60 #define TEGRA_UART_SIR_ENABLED 0x80 61 62 #define TEGRA_UART_TX_PIO 1 63 #define TEGRA_UART_TX_DMA 2 64 #define TEGRA_UART_MIN_DMA 16 65 #define TEGRA_UART_FIFO_SIZE 32 66 67 /* 68 * Tx fifo trigger level setting in tegra uart is in 69 * reverse way then conventional uart. 70 */ 71 #define TEGRA_UART_TX_TRIG_16B 0x00 72 #define TEGRA_UART_TX_TRIG_8B 0x10 73 #define TEGRA_UART_TX_TRIG_4B 0x20 74 #define TEGRA_UART_TX_TRIG_1B 0x30 75 76 #define TEGRA_UART_MAXIMUM 5 77 78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 79 #define TEGRA_UART_DEFAULT_BAUD 115200 80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 81 82 /* Tx transfer mode */ 83 #define TEGRA_TX_PIO 1 84 #define TEGRA_TX_DMA 2 85 86 /** 87 * tegra_uart_chip_data: SOC specific data. 88 * 89 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 91 * Tegra30 does not allow this. 92 * @support_clk_src_div: Clock source support the clock divider. 93 */ 94 struct tegra_uart_chip_data { 95 bool tx_fifo_full_status; 96 bool allow_txfifo_reset_fifo_mode; 97 bool support_clk_src_div; 98 }; 99 100 struct tegra_uart_port { 101 struct uart_port uport; 102 const struct tegra_uart_chip_data *cdata; 103 104 struct clk *uart_clk; 105 unsigned int current_baud; 106 107 /* Register shadow */ 108 unsigned long fcr_shadow; 109 unsigned long mcr_shadow; 110 unsigned long lcr_shadow; 111 unsigned long ier_shadow; 112 bool rts_active; 113 114 int tx_in_progress; 115 unsigned int tx_bytes; 116 117 bool enable_modem_interrupt; 118 119 bool rx_timeout; 120 int rx_in_progress; 121 int symb_bit; 122 int dma_req_sel; 123 124 struct dma_chan *rx_dma_chan; 125 struct dma_chan *tx_dma_chan; 126 dma_addr_t rx_dma_buf_phys; 127 dma_addr_t tx_dma_buf_phys; 128 unsigned char *rx_dma_buf_virt; 129 unsigned char *tx_dma_buf_virt; 130 struct dma_async_tx_descriptor *tx_dma_desc; 131 struct dma_async_tx_descriptor *rx_dma_desc; 132 dma_cookie_t tx_cookie; 133 dma_cookie_t rx_cookie; 134 int tx_bytes_requested; 135 int rx_bytes_requested; 136 }; 137 138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 140 141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 142 unsigned long reg) 143 { 144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 145 } 146 147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 148 unsigned long reg) 149 { 150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 151 } 152 153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 154 { 155 return container_of(u, struct tegra_uart_port, uport); 156 } 157 158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 159 { 160 struct tegra_uart_port *tup = to_tegra_uport(u); 161 162 /* 163 * RI - Ring detector is active 164 * CD/DCD/CAR - Carrier detect is always active. For some reason 165 * linux has different names for carrier detect. 166 * DSR - Data Set ready is active as the hardware doesn't support it. 167 * Don't know if the linux support this yet? 168 * CTS - Clear to send. Always set to active, as the hardware handles 169 * CTS automatically. 170 */ 171 if (tup->enable_modem_interrupt) 172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 173 return TIOCM_CTS; 174 } 175 176 static void set_rts(struct tegra_uart_port *tup, bool active) 177 { 178 unsigned long mcr; 179 180 mcr = tup->mcr_shadow; 181 if (active) 182 mcr |= TEGRA_UART_MCR_RTS_EN; 183 else 184 mcr &= ~TEGRA_UART_MCR_RTS_EN; 185 if (mcr != tup->mcr_shadow) { 186 tegra_uart_write(tup, mcr, UART_MCR); 187 tup->mcr_shadow = mcr; 188 } 189 return; 190 } 191 192 static void set_dtr(struct tegra_uart_port *tup, bool active) 193 { 194 unsigned long mcr; 195 196 mcr = tup->mcr_shadow; 197 if (active) 198 mcr |= UART_MCR_DTR; 199 else 200 mcr &= ~UART_MCR_DTR; 201 if (mcr != tup->mcr_shadow) { 202 tegra_uart_write(tup, mcr, UART_MCR); 203 tup->mcr_shadow = mcr; 204 } 205 return; 206 } 207 208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 209 { 210 struct tegra_uart_port *tup = to_tegra_uport(u); 211 unsigned long mcr; 212 int dtr_enable; 213 214 mcr = tup->mcr_shadow; 215 tup->rts_active = !!(mctrl & TIOCM_RTS); 216 set_rts(tup, tup->rts_active); 217 218 dtr_enable = !!(mctrl & TIOCM_DTR); 219 set_dtr(tup, dtr_enable); 220 return; 221 } 222 223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 224 { 225 struct tegra_uart_port *tup = to_tegra_uport(u); 226 unsigned long lcr; 227 228 lcr = tup->lcr_shadow; 229 if (break_ctl) 230 lcr |= UART_LCR_SBC; 231 else 232 lcr &= ~UART_LCR_SBC; 233 tegra_uart_write(tup, lcr, UART_LCR); 234 tup->lcr_shadow = lcr; 235 } 236 237 /* Wait for a symbol-time. */ 238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 239 unsigned int syms) 240 { 241 if (tup->current_baud) 242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 243 tup->current_baud)); 244 } 245 246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 247 { 248 unsigned long fcr = tup->fcr_shadow; 249 250 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 252 tegra_uart_write(tup, fcr, UART_FCR); 253 } else { 254 fcr &= ~UART_FCR_ENABLE_FIFO; 255 tegra_uart_write(tup, fcr, UART_FCR); 256 udelay(60); 257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 258 tegra_uart_write(tup, fcr, UART_FCR); 259 fcr |= UART_FCR_ENABLE_FIFO; 260 tegra_uart_write(tup, fcr, UART_FCR); 261 } 262 263 /* Dummy read to ensure the write is posted */ 264 tegra_uart_read(tup, UART_SCR); 265 266 /* Wait for the flush to propagate. */ 267 tegra_uart_wait_sym_time(tup, 1); 268 } 269 270 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 271 { 272 unsigned long rate; 273 unsigned int divisor; 274 unsigned long lcr; 275 int ret; 276 277 if (tup->current_baud == baud) 278 return 0; 279 280 if (tup->cdata->support_clk_src_div) { 281 rate = baud * 16; 282 ret = clk_set_rate(tup->uart_clk, rate); 283 if (ret < 0) { 284 dev_err(tup->uport.dev, 285 "clk_set_rate() failed for rate %lu\n", rate); 286 return ret; 287 } 288 divisor = 1; 289 } else { 290 rate = clk_get_rate(tup->uart_clk); 291 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 292 } 293 294 lcr = tup->lcr_shadow; 295 lcr |= UART_LCR_DLAB; 296 tegra_uart_write(tup, lcr, UART_LCR); 297 298 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 300 301 lcr &= ~UART_LCR_DLAB; 302 tegra_uart_write(tup, lcr, UART_LCR); 303 304 /* Dummy read to ensure the write is posted */ 305 tegra_uart_read(tup, UART_SCR); 306 307 tup->current_baud = baud; 308 309 /* wait two character intervals at new rate */ 310 tegra_uart_wait_sym_time(tup, 2); 311 return 0; 312 } 313 314 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 315 unsigned long lsr) 316 { 317 char flag = TTY_NORMAL; 318 319 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 320 if (lsr & UART_LSR_OE) { 321 /* Overrrun error */ 322 flag |= TTY_OVERRUN; 323 tup->uport.icount.overrun++; 324 dev_err(tup->uport.dev, "Got overrun errors\n"); 325 } else if (lsr & UART_LSR_PE) { 326 /* Parity error */ 327 flag |= TTY_PARITY; 328 tup->uport.icount.parity++; 329 dev_err(tup->uport.dev, "Got Parity errors\n"); 330 } else if (lsr & UART_LSR_FE) { 331 flag |= TTY_FRAME; 332 tup->uport.icount.frame++; 333 dev_err(tup->uport.dev, "Got frame errors\n"); 334 } else if (lsr & UART_LSR_BI) { 335 dev_err(tup->uport.dev, "Got Break\n"); 336 tup->uport.icount.brk++; 337 /* If FIFO read error without any data, reset Rx FIFO */ 338 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 339 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 340 } 341 } 342 return flag; 343 } 344 345 static int tegra_uart_request_port(struct uart_port *u) 346 { 347 return 0; 348 } 349 350 static void tegra_uart_release_port(struct uart_port *u) 351 { 352 /* Nothing to do here */ 353 } 354 355 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 356 { 357 struct circ_buf *xmit = &tup->uport.state->xmit; 358 int i; 359 360 for (i = 0; i < max_bytes; i++) { 361 BUG_ON(uart_circ_empty(xmit)); 362 if (tup->cdata->tx_fifo_full_status) { 363 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 364 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 365 break; 366 } 367 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 368 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 369 tup->uport.icount.tx++; 370 } 371 } 372 373 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 374 unsigned int bytes) 375 { 376 if (bytes > TEGRA_UART_MIN_DMA) 377 bytes = TEGRA_UART_MIN_DMA; 378 379 tup->tx_in_progress = TEGRA_UART_TX_PIO; 380 tup->tx_bytes = bytes; 381 tup->ier_shadow |= UART_IER_THRI; 382 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 383 } 384 385 static void tegra_uart_tx_dma_complete(void *args) 386 { 387 struct tegra_uart_port *tup = args; 388 struct circ_buf *xmit = &tup->uport.state->xmit; 389 struct dma_tx_state state; 390 unsigned long flags; 391 int count; 392 393 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state); 394 count = tup->tx_bytes_requested - state.residue; 395 async_tx_ack(tup->tx_dma_desc); 396 spin_lock_irqsave(&tup->uport.lock, flags); 397 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 398 tup->tx_in_progress = 0; 399 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 400 uart_write_wakeup(&tup->uport); 401 tegra_uart_start_next_tx(tup); 402 spin_unlock_irqrestore(&tup->uport.lock, flags); 403 } 404 405 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 406 unsigned long count) 407 { 408 struct circ_buf *xmit = &tup->uport.state->xmit; 409 dma_addr_t tx_phys_addr; 410 411 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, 412 UART_XMIT_SIZE, DMA_TO_DEVICE); 413 414 tup->tx_bytes = count & ~(0xF); 415 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 416 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 417 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 418 DMA_PREP_INTERRUPT); 419 if (!tup->tx_dma_desc) { 420 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 421 return -EIO; 422 } 423 424 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 425 tup->tx_dma_desc->callback_param = tup; 426 tup->tx_in_progress = TEGRA_UART_TX_DMA; 427 tup->tx_bytes_requested = tup->tx_bytes; 428 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 429 dma_async_issue_pending(tup->tx_dma_chan); 430 return 0; 431 } 432 433 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 434 { 435 unsigned long tail; 436 unsigned long count; 437 struct circ_buf *xmit = &tup->uport.state->xmit; 438 439 tail = (unsigned long)&xmit->buf[xmit->tail]; 440 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 441 if (!count) 442 return; 443 444 if (count < TEGRA_UART_MIN_DMA) 445 tegra_uart_start_pio_tx(tup, count); 446 else if (BYTES_TO_ALIGN(tail) > 0) 447 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 448 else 449 tegra_uart_start_tx_dma(tup, count); 450 } 451 452 /* Called by serial core driver with u->lock taken. */ 453 static void tegra_uart_start_tx(struct uart_port *u) 454 { 455 struct tegra_uart_port *tup = to_tegra_uport(u); 456 struct circ_buf *xmit = &u->state->xmit; 457 458 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 459 tegra_uart_start_next_tx(tup); 460 } 461 462 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 463 { 464 struct tegra_uart_port *tup = to_tegra_uport(u); 465 unsigned int ret = 0; 466 unsigned long flags; 467 468 spin_lock_irqsave(&u->lock, flags); 469 if (!tup->tx_in_progress) { 470 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 471 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 472 ret = TIOCSER_TEMT; 473 } 474 spin_unlock_irqrestore(&u->lock, flags); 475 return ret; 476 } 477 478 static void tegra_uart_stop_tx(struct uart_port *u) 479 { 480 struct tegra_uart_port *tup = to_tegra_uport(u); 481 struct circ_buf *xmit = &tup->uport.state->xmit; 482 struct dma_tx_state state; 483 int count; 484 485 dmaengine_terminate_all(tup->tx_dma_chan); 486 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 487 count = tup->tx_bytes_requested - state.residue; 488 async_tx_ack(tup->tx_dma_desc); 489 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 490 tup->tx_in_progress = 0; 491 return; 492 } 493 494 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 495 { 496 struct circ_buf *xmit = &tup->uport.state->xmit; 497 498 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 499 tup->tx_in_progress = 0; 500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 501 uart_write_wakeup(&tup->uport); 502 tegra_uart_start_next_tx(tup); 503 return; 504 } 505 506 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 507 struct tty_port *tty) 508 { 509 do { 510 char flag = TTY_NORMAL; 511 unsigned long lsr = 0; 512 unsigned char ch; 513 514 lsr = tegra_uart_read(tup, UART_LSR); 515 if (!(lsr & UART_LSR_DR)) 516 break; 517 518 flag = tegra_uart_decode_rx_error(tup, lsr); 519 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 520 tup->uport.icount.rx++; 521 522 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) 523 tty_insert_flip_char(tty, ch, flag); 524 } while (1); 525 526 return; 527 } 528 529 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 530 struct tty_port *tty, int count) 531 { 532 int copied; 533 534 tup->uport.icount.rx += count; 535 if (!tty) { 536 dev_err(tup->uport.dev, "No tty port\n"); 537 return; 538 } 539 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 540 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 541 copied = tty_insert_flip_string(tty, 542 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 543 if (copied != count) { 544 WARN_ON(1); 545 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 546 } 547 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 548 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 549 } 550 551 static void tegra_uart_rx_dma_complete(void *args) 552 { 553 struct tegra_uart_port *tup = args; 554 struct uart_port *u = &tup->uport; 555 int count = tup->rx_bytes_requested; 556 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 557 struct tty_port *port = &u->state->port; 558 unsigned long flags; 559 560 async_tx_ack(tup->rx_dma_desc); 561 spin_lock_irqsave(&u->lock, flags); 562 563 /* Deactivate flow control to stop sender */ 564 if (tup->rts_active) 565 set_rts(tup, false); 566 567 /* If we are here, DMA is stopped */ 568 if (count) 569 tegra_uart_copy_rx_to_tty(tup, port, count); 570 571 tegra_uart_handle_rx_pio(tup, port); 572 if (tty) { 573 tty_flip_buffer_push(port); 574 tty_kref_put(tty); 575 } 576 tegra_uart_start_rx_dma(tup); 577 578 /* Activate flow control to start transfer */ 579 if (tup->rts_active) 580 set_rts(tup, true); 581 582 spin_unlock_irqrestore(&u->lock, flags); 583 } 584 585 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) 586 { 587 struct dma_tx_state state; 588 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 589 struct tty_port *port = &tup->uport.state->port; 590 int count; 591 592 /* Deactivate flow control to stop sender */ 593 if (tup->rts_active) 594 set_rts(tup, false); 595 596 dmaengine_terminate_all(tup->rx_dma_chan); 597 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 598 count = tup->rx_bytes_requested - state.residue; 599 600 /* If we are here, DMA is stopped */ 601 if (count) 602 tegra_uart_copy_rx_to_tty(tup, port, count); 603 604 tegra_uart_handle_rx_pio(tup, port); 605 if (tty) { 606 tty_flip_buffer_push(port); 607 tty_kref_put(tty); 608 } 609 tegra_uart_start_rx_dma(tup); 610 611 if (tup->rts_active) 612 set_rts(tup, true); 613 } 614 615 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 616 { 617 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 618 619 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 620 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 621 DMA_PREP_INTERRUPT); 622 if (!tup->rx_dma_desc) { 623 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 624 return -EIO; 625 } 626 627 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 628 tup->rx_dma_desc->callback_param = tup; 629 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 630 count, DMA_TO_DEVICE); 631 tup->rx_bytes_requested = count; 632 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 633 dma_async_issue_pending(tup->rx_dma_chan); 634 return 0; 635 } 636 637 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 638 { 639 struct tegra_uart_port *tup = to_tegra_uport(u); 640 unsigned long msr; 641 642 msr = tegra_uart_read(tup, UART_MSR); 643 if (!(msr & UART_MSR_ANY_DELTA)) 644 return; 645 646 if (msr & UART_MSR_TERI) 647 tup->uport.icount.rng++; 648 if (msr & UART_MSR_DDSR) 649 tup->uport.icount.dsr++; 650 /* We may only get DDCD when HW init and reset */ 651 if (msr & UART_MSR_DDCD) 652 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 653 /* Will start/stop_tx accordingly */ 654 if (msr & UART_MSR_DCTS) 655 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 656 return; 657 } 658 659 static irqreturn_t tegra_uart_isr(int irq, void *data) 660 { 661 struct tegra_uart_port *tup = data; 662 struct uart_port *u = &tup->uport; 663 unsigned long iir; 664 unsigned long ier; 665 bool is_rx_int = false; 666 unsigned long flags; 667 668 spin_lock_irqsave(&u->lock, flags); 669 while (1) { 670 iir = tegra_uart_read(tup, UART_IIR); 671 if (iir & UART_IIR_NO_INT) { 672 if (is_rx_int) { 673 tegra_uart_handle_rx_dma(tup); 674 if (tup->rx_in_progress) { 675 ier = tup->ier_shadow; 676 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 677 TEGRA_UART_IER_EORD); 678 tup->ier_shadow = ier; 679 tegra_uart_write(tup, ier, UART_IER); 680 } 681 } 682 spin_unlock_irqrestore(&u->lock, flags); 683 return IRQ_HANDLED; 684 } 685 686 switch ((iir >> 1) & 0x7) { 687 case 0: /* Modem signal change interrupt */ 688 tegra_uart_handle_modem_signal_change(u); 689 break; 690 691 case 1: /* Transmit interrupt only triggered when using PIO */ 692 tup->ier_shadow &= ~UART_IER_THRI; 693 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 694 tegra_uart_handle_tx_pio(tup); 695 break; 696 697 case 4: /* End of data */ 698 case 6: /* Rx timeout */ 699 case 2: /* Receive */ 700 if (!is_rx_int) { 701 is_rx_int = true; 702 /* Disable Rx interrupts */ 703 ier = tup->ier_shadow; 704 ier |= UART_IER_RDI; 705 tegra_uart_write(tup, ier, UART_IER); 706 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 707 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 708 tup->ier_shadow = ier; 709 tegra_uart_write(tup, ier, UART_IER); 710 } 711 break; 712 713 case 3: /* Receive error */ 714 tegra_uart_decode_rx_error(tup, 715 tegra_uart_read(tup, UART_LSR)); 716 break; 717 718 case 5: /* break nothing to handle */ 719 case 7: /* break nothing to handle */ 720 break; 721 } 722 } 723 } 724 725 static void tegra_uart_stop_rx(struct uart_port *u) 726 { 727 struct tegra_uart_port *tup = to_tegra_uport(u); 728 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 729 struct tty_port *port = &u->state->port; 730 struct dma_tx_state state; 731 unsigned long ier; 732 int count; 733 734 if (tup->rts_active) 735 set_rts(tup, false); 736 737 if (!tup->rx_in_progress) 738 return; 739 740 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ 741 742 ier = tup->ier_shadow; 743 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 744 TEGRA_UART_IER_EORD); 745 tup->ier_shadow = ier; 746 tegra_uart_write(tup, ier, UART_IER); 747 tup->rx_in_progress = 0; 748 if (tup->rx_dma_chan) { 749 dmaengine_terminate_all(tup->rx_dma_chan); 750 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 751 async_tx_ack(tup->rx_dma_desc); 752 count = tup->rx_bytes_requested - state.residue; 753 tegra_uart_copy_rx_to_tty(tup, port, count); 754 tegra_uart_handle_rx_pio(tup, port); 755 } else { 756 tegra_uart_handle_rx_pio(tup, port); 757 } 758 if (tty) { 759 tty_flip_buffer_push(port); 760 tty_kref_put(tty); 761 } 762 return; 763 } 764 765 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 766 { 767 unsigned long flags; 768 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 769 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 770 unsigned long wait_time; 771 unsigned long lsr; 772 unsigned long msr; 773 unsigned long mcr; 774 775 /* Disable interrupts */ 776 tegra_uart_write(tup, 0, UART_IER); 777 778 lsr = tegra_uart_read(tup, UART_LSR); 779 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 780 msr = tegra_uart_read(tup, UART_MSR); 781 mcr = tegra_uart_read(tup, UART_MCR); 782 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 783 dev_err(tup->uport.dev, 784 "Tx Fifo not empty, CTS disabled, waiting\n"); 785 786 /* Wait for Tx fifo to be empty */ 787 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 788 wait_time = min(fifo_empty_time, 100lu); 789 udelay(wait_time); 790 fifo_empty_time -= wait_time; 791 if (!fifo_empty_time) { 792 msr = tegra_uart_read(tup, UART_MSR); 793 mcr = tegra_uart_read(tup, UART_MCR); 794 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 795 (msr & UART_MSR_CTS)) 796 dev_err(tup->uport.dev, 797 "Slave not ready\n"); 798 break; 799 } 800 lsr = tegra_uart_read(tup, UART_LSR); 801 } 802 } 803 804 spin_lock_irqsave(&tup->uport.lock, flags); 805 /* Reset the Rx and Tx FIFOs */ 806 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 807 tup->current_baud = 0; 808 spin_unlock_irqrestore(&tup->uport.lock, flags); 809 810 clk_disable_unprepare(tup->uart_clk); 811 } 812 813 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 814 { 815 int ret; 816 817 tup->fcr_shadow = 0; 818 tup->mcr_shadow = 0; 819 tup->lcr_shadow = 0; 820 tup->ier_shadow = 0; 821 tup->current_baud = 0; 822 823 clk_prepare_enable(tup->uart_clk); 824 825 /* Reset the UART controller to clear all previous status.*/ 826 tegra_periph_reset_assert(tup->uart_clk); 827 udelay(10); 828 tegra_periph_reset_deassert(tup->uart_clk); 829 830 tup->rx_in_progress = 0; 831 tup->tx_in_progress = 0; 832 833 /* 834 * Set the trigger level 835 * 836 * For PIO mode: 837 * 838 * For receive, this will interrupt the CPU after that many number of 839 * bytes are received, for the remaining bytes the receive timeout 840 * interrupt is received. Rx high watermark is set to 4. 841 * 842 * For transmit, if the trasnmit interrupt is enabled, this will 843 * interrupt the CPU when the number of entries in the FIFO reaches the 844 * low watermark. Tx low watermark is set to 16 bytes. 845 * 846 * For DMA mode: 847 * 848 * Set the Tx trigger to 16. This should match the DMA burst size that 849 * programmed in the DMA registers. 850 */ 851 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 852 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 853 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 854 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 855 856 /* 857 * Initialize the UART with default configuration 858 * (115200, N, 8, 1) so that the receive DMA buffer may be 859 * enqueued 860 */ 861 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 862 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 863 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 864 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 865 866 ret = tegra_uart_start_rx_dma(tup); 867 if (ret < 0) { 868 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); 869 return ret; 870 } 871 tup->rx_in_progress = 1; 872 873 /* 874 * Enable IE_RXS for the receive status interrupts like line errros. 875 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 876 * 877 * If using DMA mode, enable EORD instead of receive interrupt which 878 * will interrupt after the UART is done with the receive instead of 879 * the interrupt when the FIFO "threshold" is reached. 880 * 881 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 882 * the DATA is sitting in the FIFO and couldn't be transferred to the 883 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be 884 * triggered when there is a pause of the incomming data stream for 4 885 * characters long. 886 * 887 * For pauses in the data which is not aligned to 4 bytes, we get 888 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 889 * then the EORD. 890 */ 891 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; 892 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 893 return 0; 894 } 895 896 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 897 bool dma_to_memory) 898 { 899 struct dma_chan *dma_chan; 900 unsigned char *dma_buf; 901 dma_addr_t dma_phys; 902 int ret; 903 struct dma_slave_config dma_sconfig; 904 dma_cap_mask_t mask; 905 906 dma_cap_zero(mask); 907 dma_cap_set(DMA_SLAVE, mask); 908 dma_chan = dma_request_channel(mask, NULL, NULL); 909 if (!dma_chan) { 910 dev_err(tup->uport.dev, 911 "Dma channel is not available, will try later\n"); 912 return -EPROBE_DEFER; 913 } 914 915 if (dma_to_memory) { 916 dma_buf = dma_alloc_coherent(tup->uport.dev, 917 TEGRA_UART_RX_DMA_BUFFER_SIZE, 918 &dma_phys, GFP_KERNEL); 919 if (!dma_buf) { 920 dev_err(tup->uport.dev, 921 "Not able to allocate the dma buffer\n"); 922 dma_release_channel(dma_chan); 923 return -ENOMEM; 924 } 925 } else { 926 dma_phys = dma_map_single(tup->uport.dev, 927 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 928 DMA_TO_DEVICE); 929 dma_buf = tup->uport.state->xmit.buf; 930 } 931 932 dma_sconfig.slave_id = tup->dma_req_sel; 933 if (dma_to_memory) { 934 dma_sconfig.src_addr = tup->uport.mapbase; 935 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 936 dma_sconfig.src_maxburst = 4; 937 } else { 938 dma_sconfig.dst_addr = tup->uport.mapbase; 939 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 940 dma_sconfig.dst_maxburst = 16; 941 } 942 943 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 944 if (ret < 0) { 945 dev_err(tup->uport.dev, 946 "Dma slave config failed, err = %d\n", ret); 947 goto scrub; 948 } 949 950 if (dma_to_memory) { 951 tup->rx_dma_chan = dma_chan; 952 tup->rx_dma_buf_virt = dma_buf; 953 tup->rx_dma_buf_phys = dma_phys; 954 } else { 955 tup->tx_dma_chan = dma_chan; 956 tup->tx_dma_buf_virt = dma_buf; 957 tup->tx_dma_buf_phys = dma_phys; 958 } 959 return 0; 960 961 scrub: 962 dma_release_channel(dma_chan); 963 return ret; 964 } 965 966 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 967 bool dma_to_memory) 968 { 969 struct dma_chan *dma_chan; 970 971 if (dma_to_memory) { 972 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 973 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 974 dma_chan = tup->rx_dma_chan; 975 tup->rx_dma_chan = NULL; 976 tup->rx_dma_buf_phys = 0; 977 tup->rx_dma_buf_virt = NULL; 978 } else { 979 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 980 UART_XMIT_SIZE, DMA_TO_DEVICE); 981 dma_chan = tup->tx_dma_chan; 982 tup->tx_dma_chan = NULL; 983 tup->tx_dma_buf_phys = 0; 984 tup->tx_dma_buf_virt = NULL; 985 } 986 dma_release_channel(dma_chan); 987 } 988 989 static int tegra_uart_startup(struct uart_port *u) 990 { 991 struct tegra_uart_port *tup = to_tegra_uport(u); 992 int ret; 993 994 ret = tegra_uart_dma_channel_allocate(tup, false); 995 if (ret < 0) { 996 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret); 997 return ret; 998 } 999 1000 ret = tegra_uart_dma_channel_allocate(tup, true); 1001 if (ret < 0) { 1002 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret); 1003 goto fail_rx_dma; 1004 } 1005 1006 ret = tegra_uart_hw_init(tup); 1007 if (ret < 0) { 1008 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1009 goto fail_hw_init; 1010 } 1011 1012 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED, 1013 dev_name(u->dev), tup); 1014 if (ret < 0) { 1015 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1016 goto fail_hw_init; 1017 } 1018 return 0; 1019 1020 fail_hw_init: 1021 tegra_uart_dma_channel_free(tup, true); 1022 fail_rx_dma: 1023 tegra_uart_dma_channel_free(tup, false); 1024 return ret; 1025 } 1026 1027 static void tegra_uart_shutdown(struct uart_port *u) 1028 { 1029 struct tegra_uart_port *tup = to_tegra_uport(u); 1030 1031 tegra_uart_hw_deinit(tup); 1032 1033 tup->rx_in_progress = 0; 1034 tup->tx_in_progress = 0; 1035 1036 tegra_uart_dma_channel_free(tup, true); 1037 tegra_uart_dma_channel_free(tup, false); 1038 free_irq(u->irq, tup); 1039 } 1040 1041 static void tegra_uart_enable_ms(struct uart_port *u) 1042 { 1043 struct tegra_uart_port *tup = to_tegra_uport(u); 1044 1045 if (tup->enable_modem_interrupt) { 1046 tup->ier_shadow |= UART_IER_MSI; 1047 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1048 } 1049 } 1050 1051 static void tegra_uart_set_termios(struct uart_port *u, 1052 struct ktermios *termios, struct ktermios *oldtermios) 1053 { 1054 struct tegra_uart_port *tup = to_tegra_uport(u); 1055 unsigned int baud; 1056 unsigned long flags; 1057 unsigned int lcr; 1058 int symb_bit = 1; 1059 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1060 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1061 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1062 1063 max_divider *= 16; 1064 spin_lock_irqsave(&u->lock, flags); 1065 1066 /* Changing configuration, it is safe to stop any rx now */ 1067 if (tup->rts_active) 1068 set_rts(tup, false); 1069 1070 /* Clear all interrupts as configuration is going to be change */ 1071 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1072 tegra_uart_read(tup, UART_IER); 1073 tegra_uart_write(tup, 0, UART_IER); 1074 tegra_uart_read(tup, UART_IER); 1075 1076 /* Parity */ 1077 lcr = tup->lcr_shadow; 1078 lcr &= ~UART_LCR_PARITY; 1079 1080 /* CMSPAR isn't supported by this driver */ 1081 termios->c_cflag &= ~CMSPAR; 1082 1083 if ((termios->c_cflag & PARENB) == PARENB) { 1084 symb_bit++; 1085 if (termios->c_cflag & PARODD) { 1086 lcr |= UART_LCR_PARITY; 1087 lcr &= ~UART_LCR_EPAR; 1088 lcr &= ~UART_LCR_SPAR; 1089 } else { 1090 lcr |= UART_LCR_PARITY; 1091 lcr |= UART_LCR_EPAR; 1092 lcr &= ~UART_LCR_SPAR; 1093 } 1094 } 1095 1096 lcr &= ~UART_LCR_WLEN8; 1097 switch (termios->c_cflag & CSIZE) { 1098 case CS5: 1099 lcr |= UART_LCR_WLEN5; 1100 symb_bit += 5; 1101 break; 1102 case CS6: 1103 lcr |= UART_LCR_WLEN6; 1104 symb_bit += 6; 1105 break; 1106 case CS7: 1107 lcr |= UART_LCR_WLEN7; 1108 symb_bit += 7; 1109 break; 1110 default: 1111 lcr |= UART_LCR_WLEN8; 1112 symb_bit += 8; 1113 break; 1114 } 1115 1116 /* Stop bits */ 1117 if (termios->c_cflag & CSTOPB) { 1118 lcr |= UART_LCR_STOP; 1119 symb_bit += 2; 1120 } else { 1121 lcr &= ~UART_LCR_STOP; 1122 symb_bit++; 1123 } 1124 1125 tegra_uart_write(tup, lcr, UART_LCR); 1126 tup->lcr_shadow = lcr; 1127 tup->symb_bit = symb_bit; 1128 1129 /* Baud rate. */ 1130 baud = uart_get_baud_rate(u, termios, oldtermios, 1131 parent_clk_rate/max_divider, 1132 parent_clk_rate/16); 1133 spin_unlock_irqrestore(&u->lock, flags); 1134 tegra_set_baudrate(tup, baud); 1135 if (tty_termios_baud_rate(termios)) 1136 tty_termios_encode_baud_rate(termios, baud, baud); 1137 spin_lock_irqsave(&u->lock, flags); 1138 1139 /* Flow control */ 1140 if (termios->c_cflag & CRTSCTS) { 1141 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1142 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1143 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1144 /* if top layer has asked to set rts active then do so here */ 1145 if (tup->rts_active) 1146 set_rts(tup, true); 1147 } else { 1148 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1149 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1150 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1151 } 1152 1153 /* update the port timeout based on new settings */ 1154 uart_update_timeout(u, termios->c_cflag, baud); 1155 1156 /* Make sure all write has completed */ 1157 tegra_uart_read(tup, UART_IER); 1158 1159 /* Reenable interrupt */ 1160 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1161 tegra_uart_read(tup, UART_IER); 1162 1163 spin_unlock_irqrestore(&u->lock, flags); 1164 return; 1165 } 1166 1167 /* 1168 * Flush any TX data submitted for DMA and PIO. Called when the 1169 * TX circular buffer is reset. 1170 */ 1171 static void tegra_uart_flush_buffer(struct uart_port *u) 1172 { 1173 struct tegra_uart_port *tup = to_tegra_uport(u); 1174 1175 tup->tx_bytes = 0; 1176 if (tup->tx_dma_chan) 1177 dmaengine_terminate_all(tup->tx_dma_chan); 1178 return; 1179 } 1180 1181 static const char *tegra_uart_type(struct uart_port *u) 1182 { 1183 return TEGRA_UART_TYPE; 1184 } 1185 1186 static struct uart_ops tegra_uart_ops = { 1187 .tx_empty = tegra_uart_tx_empty, 1188 .set_mctrl = tegra_uart_set_mctrl, 1189 .get_mctrl = tegra_uart_get_mctrl, 1190 .stop_tx = tegra_uart_stop_tx, 1191 .start_tx = tegra_uart_start_tx, 1192 .stop_rx = tegra_uart_stop_rx, 1193 .flush_buffer = tegra_uart_flush_buffer, 1194 .enable_ms = tegra_uart_enable_ms, 1195 .break_ctl = tegra_uart_break_ctl, 1196 .startup = tegra_uart_startup, 1197 .shutdown = tegra_uart_shutdown, 1198 .set_termios = tegra_uart_set_termios, 1199 .type = tegra_uart_type, 1200 .request_port = tegra_uart_request_port, 1201 .release_port = tegra_uart_release_port, 1202 }; 1203 1204 static struct uart_driver tegra_uart_driver = { 1205 .owner = THIS_MODULE, 1206 .driver_name = "tegra_hsuart", 1207 .dev_name = "ttyTHS", 1208 .cons = 0, 1209 .nr = TEGRA_UART_MAXIMUM, 1210 }; 1211 1212 static int tegra_uart_parse_dt(struct platform_device *pdev, 1213 struct tegra_uart_port *tup) 1214 { 1215 struct device_node *np = pdev->dev.of_node; 1216 u32 of_dma[2]; 1217 int port; 1218 1219 if (of_property_read_u32_array(np, "nvidia,dma-request-selector", 1220 of_dma, 2) >= 0) { 1221 tup->dma_req_sel = of_dma[1]; 1222 } else { 1223 dev_err(&pdev->dev, "missing dma requestor in device tree\n"); 1224 return -EINVAL; 1225 } 1226 1227 port = of_alias_get_id(np, "serial"); 1228 if (port < 0) { 1229 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1230 return port; 1231 } 1232 tup->uport.line = port; 1233 1234 tup->enable_modem_interrupt = of_property_read_bool(np, 1235 "nvidia,enable-modem-interrupt"); 1236 return 0; 1237 } 1238 1239 struct tegra_uart_chip_data tegra20_uart_chip_data = { 1240 .tx_fifo_full_status = false, 1241 .allow_txfifo_reset_fifo_mode = true, 1242 .support_clk_src_div = false, 1243 }; 1244 1245 struct tegra_uart_chip_data tegra30_uart_chip_data = { 1246 .tx_fifo_full_status = true, 1247 .allow_txfifo_reset_fifo_mode = false, 1248 .support_clk_src_div = true, 1249 }; 1250 1251 static struct of_device_id tegra_uart_of_match[] = { 1252 { 1253 .compatible = "nvidia,tegra30-hsuart", 1254 .data = &tegra30_uart_chip_data, 1255 }, { 1256 .compatible = "nvidia,tegra20-hsuart", 1257 .data = &tegra20_uart_chip_data, 1258 }, { 1259 }, 1260 }; 1261 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1262 1263 static int tegra_uart_probe(struct platform_device *pdev) 1264 { 1265 struct tegra_uart_port *tup; 1266 struct uart_port *u; 1267 struct resource *resource; 1268 int ret; 1269 const struct tegra_uart_chip_data *cdata; 1270 const struct of_device_id *match; 1271 1272 match = of_match_device(tegra_uart_of_match, &pdev->dev); 1273 if (!match) { 1274 dev_err(&pdev->dev, "Error: No device match found\n"); 1275 return -ENODEV; 1276 } 1277 cdata = match->data; 1278 1279 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1280 if (!tup) { 1281 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1282 return -ENOMEM; 1283 } 1284 1285 ret = tegra_uart_parse_dt(pdev, tup); 1286 if (ret < 0) 1287 return ret; 1288 1289 u = &tup->uport; 1290 u->dev = &pdev->dev; 1291 u->ops = &tegra_uart_ops; 1292 u->type = PORT_TEGRA; 1293 u->fifosize = 32; 1294 tup->cdata = cdata; 1295 1296 platform_set_drvdata(pdev, tup); 1297 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1298 if (!resource) { 1299 dev_err(&pdev->dev, "No IO memory resource\n"); 1300 return -ENODEV; 1301 } 1302 1303 u->mapbase = resource->start; 1304 u->membase = devm_request_and_ioremap(&pdev->dev, resource); 1305 if (!u->membase) { 1306 dev_err(&pdev->dev, "memregion/iomap address req failed\n"); 1307 return -EADDRNOTAVAIL; 1308 } 1309 1310 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1311 if (IS_ERR(tup->uart_clk)) { 1312 dev_err(&pdev->dev, "Couldn't get the clock\n"); 1313 return PTR_ERR(tup->uart_clk); 1314 } 1315 1316 u->iotype = UPIO_MEM32; 1317 u->irq = platform_get_irq(pdev, 0); 1318 u->regshift = 2; 1319 ret = uart_add_one_port(&tegra_uart_driver, u); 1320 if (ret < 0) { 1321 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1322 return ret; 1323 } 1324 return ret; 1325 } 1326 1327 static int tegra_uart_remove(struct platform_device *pdev) 1328 { 1329 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1330 struct uart_port *u = &tup->uport; 1331 1332 uart_remove_one_port(&tegra_uart_driver, u); 1333 return 0; 1334 } 1335 1336 #ifdef CONFIG_PM_SLEEP 1337 static int tegra_uart_suspend(struct device *dev) 1338 { 1339 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1340 struct uart_port *u = &tup->uport; 1341 1342 return uart_suspend_port(&tegra_uart_driver, u); 1343 } 1344 1345 static int tegra_uart_resume(struct device *dev) 1346 { 1347 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1348 struct uart_port *u = &tup->uport; 1349 1350 return uart_resume_port(&tegra_uart_driver, u); 1351 } 1352 #endif 1353 1354 static const struct dev_pm_ops tegra_uart_pm_ops = { 1355 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1356 }; 1357 1358 static struct platform_driver tegra_uart_platform_driver = { 1359 .probe = tegra_uart_probe, 1360 .remove = tegra_uart_remove, 1361 .driver = { 1362 .name = "serial-tegra", 1363 .of_match_table = tegra_uart_of_match, 1364 .pm = &tegra_uart_pm_ops, 1365 }, 1366 }; 1367 1368 static int __init tegra_uart_init(void) 1369 { 1370 int ret; 1371 1372 ret = uart_register_driver(&tegra_uart_driver); 1373 if (ret < 0) { 1374 pr_err("Could not register %s driver\n", 1375 tegra_uart_driver.driver_name); 1376 return ret; 1377 } 1378 1379 ret = platform_driver_register(&tegra_uart_platform_driver); 1380 if (ret < 0) { 1381 pr_err("Uart platfrom driver register failed, e = %d\n", ret); 1382 uart_unregister_driver(&tegra_uart_driver); 1383 return ret; 1384 } 1385 return 0; 1386 } 1387 1388 static void __exit tegra_uart_exit(void) 1389 { 1390 pr_info("Unloading tegra uart driver\n"); 1391 platform_driver_unregister(&tegra_uart_platform_driver); 1392 uart_unregister_driver(&tegra_uart_driver); 1393 } 1394 1395 module_init(tegra_uart_init); 1396 module_exit(tegra_uart_exit); 1397 1398 MODULE_ALIAS("platform:serial-tegra"); 1399 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1400 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1401 MODULE_LICENSE("GPL v2"); 1402