1 /* 2 * serial_tegra.c 3 * 4 * High-speed serial driver for NVIDIA Tegra SoCs 5 * 6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/debugfs.h> 25 #include <linux/delay.h> 26 #include <linux/dmaengine.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/io.h> 31 #include <linux/irq.h> 32 #include <linux/module.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/pagemap.h> 36 #include <linux/platform_device.h> 37 #include <linux/serial.h> 38 #include <linux/serial_8250.h> 39 #include <linux/serial_core.h> 40 #include <linux/serial_reg.h> 41 #include <linux/slab.h> 42 #include <linux/string.h> 43 #include <linux/termios.h> 44 #include <linux/tty.h> 45 #include <linux/tty_flip.h> 46 47 #include <linux/clk/tegra.h> 48 49 #define TEGRA_UART_TYPE "TEGRA_UART" 50 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 51 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 52 53 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096 54 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100 55 #define TEGRA_UART_IER_EORD 0x20 56 #define TEGRA_UART_MCR_RTS_EN 0x40 57 #define TEGRA_UART_MCR_CTS_EN 0x20 58 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \ 59 UART_LSR_PE | UART_LSR_FE) 60 #define TEGRA_UART_IRDA_CSR 0x08 61 #define TEGRA_UART_SIR_ENABLED 0x80 62 63 #define TEGRA_UART_TX_PIO 1 64 #define TEGRA_UART_TX_DMA 2 65 #define TEGRA_UART_MIN_DMA 16 66 #define TEGRA_UART_FIFO_SIZE 32 67 68 /* 69 * Tx fifo trigger level setting in tegra uart is in 70 * reverse way then conventional uart. 71 */ 72 #define TEGRA_UART_TX_TRIG_16B 0x00 73 #define TEGRA_UART_TX_TRIG_8B 0x10 74 #define TEGRA_UART_TX_TRIG_4B 0x20 75 #define TEGRA_UART_TX_TRIG_1B 0x30 76 77 #define TEGRA_UART_MAXIMUM 5 78 79 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ 80 #define TEGRA_UART_DEFAULT_BAUD 115200 81 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8 82 83 /* Tx transfer mode */ 84 #define TEGRA_TX_PIO 1 85 #define TEGRA_TX_DMA 2 86 87 /** 88 * tegra_uart_chip_data: SOC specific data. 89 * 90 * @tx_fifo_full_status: Status flag available for checking tx fifo full. 91 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. 92 * Tegra30 does not allow this. 93 * @support_clk_src_div: Clock source support the clock divider. 94 */ 95 struct tegra_uart_chip_data { 96 bool tx_fifo_full_status; 97 bool allow_txfifo_reset_fifo_mode; 98 bool support_clk_src_div; 99 }; 100 101 struct tegra_uart_port { 102 struct uart_port uport; 103 const struct tegra_uart_chip_data *cdata; 104 105 struct clk *uart_clk; 106 unsigned int current_baud; 107 108 /* Register shadow */ 109 unsigned long fcr_shadow; 110 unsigned long mcr_shadow; 111 unsigned long lcr_shadow; 112 unsigned long ier_shadow; 113 bool rts_active; 114 115 int tx_in_progress; 116 unsigned int tx_bytes; 117 118 bool enable_modem_interrupt; 119 120 bool rx_timeout; 121 int rx_in_progress; 122 int symb_bit; 123 int dma_req_sel; 124 125 struct dma_chan *rx_dma_chan; 126 struct dma_chan *tx_dma_chan; 127 dma_addr_t rx_dma_buf_phys; 128 dma_addr_t tx_dma_buf_phys; 129 unsigned char *rx_dma_buf_virt; 130 unsigned char *tx_dma_buf_virt; 131 struct dma_async_tx_descriptor *tx_dma_desc; 132 struct dma_async_tx_descriptor *rx_dma_desc; 133 dma_cookie_t tx_cookie; 134 dma_cookie_t rx_cookie; 135 int tx_bytes_requested; 136 int rx_bytes_requested; 137 }; 138 139 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); 140 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); 141 142 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, 143 unsigned long reg) 144 { 145 return readl(tup->uport.membase + (reg << tup->uport.regshift)); 146 } 147 148 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, 149 unsigned long reg) 150 { 151 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); 152 } 153 154 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) 155 { 156 return container_of(u, struct tegra_uart_port, uport); 157 } 158 159 static unsigned int tegra_uart_get_mctrl(struct uart_port *u) 160 { 161 struct tegra_uart_port *tup = to_tegra_uport(u); 162 163 /* 164 * RI - Ring detector is active 165 * CD/DCD/CAR - Carrier detect is always active. For some reason 166 * linux has different names for carrier detect. 167 * DSR - Data Set ready is active as the hardware doesn't support it. 168 * Don't know if the linux support this yet? 169 * CTS - Clear to send. Always set to active, as the hardware handles 170 * CTS automatically. 171 */ 172 if (tup->enable_modem_interrupt) 173 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS; 174 return TIOCM_CTS; 175 } 176 177 static void set_rts(struct tegra_uart_port *tup, bool active) 178 { 179 unsigned long mcr; 180 181 mcr = tup->mcr_shadow; 182 if (active) 183 mcr |= TEGRA_UART_MCR_RTS_EN; 184 else 185 mcr &= ~TEGRA_UART_MCR_RTS_EN; 186 if (mcr != tup->mcr_shadow) { 187 tegra_uart_write(tup, mcr, UART_MCR); 188 tup->mcr_shadow = mcr; 189 } 190 return; 191 } 192 193 static void set_dtr(struct tegra_uart_port *tup, bool active) 194 { 195 unsigned long mcr; 196 197 mcr = tup->mcr_shadow; 198 if (active) 199 mcr |= UART_MCR_DTR; 200 else 201 mcr &= ~UART_MCR_DTR; 202 if (mcr != tup->mcr_shadow) { 203 tegra_uart_write(tup, mcr, UART_MCR); 204 tup->mcr_shadow = mcr; 205 } 206 return; 207 } 208 209 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) 210 { 211 struct tegra_uart_port *tup = to_tegra_uport(u); 212 unsigned long mcr; 213 int dtr_enable; 214 215 mcr = tup->mcr_shadow; 216 tup->rts_active = !!(mctrl & TIOCM_RTS); 217 set_rts(tup, tup->rts_active); 218 219 dtr_enable = !!(mctrl & TIOCM_DTR); 220 set_dtr(tup, dtr_enable); 221 return; 222 } 223 224 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) 225 { 226 struct tegra_uart_port *tup = to_tegra_uport(u); 227 unsigned long lcr; 228 229 lcr = tup->lcr_shadow; 230 if (break_ctl) 231 lcr |= UART_LCR_SBC; 232 else 233 lcr &= ~UART_LCR_SBC; 234 tegra_uart_write(tup, lcr, UART_LCR); 235 tup->lcr_shadow = lcr; 236 } 237 238 /* Wait for a symbol-time. */ 239 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, 240 unsigned int syms) 241 { 242 if (tup->current_baud) 243 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, 244 tup->current_baud)); 245 } 246 247 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) 248 { 249 unsigned long fcr = tup->fcr_shadow; 250 251 if (tup->cdata->allow_txfifo_reset_fifo_mode) { 252 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 253 tegra_uart_write(tup, fcr, UART_FCR); 254 } else { 255 fcr &= ~UART_FCR_ENABLE_FIFO; 256 tegra_uart_write(tup, fcr, UART_FCR); 257 udelay(60); 258 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 259 tegra_uart_write(tup, fcr, UART_FCR); 260 fcr |= UART_FCR_ENABLE_FIFO; 261 tegra_uart_write(tup, fcr, UART_FCR); 262 } 263 264 /* Dummy read to ensure the write is posted */ 265 tegra_uart_read(tup, UART_SCR); 266 267 /* Wait for the flush to propagate. */ 268 tegra_uart_wait_sym_time(tup, 1); 269 } 270 271 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) 272 { 273 unsigned long rate; 274 unsigned int divisor; 275 unsigned long lcr; 276 int ret; 277 278 if (tup->current_baud == baud) 279 return 0; 280 281 if (tup->cdata->support_clk_src_div) { 282 rate = baud * 16; 283 ret = clk_set_rate(tup->uart_clk, rate); 284 if (ret < 0) { 285 dev_err(tup->uport.dev, 286 "clk_set_rate() failed for rate %lu\n", rate); 287 return ret; 288 } 289 divisor = 1; 290 } else { 291 rate = clk_get_rate(tup->uart_clk); 292 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 293 } 294 295 lcr = tup->lcr_shadow; 296 lcr |= UART_LCR_DLAB; 297 tegra_uart_write(tup, lcr, UART_LCR); 298 299 tegra_uart_write(tup, divisor & 0xFF, UART_TX); 300 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); 301 302 lcr &= ~UART_LCR_DLAB; 303 tegra_uart_write(tup, lcr, UART_LCR); 304 305 /* Dummy read to ensure the write is posted */ 306 tegra_uart_read(tup, UART_SCR); 307 308 tup->current_baud = baud; 309 310 /* wait two character intervals at new rate */ 311 tegra_uart_wait_sym_time(tup, 2); 312 return 0; 313 } 314 315 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, 316 unsigned long lsr) 317 { 318 char flag = TTY_NORMAL; 319 320 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) { 321 if (lsr & UART_LSR_OE) { 322 /* Overrrun error */ 323 flag |= TTY_OVERRUN; 324 tup->uport.icount.overrun++; 325 dev_err(tup->uport.dev, "Got overrun errors\n"); 326 } else if (lsr & UART_LSR_PE) { 327 /* Parity error */ 328 flag |= TTY_PARITY; 329 tup->uport.icount.parity++; 330 dev_err(tup->uport.dev, "Got Parity errors\n"); 331 } else if (lsr & UART_LSR_FE) { 332 flag |= TTY_FRAME; 333 tup->uport.icount.frame++; 334 dev_err(tup->uport.dev, "Got frame errors\n"); 335 } else if (lsr & UART_LSR_BI) { 336 dev_err(tup->uport.dev, "Got Break\n"); 337 tup->uport.icount.brk++; 338 /* If FIFO read error without any data, reset Rx FIFO */ 339 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) 340 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); 341 } 342 } 343 return flag; 344 } 345 346 static int tegra_uart_request_port(struct uart_port *u) 347 { 348 return 0; 349 } 350 351 static void tegra_uart_release_port(struct uart_port *u) 352 { 353 /* Nothing to do here */ 354 } 355 356 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) 357 { 358 struct circ_buf *xmit = &tup->uport.state->xmit; 359 int i; 360 361 for (i = 0; i < max_bytes; i++) { 362 BUG_ON(uart_circ_empty(xmit)); 363 if (tup->cdata->tx_fifo_full_status) { 364 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 365 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) 366 break; 367 } 368 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); 369 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 370 tup->uport.icount.tx++; 371 } 372 } 373 374 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, 375 unsigned int bytes) 376 { 377 if (bytes > TEGRA_UART_MIN_DMA) 378 bytes = TEGRA_UART_MIN_DMA; 379 380 tup->tx_in_progress = TEGRA_UART_TX_PIO; 381 tup->tx_bytes = bytes; 382 tup->ier_shadow |= UART_IER_THRI; 383 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 384 } 385 386 static void tegra_uart_tx_dma_complete(void *args) 387 { 388 struct tegra_uart_port *tup = args; 389 struct circ_buf *xmit = &tup->uport.state->xmit; 390 struct dma_tx_state state; 391 unsigned long flags; 392 int count; 393 394 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state); 395 count = tup->tx_bytes_requested - state.residue; 396 async_tx_ack(tup->tx_dma_desc); 397 spin_lock_irqsave(&tup->uport.lock, flags); 398 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 399 tup->tx_in_progress = 0; 400 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 401 uart_write_wakeup(&tup->uport); 402 tegra_uart_start_next_tx(tup); 403 spin_unlock_irqrestore(&tup->uport.lock, flags); 404 } 405 406 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, 407 unsigned long count) 408 { 409 struct circ_buf *xmit = &tup->uport.state->xmit; 410 dma_addr_t tx_phys_addr; 411 412 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, 413 UART_XMIT_SIZE, DMA_TO_DEVICE); 414 415 tup->tx_bytes = count & ~(0xF); 416 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; 417 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, 418 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, 419 DMA_PREP_INTERRUPT); 420 if (!tup->tx_dma_desc) { 421 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); 422 return -EIO; 423 } 424 425 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; 426 tup->tx_dma_desc->callback_param = tup; 427 tup->tx_in_progress = TEGRA_UART_TX_DMA; 428 tup->tx_bytes_requested = tup->tx_bytes; 429 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); 430 dma_async_issue_pending(tup->tx_dma_chan); 431 return 0; 432 } 433 434 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) 435 { 436 unsigned long tail; 437 unsigned long count; 438 struct circ_buf *xmit = &tup->uport.state->xmit; 439 440 tail = (unsigned long)&xmit->buf[xmit->tail]; 441 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 442 if (!count) 443 return; 444 445 if (count < TEGRA_UART_MIN_DMA) 446 tegra_uart_start_pio_tx(tup, count); 447 else if (BYTES_TO_ALIGN(tail) > 0) 448 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); 449 else 450 tegra_uart_start_tx_dma(tup, count); 451 } 452 453 /* Called by serial core driver with u->lock taken. */ 454 static void tegra_uart_start_tx(struct uart_port *u) 455 { 456 struct tegra_uart_port *tup = to_tegra_uport(u); 457 struct circ_buf *xmit = &u->state->xmit; 458 459 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) 460 tegra_uart_start_next_tx(tup); 461 } 462 463 static unsigned int tegra_uart_tx_empty(struct uart_port *u) 464 { 465 struct tegra_uart_port *tup = to_tegra_uport(u); 466 unsigned int ret = 0; 467 unsigned long flags; 468 469 spin_lock_irqsave(&u->lock, flags); 470 if (!tup->tx_in_progress) { 471 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 472 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 473 ret = TIOCSER_TEMT; 474 } 475 spin_unlock_irqrestore(&u->lock, flags); 476 return ret; 477 } 478 479 static void tegra_uart_stop_tx(struct uart_port *u) 480 { 481 struct tegra_uart_port *tup = to_tegra_uport(u); 482 struct circ_buf *xmit = &tup->uport.state->xmit; 483 struct dma_tx_state state; 484 int count; 485 486 dmaengine_terminate_all(tup->tx_dma_chan); 487 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 488 count = tup->tx_bytes_requested - state.residue; 489 async_tx_ack(tup->tx_dma_desc); 490 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 491 tup->tx_in_progress = 0; 492 return; 493 } 494 495 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) 496 { 497 struct circ_buf *xmit = &tup->uport.state->xmit; 498 499 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); 500 tup->tx_in_progress = 0; 501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 502 uart_write_wakeup(&tup->uport); 503 tegra_uart_start_next_tx(tup); 504 return; 505 } 506 507 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, 508 struct tty_port *tty) 509 { 510 do { 511 char flag = TTY_NORMAL; 512 unsigned long lsr = 0; 513 unsigned char ch; 514 515 lsr = tegra_uart_read(tup, UART_LSR); 516 if (!(lsr & UART_LSR_DR)) 517 break; 518 519 flag = tegra_uart_decode_rx_error(tup, lsr); 520 ch = (unsigned char) tegra_uart_read(tup, UART_RX); 521 tup->uport.icount.rx++; 522 523 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) 524 tty_insert_flip_char(tty, ch, flag); 525 } while (1); 526 527 return; 528 } 529 530 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, 531 struct tty_port *tty, int count) 532 { 533 int copied; 534 535 tup->uport.icount.rx += count; 536 if (!tty) { 537 dev_err(tup->uport.dev, "No tty port\n"); 538 return; 539 } 540 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, 541 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 542 copied = tty_insert_flip_string(tty, 543 ((unsigned char *)(tup->rx_dma_buf_virt)), count); 544 if (copied != count) { 545 WARN_ON(1); 546 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); 547 } 548 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 549 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 550 } 551 552 static void tegra_uart_rx_dma_complete(void *args) 553 { 554 struct tegra_uart_port *tup = args; 555 struct uart_port *u = &tup->uport; 556 int count = tup->rx_bytes_requested; 557 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 558 struct tty_port *port = &u->state->port; 559 unsigned long flags; 560 561 async_tx_ack(tup->rx_dma_desc); 562 spin_lock_irqsave(&u->lock, flags); 563 564 /* Deactivate flow control to stop sender */ 565 if (tup->rts_active) 566 set_rts(tup, false); 567 568 /* If we are here, DMA is stopped */ 569 if (count) 570 tegra_uart_copy_rx_to_tty(tup, port, count); 571 572 tegra_uart_handle_rx_pio(tup, port); 573 if (tty) { 574 spin_unlock_irqrestore(&u->lock, flags); 575 tty_flip_buffer_push(port); 576 spin_lock_irqsave(&u->lock, flags); 577 tty_kref_put(tty); 578 } 579 tegra_uart_start_rx_dma(tup); 580 581 /* Activate flow control to start transfer */ 582 if (tup->rts_active) 583 set_rts(tup, true); 584 585 spin_unlock_irqrestore(&u->lock, flags); 586 } 587 588 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup, 589 unsigned long *flags) 590 { 591 struct dma_tx_state state; 592 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); 593 struct tty_port *port = &tup->uport.state->port; 594 struct uart_port *u = &tup->uport; 595 int count; 596 597 /* Deactivate flow control to stop sender */ 598 if (tup->rts_active) 599 set_rts(tup, false); 600 601 dmaengine_terminate_all(tup->rx_dma_chan); 602 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 603 count = tup->rx_bytes_requested - state.residue; 604 605 /* If we are here, DMA is stopped */ 606 if (count) 607 tegra_uart_copy_rx_to_tty(tup, port, count); 608 609 tegra_uart_handle_rx_pio(tup, port); 610 if (tty) { 611 spin_unlock_irqrestore(&u->lock, *flags); 612 tty_flip_buffer_push(port); 613 spin_lock_irqsave(&u->lock, *flags); 614 tty_kref_put(tty); 615 } 616 tegra_uart_start_rx_dma(tup); 617 618 if (tup->rts_active) 619 set_rts(tup, true); 620 } 621 622 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) 623 { 624 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE; 625 626 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, 627 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, 628 DMA_PREP_INTERRUPT); 629 if (!tup->rx_dma_desc) { 630 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); 631 return -EIO; 632 } 633 634 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; 635 tup->rx_dma_desc->callback_param = tup; 636 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, 637 count, DMA_TO_DEVICE); 638 tup->rx_bytes_requested = count; 639 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); 640 dma_async_issue_pending(tup->rx_dma_chan); 641 return 0; 642 } 643 644 static void tegra_uart_handle_modem_signal_change(struct uart_port *u) 645 { 646 struct tegra_uart_port *tup = to_tegra_uport(u); 647 unsigned long msr; 648 649 msr = tegra_uart_read(tup, UART_MSR); 650 if (!(msr & UART_MSR_ANY_DELTA)) 651 return; 652 653 if (msr & UART_MSR_TERI) 654 tup->uport.icount.rng++; 655 if (msr & UART_MSR_DDSR) 656 tup->uport.icount.dsr++; 657 /* We may only get DDCD when HW init and reset */ 658 if (msr & UART_MSR_DDCD) 659 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); 660 /* Will start/stop_tx accordingly */ 661 if (msr & UART_MSR_DCTS) 662 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); 663 return; 664 } 665 666 static irqreturn_t tegra_uart_isr(int irq, void *data) 667 { 668 struct tegra_uart_port *tup = data; 669 struct uart_port *u = &tup->uport; 670 unsigned long iir; 671 unsigned long ier; 672 bool is_rx_int = false; 673 unsigned long flags; 674 675 spin_lock_irqsave(&u->lock, flags); 676 while (1) { 677 iir = tegra_uart_read(tup, UART_IIR); 678 if (iir & UART_IIR_NO_INT) { 679 if (is_rx_int) { 680 tegra_uart_handle_rx_dma(tup, &flags); 681 if (tup->rx_in_progress) { 682 ier = tup->ier_shadow; 683 ier |= (UART_IER_RLSI | UART_IER_RTOIE | 684 TEGRA_UART_IER_EORD); 685 tup->ier_shadow = ier; 686 tegra_uart_write(tup, ier, UART_IER); 687 } 688 } 689 spin_unlock_irqrestore(&u->lock, flags); 690 return IRQ_HANDLED; 691 } 692 693 switch ((iir >> 1) & 0x7) { 694 case 0: /* Modem signal change interrupt */ 695 tegra_uart_handle_modem_signal_change(u); 696 break; 697 698 case 1: /* Transmit interrupt only triggered when using PIO */ 699 tup->ier_shadow &= ~UART_IER_THRI; 700 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 701 tegra_uart_handle_tx_pio(tup); 702 break; 703 704 case 4: /* End of data */ 705 case 6: /* Rx timeout */ 706 case 2: /* Receive */ 707 if (!is_rx_int) { 708 is_rx_int = true; 709 /* Disable Rx interrupts */ 710 ier = tup->ier_shadow; 711 ier |= UART_IER_RDI; 712 tegra_uart_write(tup, ier, UART_IER); 713 ier &= ~(UART_IER_RDI | UART_IER_RLSI | 714 UART_IER_RTOIE | TEGRA_UART_IER_EORD); 715 tup->ier_shadow = ier; 716 tegra_uart_write(tup, ier, UART_IER); 717 } 718 break; 719 720 case 3: /* Receive error */ 721 tegra_uart_decode_rx_error(tup, 722 tegra_uart_read(tup, UART_LSR)); 723 break; 724 725 case 5: /* break nothing to handle */ 726 case 7: /* break nothing to handle */ 727 break; 728 } 729 } 730 } 731 732 static void tegra_uart_stop_rx(struct uart_port *u) 733 { 734 struct tegra_uart_port *tup = to_tegra_uport(u); 735 struct tty_struct *tty; 736 struct tty_port *port = &u->state->port; 737 struct dma_tx_state state; 738 unsigned long ier; 739 int count; 740 741 if (tup->rts_active) 742 set_rts(tup, false); 743 744 if (!tup->rx_in_progress) 745 return; 746 747 tty = tty_port_tty_get(&tup->uport.state->port); 748 749 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ 750 751 ier = tup->ier_shadow; 752 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | 753 TEGRA_UART_IER_EORD); 754 tup->ier_shadow = ier; 755 tegra_uart_write(tup, ier, UART_IER); 756 tup->rx_in_progress = 0; 757 if (tup->rx_dma_chan) { 758 dmaengine_terminate_all(tup->rx_dma_chan); 759 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 760 async_tx_ack(tup->rx_dma_desc); 761 count = tup->rx_bytes_requested - state.residue; 762 tegra_uart_copy_rx_to_tty(tup, port, count); 763 tegra_uart_handle_rx_pio(tup, port); 764 } else { 765 tegra_uart_handle_rx_pio(tup, port); 766 } 767 if (tty) { 768 tty_flip_buffer_push(port); 769 tty_kref_put(tty); 770 } 771 return; 772 } 773 774 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) 775 { 776 unsigned long flags; 777 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); 778 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; 779 unsigned long wait_time; 780 unsigned long lsr; 781 unsigned long msr; 782 unsigned long mcr; 783 784 /* Disable interrupts */ 785 tegra_uart_write(tup, 0, UART_IER); 786 787 lsr = tegra_uart_read(tup, UART_LSR); 788 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 789 msr = tegra_uart_read(tup, UART_MSR); 790 mcr = tegra_uart_read(tup, UART_MCR); 791 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) 792 dev_err(tup->uport.dev, 793 "Tx Fifo not empty, CTS disabled, waiting\n"); 794 795 /* Wait for Tx fifo to be empty */ 796 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { 797 wait_time = min(fifo_empty_time, 100lu); 798 udelay(wait_time); 799 fifo_empty_time -= wait_time; 800 if (!fifo_empty_time) { 801 msr = tegra_uart_read(tup, UART_MSR); 802 mcr = tegra_uart_read(tup, UART_MCR); 803 if ((mcr & TEGRA_UART_MCR_CTS_EN) && 804 (msr & UART_MSR_CTS)) 805 dev_err(tup->uport.dev, 806 "Slave not ready\n"); 807 break; 808 } 809 lsr = tegra_uart_read(tup, UART_LSR); 810 } 811 } 812 813 spin_lock_irqsave(&tup->uport.lock, flags); 814 /* Reset the Rx and Tx FIFOs */ 815 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 816 tup->current_baud = 0; 817 spin_unlock_irqrestore(&tup->uport.lock, flags); 818 819 clk_disable_unprepare(tup->uart_clk); 820 } 821 822 static int tegra_uart_hw_init(struct tegra_uart_port *tup) 823 { 824 int ret; 825 826 tup->fcr_shadow = 0; 827 tup->mcr_shadow = 0; 828 tup->lcr_shadow = 0; 829 tup->ier_shadow = 0; 830 tup->current_baud = 0; 831 832 clk_prepare_enable(tup->uart_clk); 833 834 /* Reset the UART controller to clear all previous status.*/ 835 tegra_periph_reset_assert(tup->uart_clk); 836 udelay(10); 837 tegra_periph_reset_deassert(tup->uart_clk); 838 839 tup->rx_in_progress = 0; 840 tup->tx_in_progress = 0; 841 842 /* 843 * Set the trigger level 844 * 845 * For PIO mode: 846 * 847 * For receive, this will interrupt the CPU after that many number of 848 * bytes are received, for the remaining bytes the receive timeout 849 * interrupt is received. Rx high watermark is set to 4. 850 * 851 * For transmit, if the trasnmit interrupt is enabled, this will 852 * interrupt the CPU when the number of entries in the FIFO reaches the 853 * low watermark. Tx low watermark is set to 16 bytes. 854 * 855 * For DMA mode: 856 * 857 * Set the Tx trigger to 16. This should match the DMA burst size that 858 * programmed in the DMA registers. 859 */ 860 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; 861 tup->fcr_shadow |= UART_FCR_R_TRIG_01; 862 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; 863 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 864 865 /* 866 * Initialize the UART with default configuration 867 * (115200, N, 8, 1) so that the receive DMA buffer may be 868 * enqueued 869 */ 870 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; 871 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); 872 tup->fcr_shadow |= UART_FCR_DMA_SELECT; 873 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); 874 875 ret = tegra_uart_start_rx_dma(tup); 876 if (ret < 0) { 877 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); 878 return ret; 879 } 880 tup->rx_in_progress = 1; 881 882 /* 883 * Enable IE_RXS for the receive status interrupts like line errros. 884 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. 885 * 886 * If using DMA mode, enable EORD instead of receive interrupt which 887 * will interrupt after the UART is done with the receive instead of 888 * the interrupt when the FIFO "threshold" is reached. 889 * 890 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when 891 * the DATA is sitting in the FIFO and couldn't be transferred to the 892 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be 893 * triggered when there is a pause of the incomming data stream for 4 894 * characters long. 895 * 896 * For pauses in the data which is not aligned to 4 bytes, we get 897 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first 898 * then the EORD. 899 */ 900 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; 901 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 902 return 0; 903 } 904 905 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, 906 bool dma_to_memory) 907 { 908 struct dma_chan *dma_chan; 909 unsigned char *dma_buf; 910 dma_addr_t dma_phys; 911 int ret; 912 struct dma_slave_config dma_sconfig; 913 dma_cap_mask_t mask; 914 915 dma_cap_zero(mask); 916 dma_cap_set(DMA_SLAVE, mask); 917 dma_chan = dma_request_channel(mask, NULL, NULL); 918 if (!dma_chan) { 919 dev_err(tup->uport.dev, 920 "Dma channel is not available, will try later\n"); 921 return -EPROBE_DEFER; 922 } 923 924 if (dma_to_memory) { 925 dma_buf = dma_alloc_coherent(tup->uport.dev, 926 TEGRA_UART_RX_DMA_BUFFER_SIZE, 927 &dma_phys, GFP_KERNEL); 928 if (!dma_buf) { 929 dev_err(tup->uport.dev, 930 "Not able to allocate the dma buffer\n"); 931 dma_release_channel(dma_chan); 932 return -ENOMEM; 933 } 934 } else { 935 dma_phys = dma_map_single(tup->uport.dev, 936 tup->uport.state->xmit.buf, UART_XMIT_SIZE, 937 DMA_TO_DEVICE); 938 dma_buf = tup->uport.state->xmit.buf; 939 } 940 941 dma_sconfig.slave_id = tup->dma_req_sel; 942 if (dma_to_memory) { 943 dma_sconfig.src_addr = tup->uport.mapbase; 944 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 945 dma_sconfig.src_maxburst = 4; 946 } else { 947 dma_sconfig.dst_addr = tup->uport.mapbase; 948 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 949 dma_sconfig.dst_maxburst = 16; 950 } 951 952 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 953 if (ret < 0) { 954 dev_err(tup->uport.dev, 955 "Dma slave config failed, err = %d\n", ret); 956 goto scrub; 957 } 958 959 if (dma_to_memory) { 960 tup->rx_dma_chan = dma_chan; 961 tup->rx_dma_buf_virt = dma_buf; 962 tup->rx_dma_buf_phys = dma_phys; 963 } else { 964 tup->tx_dma_chan = dma_chan; 965 tup->tx_dma_buf_virt = dma_buf; 966 tup->tx_dma_buf_phys = dma_phys; 967 } 968 return 0; 969 970 scrub: 971 dma_release_channel(dma_chan); 972 return ret; 973 } 974 975 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, 976 bool dma_to_memory) 977 { 978 struct dma_chan *dma_chan; 979 980 if (dma_to_memory) { 981 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, 982 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); 983 dma_chan = tup->rx_dma_chan; 984 tup->rx_dma_chan = NULL; 985 tup->rx_dma_buf_phys = 0; 986 tup->rx_dma_buf_virt = NULL; 987 } else { 988 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, 989 UART_XMIT_SIZE, DMA_TO_DEVICE); 990 dma_chan = tup->tx_dma_chan; 991 tup->tx_dma_chan = NULL; 992 tup->tx_dma_buf_phys = 0; 993 tup->tx_dma_buf_virt = NULL; 994 } 995 dma_release_channel(dma_chan); 996 } 997 998 static int tegra_uart_startup(struct uart_port *u) 999 { 1000 struct tegra_uart_port *tup = to_tegra_uport(u); 1001 int ret; 1002 1003 ret = tegra_uart_dma_channel_allocate(tup, false); 1004 if (ret < 0) { 1005 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret); 1006 return ret; 1007 } 1008 1009 ret = tegra_uart_dma_channel_allocate(tup, true); 1010 if (ret < 0) { 1011 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret); 1012 goto fail_rx_dma; 1013 } 1014 1015 ret = tegra_uart_hw_init(tup); 1016 if (ret < 0) { 1017 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); 1018 goto fail_hw_init; 1019 } 1020 1021 ret = request_irq(u->irq, tegra_uart_isr, 0, 1022 dev_name(u->dev), tup); 1023 if (ret < 0) { 1024 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); 1025 goto fail_hw_init; 1026 } 1027 return 0; 1028 1029 fail_hw_init: 1030 tegra_uart_dma_channel_free(tup, true); 1031 fail_rx_dma: 1032 tegra_uart_dma_channel_free(tup, false); 1033 return ret; 1034 } 1035 1036 static void tegra_uart_shutdown(struct uart_port *u) 1037 { 1038 struct tegra_uart_port *tup = to_tegra_uport(u); 1039 1040 tegra_uart_hw_deinit(tup); 1041 1042 tup->rx_in_progress = 0; 1043 tup->tx_in_progress = 0; 1044 1045 tegra_uart_dma_channel_free(tup, true); 1046 tegra_uart_dma_channel_free(tup, false); 1047 free_irq(u->irq, tup); 1048 } 1049 1050 static void tegra_uart_enable_ms(struct uart_port *u) 1051 { 1052 struct tegra_uart_port *tup = to_tegra_uport(u); 1053 1054 if (tup->enable_modem_interrupt) { 1055 tup->ier_shadow |= UART_IER_MSI; 1056 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1057 } 1058 } 1059 1060 static void tegra_uart_set_termios(struct uart_port *u, 1061 struct ktermios *termios, struct ktermios *oldtermios) 1062 { 1063 struct tegra_uart_port *tup = to_tegra_uport(u); 1064 unsigned int baud; 1065 unsigned long flags; 1066 unsigned int lcr; 1067 int symb_bit = 1; 1068 struct clk *parent_clk = clk_get_parent(tup->uart_clk); 1069 unsigned long parent_clk_rate = clk_get_rate(parent_clk); 1070 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; 1071 1072 max_divider *= 16; 1073 spin_lock_irqsave(&u->lock, flags); 1074 1075 /* Changing configuration, it is safe to stop any rx now */ 1076 if (tup->rts_active) 1077 set_rts(tup, false); 1078 1079 /* Clear all interrupts as configuration is going to be change */ 1080 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); 1081 tegra_uart_read(tup, UART_IER); 1082 tegra_uart_write(tup, 0, UART_IER); 1083 tegra_uart_read(tup, UART_IER); 1084 1085 /* Parity */ 1086 lcr = tup->lcr_shadow; 1087 lcr &= ~UART_LCR_PARITY; 1088 1089 /* CMSPAR isn't supported by this driver */ 1090 termios->c_cflag &= ~CMSPAR; 1091 1092 if ((termios->c_cflag & PARENB) == PARENB) { 1093 symb_bit++; 1094 if (termios->c_cflag & PARODD) { 1095 lcr |= UART_LCR_PARITY; 1096 lcr &= ~UART_LCR_EPAR; 1097 lcr &= ~UART_LCR_SPAR; 1098 } else { 1099 lcr |= UART_LCR_PARITY; 1100 lcr |= UART_LCR_EPAR; 1101 lcr &= ~UART_LCR_SPAR; 1102 } 1103 } 1104 1105 lcr &= ~UART_LCR_WLEN8; 1106 switch (termios->c_cflag & CSIZE) { 1107 case CS5: 1108 lcr |= UART_LCR_WLEN5; 1109 symb_bit += 5; 1110 break; 1111 case CS6: 1112 lcr |= UART_LCR_WLEN6; 1113 symb_bit += 6; 1114 break; 1115 case CS7: 1116 lcr |= UART_LCR_WLEN7; 1117 symb_bit += 7; 1118 break; 1119 default: 1120 lcr |= UART_LCR_WLEN8; 1121 symb_bit += 8; 1122 break; 1123 } 1124 1125 /* Stop bits */ 1126 if (termios->c_cflag & CSTOPB) { 1127 lcr |= UART_LCR_STOP; 1128 symb_bit += 2; 1129 } else { 1130 lcr &= ~UART_LCR_STOP; 1131 symb_bit++; 1132 } 1133 1134 tegra_uart_write(tup, lcr, UART_LCR); 1135 tup->lcr_shadow = lcr; 1136 tup->symb_bit = symb_bit; 1137 1138 /* Baud rate. */ 1139 baud = uart_get_baud_rate(u, termios, oldtermios, 1140 parent_clk_rate/max_divider, 1141 parent_clk_rate/16); 1142 spin_unlock_irqrestore(&u->lock, flags); 1143 tegra_set_baudrate(tup, baud); 1144 if (tty_termios_baud_rate(termios)) 1145 tty_termios_encode_baud_rate(termios, baud, baud); 1146 spin_lock_irqsave(&u->lock, flags); 1147 1148 /* Flow control */ 1149 if (termios->c_cflag & CRTSCTS) { 1150 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; 1151 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1152 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1153 /* if top layer has asked to set rts active then do so here */ 1154 if (tup->rts_active) 1155 set_rts(tup, true); 1156 } else { 1157 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; 1158 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; 1159 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); 1160 } 1161 1162 /* update the port timeout based on new settings */ 1163 uart_update_timeout(u, termios->c_cflag, baud); 1164 1165 /* Make sure all write has completed */ 1166 tegra_uart_read(tup, UART_IER); 1167 1168 /* Reenable interrupt */ 1169 tegra_uart_write(tup, tup->ier_shadow, UART_IER); 1170 tegra_uart_read(tup, UART_IER); 1171 1172 spin_unlock_irqrestore(&u->lock, flags); 1173 return; 1174 } 1175 1176 /* 1177 * Flush any TX data submitted for DMA and PIO. Called when the 1178 * TX circular buffer is reset. 1179 */ 1180 static void tegra_uart_flush_buffer(struct uart_port *u) 1181 { 1182 struct tegra_uart_port *tup = to_tegra_uport(u); 1183 1184 tup->tx_bytes = 0; 1185 if (tup->tx_dma_chan) 1186 dmaengine_terminate_all(tup->tx_dma_chan); 1187 return; 1188 } 1189 1190 static const char *tegra_uart_type(struct uart_port *u) 1191 { 1192 return TEGRA_UART_TYPE; 1193 } 1194 1195 static struct uart_ops tegra_uart_ops = { 1196 .tx_empty = tegra_uart_tx_empty, 1197 .set_mctrl = tegra_uart_set_mctrl, 1198 .get_mctrl = tegra_uart_get_mctrl, 1199 .stop_tx = tegra_uart_stop_tx, 1200 .start_tx = tegra_uart_start_tx, 1201 .stop_rx = tegra_uart_stop_rx, 1202 .flush_buffer = tegra_uart_flush_buffer, 1203 .enable_ms = tegra_uart_enable_ms, 1204 .break_ctl = tegra_uart_break_ctl, 1205 .startup = tegra_uart_startup, 1206 .shutdown = tegra_uart_shutdown, 1207 .set_termios = tegra_uart_set_termios, 1208 .type = tegra_uart_type, 1209 .request_port = tegra_uart_request_port, 1210 .release_port = tegra_uart_release_port, 1211 }; 1212 1213 static struct uart_driver tegra_uart_driver = { 1214 .owner = THIS_MODULE, 1215 .driver_name = "tegra_hsuart", 1216 .dev_name = "ttyTHS", 1217 .cons = NULL, 1218 .nr = TEGRA_UART_MAXIMUM, 1219 }; 1220 1221 static int tegra_uart_parse_dt(struct platform_device *pdev, 1222 struct tegra_uart_port *tup) 1223 { 1224 struct device_node *np = pdev->dev.of_node; 1225 u32 of_dma[2]; 1226 int port; 1227 1228 if (of_property_read_u32_array(np, "nvidia,dma-request-selector", 1229 of_dma, 2) >= 0) { 1230 tup->dma_req_sel = of_dma[1]; 1231 } else { 1232 dev_err(&pdev->dev, "missing dma requestor in device tree\n"); 1233 return -EINVAL; 1234 } 1235 1236 port = of_alias_get_id(np, "serial"); 1237 if (port < 0) { 1238 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1239 return port; 1240 } 1241 tup->uport.line = port; 1242 1243 tup->enable_modem_interrupt = of_property_read_bool(np, 1244 "nvidia,enable-modem-interrupt"); 1245 return 0; 1246 } 1247 1248 static struct tegra_uart_chip_data tegra20_uart_chip_data = { 1249 .tx_fifo_full_status = false, 1250 .allow_txfifo_reset_fifo_mode = true, 1251 .support_clk_src_div = false, 1252 }; 1253 1254 static struct tegra_uart_chip_data tegra30_uart_chip_data = { 1255 .tx_fifo_full_status = true, 1256 .allow_txfifo_reset_fifo_mode = false, 1257 .support_clk_src_div = true, 1258 }; 1259 1260 static struct of_device_id tegra_uart_of_match[] = { 1261 { 1262 .compatible = "nvidia,tegra30-hsuart", 1263 .data = &tegra30_uart_chip_data, 1264 }, { 1265 .compatible = "nvidia,tegra20-hsuart", 1266 .data = &tegra20_uart_chip_data, 1267 }, { 1268 }, 1269 }; 1270 MODULE_DEVICE_TABLE(of, tegra_uart_of_match); 1271 1272 static int tegra_uart_probe(struct platform_device *pdev) 1273 { 1274 struct tegra_uart_port *tup; 1275 struct uart_port *u; 1276 struct resource *resource; 1277 int ret; 1278 const struct tegra_uart_chip_data *cdata; 1279 const struct of_device_id *match; 1280 1281 match = of_match_device(tegra_uart_of_match, &pdev->dev); 1282 if (!match) { 1283 dev_err(&pdev->dev, "Error: No device match found\n"); 1284 return -ENODEV; 1285 } 1286 cdata = match->data; 1287 1288 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); 1289 if (!tup) { 1290 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); 1291 return -ENOMEM; 1292 } 1293 1294 ret = tegra_uart_parse_dt(pdev, tup); 1295 if (ret < 0) 1296 return ret; 1297 1298 u = &tup->uport; 1299 u->dev = &pdev->dev; 1300 u->ops = &tegra_uart_ops; 1301 u->type = PORT_TEGRA; 1302 u->fifosize = 32; 1303 tup->cdata = cdata; 1304 1305 platform_set_drvdata(pdev, tup); 1306 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1307 if (!resource) { 1308 dev_err(&pdev->dev, "No IO memory resource\n"); 1309 return -ENODEV; 1310 } 1311 1312 u->mapbase = resource->start; 1313 u->membase = devm_ioremap_resource(&pdev->dev, resource); 1314 if (IS_ERR(u->membase)) 1315 return PTR_ERR(u->membase); 1316 1317 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); 1318 if (IS_ERR(tup->uart_clk)) { 1319 dev_err(&pdev->dev, "Couldn't get the clock\n"); 1320 return PTR_ERR(tup->uart_clk); 1321 } 1322 1323 u->iotype = UPIO_MEM32; 1324 u->irq = platform_get_irq(pdev, 0); 1325 u->regshift = 2; 1326 ret = uart_add_one_port(&tegra_uart_driver, u); 1327 if (ret < 0) { 1328 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); 1329 return ret; 1330 } 1331 return ret; 1332 } 1333 1334 static int tegra_uart_remove(struct platform_device *pdev) 1335 { 1336 struct tegra_uart_port *tup = platform_get_drvdata(pdev); 1337 struct uart_port *u = &tup->uport; 1338 1339 uart_remove_one_port(&tegra_uart_driver, u); 1340 return 0; 1341 } 1342 1343 #ifdef CONFIG_PM_SLEEP 1344 static int tegra_uart_suspend(struct device *dev) 1345 { 1346 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1347 struct uart_port *u = &tup->uport; 1348 1349 return uart_suspend_port(&tegra_uart_driver, u); 1350 } 1351 1352 static int tegra_uart_resume(struct device *dev) 1353 { 1354 struct tegra_uart_port *tup = dev_get_drvdata(dev); 1355 struct uart_port *u = &tup->uport; 1356 1357 return uart_resume_port(&tegra_uart_driver, u); 1358 } 1359 #endif 1360 1361 static const struct dev_pm_ops tegra_uart_pm_ops = { 1362 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume) 1363 }; 1364 1365 static struct platform_driver tegra_uart_platform_driver = { 1366 .probe = tegra_uart_probe, 1367 .remove = tegra_uart_remove, 1368 .driver = { 1369 .name = "serial-tegra", 1370 .of_match_table = tegra_uart_of_match, 1371 .pm = &tegra_uart_pm_ops, 1372 }, 1373 }; 1374 1375 static int __init tegra_uart_init(void) 1376 { 1377 int ret; 1378 1379 ret = uart_register_driver(&tegra_uart_driver); 1380 if (ret < 0) { 1381 pr_err("Could not register %s driver\n", 1382 tegra_uart_driver.driver_name); 1383 return ret; 1384 } 1385 1386 ret = platform_driver_register(&tegra_uart_platform_driver); 1387 if (ret < 0) { 1388 pr_err("Uart platform driver register failed, e = %d\n", ret); 1389 uart_unregister_driver(&tegra_uart_driver); 1390 return ret; 1391 } 1392 return 0; 1393 } 1394 1395 static void __exit tegra_uart_exit(void) 1396 { 1397 pr_info("Unloading tegra uart driver\n"); 1398 platform_driver_unregister(&tegra_uart_platform_driver); 1399 uart_unregister_driver(&tegra_uart_driver); 1400 } 1401 1402 module_init(tegra_uart_init); 1403 module_exit(tegra_uart_exit); 1404 1405 MODULE_ALIAS("platform:serial-tegra"); 1406 MODULE_DESCRIPTION("High speed UART driver for tegra chipset"); 1407 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1408 MODULE_LICENSE("GPL v2"); 1409