1 /*
2  * serial_tegra.c
3  *
4  * High-speed serial driver for NVIDIA Tegra SoCs
5  *
6  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
7  *
8  * Author: Laxman Dewangan <ldewangan@nvidia.com>
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms and conditions of the GNU General Public License,
12  * version 2, as published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22 
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial_reg.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/termios.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 
48 #define TEGRA_UART_TYPE				"TEGRA_UART"
49 #define TX_EMPTY_STATUS				(UART_LSR_TEMT | UART_LSR_THRE)
50 #define BYTES_TO_ALIGN(x)			((unsigned long)(x) & 0x3)
51 
52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE		4096
53 #define TEGRA_UART_LSR_TXFIFO_FULL		0x100
54 #define TEGRA_UART_IER_EORD			0x20
55 #define TEGRA_UART_MCR_RTS_EN			0x40
56 #define TEGRA_UART_MCR_CTS_EN			0x20
57 #define TEGRA_UART_LSR_ANY			(UART_LSR_OE | UART_LSR_BI | \
58 						UART_LSR_PE | UART_LSR_FE)
59 #define TEGRA_UART_IRDA_CSR			0x08
60 #define TEGRA_UART_SIR_ENABLED			0x80
61 
62 #define TEGRA_UART_TX_PIO			1
63 #define TEGRA_UART_TX_DMA			2
64 #define TEGRA_UART_MIN_DMA			16
65 #define TEGRA_UART_FIFO_SIZE			32
66 
67 /*
68  * Tx fifo trigger level setting in tegra uart is in
69  * reverse way then conventional uart.
70  */
71 #define TEGRA_UART_TX_TRIG_16B			0x00
72 #define TEGRA_UART_TX_TRIG_8B			0x10
73 #define TEGRA_UART_TX_TRIG_4B			0x20
74 #define TEGRA_UART_TX_TRIG_1B			0x30
75 
76 #define TEGRA_UART_MAXIMUM			5
77 
78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
79 #define TEGRA_UART_DEFAULT_BAUD			115200
80 #define TEGRA_UART_DEFAULT_LSR			UART_LCR_WLEN8
81 
82 /* Tx transfer mode */
83 #define TEGRA_TX_PIO				1
84 #define TEGRA_TX_DMA				2
85 
86 /**
87  * tegra_uart_chip_data: SOC specific data.
88  *
89  * @tx_fifo_full_status: Status flag available for checking tx fifo full.
90  * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
91  *			Tegra30 does not allow this.
92  * @support_clk_src_div: Clock source support the clock divider.
93  */
94 struct tegra_uart_chip_data {
95 	bool	tx_fifo_full_status;
96 	bool	allow_txfifo_reset_fifo_mode;
97 	bool	support_clk_src_div;
98 };
99 
100 struct tegra_uart_port {
101 	struct uart_port			uport;
102 	const struct tegra_uart_chip_data	*cdata;
103 
104 	struct clk				*uart_clk;
105 	struct reset_control			*rst;
106 	unsigned int				current_baud;
107 
108 	/* Register shadow */
109 	unsigned long				fcr_shadow;
110 	unsigned long				mcr_shadow;
111 	unsigned long				lcr_shadow;
112 	unsigned long				ier_shadow;
113 	bool					rts_active;
114 
115 	int					tx_in_progress;
116 	unsigned int				tx_bytes;
117 
118 	bool					enable_modem_interrupt;
119 
120 	bool					rx_timeout;
121 	int					rx_in_progress;
122 	int					symb_bit;
123 
124 	struct dma_chan				*rx_dma_chan;
125 	struct dma_chan				*tx_dma_chan;
126 	dma_addr_t				rx_dma_buf_phys;
127 	dma_addr_t				tx_dma_buf_phys;
128 	unsigned char				*rx_dma_buf_virt;
129 	unsigned char				*tx_dma_buf_virt;
130 	struct dma_async_tx_descriptor		*tx_dma_desc;
131 	struct dma_async_tx_descriptor		*rx_dma_desc;
132 	dma_cookie_t				tx_cookie;
133 	dma_cookie_t				rx_cookie;
134 	int					tx_bytes_requested;
135 	int					rx_bytes_requested;
136 };
137 
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
140 
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
142 		unsigned long reg)
143 {
144 	return readl(tup->uport.membase + (reg << tup->uport.regshift));
145 }
146 
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
148 	unsigned long reg)
149 {
150 	writel(val, tup->uport.membase + (reg << tup->uport.regshift));
151 }
152 
153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
154 {
155 	return container_of(u, struct tegra_uart_port, uport);
156 }
157 
158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
159 {
160 	struct tegra_uart_port *tup = to_tegra_uport(u);
161 
162 	/*
163 	 * RI - Ring detector is active
164 	 * CD/DCD/CAR - Carrier detect is always active. For some reason
165 	 *	linux has different names for carrier detect.
166 	 * DSR - Data Set ready is active as the hardware doesn't support it.
167 	 *	Don't know if the linux support this yet?
168 	 * CTS - Clear to send. Always set to active, as the hardware handles
169 	 *	CTS automatically.
170 	 */
171 	if (tup->enable_modem_interrupt)
172 		return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
173 	return TIOCM_CTS;
174 }
175 
176 static void set_rts(struct tegra_uart_port *tup, bool active)
177 {
178 	unsigned long mcr;
179 
180 	mcr = tup->mcr_shadow;
181 	if (active)
182 		mcr |= TEGRA_UART_MCR_RTS_EN;
183 	else
184 		mcr &= ~TEGRA_UART_MCR_RTS_EN;
185 	if (mcr != tup->mcr_shadow) {
186 		tegra_uart_write(tup, mcr, UART_MCR);
187 		tup->mcr_shadow = mcr;
188 	}
189 	return;
190 }
191 
192 static void set_dtr(struct tegra_uart_port *tup, bool active)
193 {
194 	unsigned long mcr;
195 
196 	mcr = tup->mcr_shadow;
197 	if (active)
198 		mcr |= UART_MCR_DTR;
199 	else
200 		mcr &= ~UART_MCR_DTR;
201 	if (mcr != tup->mcr_shadow) {
202 		tegra_uart_write(tup, mcr, UART_MCR);
203 		tup->mcr_shadow = mcr;
204 	}
205 	return;
206 }
207 
208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
209 {
210 	struct tegra_uart_port *tup = to_tegra_uport(u);
211 	unsigned long mcr;
212 	int dtr_enable;
213 
214 	mcr = tup->mcr_shadow;
215 	tup->rts_active = !!(mctrl & TIOCM_RTS);
216 	set_rts(tup, tup->rts_active);
217 
218 	dtr_enable = !!(mctrl & TIOCM_DTR);
219 	set_dtr(tup, dtr_enable);
220 	return;
221 }
222 
223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
224 {
225 	struct tegra_uart_port *tup = to_tegra_uport(u);
226 	unsigned long lcr;
227 
228 	lcr = tup->lcr_shadow;
229 	if (break_ctl)
230 		lcr |= UART_LCR_SBC;
231 	else
232 		lcr &= ~UART_LCR_SBC;
233 	tegra_uart_write(tup, lcr, UART_LCR);
234 	tup->lcr_shadow = lcr;
235 }
236 
237 /* Wait for a symbol-time. */
238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
239 		unsigned int syms)
240 {
241 	if (tup->current_baud)
242 		udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
243 			tup->current_baud));
244 }
245 
246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
247 {
248 	unsigned long fcr = tup->fcr_shadow;
249 
250 	if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251 		fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
252 		tegra_uart_write(tup, fcr, UART_FCR);
253 	} else {
254 		fcr &= ~UART_FCR_ENABLE_FIFO;
255 		tegra_uart_write(tup, fcr, UART_FCR);
256 		udelay(60);
257 		fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
258 		tegra_uart_write(tup, fcr, UART_FCR);
259 		fcr |= UART_FCR_ENABLE_FIFO;
260 		tegra_uart_write(tup, fcr, UART_FCR);
261 	}
262 
263 	/* Dummy read to ensure the write is posted */
264 	tegra_uart_read(tup, UART_SCR);
265 
266 	/* Wait for the flush to propagate. */
267 	tegra_uart_wait_sym_time(tup, 1);
268 }
269 
270 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
271 {
272 	unsigned long rate;
273 	unsigned int divisor;
274 	unsigned long lcr;
275 	int ret;
276 
277 	if (tup->current_baud == baud)
278 		return 0;
279 
280 	if (tup->cdata->support_clk_src_div) {
281 		rate = baud * 16;
282 		ret = clk_set_rate(tup->uart_clk, rate);
283 		if (ret < 0) {
284 			dev_err(tup->uport.dev,
285 				"clk_set_rate() failed for rate %lu\n", rate);
286 			return ret;
287 		}
288 		divisor = 1;
289 	} else {
290 		rate = clk_get_rate(tup->uart_clk);
291 		divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
292 	}
293 
294 	lcr = tup->lcr_shadow;
295 	lcr |= UART_LCR_DLAB;
296 	tegra_uart_write(tup, lcr, UART_LCR);
297 
298 	tegra_uart_write(tup, divisor & 0xFF, UART_TX);
299 	tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
300 
301 	lcr &= ~UART_LCR_DLAB;
302 	tegra_uart_write(tup, lcr, UART_LCR);
303 
304 	/* Dummy read to ensure the write is posted */
305 	tegra_uart_read(tup, UART_SCR);
306 
307 	tup->current_baud = baud;
308 
309 	/* wait two character intervals at new rate */
310 	tegra_uart_wait_sym_time(tup, 2);
311 	return 0;
312 }
313 
314 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
315 			unsigned long lsr)
316 {
317 	char flag = TTY_NORMAL;
318 
319 	if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
320 		if (lsr & UART_LSR_OE) {
321 			/* Overrrun error */
322 			flag |= TTY_OVERRUN;
323 			tup->uport.icount.overrun++;
324 			dev_err(tup->uport.dev, "Got overrun errors\n");
325 		} else if (lsr & UART_LSR_PE) {
326 			/* Parity error */
327 			flag |= TTY_PARITY;
328 			tup->uport.icount.parity++;
329 			dev_err(tup->uport.dev, "Got Parity errors\n");
330 		} else if (lsr & UART_LSR_FE) {
331 			flag |= TTY_FRAME;
332 			tup->uport.icount.frame++;
333 			dev_err(tup->uport.dev, "Got frame errors\n");
334 		} else if (lsr & UART_LSR_BI) {
335 			dev_err(tup->uport.dev, "Got Break\n");
336 			tup->uport.icount.brk++;
337 			/* If FIFO read error without any data, reset Rx FIFO */
338 			if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
339 				tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
340 		}
341 	}
342 	return flag;
343 }
344 
345 static int tegra_uart_request_port(struct uart_port *u)
346 {
347 	return 0;
348 }
349 
350 static void tegra_uart_release_port(struct uart_port *u)
351 {
352 	/* Nothing to do here */
353 }
354 
355 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
356 {
357 	struct circ_buf *xmit = &tup->uport.state->xmit;
358 	int i;
359 
360 	for (i = 0; i < max_bytes; i++) {
361 		BUG_ON(uart_circ_empty(xmit));
362 		if (tup->cdata->tx_fifo_full_status) {
363 			unsigned long lsr = tegra_uart_read(tup, UART_LSR);
364 			if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
365 				break;
366 		}
367 		tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
368 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
369 		tup->uport.icount.tx++;
370 	}
371 }
372 
373 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
374 		unsigned int bytes)
375 {
376 	if (bytes > TEGRA_UART_MIN_DMA)
377 		bytes = TEGRA_UART_MIN_DMA;
378 
379 	tup->tx_in_progress = TEGRA_UART_TX_PIO;
380 	tup->tx_bytes = bytes;
381 	tup->ier_shadow |= UART_IER_THRI;
382 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
383 }
384 
385 static void tegra_uart_tx_dma_complete(void *args)
386 {
387 	struct tegra_uart_port *tup = args;
388 	struct circ_buf *xmit = &tup->uport.state->xmit;
389 	struct dma_tx_state state;
390 	unsigned long flags;
391 	int count;
392 
393 	dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
394 	count = tup->tx_bytes_requested - state.residue;
395 	async_tx_ack(tup->tx_dma_desc);
396 	spin_lock_irqsave(&tup->uport.lock, flags);
397 	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
398 	tup->tx_in_progress = 0;
399 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
400 		uart_write_wakeup(&tup->uport);
401 	tegra_uart_start_next_tx(tup);
402 	spin_unlock_irqrestore(&tup->uport.lock, flags);
403 }
404 
405 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
406 		unsigned long count)
407 {
408 	struct circ_buf *xmit = &tup->uport.state->xmit;
409 	dma_addr_t tx_phys_addr;
410 
411 	dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
412 				UART_XMIT_SIZE, DMA_TO_DEVICE);
413 
414 	tup->tx_bytes = count & ~(0xF);
415 	tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
416 	tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
417 				tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
418 				DMA_PREP_INTERRUPT);
419 	if (!tup->tx_dma_desc) {
420 		dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
421 		return -EIO;
422 	}
423 
424 	tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
425 	tup->tx_dma_desc->callback_param = tup;
426 	tup->tx_in_progress = TEGRA_UART_TX_DMA;
427 	tup->tx_bytes_requested = tup->tx_bytes;
428 	tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
429 	dma_async_issue_pending(tup->tx_dma_chan);
430 	return 0;
431 }
432 
433 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
434 {
435 	unsigned long tail;
436 	unsigned long count;
437 	struct circ_buf *xmit = &tup->uport.state->xmit;
438 
439 	tail = (unsigned long)&xmit->buf[xmit->tail];
440 	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
441 	if (!count)
442 		return;
443 
444 	if (count < TEGRA_UART_MIN_DMA)
445 		tegra_uart_start_pio_tx(tup, count);
446 	else if (BYTES_TO_ALIGN(tail) > 0)
447 		tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
448 	else
449 		tegra_uart_start_tx_dma(tup, count);
450 }
451 
452 /* Called by serial core driver with u->lock taken. */
453 static void tegra_uart_start_tx(struct uart_port *u)
454 {
455 	struct tegra_uart_port *tup = to_tegra_uport(u);
456 	struct circ_buf *xmit = &u->state->xmit;
457 
458 	if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
459 		tegra_uart_start_next_tx(tup);
460 }
461 
462 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
463 {
464 	struct tegra_uart_port *tup = to_tegra_uport(u);
465 	unsigned int ret = 0;
466 	unsigned long flags;
467 
468 	spin_lock_irqsave(&u->lock, flags);
469 	if (!tup->tx_in_progress) {
470 		unsigned long lsr = tegra_uart_read(tup, UART_LSR);
471 		if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
472 			ret = TIOCSER_TEMT;
473 	}
474 	spin_unlock_irqrestore(&u->lock, flags);
475 	return ret;
476 }
477 
478 static void tegra_uart_stop_tx(struct uart_port *u)
479 {
480 	struct tegra_uart_port *tup = to_tegra_uport(u);
481 	struct circ_buf *xmit = &tup->uport.state->xmit;
482 	struct dma_tx_state state;
483 	int count;
484 
485 	if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
486 		return;
487 
488 	dmaengine_terminate_all(tup->tx_dma_chan);
489 	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
490 	count = tup->tx_bytes_requested - state.residue;
491 	async_tx_ack(tup->tx_dma_desc);
492 	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
493 	tup->tx_in_progress = 0;
494 	return;
495 }
496 
497 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
498 {
499 	struct circ_buf *xmit = &tup->uport.state->xmit;
500 
501 	tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
502 	tup->tx_in_progress = 0;
503 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
504 		uart_write_wakeup(&tup->uport);
505 	tegra_uart_start_next_tx(tup);
506 	return;
507 }
508 
509 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
510 		struct tty_port *tty)
511 {
512 	do {
513 		char flag = TTY_NORMAL;
514 		unsigned long lsr = 0;
515 		unsigned char ch;
516 
517 		lsr = tegra_uart_read(tup, UART_LSR);
518 		if (!(lsr & UART_LSR_DR))
519 			break;
520 
521 		flag = tegra_uart_decode_rx_error(tup, lsr);
522 		ch = (unsigned char) tegra_uart_read(tup, UART_RX);
523 		tup->uport.icount.rx++;
524 
525 		if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
526 			tty_insert_flip_char(tty, ch, flag);
527 	} while (1);
528 
529 	return;
530 }
531 
532 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
533 		struct tty_port *tty, int count)
534 {
535 	int copied;
536 
537 	tup->uport.icount.rx += count;
538 	if (!tty) {
539 		dev_err(tup->uport.dev, "No tty port\n");
540 		return;
541 	}
542 	dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
543 				TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
544 	copied = tty_insert_flip_string(tty,
545 			((unsigned char *)(tup->rx_dma_buf_virt)), count);
546 	if (copied != count) {
547 		WARN_ON(1);
548 		dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
549 	}
550 	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
551 				TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
552 }
553 
554 static void tegra_uart_rx_dma_complete(void *args)
555 {
556 	struct tegra_uart_port *tup = args;
557 	struct uart_port *u = &tup->uport;
558 	int count = tup->rx_bytes_requested;
559 	struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
560 	struct tty_port *port = &u->state->port;
561 	unsigned long flags;
562 
563 	async_tx_ack(tup->rx_dma_desc);
564 	spin_lock_irqsave(&u->lock, flags);
565 
566 	/* Deactivate flow control to stop sender */
567 	if (tup->rts_active)
568 		set_rts(tup, false);
569 
570 	/* If we are here, DMA is stopped */
571 	if (count)
572 		tegra_uart_copy_rx_to_tty(tup, port, count);
573 
574 	tegra_uart_handle_rx_pio(tup, port);
575 	if (tty) {
576 		spin_unlock_irqrestore(&u->lock, flags);
577 		tty_flip_buffer_push(port);
578 		spin_lock_irqsave(&u->lock, flags);
579 		tty_kref_put(tty);
580 	}
581 	tegra_uart_start_rx_dma(tup);
582 
583 	/* Activate flow control to start transfer */
584 	if (tup->rts_active)
585 		set_rts(tup, true);
586 
587 	spin_unlock_irqrestore(&u->lock, flags);
588 }
589 
590 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup,
591 		unsigned long *flags)
592 {
593 	struct dma_tx_state state;
594 	struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
595 	struct tty_port *port = &tup->uport.state->port;
596 	struct uart_port *u = &tup->uport;
597 	int count;
598 
599 	/* Deactivate flow control to stop sender */
600 	if (tup->rts_active)
601 		set_rts(tup, false);
602 
603 	dmaengine_terminate_all(tup->rx_dma_chan);
604 	dmaengine_tx_status(tup->rx_dma_chan,  tup->rx_cookie, &state);
605 	async_tx_ack(tup->rx_dma_desc);
606 	count = tup->rx_bytes_requested - state.residue;
607 
608 	/* If we are here, DMA is stopped */
609 	if (count)
610 		tegra_uart_copy_rx_to_tty(tup, port, count);
611 
612 	tegra_uart_handle_rx_pio(tup, port);
613 	if (tty) {
614 		spin_unlock_irqrestore(&u->lock, *flags);
615 		tty_flip_buffer_push(port);
616 		spin_lock_irqsave(&u->lock, *flags);
617 		tty_kref_put(tty);
618 	}
619 	tegra_uart_start_rx_dma(tup);
620 
621 	if (tup->rts_active)
622 		set_rts(tup, true);
623 }
624 
625 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
626 {
627 	unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
628 
629 	tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
630 				tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
631 				DMA_PREP_INTERRUPT);
632 	if (!tup->rx_dma_desc) {
633 		dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
634 		return -EIO;
635 	}
636 
637 	tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
638 	tup->rx_dma_desc->callback_param = tup;
639 	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
640 				count, DMA_TO_DEVICE);
641 	tup->rx_bytes_requested = count;
642 	tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
643 	dma_async_issue_pending(tup->rx_dma_chan);
644 	return 0;
645 }
646 
647 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
648 {
649 	struct tegra_uart_port *tup = to_tegra_uport(u);
650 	unsigned long msr;
651 
652 	msr = tegra_uart_read(tup, UART_MSR);
653 	if (!(msr & UART_MSR_ANY_DELTA))
654 		return;
655 
656 	if (msr & UART_MSR_TERI)
657 		tup->uport.icount.rng++;
658 	if (msr & UART_MSR_DDSR)
659 		tup->uport.icount.dsr++;
660 	/* We may only get DDCD when HW init and reset */
661 	if (msr & UART_MSR_DDCD)
662 		uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
663 	/* Will start/stop_tx accordingly */
664 	if (msr & UART_MSR_DCTS)
665 		uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
666 	return;
667 }
668 
669 static irqreturn_t tegra_uart_isr(int irq, void *data)
670 {
671 	struct tegra_uart_port *tup = data;
672 	struct uart_port *u = &tup->uport;
673 	unsigned long iir;
674 	unsigned long ier;
675 	bool is_rx_int = false;
676 	unsigned long flags;
677 
678 	spin_lock_irqsave(&u->lock, flags);
679 	while (1) {
680 		iir = tegra_uart_read(tup, UART_IIR);
681 		if (iir & UART_IIR_NO_INT) {
682 			if (is_rx_int) {
683 				tegra_uart_handle_rx_dma(tup, &flags);
684 				if (tup->rx_in_progress) {
685 					ier = tup->ier_shadow;
686 					ier |= (UART_IER_RLSI | UART_IER_RTOIE |
687 						TEGRA_UART_IER_EORD);
688 					tup->ier_shadow = ier;
689 					tegra_uart_write(tup, ier, UART_IER);
690 				}
691 			}
692 			spin_unlock_irqrestore(&u->lock, flags);
693 			return IRQ_HANDLED;
694 		}
695 
696 		switch ((iir >> 1) & 0x7) {
697 		case 0: /* Modem signal change interrupt */
698 			tegra_uart_handle_modem_signal_change(u);
699 			break;
700 
701 		case 1: /* Transmit interrupt only triggered when using PIO */
702 			tup->ier_shadow &= ~UART_IER_THRI;
703 			tegra_uart_write(tup, tup->ier_shadow, UART_IER);
704 			tegra_uart_handle_tx_pio(tup);
705 			break;
706 
707 		case 4: /* End of data */
708 		case 6: /* Rx timeout */
709 		case 2: /* Receive */
710 			if (!is_rx_int) {
711 				is_rx_int = true;
712 				/* Disable Rx interrupts */
713 				ier = tup->ier_shadow;
714 				ier |= UART_IER_RDI;
715 				tegra_uart_write(tup, ier, UART_IER);
716 				ier &= ~(UART_IER_RDI | UART_IER_RLSI |
717 					UART_IER_RTOIE | TEGRA_UART_IER_EORD);
718 				tup->ier_shadow = ier;
719 				tegra_uart_write(tup, ier, UART_IER);
720 			}
721 			break;
722 
723 		case 3: /* Receive error */
724 			tegra_uart_decode_rx_error(tup,
725 					tegra_uart_read(tup, UART_LSR));
726 			break;
727 
728 		case 5: /* break nothing to handle */
729 		case 7: /* break nothing to handle */
730 			break;
731 		}
732 	}
733 }
734 
735 static void tegra_uart_stop_rx(struct uart_port *u)
736 {
737 	struct tegra_uart_port *tup = to_tegra_uport(u);
738 	struct tty_struct *tty;
739 	struct tty_port *port = &u->state->port;
740 	struct dma_tx_state state;
741 	unsigned long ier;
742 	int count;
743 
744 	if (tup->rts_active)
745 		set_rts(tup, false);
746 
747 	if (!tup->rx_in_progress)
748 		return;
749 
750 	tty = tty_port_tty_get(&tup->uport.state->port);
751 
752 	tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
753 
754 	ier = tup->ier_shadow;
755 	ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
756 					TEGRA_UART_IER_EORD);
757 	tup->ier_shadow = ier;
758 	tegra_uart_write(tup, ier, UART_IER);
759 	tup->rx_in_progress = 0;
760 	if (tup->rx_dma_chan) {
761 		dmaengine_terminate_all(tup->rx_dma_chan);
762 		dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
763 		async_tx_ack(tup->rx_dma_desc);
764 		count = tup->rx_bytes_requested - state.residue;
765 		tegra_uart_copy_rx_to_tty(tup, port, count);
766 		tegra_uart_handle_rx_pio(tup, port);
767 	} else {
768 		tegra_uart_handle_rx_pio(tup, port);
769 	}
770 	if (tty) {
771 		tty_flip_buffer_push(port);
772 		tty_kref_put(tty);
773 	}
774 	return;
775 }
776 
777 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
778 {
779 	unsigned long flags;
780 	unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
781 	unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
782 	unsigned long wait_time;
783 	unsigned long lsr;
784 	unsigned long msr;
785 	unsigned long mcr;
786 
787 	/* Disable interrupts */
788 	tegra_uart_write(tup, 0, UART_IER);
789 
790 	lsr = tegra_uart_read(tup, UART_LSR);
791 	if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
792 		msr = tegra_uart_read(tup, UART_MSR);
793 		mcr = tegra_uart_read(tup, UART_MCR);
794 		if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
795 			dev_err(tup->uport.dev,
796 				"Tx Fifo not empty, CTS disabled, waiting\n");
797 
798 		/* Wait for Tx fifo to be empty */
799 		while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
800 			wait_time = min(fifo_empty_time, 100lu);
801 			udelay(wait_time);
802 			fifo_empty_time -= wait_time;
803 			if (!fifo_empty_time) {
804 				msr = tegra_uart_read(tup, UART_MSR);
805 				mcr = tegra_uart_read(tup, UART_MCR);
806 				if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
807 					(msr & UART_MSR_CTS))
808 					dev_err(tup->uport.dev,
809 						"Slave not ready\n");
810 				break;
811 			}
812 			lsr = tegra_uart_read(tup, UART_LSR);
813 		}
814 	}
815 
816 	spin_lock_irqsave(&tup->uport.lock, flags);
817 	/* Reset the Rx and Tx FIFOs */
818 	tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
819 	tup->current_baud = 0;
820 	spin_unlock_irqrestore(&tup->uport.lock, flags);
821 
822 	clk_disable_unprepare(tup->uart_clk);
823 }
824 
825 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
826 {
827 	int ret;
828 
829 	tup->fcr_shadow = 0;
830 	tup->mcr_shadow = 0;
831 	tup->lcr_shadow = 0;
832 	tup->ier_shadow = 0;
833 	tup->current_baud = 0;
834 
835 	clk_prepare_enable(tup->uart_clk);
836 
837 	/* Reset the UART controller to clear all previous status.*/
838 	reset_control_assert(tup->rst);
839 	udelay(10);
840 	reset_control_deassert(tup->rst);
841 
842 	tup->rx_in_progress = 0;
843 	tup->tx_in_progress = 0;
844 
845 	/*
846 	 * Set the trigger level
847 	 *
848 	 * For PIO mode:
849 	 *
850 	 * For receive, this will interrupt the CPU after that many number of
851 	 * bytes are received, for the remaining bytes the receive timeout
852 	 * interrupt is received. Rx high watermark is set to 4.
853 	 *
854 	 * For transmit, if the trasnmit interrupt is enabled, this will
855 	 * interrupt the CPU when the number of entries in the FIFO reaches the
856 	 * low watermark. Tx low watermark is set to 16 bytes.
857 	 *
858 	 * For DMA mode:
859 	 *
860 	 * Set the Tx trigger to 16. This should match the DMA burst size that
861 	 * programmed in the DMA registers.
862 	 */
863 	tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
864 	tup->fcr_shadow |= UART_FCR_R_TRIG_01;
865 	tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
866 	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
867 
868 	/*
869 	 * Initialize the UART with default configuration
870 	 * (115200, N, 8, 1) so that the receive DMA buffer may be
871 	 * enqueued
872 	 */
873 	tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
874 	tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
875 	tup->fcr_shadow |= UART_FCR_DMA_SELECT;
876 	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
877 
878 	ret = tegra_uart_start_rx_dma(tup);
879 	if (ret < 0) {
880 		dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
881 		return ret;
882 	}
883 	tup->rx_in_progress = 1;
884 
885 	/*
886 	 * Enable IE_RXS for the receive status interrupts like line errros.
887 	 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
888 	 *
889 	 * If using DMA mode, enable EORD instead of receive interrupt which
890 	 * will interrupt after the UART is done with the receive instead of
891 	 * the interrupt when the FIFO "threshold" is reached.
892 	 *
893 	 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
894 	 * the DATA is sitting in the FIFO and couldn't be transferred to the
895 	 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
896 	 * triggered when there is a pause of the incomming data stream for 4
897 	 * characters long.
898 	 *
899 	 * For pauses in the data which is not aligned to 4 bytes, we get
900 	 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
901 	 * then the EORD.
902 	 */
903 	tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
904 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
905 	return 0;
906 }
907 
908 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
909 			bool dma_to_memory)
910 {
911 	struct dma_chan *dma_chan;
912 	unsigned char *dma_buf;
913 	dma_addr_t dma_phys;
914 	int ret;
915 	struct dma_slave_config dma_sconfig;
916 
917 	dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
918 						dma_to_memory ? "rx" : "tx");
919 	if (IS_ERR(dma_chan)) {
920 		ret = PTR_ERR(dma_chan);
921 		dev_err(tup->uport.dev,
922 			"DMA channel alloc failed: %d\n", ret);
923 		return ret;
924 	}
925 
926 	if (dma_to_memory) {
927 		dma_buf = dma_alloc_coherent(tup->uport.dev,
928 				TEGRA_UART_RX_DMA_BUFFER_SIZE,
929 				 &dma_phys, GFP_KERNEL);
930 		if (!dma_buf) {
931 			dev_err(tup->uport.dev,
932 				"Not able to allocate the dma buffer\n");
933 			dma_release_channel(dma_chan);
934 			return -ENOMEM;
935 		}
936 	} else {
937 		dma_phys = dma_map_single(tup->uport.dev,
938 			tup->uport.state->xmit.buf, UART_XMIT_SIZE,
939 			DMA_TO_DEVICE);
940 		dma_buf = tup->uport.state->xmit.buf;
941 	}
942 
943 	if (dma_to_memory) {
944 		dma_sconfig.src_addr = tup->uport.mapbase;
945 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
946 		dma_sconfig.src_maxburst = 4;
947 	} else {
948 		dma_sconfig.dst_addr = tup->uport.mapbase;
949 		dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
950 		dma_sconfig.dst_maxburst = 16;
951 	}
952 
953 	ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
954 	if (ret < 0) {
955 		dev_err(tup->uport.dev,
956 			"Dma slave config failed, err = %d\n", ret);
957 		goto scrub;
958 	}
959 
960 	if (dma_to_memory) {
961 		tup->rx_dma_chan = dma_chan;
962 		tup->rx_dma_buf_virt = dma_buf;
963 		tup->rx_dma_buf_phys = dma_phys;
964 	} else {
965 		tup->tx_dma_chan = dma_chan;
966 		tup->tx_dma_buf_virt = dma_buf;
967 		tup->tx_dma_buf_phys = dma_phys;
968 	}
969 	return 0;
970 
971 scrub:
972 	dma_release_channel(dma_chan);
973 	return ret;
974 }
975 
976 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
977 		bool dma_to_memory)
978 {
979 	struct dma_chan *dma_chan;
980 
981 	if (dma_to_memory) {
982 		dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
983 				tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
984 		dma_chan = tup->rx_dma_chan;
985 		tup->rx_dma_chan = NULL;
986 		tup->rx_dma_buf_phys = 0;
987 		tup->rx_dma_buf_virt = NULL;
988 	} else {
989 		dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
990 			UART_XMIT_SIZE, DMA_TO_DEVICE);
991 		dma_chan = tup->tx_dma_chan;
992 		tup->tx_dma_chan = NULL;
993 		tup->tx_dma_buf_phys = 0;
994 		tup->tx_dma_buf_virt = NULL;
995 	}
996 	dma_release_channel(dma_chan);
997 }
998 
999 static int tegra_uart_startup(struct uart_port *u)
1000 {
1001 	struct tegra_uart_port *tup = to_tegra_uport(u);
1002 	int ret;
1003 
1004 	ret = tegra_uart_dma_channel_allocate(tup, false);
1005 	if (ret < 0) {
1006 		dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
1007 		return ret;
1008 	}
1009 
1010 	ret = tegra_uart_dma_channel_allocate(tup, true);
1011 	if (ret < 0) {
1012 		dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1013 		goto fail_rx_dma;
1014 	}
1015 
1016 	ret = tegra_uart_hw_init(tup);
1017 	if (ret < 0) {
1018 		dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1019 		goto fail_hw_init;
1020 	}
1021 
1022 	ret = request_irq(u->irq, tegra_uart_isr, 0,
1023 				dev_name(u->dev), tup);
1024 	if (ret < 0) {
1025 		dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1026 		goto fail_hw_init;
1027 	}
1028 	return 0;
1029 
1030 fail_hw_init:
1031 	tegra_uart_dma_channel_free(tup, true);
1032 fail_rx_dma:
1033 	tegra_uart_dma_channel_free(tup, false);
1034 	return ret;
1035 }
1036 
1037 static void tegra_uart_shutdown(struct uart_port *u)
1038 {
1039 	struct tegra_uart_port *tup = to_tegra_uport(u);
1040 
1041 	tegra_uart_hw_deinit(tup);
1042 
1043 	tup->rx_in_progress = 0;
1044 	tup->tx_in_progress = 0;
1045 
1046 	tegra_uart_dma_channel_free(tup, true);
1047 	tegra_uart_dma_channel_free(tup, false);
1048 	free_irq(u->irq, tup);
1049 }
1050 
1051 static void tegra_uart_enable_ms(struct uart_port *u)
1052 {
1053 	struct tegra_uart_port *tup = to_tegra_uport(u);
1054 
1055 	if (tup->enable_modem_interrupt) {
1056 		tup->ier_shadow |= UART_IER_MSI;
1057 		tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1058 	}
1059 }
1060 
1061 static void tegra_uart_set_termios(struct uart_port *u,
1062 		struct ktermios *termios, struct ktermios *oldtermios)
1063 {
1064 	struct tegra_uart_port *tup = to_tegra_uport(u);
1065 	unsigned int baud;
1066 	unsigned long flags;
1067 	unsigned int lcr;
1068 	int symb_bit = 1;
1069 	struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1070 	unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1071 	int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1072 
1073 	max_divider *= 16;
1074 	spin_lock_irqsave(&u->lock, flags);
1075 
1076 	/* Changing configuration, it is safe to stop any rx now */
1077 	if (tup->rts_active)
1078 		set_rts(tup, false);
1079 
1080 	/* Clear all interrupts as configuration is going to be change */
1081 	tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1082 	tegra_uart_read(tup, UART_IER);
1083 	tegra_uart_write(tup, 0, UART_IER);
1084 	tegra_uart_read(tup, UART_IER);
1085 
1086 	/* Parity */
1087 	lcr = tup->lcr_shadow;
1088 	lcr &= ~UART_LCR_PARITY;
1089 
1090 	/* CMSPAR isn't supported by this driver */
1091 	termios->c_cflag &= ~CMSPAR;
1092 
1093 	if ((termios->c_cflag & PARENB) == PARENB) {
1094 		symb_bit++;
1095 		if (termios->c_cflag & PARODD) {
1096 			lcr |= UART_LCR_PARITY;
1097 			lcr &= ~UART_LCR_EPAR;
1098 			lcr &= ~UART_LCR_SPAR;
1099 		} else {
1100 			lcr |= UART_LCR_PARITY;
1101 			lcr |= UART_LCR_EPAR;
1102 			lcr &= ~UART_LCR_SPAR;
1103 		}
1104 	}
1105 
1106 	lcr &= ~UART_LCR_WLEN8;
1107 	switch (termios->c_cflag & CSIZE) {
1108 	case CS5:
1109 		lcr |= UART_LCR_WLEN5;
1110 		symb_bit += 5;
1111 		break;
1112 	case CS6:
1113 		lcr |= UART_LCR_WLEN6;
1114 		symb_bit += 6;
1115 		break;
1116 	case CS7:
1117 		lcr |= UART_LCR_WLEN7;
1118 		symb_bit += 7;
1119 		break;
1120 	default:
1121 		lcr |= UART_LCR_WLEN8;
1122 		symb_bit += 8;
1123 		break;
1124 	}
1125 
1126 	/* Stop bits */
1127 	if (termios->c_cflag & CSTOPB) {
1128 		lcr |= UART_LCR_STOP;
1129 		symb_bit += 2;
1130 	} else {
1131 		lcr &= ~UART_LCR_STOP;
1132 		symb_bit++;
1133 	}
1134 
1135 	tegra_uart_write(tup, lcr, UART_LCR);
1136 	tup->lcr_shadow = lcr;
1137 	tup->symb_bit = symb_bit;
1138 
1139 	/* Baud rate. */
1140 	baud = uart_get_baud_rate(u, termios, oldtermios,
1141 			parent_clk_rate/max_divider,
1142 			parent_clk_rate/16);
1143 	spin_unlock_irqrestore(&u->lock, flags);
1144 	tegra_set_baudrate(tup, baud);
1145 	if (tty_termios_baud_rate(termios))
1146 		tty_termios_encode_baud_rate(termios, baud, baud);
1147 	spin_lock_irqsave(&u->lock, flags);
1148 
1149 	/* Flow control */
1150 	if (termios->c_cflag & CRTSCTS)	{
1151 		tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1152 		tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1153 		tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1154 		/* if top layer has asked to set rts active then do so here */
1155 		if (tup->rts_active)
1156 			set_rts(tup, true);
1157 	} else {
1158 		tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1159 		tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1160 		tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1161 	}
1162 
1163 	/* update the port timeout based on new settings */
1164 	uart_update_timeout(u, termios->c_cflag, baud);
1165 
1166 	/* Make sure all write has completed */
1167 	tegra_uart_read(tup, UART_IER);
1168 
1169 	/* Reenable interrupt */
1170 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1171 	tegra_uart_read(tup, UART_IER);
1172 
1173 	spin_unlock_irqrestore(&u->lock, flags);
1174 	return;
1175 }
1176 
1177 /*
1178  * Flush any TX data submitted for DMA and PIO. Called when the
1179  * TX circular buffer is reset.
1180  */
1181 static void tegra_uart_flush_buffer(struct uart_port *u)
1182 {
1183 	struct tegra_uart_port *tup = to_tegra_uport(u);
1184 
1185 	tup->tx_bytes = 0;
1186 	if (tup->tx_dma_chan)
1187 		dmaengine_terminate_all(tup->tx_dma_chan);
1188 	return;
1189 }
1190 
1191 static const char *tegra_uart_type(struct uart_port *u)
1192 {
1193 	return TEGRA_UART_TYPE;
1194 }
1195 
1196 static struct uart_ops tegra_uart_ops = {
1197 	.tx_empty	= tegra_uart_tx_empty,
1198 	.set_mctrl	= tegra_uart_set_mctrl,
1199 	.get_mctrl	= tegra_uart_get_mctrl,
1200 	.stop_tx	= tegra_uart_stop_tx,
1201 	.start_tx	= tegra_uart_start_tx,
1202 	.stop_rx	= tegra_uart_stop_rx,
1203 	.flush_buffer	= tegra_uart_flush_buffer,
1204 	.enable_ms	= tegra_uart_enable_ms,
1205 	.break_ctl	= tegra_uart_break_ctl,
1206 	.startup	= tegra_uart_startup,
1207 	.shutdown	= tegra_uart_shutdown,
1208 	.set_termios	= tegra_uart_set_termios,
1209 	.type		= tegra_uart_type,
1210 	.request_port	= tegra_uart_request_port,
1211 	.release_port	= tegra_uart_release_port,
1212 };
1213 
1214 static struct uart_driver tegra_uart_driver = {
1215 	.owner		= THIS_MODULE,
1216 	.driver_name	= "tegra_hsuart",
1217 	.dev_name	= "ttyTHS",
1218 	.cons		= NULL,
1219 	.nr		= TEGRA_UART_MAXIMUM,
1220 };
1221 
1222 static int tegra_uart_parse_dt(struct platform_device *pdev,
1223 	struct tegra_uart_port *tup)
1224 {
1225 	struct device_node *np = pdev->dev.of_node;
1226 	int port;
1227 
1228 	port = of_alias_get_id(np, "serial");
1229 	if (port < 0) {
1230 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1231 		return port;
1232 	}
1233 	tup->uport.line = port;
1234 
1235 	tup->enable_modem_interrupt = of_property_read_bool(np,
1236 					"nvidia,enable-modem-interrupt");
1237 	return 0;
1238 }
1239 
1240 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1241 	.tx_fifo_full_status		= false,
1242 	.allow_txfifo_reset_fifo_mode	= true,
1243 	.support_clk_src_div		= false,
1244 };
1245 
1246 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1247 	.tx_fifo_full_status		= true,
1248 	.allow_txfifo_reset_fifo_mode	= false,
1249 	.support_clk_src_div		= true,
1250 };
1251 
1252 static struct of_device_id tegra_uart_of_match[] = {
1253 	{
1254 		.compatible	= "nvidia,tegra30-hsuart",
1255 		.data		= &tegra30_uart_chip_data,
1256 	}, {
1257 		.compatible	= "nvidia,tegra20-hsuart",
1258 		.data		= &tegra20_uart_chip_data,
1259 	}, {
1260 	},
1261 };
1262 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1263 
1264 static int tegra_uart_probe(struct platform_device *pdev)
1265 {
1266 	struct tegra_uart_port *tup;
1267 	struct uart_port *u;
1268 	struct resource *resource;
1269 	int ret;
1270 	const struct tegra_uart_chip_data *cdata;
1271 	const struct of_device_id *match;
1272 
1273 	match = of_match_device(tegra_uart_of_match, &pdev->dev);
1274 	if (!match) {
1275 		dev_err(&pdev->dev, "Error: No device match found\n");
1276 		return -ENODEV;
1277 	}
1278 	cdata = match->data;
1279 
1280 	tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1281 	if (!tup) {
1282 		dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1283 		return -ENOMEM;
1284 	}
1285 
1286 	ret = tegra_uart_parse_dt(pdev, tup);
1287 	if (ret < 0)
1288 		return ret;
1289 
1290 	u = &tup->uport;
1291 	u->dev = &pdev->dev;
1292 	u->ops = &tegra_uart_ops;
1293 	u->type = PORT_TEGRA;
1294 	u->fifosize = 32;
1295 	tup->cdata = cdata;
1296 
1297 	platform_set_drvdata(pdev, tup);
1298 	resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299 	if (!resource) {
1300 		dev_err(&pdev->dev, "No IO memory resource\n");
1301 		return -ENODEV;
1302 	}
1303 
1304 	u->mapbase = resource->start;
1305 	u->membase = devm_ioremap_resource(&pdev->dev, resource);
1306 	if (IS_ERR(u->membase))
1307 		return PTR_ERR(u->membase);
1308 
1309 	tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1310 	if (IS_ERR(tup->uart_clk)) {
1311 		dev_err(&pdev->dev, "Couldn't get the clock\n");
1312 		return PTR_ERR(tup->uart_clk);
1313 	}
1314 
1315 	tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1316 	if (IS_ERR(tup->rst)) {
1317 		dev_err(&pdev->dev, "Couldn't get the reset\n");
1318 		return PTR_ERR(tup->rst);
1319 	}
1320 
1321 	u->iotype = UPIO_MEM32;
1322 	u->irq = platform_get_irq(pdev, 0);
1323 	u->regshift = 2;
1324 	ret = uart_add_one_port(&tegra_uart_driver, u);
1325 	if (ret < 0) {
1326 		dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1327 		return ret;
1328 	}
1329 	return ret;
1330 }
1331 
1332 static int tegra_uart_remove(struct platform_device *pdev)
1333 {
1334 	struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1335 	struct uart_port *u = &tup->uport;
1336 
1337 	uart_remove_one_port(&tegra_uart_driver, u);
1338 	return 0;
1339 }
1340 
1341 #ifdef CONFIG_PM_SLEEP
1342 static int tegra_uart_suspend(struct device *dev)
1343 {
1344 	struct tegra_uart_port *tup = dev_get_drvdata(dev);
1345 	struct uart_port *u = &tup->uport;
1346 
1347 	return uart_suspend_port(&tegra_uart_driver, u);
1348 }
1349 
1350 static int tegra_uart_resume(struct device *dev)
1351 {
1352 	struct tegra_uart_port *tup = dev_get_drvdata(dev);
1353 	struct uart_port *u = &tup->uport;
1354 
1355 	return uart_resume_port(&tegra_uart_driver, u);
1356 }
1357 #endif
1358 
1359 static const struct dev_pm_ops tegra_uart_pm_ops = {
1360 	SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1361 };
1362 
1363 static struct platform_driver tegra_uart_platform_driver = {
1364 	.probe		= tegra_uart_probe,
1365 	.remove		= tegra_uart_remove,
1366 	.driver		= {
1367 		.name	= "serial-tegra",
1368 		.of_match_table = tegra_uart_of_match,
1369 		.pm	= &tegra_uart_pm_ops,
1370 	},
1371 };
1372 
1373 static int __init tegra_uart_init(void)
1374 {
1375 	int ret;
1376 
1377 	ret = uart_register_driver(&tegra_uart_driver);
1378 	if (ret < 0) {
1379 		pr_err("Could not register %s driver\n",
1380 			tegra_uart_driver.driver_name);
1381 		return ret;
1382 	}
1383 
1384 	ret = platform_driver_register(&tegra_uart_platform_driver);
1385 	if (ret < 0) {
1386 		pr_err("Uart platform driver register failed, e = %d\n", ret);
1387 		uart_unregister_driver(&tegra_uart_driver);
1388 		return ret;
1389 	}
1390 	return 0;
1391 }
1392 
1393 static void __exit tegra_uart_exit(void)
1394 {
1395 	pr_info("Unloading tegra uart driver\n");
1396 	platform_driver_unregister(&tegra_uart_platform_driver);
1397 	uart_unregister_driver(&tegra_uart_driver);
1398 }
1399 
1400 module_init(tegra_uart_init);
1401 module_exit(tegra_uart_exit);
1402 
1403 MODULE_ALIAS("platform:serial-tegra");
1404 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1405 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1406 MODULE_LICENSE("GPL v2");
1407