1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * serial_tegra.c
4  *
5  * High-speed serial driver for NVIDIA Tegra SoCs
6  *
7  * Copyright (c) 2012-2019, NVIDIA CORPORATION.  All rights reserved.
8  *
9  * Author: Laxman Dewangan <ldewangan@nvidia.com>
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pagemap.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/serial_core.h>
30 #include <linux/serial_reg.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <linux/termios.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 
37 #define TEGRA_UART_TYPE				"TEGRA_UART"
38 #define TX_EMPTY_STATUS				(UART_LSR_TEMT | UART_LSR_THRE)
39 #define BYTES_TO_ALIGN(x)			((unsigned long)(x) & 0x3)
40 
41 #define TEGRA_UART_RX_DMA_BUFFER_SIZE		4096
42 #define TEGRA_UART_LSR_TXFIFO_FULL		0x100
43 #define TEGRA_UART_IER_EORD			0x20
44 #define TEGRA_UART_MCR_RTS_EN			0x40
45 #define TEGRA_UART_MCR_CTS_EN			0x20
46 #define TEGRA_UART_LSR_ANY			(UART_LSR_OE | UART_LSR_BI | \
47 						UART_LSR_PE | UART_LSR_FE)
48 #define TEGRA_UART_IRDA_CSR			0x08
49 #define TEGRA_UART_SIR_ENABLED			0x80
50 
51 #define TEGRA_UART_TX_PIO			1
52 #define TEGRA_UART_TX_DMA			2
53 #define TEGRA_UART_MIN_DMA			16
54 #define TEGRA_UART_FIFO_SIZE			32
55 
56 /*
57  * Tx fifo trigger level setting in tegra uart is in
58  * reverse way then conventional uart.
59  */
60 #define TEGRA_UART_TX_TRIG_16B			0x00
61 #define TEGRA_UART_TX_TRIG_8B			0x10
62 #define TEGRA_UART_TX_TRIG_4B			0x20
63 #define TEGRA_UART_TX_TRIG_1B			0x30
64 
65 #define TEGRA_UART_MAXIMUM			8
66 
67 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68 #define TEGRA_UART_DEFAULT_BAUD			115200
69 #define TEGRA_UART_DEFAULT_LSR			UART_LCR_WLEN8
70 
71 /* Tx transfer mode */
72 #define TEGRA_TX_PIO				1
73 #define TEGRA_TX_DMA				2
74 
75 #define TEGRA_UART_FCR_IIR_FIFO_EN		0x40
76 
77 /**
78  * struct tegra_uart_chip_data: SOC specific data.
79  *
80  * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81  * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
82  *			Tegra30 does not allow this.
83  * @support_clk_src_div: Clock source support the clock divider.
84  * @fifo_mode_enable_status: Is FIFO mode enabled?
85  * @uart_max_port: Maximum number of UART ports
86  * @max_dma_burst_bytes: Maximum size of DMA bursts
87  * @error_tolerance_low_range: Lowest number in the error tolerance range
88  * @error_tolerance_high_range: Highest number in the error tolerance range
89  */
90 struct tegra_uart_chip_data {
91 	bool	tx_fifo_full_status;
92 	bool	allow_txfifo_reset_fifo_mode;
93 	bool	support_clk_src_div;
94 	bool	fifo_mode_enable_status;
95 	int	uart_max_port;
96 	int	max_dma_burst_bytes;
97 	int	error_tolerance_low_range;
98 	int	error_tolerance_high_range;
99 };
100 
101 struct tegra_baud_tolerance {
102 	u32 lower_range_baud;
103 	u32 upper_range_baud;
104 	s32 tolerance;
105 };
106 
107 struct tegra_uart_port {
108 	struct uart_port			uport;
109 	const struct tegra_uart_chip_data	*cdata;
110 
111 	struct clk				*uart_clk;
112 	struct reset_control			*rst;
113 	unsigned int				current_baud;
114 
115 	/* Register shadow */
116 	unsigned long				fcr_shadow;
117 	unsigned long				mcr_shadow;
118 	unsigned long				lcr_shadow;
119 	unsigned long				ier_shadow;
120 	bool					rts_active;
121 
122 	int					tx_in_progress;
123 	unsigned int				tx_bytes;
124 
125 	bool					enable_modem_interrupt;
126 
127 	bool					rx_timeout;
128 	int					rx_in_progress;
129 	int					symb_bit;
130 
131 	struct dma_chan				*rx_dma_chan;
132 	struct dma_chan				*tx_dma_chan;
133 	dma_addr_t				rx_dma_buf_phys;
134 	dma_addr_t				tx_dma_buf_phys;
135 	unsigned char				*rx_dma_buf_virt;
136 	unsigned char				*tx_dma_buf_virt;
137 	struct dma_async_tx_descriptor		*tx_dma_desc;
138 	struct dma_async_tx_descriptor		*rx_dma_desc;
139 	dma_cookie_t				tx_cookie;
140 	dma_cookie_t				rx_cookie;
141 	unsigned int				tx_bytes_requested;
142 	unsigned int				rx_bytes_requested;
143 	struct tegra_baud_tolerance		*baud_tolerance;
144 	int					n_adjustable_baud_rates;
145 	int					required_rate;
146 	int					configured_rate;
147 	bool					use_rx_pio;
148 	bool					use_tx_pio;
149 	bool					rx_dma_active;
150 };
151 
152 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
153 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
154 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
155 					bool dma_to_memory);
156 
157 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
158 		unsigned long reg)
159 {
160 	return readl(tup->uport.membase + (reg << tup->uport.regshift));
161 }
162 
163 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
164 	unsigned long reg)
165 {
166 	writel(val, tup->uport.membase + (reg << tup->uport.regshift));
167 }
168 
169 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
170 {
171 	return container_of(u, struct tegra_uart_port, uport);
172 }
173 
174 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
175 {
176 	struct tegra_uart_port *tup = to_tegra_uport(u);
177 
178 	/*
179 	 * RI - Ring detector is active
180 	 * CD/DCD/CAR - Carrier detect is always active. For some reason
181 	 *	linux has different names for carrier detect.
182 	 * DSR - Data Set ready is active as the hardware doesn't support it.
183 	 *	Don't know if the linux support this yet?
184 	 * CTS - Clear to send. Always set to active, as the hardware handles
185 	 *	CTS automatically.
186 	 */
187 	if (tup->enable_modem_interrupt)
188 		return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
189 	return TIOCM_CTS;
190 }
191 
192 static void set_rts(struct tegra_uart_port *tup, bool active)
193 {
194 	unsigned long mcr;
195 
196 	mcr = tup->mcr_shadow;
197 	if (active)
198 		mcr |= TEGRA_UART_MCR_RTS_EN;
199 	else
200 		mcr &= ~TEGRA_UART_MCR_RTS_EN;
201 	if (mcr != tup->mcr_shadow) {
202 		tegra_uart_write(tup, mcr, UART_MCR);
203 		tup->mcr_shadow = mcr;
204 	}
205 }
206 
207 static void set_dtr(struct tegra_uart_port *tup, bool active)
208 {
209 	unsigned long mcr;
210 
211 	mcr = tup->mcr_shadow;
212 	if (active)
213 		mcr |= UART_MCR_DTR;
214 	else
215 		mcr &= ~UART_MCR_DTR;
216 	if (mcr != tup->mcr_shadow) {
217 		tegra_uart_write(tup, mcr, UART_MCR);
218 		tup->mcr_shadow = mcr;
219 	}
220 }
221 
222 static void set_loopbk(struct tegra_uart_port *tup, bool active)
223 {
224 	unsigned long mcr = tup->mcr_shadow;
225 
226 	if (active)
227 		mcr |= UART_MCR_LOOP;
228 	else
229 		mcr &= ~UART_MCR_LOOP;
230 
231 	if (mcr != tup->mcr_shadow) {
232 		tegra_uart_write(tup, mcr, UART_MCR);
233 		tup->mcr_shadow = mcr;
234 	}
235 }
236 
237 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
238 {
239 	struct tegra_uart_port *tup = to_tegra_uport(u);
240 	int enable;
241 
242 	tup->rts_active = !!(mctrl & TIOCM_RTS);
243 	set_rts(tup, tup->rts_active);
244 
245 	enable = !!(mctrl & TIOCM_DTR);
246 	set_dtr(tup, enable);
247 
248 	enable = !!(mctrl & TIOCM_LOOP);
249 	set_loopbk(tup, enable);
250 }
251 
252 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
253 {
254 	struct tegra_uart_port *tup = to_tegra_uport(u);
255 	unsigned long lcr;
256 
257 	lcr = tup->lcr_shadow;
258 	if (break_ctl)
259 		lcr |= UART_LCR_SBC;
260 	else
261 		lcr &= ~UART_LCR_SBC;
262 	tegra_uart_write(tup, lcr, UART_LCR);
263 	tup->lcr_shadow = lcr;
264 }
265 
266 /**
267  * tegra_uart_wait_cycle_time: Wait for N UART clock periods
268  *
269  * @tup:	Tegra serial port data structure.
270  * @cycles:	Number of clock periods to wait.
271  *
272  * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
273  * clock speed is 16X the current baud rate.
274  */
275 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
276 				       unsigned int cycles)
277 {
278 	if (tup->current_baud)
279 		udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
280 }
281 
282 /* Wait for a symbol-time. */
283 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
284 		unsigned int syms)
285 {
286 	if (tup->current_baud)
287 		udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
288 			tup->current_baud));
289 }
290 
291 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
292 {
293 	unsigned long iir;
294 	unsigned int tmout = 100;
295 
296 	do {
297 		iir = tegra_uart_read(tup, UART_IIR);
298 		if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
299 			return 0;
300 		udelay(1);
301 	} while (--tmout);
302 
303 	return -ETIMEDOUT;
304 }
305 
306 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
307 {
308 	unsigned long fcr = tup->fcr_shadow;
309 	unsigned int lsr, tmout = 10000;
310 
311 	if (tup->rts_active)
312 		set_rts(tup, false);
313 
314 	if (tup->cdata->allow_txfifo_reset_fifo_mode) {
315 		fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
316 		tegra_uart_write(tup, fcr, UART_FCR);
317 	} else {
318 		fcr &= ~UART_FCR_ENABLE_FIFO;
319 		tegra_uart_write(tup, fcr, UART_FCR);
320 		udelay(60);
321 		fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
322 		tegra_uart_write(tup, fcr, UART_FCR);
323 		fcr |= UART_FCR_ENABLE_FIFO;
324 		tegra_uart_write(tup, fcr, UART_FCR);
325 		if (tup->cdata->fifo_mode_enable_status)
326 			tegra_uart_wait_fifo_mode_enabled(tup);
327 	}
328 
329 	/* Dummy read to ensure the write is posted */
330 	tegra_uart_read(tup, UART_SCR);
331 
332 	/*
333 	 * For all tegra devices (up to t210), there is a hardware issue that
334 	 * requires software to wait for 32 UART clock periods for the flush
335 	 * to propagate, otherwise data could be lost.
336 	 */
337 	tegra_uart_wait_cycle_time(tup, 32);
338 
339 	do {
340 		lsr = tegra_uart_read(tup, UART_LSR);
341 		if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
342 			break;
343 		udelay(1);
344 	} while (--tmout);
345 
346 	if (tup->rts_active)
347 		set_rts(tup, true);
348 }
349 
350 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
351 				     unsigned int baud, long rate)
352 {
353 	int i;
354 
355 	for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
356 		if (baud >= tup->baud_tolerance[i].lower_range_baud &&
357 		    baud <= tup->baud_tolerance[i].upper_range_baud)
358 			return (rate + (rate *
359 				tup->baud_tolerance[i].tolerance) / 10000);
360 	}
361 
362 	return rate;
363 }
364 
365 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
366 {
367 	long diff;
368 
369 	diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
370 		/ tup->required_rate;
371 	if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
372 	    diff > (tup->cdata->error_tolerance_high_range * 100)) {
373 		dev_err(tup->uport.dev,
374 			"configured baud rate is out of range by %ld", diff);
375 		return -EIO;
376 	}
377 
378 	return 0;
379 }
380 
381 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
382 {
383 	unsigned long rate;
384 	unsigned int divisor;
385 	unsigned long lcr;
386 	unsigned long flags;
387 	int ret;
388 
389 	if (tup->current_baud == baud)
390 		return 0;
391 
392 	if (tup->cdata->support_clk_src_div) {
393 		rate = baud * 16;
394 		tup->required_rate = rate;
395 
396 		if (tup->n_adjustable_baud_rates)
397 			rate = tegra_get_tolerance_rate(tup, baud, rate);
398 
399 		ret = clk_set_rate(tup->uart_clk, rate);
400 		if (ret < 0) {
401 			dev_err(tup->uport.dev,
402 				"clk_set_rate() failed for rate %lu\n", rate);
403 			return ret;
404 		}
405 		tup->configured_rate = clk_get_rate(tup->uart_clk);
406 		divisor = 1;
407 		ret = tegra_check_rate_in_range(tup);
408 		if (ret < 0)
409 			return ret;
410 	} else {
411 		rate = clk_get_rate(tup->uart_clk);
412 		divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
413 	}
414 
415 	spin_lock_irqsave(&tup->uport.lock, flags);
416 	lcr = tup->lcr_shadow;
417 	lcr |= UART_LCR_DLAB;
418 	tegra_uart_write(tup, lcr, UART_LCR);
419 
420 	tegra_uart_write(tup, divisor & 0xFF, UART_TX);
421 	tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
422 
423 	lcr &= ~UART_LCR_DLAB;
424 	tegra_uart_write(tup, lcr, UART_LCR);
425 
426 	/* Dummy read to ensure the write is posted */
427 	tegra_uart_read(tup, UART_SCR);
428 	spin_unlock_irqrestore(&tup->uport.lock, flags);
429 
430 	tup->current_baud = baud;
431 
432 	/* wait two character intervals at new rate */
433 	tegra_uart_wait_sym_time(tup, 2);
434 	return 0;
435 }
436 
437 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
438 			unsigned long lsr)
439 {
440 	char flag = TTY_NORMAL;
441 
442 	if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
443 		if (lsr & UART_LSR_OE) {
444 			/* Overrun error */
445 			flag = TTY_OVERRUN;
446 			tup->uport.icount.overrun++;
447 			dev_dbg(tup->uport.dev, "Got overrun errors\n");
448 		} else if (lsr & UART_LSR_PE) {
449 			/* Parity error */
450 			flag = TTY_PARITY;
451 			tup->uport.icount.parity++;
452 			dev_dbg(tup->uport.dev, "Got Parity errors\n");
453 		} else if (lsr & UART_LSR_FE) {
454 			flag = TTY_FRAME;
455 			tup->uport.icount.frame++;
456 			dev_dbg(tup->uport.dev, "Got frame errors\n");
457 		} else if (lsr & UART_LSR_BI) {
458 			/*
459 			 * Break error
460 			 * If FIFO read error without any data, reset Rx FIFO
461 			 */
462 			if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
463 				tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
464 			if (tup->uport.ignore_status_mask & UART_LSR_BI)
465 				return TTY_BREAK;
466 			flag = TTY_BREAK;
467 			tup->uport.icount.brk++;
468 			dev_dbg(tup->uport.dev, "Got Break\n");
469 		}
470 		uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
471 	}
472 
473 	return flag;
474 }
475 
476 static int tegra_uart_request_port(struct uart_port *u)
477 {
478 	return 0;
479 }
480 
481 static void tegra_uart_release_port(struct uart_port *u)
482 {
483 	/* Nothing to do here */
484 }
485 
486 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
487 {
488 	struct circ_buf *xmit = &tup->uport.state->xmit;
489 	int i;
490 
491 	for (i = 0; i < max_bytes; i++) {
492 		BUG_ON(uart_circ_empty(xmit));
493 		if (tup->cdata->tx_fifo_full_status) {
494 			unsigned long lsr = tegra_uart_read(tup, UART_LSR);
495 			if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
496 				break;
497 		}
498 		tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
499 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
500 		tup->uport.icount.tx++;
501 	}
502 }
503 
504 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
505 		unsigned int bytes)
506 {
507 	if (bytes > TEGRA_UART_MIN_DMA)
508 		bytes = TEGRA_UART_MIN_DMA;
509 
510 	tup->tx_in_progress = TEGRA_UART_TX_PIO;
511 	tup->tx_bytes = bytes;
512 	tup->ier_shadow |= UART_IER_THRI;
513 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
514 }
515 
516 static void tegra_uart_tx_dma_complete(void *args)
517 {
518 	struct tegra_uart_port *tup = args;
519 	struct circ_buf *xmit = &tup->uport.state->xmit;
520 	struct dma_tx_state state;
521 	unsigned long flags;
522 	unsigned int count;
523 
524 	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
525 	count = tup->tx_bytes_requested - state.residue;
526 	async_tx_ack(tup->tx_dma_desc);
527 	spin_lock_irqsave(&tup->uport.lock, flags);
528 	uart_xmit_advance(&tup->uport, count);
529 	tup->tx_in_progress = 0;
530 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
531 		uart_write_wakeup(&tup->uport);
532 	tegra_uart_start_next_tx(tup);
533 	spin_unlock_irqrestore(&tup->uport.lock, flags);
534 }
535 
536 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
537 		unsigned long count)
538 {
539 	struct circ_buf *xmit = &tup->uport.state->xmit;
540 	dma_addr_t tx_phys_addr;
541 
542 	tup->tx_bytes = count & ~(0xF);
543 	tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
544 
545 	dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
546 				   tup->tx_bytes, DMA_TO_DEVICE);
547 
548 	tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
549 				tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
550 				DMA_PREP_INTERRUPT);
551 	if (!tup->tx_dma_desc) {
552 		dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
553 		return -EIO;
554 	}
555 
556 	tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
557 	tup->tx_dma_desc->callback_param = tup;
558 	tup->tx_in_progress = TEGRA_UART_TX_DMA;
559 	tup->tx_bytes_requested = tup->tx_bytes;
560 	tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
561 	dma_async_issue_pending(tup->tx_dma_chan);
562 	return 0;
563 }
564 
565 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
566 {
567 	unsigned long tail;
568 	unsigned long count;
569 	struct circ_buf *xmit = &tup->uport.state->xmit;
570 
571 	if (!tup->current_baud)
572 		return;
573 
574 	tail = (unsigned long)&xmit->buf[xmit->tail];
575 	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
576 	if (!count)
577 		return;
578 
579 	if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
580 		tegra_uart_start_pio_tx(tup, count);
581 	else if (BYTES_TO_ALIGN(tail) > 0)
582 		tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
583 	else
584 		tegra_uart_start_tx_dma(tup, count);
585 }
586 
587 /* Called by serial core driver with u->lock taken. */
588 static void tegra_uart_start_tx(struct uart_port *u)
589 {
590 	struct tegra_uart_port *tup = to_tegra_uport(u);
591 	struct circ_buf *xmit = &u->state->xmit;
592 
593 	if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
594 		tegra_uart_start_next_tx(tup);
595 }
596 
597 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
598 {
599 	struct tegra_uart_port *tup = to_tegra_uport(u);
600 	unsigned int ret = 0;
601 	unsigned long flags;
602 
603 	spin_lock_irqsave(&u->lock, flags);
604 	if (!tup->tx_in_progress) {
605 		unsigned long lsr = tegra_uart_read(tup, UART_LSR);
606 		if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
607 			ret = TIOCSER_TEMT;
608 	}
609 	spin_unlock_irqrestore(&u->lock, flags);
610 	return ret;
611 }
612 
613 static void tegra_uart_stop_tx(struct uart_port *u)
614 {
615 	struct tegra_uart_port *tup = to_tegra_uport(u);
616 	struct dma_tx_state state;
617 	unsigned int count;
618 
619 	if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
620 		return;
621 
622 	dmaengine_terminate_all(tup->tx_dma_chan);
623 	dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
624 	count = tup->tx_bytes_requested - state.residue;
625 	async_tx_ack(tup->tx_dma_desc);
626 	uart_xmit_advance(&tup->uport, count);
627 	tup->tx_in_progress = 0;
628 }
629 
630 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
631 {
632 	struct circ_buf *xmit = &tup->uport.state->xmit;
633 
634 	tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
635 	tup->tx_in_progress = 0;
636 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
637 		uart_write_wakeup(&tup->uport);
638 	tegra_uart_start_next_tx(tup);
639 }
640 
641 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
642 		struct tty_port *port)
643 {
644 	do {
645 		char flag = TTY_NORMAL;
646 		unsigned long lsr = 0;
647 		unsigned char ch;
648 
649 		lsr = tegra_uart_read(tup, UART_LSR);
650 		if (!(lsr & UART_LSR_DR))
651 			break;
652 
653 		flag = tegra_uart_decode_rx_error(tup, lsr);
654 		if (flag != TTY_NORMAL)
655 			continue;
656 
657 		ch = (unsigned char) tegra_uart_read(tup, UART_RX);
658 		tup->uport.icount.rx++;
659 
660 		if (uart_handle_sysrq_char(&tup->uport, ch))
661 			continue;
662 
663 		if (tup->uport.ignore_status_mask & UART_LSR_DR)
664 			continue;
665 
666 		tty_insert_flip_char(port, ch, flag);
667 	} while (1);
668 }
669 
670 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
671 				      struct tty_port *port,
672 				      unsigned int count)
673 {
674 	int copied;
675 
676 	/* If count is zero, then there is no data to be copied */
677 	if (!count)
678 		return;
679 
680 	tup->uport.icount.rx += count;
681 
682 	if (tup->uport.ignore_status_mask & UART_LSR_DR)
683 		return;
684 
685 	dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
686 				count, DMA_FROM_DEVICE);
687 	copied = tty_insert_flip_string(port,
688 			((unsigned char *)(tup->rx_dma_buf_virt)), count);
689 	if (copied != count) {
690 		WARN_ON(1);
691 		dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
692 	}
693 	dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
694 				   count, DMA_TO_DEVICE);
695 }
696 
697 static void do_handle_rx_pio(struct tegra_uart_port *tup)
698 {
699 	struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
700 	struct tty_port *port = &tup->uport.state->port;
701 
702 	tegra_uart_handle_rx_pio(tup, port);
703 	if (tty) {
704 		tty_flip_buffer_push(port);
705 		tty_kref_put(tty);
706 	}
707 }
708 
709 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
710 				      unsigned int residue)
711 {
712 	struct tty_port *port = &tup->uport.state->port;
713 	unsigned int count;
714 
715 	async_tx_ack(tup->rx_dma_desc);
716 	count = tup->rx_bytes_requested - residue;
717 
718 	/* If we are here, DMA is stopped */
719 	tegra_uart_copy_rx_to_tty(tup, port, count);
720 
721 	do_handle_rx_pio(tup);
722 }
723 
724 static void tegra_uart_rx_dma_complete(void *args)
725 {
726 	struct tegra_uart_port *tup = args;
727 	struct uart_port *u = &tup->uport;
728 	unsigned long flags;
729 	struct dma_tx_state state;
730 	enum dma_status status;
731 
732 	spin_lock_irqsave(&u->lock, flags);
733 
734 	status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
735 
736 	if (status == DMA_IN_PROGRESS) {
737 		dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
738 		goto done;
739 	}
740 
741 	/* Deactivate flow control to stop sender */
742 	if (tup->rts_active)
743 		set_rts(tup, false);
744 
745 	tup->rx_dma_active = false;
746 	tegra_uart_rx_buffer_push(tup, 0);
747 	tegra_uart_start_rx_dma(tup);
748 
749 	/* Activate flow control to start transfer */
750 	if (tup->rts_active)
751 		set_rts(tup, true);
752 
753 done:
754 	spin_unlock_irqrestore(&u->lock, flags);
755 }
756 
757 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
758 {
759 	struct dma_tx_state state;
760 
761 	if (!tup->rx_dma_active) {
762 		do_handle_rx_pio(tup);
763 		return;
764 	}
765 
766 	dmaengine_terminate_all(tup->rx_dma_chan);
767 	dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
768 
769 	tegra_uart_rx_buffer_push(tup, state.residue);
770 	tup->rx_dma_active = false;
771 }
772 
773 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
774 {
775 	/* Deactivate flow control to stop sender */
776 	if (tup->rts_active)
777 		set_rts(tup, false);
778 
779 	tegra_uart_terminate_rx_dma(tup);
780 
781 	if (tup->rts_active)
782 		set_rts(tup, true);
783 }
784 
785 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
786 {
787 	unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
788 
789 	if (tup->rx_dma_active)
790 		return 0;
791 
792 	tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
793 				tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
794 				DMA_PREP_INTERRUPT);
795 	if (!tup->rx_dma_desc) {
796 		dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
797 		return -EIO;
798 	}
799 
800 	tup->rx_dma_active = true;
801 	tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
802 	tup->rx_dma_desc->callback_param = tup;
803 	tup->rx_bytes_requested = count;
804 	tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
805 	dma_async_issue_pending(tup->rx_dma_chan);
806 	return 0;
807 }
808 
809 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
810 {
811 	struct tegra_uart_port *tup = to_tegra_uport(u);
812 	unsigned long msr;
813 
814 	msr = tegra_uart_read(tup, UART_MSR);
815 	if (!(msr & UART_MSR_ANY_DELTA))
816 		return;
817 
818 	if (msr & UART_MSR_TERI)
819 		tup->uport.icount.rng++;
820 	if (msr & UART_MSR_DDSR)
821 		tup->uport.icount.dsr++;
822 	/* We may only get DDCD when HW init and reset */
823 	if (msr & UART_MSR_DDCD)
824 		uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
825 	/* Will start/stop_tx accordingly */
826 	if (msr & UART_MSR_DCTS)
827 		uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
828 }
829 
830 static irqreturn_t tegra_uart_isr(int irq, void *data)
831 {
832 	struct tegra_uart_port *tup = data;
833 	struct uart_port *u = &tup->uport;
834 	unsigned long iir;
835 	unsigned long ier;
836 	bool is_rx_start = false;
837 	bool is_rx_int = false;
838 	unsigned long flags;
839 
840 	spin_lock_irqsave(&u->lock, flags);
841 	while (1) {
842 		iir = tegra_uart_read(tup, UART_IIR);
843 		if (iir & UART_IIR_NO_INT) {
844 			if (!tup->use_rx_pio && is_rx_int) {
845 				tegra_uart_handle_rx_dma(tup);
846 				if (tup->rx_in_progress) {
847 					ier = tup->ier_shadow;
848 					ier |= (UART_IER_RLSI | UART_IER_RTOIE |
849 						TEGRA_UART_IER_EORD | UART_IER_RDI);
850 					tup->ier_shadow = ier;
851 					tegra_uart_write(tup, ier, UART_IER);
852 				}
853 			} else if (is_rx_start) {
854 				tegra_uart_start_rx_dma(tup);
855 			}
856 			spin_unlock_irqrestore(&u->lock, flags);
857 			return IRQ_HANDLED;
858 		}
859 
860 		switch ((iir >> 1) & 0x7) {
861 		case 0: /* Modem signal change interrupt */
862 			tegra_uart_handle_modem_signal_change(u);
863 			break;
864 
865 		case 1: /* Transmit interrupt only triggered when using PIO */
866 			tup->ier_shadow &= ~UART_IER_THRI;
867 			tegra_uart_write(tup, tup->ier_shadow, UART_IER);
868 			tegra_uart_handle_tx_pio(tup);
869 			break;
870 
871 		case 4: /* End of data */
872 		case 6: /* Rx timeout */
873 			if (!tup->use_rx_pio) {
874 				is_rx_int = tup->rx_in_progress;
875 				/* Disable Rx interrupts */
876 				ier = tup->ier_shadow;
877 				ier &= ~(UART_IER_RDI | UART_IER_RLSI |
878 					UART_IER_RTOIE | TEGRA_UART_IER_EORD);
879 				tup->ier_shadow = ier;
880 				tegra_uart_write(tup, ier, UART_IER);
881 				break;
882 			}
883 			fallthrough;
884 		case 2: /* Receive */
885 			if (!tup->use_rx_pio) {
886 				is_rx_start = tup->rx_in_progress;
887 				tup->ier_shadow  &= ~UART_IER_RDI;
888 				tegra_uart_write(tup, tup->ier_shadow,
889 						 UART_IER);
890 			} else {
891 				do_handle_rx_pio(tup);
892 			}
893 			break;
894 
895 		case 3: /* Receive error */
896 			tegra_uart_decode_rx_error(tup,
897 					tegra_uart_read(tup, UART_LSR));
898 			break;
899 
900 		case 5: /* break nothing to handle */
901 		case 7: /* break nothing to handle */
902 			break;
903 		}
904 	}
905 }
906 
907 static void tegra_uart_stop_rx(struct uart_port *u)
908 {
909 	struct tegra_uart_port *tup = to_tegra_uport(u);
910 	struct tty_port *port = &tup->uport.state->port;
911 	unsigned long ier;
912 
913 	if (tup->rts_active)
914 		set_rts(tup, false);
915 
916 	if (!tup->rx_in_progress)
917 		return;
918 
919 	tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
920 
921 	ier = tup->ier_shadow;
922 	ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
923 					TEGRA_UART_IER_EORD);
924 	tup->ier_shadow = ier;
925 	tegra_uart_write(tup, ier, UART_IER);
926 	tup->rx_in_progress = 0;
927 
928 	if (!tup->use_rx_pio)
929 		tegra_uart_terminate_rx_dma(tup);
930 	else
931 		tegra_uart_handle_rx_pio(tup, port);
932 }
933 
934 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
935 {
936 	unsigned long flags;
937 	unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
938 	unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
939 	unsigned long wait_time;
940 	unsigned long lsr;
941 	unsigned long msr;
942 	unsigned long mcr;
943 
944 	/* Disable interrupts */
945 	tegra_uart_write(tup, 0, UART_IER);
946 
947 	lsr = tegra_uart_read(tup, UART_LSR);
948 	if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
949 		msr = tegra_uart_read(tup, UART_MSR);
950 		mcr = tegra_uart_read(tup, UART_MCR);
951 		if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
952 			dev_err(tup->uport.dev,
953 				"Tx Fifo not empty, CTS disabled, waiting\n");
954 
955 		/* Wait for Tx fifo to be empty */
956 		while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
957 			wait_time = min(fifo_empty_time, 100lu);
958 			udelay(wait_time);
959 			fifo_empty_time -= wait_time;
960 			if (!fifo_empty_time) {
961 				msr = tegra_uart_read(tup, UART_MSR);
962 				mcr = tegra_uart_read(tup, UART_MCR);
963 				if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
964 					(msr & UART_MSR_CTS))
965 					dev_err(tup->uport.dev,
966 						"Slave not ready\n");
967 				break;
968 			}
969 			lsr = tegra_uart_read(tup, UART_LSR);
970 		}
971 	}
972 
973 	spin_lock_irqsave(&tup->uport.lock, flags);
974 	/* Reset the Rx and Tx FIFOs */
975 	tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
976 	tup->current_baud = 0;
977 	spin_unlock_irqrestore(&tup->uport.lock, flags);
978 
979 	tup->rx_in_progress = 0;
980 	tup->tx_in_progress = 0;
981 
982 	if (!tup->use_rx_pio)
983 		tegra_uart_dma_channel_free(tup, true);
984 	if (!tup->use_tx_pio)
985 		tegra_uart_dma_channel_free(tup, false);
986 
987 	clk_disable_unprepare(tup->uart_clk);
988 }
989 
990 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
991 {
992 	int ret;
993 
994 	tup->fcr_shadow = 0;
995 	tup->mcr_shadow = 0;
996 	tup->lcr_shadow = 0;
997 	tup->ier_shadow = 0;
998 	tup->current_baud = 0;
999 
1000 	clk_prepare_enable(tup->uart_clk);
1001 
1002 	/* Reset the UART controller to clear all previous status.*/
1003 	reset_control_assert(tup->rst);
1004 	udelay(10);
1005 	reset_control_deassert(tup->rst);
1006 
1007 	tup->rx_in_progress = 0;
1008 	tup->tx_in_progress = 0;
1009 
1010 	/*
1011 	 * Set the trigger level
1012 	 *
1013 	 * For PIO mode:
1014 	 *
1015 	 * For receive, this will interrupt the CPU after that many number of
1016 	 * bytes are received, for the remaining bytes the receive timeout
1017 	 * interrupt is received. Rx high watermark is set to 4.
1018 	 *
1019 	 * For transmit, if the trasnmit interrupt is enabled, this will
1020 	 * interrupt the CPU when the number of entries in the FIFO reaches the
1021 	 * low watermark. Tx low watermark is set to 16 bytes.
1022 	 *
1023 	 * For DMA mode:
1024 	 *
1025 	 * Set the Tx trigger to 16. This should match the DMA burst size that
1026 	 * programmed in the DMA registers.
1027 	 */
1028 	tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1029 
1030 	if (tup->use_rx_pio) {
1031 		tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1032 	} else {
1033 		if (tup->cdata->max_dma_burst_bytes == 8)
1034 			tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1035 		else
1036 			tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1037 	}
1038 
1039 	tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1040 	tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1041 
1042 	/* Dummy read to ensure the write is posted */
1043 	tegra_uart_read(tup, UART_SCR);
1044 
1045 	if (tup->cdata->fifo_mode_enable_status) {
1046 		ret = tegra_uart_wait_fifo_mode_enabled(tup);
1047 		if (ret < 0) {
1048 			dev_err(tup->uport.dev,
1049 				"Failed to enable FIFO mode: %d\n", ret);
1050 			return ret;
1051 		}
1052 	} else {
1053 		/*
1054 		 * For all tegra devices (up to t210), there is a hardware
1055 		 * issue that requires software to wait for 3 UART clock
1056 		 * periods after enabling the TX fifo, otherwise data could
1057 		 * be lost.
1058 		 */
1059 		tegra_uart_wait_cycle_time(tup, 3);
1060 	}
1061 
1062 	/*
1063 	 * Initialize the UART with default configuration
1064 	 * (115200, N, 8, 1) so that the receive DMA buffer may be
1065 	 * enqueued
1066 	 */
1067 	ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1068 	if (ret < 0) {
1069 		dev_err(tup->uport.dev, "Failed to set baud rate\n");
1070 		return ret;
1071 	}
1072 	if (!tup->use_rx_pio) {
1073 		tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1074 		tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1075 		tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1076 	} else {
1077 		tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1078 	}
1079 	tup->rx_in_progress = 1;
1080 
1081 	/*
1082 	 * Enable IE_RXS for the receive status interrupts like line errors.
1083 	 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1084 	 *
1085 	 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1086 	 * the DATA is sitting in the FIFO and couldn't be transferred to the
1087 	 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
1088 	 * triggered when there is a pause of the incomming data stream for 4
1089 	 * characters long.
1090 	 *
1091 	 * For pauses in the data which is not aligned to 4 bytes, we get
1092 	 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1093 	 * then the EORD.
1094 	 */
1095 	tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1096 
1097 	/*
1098 	 * If using DMA mode, enable EORD interrupt to notify about RX
1099 	 * completion.
1100 	 */
1101 	if (!tup->use_rx_pio)
1102 		tup->ier_shadow |= TEGRA_UART_IER_EORD;
1103 
1104 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1105 	return 0;
1106 }
1107 
1108 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1109 		bool dma_to_memory)
1110 {
1111 	if (dma_to_memory) {
1112 		dmaengine_terminate_all(tup->rx_dma_chan);
1113 		dma_release_channel(tup->rx_dma_chan);
1114 		dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1115 				tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1116 		tup->rx_dma_chan = NULL;
1117 		tup->rx_dma_buf_phys = 0;
1118 		tup->rx_dma_buf_virt = NULL;
1119 	} else {
1120 		dmaengine_terminate_all(tup->tx_dma_chan);
1121 		dma_release_channel(tup->tx_dma_chan);
1122 		dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1123 			UART_XMIT_SIZE, DMA_TO_DEVICE);
1124 		tup->tx_dma_chan = NULL;
1125 		tup->tx_dma_buf_phys = 0;
1126 		tup->tx_dma_buf_virt = NULL;
1127 	}
1128 }
1129 
1130 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1131 			bool dma_to_memory)
1132 {
1133 	struct dma_chan *dma_chan;
1134 	unsigned char *dma_buf;
1135 	dma_addr_t dma_phys;
1136 	int ret;
1137 	struct dma_slave_config dma_sconfig;
1138 
1139 	dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1140 	if (IS_ERR(dma_chan)) {
1141 		ret = PTR_ERR(dma_chan);
1142 		dev_err(tup->uport.dev,
1143 			"DMA channel alloc failed: %d\n", ret);
1144 		return ret;
1145 	}
1146 
1147 	if (dma_to_memory) {
1148 		dma_buf = dma_alloc_coherent(tup->uport.dev,
1149 				TEGRA_UART_RX_DMA_BUFFER_SIZE,
1150 				 &dma_phys, GFP_KERNEL);
1151 		if (!dma_buf) {
1152 			dev_err(tup->uport.dev,
1153 				"Not able to allocate the dma buffer\n");
1154 			dma_release_channel(dma_chan);
1155 			return -ENOMEM;
1156 		}
1157 		dma_sync_single_for_device(tup->uport.dev, dma_phys,
1158 					   TEGRA_UART_RX_DMA_BUFFER_SIZE,
1159 					   DMA_TO_DEVICE);
1160 		dma_sconfig.src_addr = tup->uport.mapbase;
1161 		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1162 		dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1163 		tup->rx_dma_chan = dma_chan;
1164 		tup->rx_dma_buf_virt = dma_buf;
1165 		tup->rx_dma_buf_phys = dma_phys;
1166 	} else {
1167 		dma_phys = dma_map_single(tup->uport.dev,
1168 			tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1169 			DMA_TO_DEVICE);
1170 		if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1171 			dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1172 			dma_release_channel(dma_chan);
1173 			return -ENOMEM;
1174 		}
1175 		dma_buf = tup->uport.state->xmit.buf;
1176 		dma_sconfig.dst_addr = tup->uport.mapbase;
1177 		dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1178 		dma_sconfig.dst_maxburst = 16;
1179 		tup->tx_dma_chan = dma_chan;
1180 		tup->tx_dma_buf_virt = dma_buf;
1181 		tup->tx_dma_buf_phys = dma_phys;
1182 	}
1183 
1184 	ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1185 	if (ret < 0) {
1186 		dev_err(tup->uport.dev,
1187 			"Dma slave config failed, err = %d\n", ret);
1188 		tegra_uart_dma_channel_free(tup, dma_to_memory);
1189 		return ret;
1190 	}
1191 
1192 	return 0;
1193 }
1194 
1195 static int tegra_uart_startup(struct uart_port *u)
1196 {
1197 	struct tegra_uart_port *tup = to_tegra_uport(u);
1198 	int ret;
1199 
1200 	if (!tup->use_tx_pio) {
1201 		ret = tegra_uart_dma_channel_allocate(tup, false);
1202 		if (ret < 0) {
1203 			dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1204 				ret);
1205 			return ret;
1206 		}
1207 	}
1208 
1209 	if (!tup->use_rx_pio) {
1210 		ret = tegra_uart_dma_channel_allocate(tup, true);
1211 		if (ret < 0) {
1212 			dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1213 				ret);
1214 			goto fail_rx_dma;
1215 		}
1216 	}
1217 
1218 	ret = tegra_uart_hw_init(tup);
1219 	if (ret < 0) {
1220 		dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1221 		goto fail_hw_init;
1222 	}
1223 
1224 	ret = request_irq(u->irq, tegra_uart_isr, 0,
1225 				dev_name(u->dev), tup);
1226 	if (ret < 0) {
1227 		dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1228 		goto fail_hw_init;
1229 	}
1230 	return 0;
1231 
1232 fail_hw_init:
1233 	if (!tup->use_rx_pio)
1234 		tegra_uart_dma_channel_free(tup, true);
1235 fail_rx_dma:
1236 	if (!tup->use_tx_pio)
1237 		tegra_uart_dma_channel_free(tup, false);
1238 	return ret;
1239 }
1240 
1241 /*
1242  * Flush any TX data submitted for DMA and PIO. Called when the
1243  * TX circular buffer is reset.
1244  */
1245 static void tegra_uart_flush_buffer(struct uart_port *u)
1246 {
1247 	struct tegra_uart_port *tup = to_tegra_uport(u);
1248 
1249 	tup->tx_bytes = 0;
1250 	if (tup->tx_dma_chan)
1251 		dmaengine_terminate_all(tup->tx_dma_chan);
1252 }
1253 
1254 static void tegra_uart_shutdown(struct uart_port *u)
1255 {
1256 	struct tegra_uart_port *tup = to_tegra_uport(u);
1257 
1258 	tegra_uart_hw_deinit(tup);
1259 	free_irq(u->irq, tup);
1260 }
1261 
1262 static void tegra_uart_enable_ms(struct uart_port *u)
1263 {
1264 	struct tegra_uart_port *tup = to_tegra_uport(u);
1265 
1266 	if (tup->enable_modem_interrupt) {
1267 		tup->ier_shadow |= UART_IER_MSI;
1268 		tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1269 	}
1270 }
1271 
1272 static void tegra_uart_set_termios(struct uart_port *u,
1273 				   struct ktermios *termios,
1274 				   const struct ktermios *oldtermios)
1275 {
1276 	struct tegra_uart_port *tup = to_tegra_uport(u);
1277 	unsigned int baud;
1278 	unsigned long flags;
1279 	unsigned int lcr;
1280 	unsigned char char_bits;
1281 	struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1282 	unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1283 	int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1284 	int ret;
1285 
1286 	max_divider *= 16;
1287 	spin_lock_irqsave(&u->lock, flags);
1288 
1289 	/* Changing configuration, it is safe to stop any rx now */
1290 	if (tup->rts_active)
1291 		set_rts(tup, false);
1292 
1293 	/* Clear all interrupts as configuration is going to be changed */
1294 	tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1295 	tegra_uart_read(tup, UART_IER);
1296 	tegra_uart_write(tup, 0, UART_IER);
1297 	tegra_uart_read(tup, UART_IER);
1298 
1299 	/* Parity */
1300 	lcr = tup->lcr_shadow;
1301 	lcr &= ~UART_LCR_PARITY;
1302 
1303 	/* CMSPAR isn't supported by this driver */
1304 	termios->c_cflag &= ~CMSPAR;
1305 
1306 	if ((termios->c_cflag & PARENB) == PARENB) {
1307 		if (termios->c_cflag & PARODD) {
1308 			lcr |= UART_LCR_PARITY;
1309 			lcr &= ~UART_LCR_EPAR;
1310 			lcr &= ~UART_LCR_SPAR;
1311 		} else {
1312 			lcr |= UART_LCR_PARITY;
1313 			lcr |= UART_LCR_EPAR;
1314 			lcr &= ~UART_LCR_SPAR;
1315 		}
1316 	}
1317 
1318 	char_bits = tty_get_char_size(termios->c_cflag);
1319 	lcr &= ~UART_LCR_WLEN8;
1320 	lcr |= UART_LCR_WLEN(char_bits);
1321 
1322 	/* Stop bits */
1323 	if (termios->c_cflag & CSTOPB)
1324 		lcr |= UART_LCR_STOP;
1325 	else
1326 		lcr &= ~UART_LCR_STOP;
1327 
1328 	tegra_uart_write(tup, lcr, UART_LCR);
1329 	tup->lcr_shadow = lcr;
1330 	tup->symb_bit = tty_get_frame_size(termios->c_cflag);
1331 
1332 	/* Baud rate. */
1333 	baud = uart_get_baud_rate(u, termios, oldtermios,
1334 			parent_clk_rate/max_divider,
1335 			parent_clk_rate/16);
1336 	spin_unlock_irqrestore(&u->lock, flags);
1337 	ret = tegra_set_baudrate(tup, baud);
1338 	if (ret < 0) {
1339 		dev_err(tup->uport.dev, "Failed to set baud rate\n");
1340 		return;
1341 	}
1342 	if (tty_termios_baud_rate(termios))
1343 		tty_termios_encode_baud_rate(termios, baud, baud);
1344 	spin_lock_irqsave(&u->lock, flags);
1345 
1346 	/* Flow control */
1347 	if (termios->c_cflag & CRTSCTS)	{
1348 		tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1349 		tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1350 		tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1351 		/* if top layer has asked to set rts active then do so here */
1352 		if (tup->rts_active)
1353 			set_rts(tup, true);
1354 	} else {
1355 		tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1356 		tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1357 		tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1358 	}
1359 
1360 	/* update the port timeout based on new settings */
1361 	uart_update_timeout(u, termios->c_cflag, baud);
1362 
1363 	/* Make sure all writes have completed */
1364 	tegra_uart_read(tup, UART_IER);
1365 
1366 	/* Re-enable interrupt */
1367 	tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1368 	tegra_uart_read(tup, UART_IER);
1369 
1370 	tup->uport.ignore_status_mask = 0;
1371 	/* Ignore all characters if CREAD is not set */
1372 	if ((termios->c_cflag & CREAD) == 0)
1373 		tup->uport.ignore_status_mask |= UART_LSR_DR;
1374 	if (termios->c_iflag & IGNBRK)
1375 		tup->uport.ignore_status_mask |= UART_LSR_BI;
1376 
1377 	spin_unlock_irqrestore(&u->lock, flags);
1378 }
1379 
1380 static const char *tegra_uart_type(struct uart_port *u)
1381 {
1382 	return TEGRA_UART_TYPE;
1383 }
1384 
1385 static const struct uart_ops tegra_uart_ops = {
1386 	.tx_empty	= tegra_uart_tx_empty,
1387 	.set_mctrl	= tegra_uart_set_mctrl,
1388 	.get_mctrl	= tegra_uart_get_mctrl,
1389 	.stop_tx	= tegra_uart_stop_tx,
1390 	.start_tx	= tegra_uart_start_tx,
1391 	.stop_rx	= tegra_uart_stop_rx,
1392 	.flush_buffer	= tegra_uart_flush_buffer,
1393 	.enable_ms	= tegra_uart_enable_ms,
1394 	.break_ctl	= tegra_uart_break_ctl,
1395 	.startup	= tegra_uart_startup,
1396 	.shutdown	= tegra_uart_shutdown,
1397 	.set_termios	= tegra_uart_set_termios,
1398 	.type		= tegra_uart_type,
1399 	.request_port	= tegra_uart_request_port,
1400 	.release_port	= tegra_uart_release_port,
1401 };
1402 
1403 static struct uart_driver tegra_uart_driver = {
1404 	.owner		= THIS_MODULE,
1405 	.driver_name	= "tegra_hsuart",
1406 	.dev_name	= "ttyTHS",
1407 	.cons		= NULL,
1408 	.nr		= TEGRA_UART_MAXIMUM,
1409 };
1410 
1411 static int tegra_uart_parse_dt(struct platform_device *pdev,
1412 	struct tegra_uart_port *tup)
1413 {
1414 	struct device_node *np = pdev->dev.of_node;
1415 	int port;
1416 	int ret;
1417 	int index;
1418 	u32 pval;
1419 	int count;
1420 	int n_entries;
1421 
1422 	port = of_alias_get_id(np, "serial");
1423 	if (port < 0) {
1424 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1425 		return port;
1426 	}
1427 	tup->uport.line = port;
1428 
1429 	tup->enable_modem_interrupt = of_property_read_bool(np,
1430 					"nvidia,enable-modem-interrupt");
1431 
1432 	index = of_property_match_string(np, "dma-names", "rx");
1433 	if (index < 0) {
1434 		tup->use_rx_pio = true;
1435 		dev_info(&pdev->dev, "RX in PIO mode\n");
1436 	}
1437 	index = of_property_match_string(np, "dma-names", "tx");
1438 	if (index < 0) {
1439 		tup->use_tx_pio = true;
1440 		dev_info(&pdev->dev, "TX in PIO mode\n");
1441 	}
1442 
1443 	n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1444 	if (n_entries > 0) {
1445 		tup->n_adjustable_baud_rates = n_entries / 3;
1446 		tup->baud_tolerance =
1447 		devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1448 			     sizeof(*tup->baud_tolerance), GFP_KERNEL);
1449 		if (!tup->baud_tolerance)
1450 			return -ENOMEM;
1451 		for (count = 0, index = 0; count < n_entries; count += 3,
1452 		     index++) {
1453 			ret =
1454 			of_property_read_u32_index(np,
1455 						   "nvidia,adjust-baud-rates",
1456 						   count, &pval);
1457 			if (!ret)
1458 				tup->baud_tolerance[index].lower_range_baud =
1459 				pval;
1460 			ret =
1461 			of_property_read_u32_index(np,
1462 						   "nvidia,adjust-baud-rates",
1463 						   count + 1, &pval);
1464 			if (!ret)
1465 				tup->baud_tolerance[index].upper_range_baud =
1466 				pval;
1467 			ret =
1468 			of_property_read_u32_index(np,
1469 						   "nvidia,adjust-baud-rates",
1470 						   count + 2, &pval);
1471 			if (!ret)
1472 				tup->baud_tolerance[index].tolerance =
1473 				(s32)pval;
1474 		}
1475 	} else {
1476 		tup->n_adjustable_baud_rates = 0;
1477 	}
1478 
1479 	return 0;
1480 }
1481 
1482 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1483 	.tx_fifo_full_status		= false,
1484 	.allow_txfifo_reset_fifo_mode	= true,
1485 	.support_clk_src_div		= false,
1486 	.fifo_mode_enable_status	= false,
1487 	.uart_max_port			= 5,
1488 	.max_dma_burst_bytes		= 4,
1489 	.error_tolerance_low_range	= -4,
1490 	.error_tolerance_high_range	= 4,
1491 };
1492 
1493 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1494 	.tx_fifo_full_status		= true,
1495 	.allow_txfifo_reset_fifo_mode	= false,
1496 	.support_clk_src_div		= true,
1497 	.fifo_mode_enable_status	= false,
1498 	.uart_max_port			= 5,
1499 	.max_dma_burst_bytes		= 4,
1500 	.error_tolerance_low_range	= -4,
1501 	.error_tolerance_high_range	= 4,
1502 };
1503 
1504 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1505 	.tx_fifo_full_status		= true,
1506 	.allow_txfifo_reset_fifo_mode	= false,
1507 	.support_clk_src_div		= true,
1508 	.fifo_mode_enable_status	= true,
1509 	.uart_max_port			= 8,
1510 	.max_dma_burst_bytes		= 8,
1511 	.error_tolerance_low_range	= 0,
1512 	.error_tolerance_high_range	= 4,
1513 };
1514 
1515 static struct tegra_uart_chip_data tegra194_uart_chip_data = {
1516 	.tx_fifo_full_status		= true,
1517 	.allow_txfifo_reset_fifo_mode	= false,
1518 	.support_clk_src_div		= true,
1519 	.fifo_mode_enable_status	= true,
1520 	.uart_max_port			= 8,
1521 	.max_dma_burst_bytes		= 8,
1522 	.error_tolerance_low_range	= -2,
1523 	.error_tolerance_high_range	= 2,
1524 };
1525 
1526 static const struct of_device_id tegra_uart_of_match[] = {
1527 	{
1528 		.compatible	= "nvidia,tegra30-hsuart",
1529 		.data		= &tegra30_uart_chip_data,
1530 	}, {
1531 		.compatible	= "nvidia,tegra20-hsuart",
1532 		.data		= &tegra20_uart_chip_data,
1533 	}, {
1534 		.compatible     = "nvidia,tegra186-hsuart",
1535 		.data		= &tegra186_uart_chip_data,
1536 	}, {
1537 		.compatible     = "nvidia,tegra194-hsuart",
1538 		.data		= &tegra194_uart_chip_data,
1539 	}, {
1540 	},
1541 };
1542 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1543 
1544 static int tegra_uart_probe(struct platform_device *pdev)
1545 {
1546 	struct tegra_uart_port *tup;
1547 	struct uart_port *u;
1548 	struct resource *resource;
1549 	int ret;
1550 	const struct tegra_uart_chip_data *cdata;
1551 
1552 	cdata = of_device_get_match_data(&pdev->dev);
1553 	if (!cdata) {
1554 		dev_err(&pdev->dev, "Error: No device match found\n");
1555 		return -ENODEV;
1556 	}
1557 
1558 	tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1559 	if (!tup) {
1560 		dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1561 		return -ENOMEM;
1562 	}
1563 
1564 	ret = tegra_uart_parse_dt(pdev, tup);
1565 	if (ret < 0)
1566 		return ret;
1567 
1568 	u = &tup->uport;
1569 	u->dev = &pdev->dev;
1570 	u->ops = &tegra_uart_ops;
1571 	u->type = PORT_TEGRA;
1572 	u->fifosize = 32;
1573 	tup->cdata = cdata;
1574 
1575 	platform_set_drvdata(pdev, tup);
1576 	resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1577 	if (!resource) {
1578 		dev_err(&pdev->dev, "No IO memory resource\n");
1579 		return -ENODEV;
1580 	}
1581 
1582 	u->mapbase = resource->start;
1583 	u->membase = devm_ioremap_resource(&pdev->dev, resource);
1584 	if (IS_ERR(u->membase))
1585 		return PTR_ERR(u->membase);
1586 
1587 	tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1588 	if (IS_ERR(tup->uart_clk)) {
1589 		dev_err(&pdev->dev, "Couldn't get the clock\n");
1590 		return PTR_ERR(tup->uart_clk);
1591 	}
1592 
1593 	tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1594 	if (IS_ERR(tup->rst)) {
1595 		dev_err(&pdev->dev, "Couldn't get the reset\n");
1596 		return PTR_ERR(tup->rst);
1597 	}
1598 
1599 	u->iotype = UPIO_MEM32;
1600 	ret = platform_get_irq(pdev, 0);
1601 	if (ret < 0)
1602 		return ret;
1603 	u->irq = ret;
1604 	u->regshift = 2;
1605 	ret = uart_add_one_port(&tegra_uart_driver, u);
1606 	if (ret < 0) {
1607 		dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1608 		return ret;
1609 	}
1610 	return ret;
1611 }
1612 
1613 static int tegra_uart_remove(struct platform_device *pdev)
1614 {
1615 	struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1616 	struct uart_port *u = &tup->uport;
1617 
1618 	uart_remove_one_port(&tegra_uart_driver, u);
1619 	return 0;
1620 }
1621 
1622 #ifdef CONFIG_PM_SLEEP
1623 static int tegra_uart_suspend(struct device *dev)
1624 {
1625 	struct tegra_uart_port *tup = dev_get_drvdata(dev);
1626 	struct uart_port *u = &tup->uport;
1627 
1628 	return uart_suspend_port(&tegra_uart_driver, u);
1629 }
1630 
1631 static int tegra_uart_resume(struct device *dev)
1632 {
1633 	struct tegra_uart_port *tup = dev_get_drvdata(dev);
1634 	struct uart_port *u = &tup->uport;
1635 
1636 	return uart_resume_port(&tegra_uart_driver, u);
1637 }
1638 #endif
1639 
1640 static const struct dev_pm_ops tegra_uart_pm_ops = {
1641 	SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1642 };
1643 
1644 static struct platform_driver tegra_uart_platform_driver = {
1645 	.probe		= tegra_uart_probe,
1646 	.remove		= tegra_uart_remove,
1647 	.driver		= {
1648 		.name	= "serial-tegra",
1649 		.of_match_table = tegra_uart_of_match,
1650 		.pm	= &tegra_uart_pm_ops,
1651 	},
1652 };
1653 
1654 static int __init tegra_uart_init(void)
1655 {
1656 	int ret;
1657 	struct device_node *node;
1658 	const struct of_device_id *match = NULL;
1659 	const struct tegra_uart_chip_data *cdata = NULL;
1660 
1661 	node = of_find_matching_node(NULL, tegra_uart_of_match);
1662 	if (node)
1663 		match = of_match_node(tegra_uart_of_match, node);
1664 	of_node_put(node);
1665 	if (match)
1666 		cdata = match->data;
1667 	if (cdata)
1668 		tegra_uart_driver.nr = cdata->uart_max_port;
1669 
1670 	ret = uart_register_driver(&tegra_uart_driver);
1671 	if (ret < 0) {
1672 		pr_err("Could not register %s driver\n",
1673 		       tegra_uart_driver.driver_name);
1674 		return ret;
1675 	}
1676 
1677 	ret = platform_driver_register(&tegra_uart_platform_driver);
1678 	if (ret < 0) {
1679 		pr_err("Uart platform driver register failed, e = %d\n", ret);
1680 		uart_unregister_driver(&tegra_uart_driver);
1681 		return ret;
1682 	}
1683 	return 0;
1684 }
1685 
1686 static void __exit tegra_uart_exit(void)
1687 {
1688 	pr_info("Unloading tegra uart driver\n");
1689 	platform_driver_unregister(&tegra_uart_platform_driver);
1690 	uart_unregister_driver(&tegra_uart_driver);
1691 }
1692 
1693 module_init(tegra_uart_init);
1694 module_exit(tegra_uart_exit);
1695 
1696 MODULE_ALIAS("platform:serial-tegra");
1697 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1698 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1699 MODULE_LICENSE("GPL v2");
1700