1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/console.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/io.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/platform_data/serial-sccnxp.h> 29 30 #define SCCNXP_NAME "uart-sccnxp" 31 #define SCCNXP_MAJOR 204 32 #define SCCNXP_MINOR 205 33 34 #define SCCNXP_MR_REG (0x00) 35 # define MR0_BAUD_NORMAL (0 << 0) 36 # define MR0_BAUD_EXT1 (1 << 0) 37 # define MR0_BAUD_EXT2 (5 << 0) 38 # define MR0_FIFO (1 << 3) 39 # define MR0_TXLVL (1 << 4) 40 # define MR1_BITS_5 (0 << 0) 41 # define MR1_BITS_6 (1 << 0) 42 # define MR1_BITS_7 (2 << 0) 43 # define MR1_BITS_8 (3 << 0) 44 # define MR1_PAR_EVN (0 << 2) 45 # define MR1_PAR_ODD (1 << 2) 46 # define MR1_PAR_NO (4 << 2) 47 # define MR2_STOP1 (7 << 0) 48 # define MR2_STOP2 (0xf << 0) 49 #define SCCNXP_SR_REG (0x01) 50 #define SCCNXP_CSR_REG SCCNXP_SR_REG 51 # define SR_RXRDY (1 << 0) 52 # define SR_FULL (1 << 1) 53 # define SR_TXRDY (1 << 2) 54 # define SR_TXEMT (1 << 3) 55 # define SR_OVR (1 << 4) 56 # define SR_PE (1 << 5) 57 # define SR_FE (1 << 6) 58 # define SR_BRK (1 << 7) 59 #define SCCNXP_CR_REG (0x02) 60 # define CR_RX_ENABLE (1 << 0) 61 # define CR_RX_DISABLE (1 << 1) 62 # define CR_TX_ENABLE (1 << 2) 63 # define CR_TX_DISABLE (1 << 3) 64 # define CR_CMD_MRPTR1 (0x01 << 4) 65 # define CR_CMD_RX_RESET (0x02 << 4) 66 # define CR_CMD_TX_RESET (0x03 << 4) 67 # define CR_CMD_STATUS_RESET (0x04 << 4) 68 # define CR_CMD_BREAK_RESET (0x05 << 4) 69 # define CR_CMD_START_BREAK (0x06 << 4) 70 # define CR_CMD_STOP_BREAK (0x07 << 4) 71 # define CR_CMD_MRPTR0 (0x0b << 4) 72 #define SCCNXP_RHR_REG (0x03) 73 #define SCCNXP_THR_REG SCCNXP_RHR_REG 74 #define SCCNXP_IPCR_REG (0x04) 75 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 76 # define ACR_BAUD0 (0 << 7) 77 # define ACR_BAUD1 (1 << 7) 78 # define ACR_TIMER_MODE (6 << 4) 79 #define SCCNXP_ISR_REG (0x05) 80 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 81 # define IMR_TXRDY (1 << 0) 82 # define IMR_RXRDY (1 << 1) 83 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 84 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 85 #define SCCNXP_IPR_REG (0x0d) 86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 87 #define SCCNXP_SOP_REG (0x0e) 88 #define SCCNXP_ROP_REG (0x0f) 89 90 /* Route helpers */ 91 #define MCTRL_MASK(sig) (0xf << (sig)) 92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 94 95 /* Supported chip types */ 96 enum { 97 SCCNXP_TYPE_SC2681 = 2681, 98 SCCNXP_TYPE_SC2691 = 2691, 99 SCCNXP_TYPE_SC2692 = 2692, 100 SCCNXP_TYPE_SC2891 = 2891, 101 SCCNXP_TYPE_SC2892 = 2892, 102 SCCNXP_TYPE_SC28202 = 28202, 103 SCCNXP_TYPE_SC68681 = 68681, 104 SCCNXP_TYPE_SC68692 = 68692, 105 }; 106 107 struct sccnxp_port { 108 struct uart_driver uart; 109 struct uart_port port[SCCNXP_MAX_UARTS]; 110 bool opened[SCCNXP_MAX_UARTS]; 111 112 const char *name; 113 int irq; 114 115 u8 imr; 116 u8 addr_mask; 117 int freq_std; 118 119 int flags; 120 #define SCCNXP_HAVE_IO 0x00000001 121 #define SCCNXP_HAVE_MR0 0x00000002 122 123 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 124 struct console console; 125 #endif 126 127 spinlock_t lock; 128 129 bool poll; 130 struct timer_list timer; 131 132 struct sccnxp_pdata pdata; 133 }; 134 135 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 136 { 137 return readb(base + (reg << shift)); 138 } 139 140 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 141 { 142 writeb(v, base + (reg << shift)); 143 } 144 145 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 146 { 147 struct sccnxp_port *s = dev_get_drvdata(port->dev); 148 149 return sccnxp_raw_read(port->membase, reg & s->addr_mask, 150 port->regshift); 151 } 152 153 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 154 { 155 struct sccnxp_port *s = dev_get_drvdata(port->dev); 156 157 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v); 158 } 159 160 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 161 { 162 return sccnxp_read(port, (port->line << 3) + reg); 163 } 164 165 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 166 { 167 sccnxp_write(port, (port->line << 3) + reg, v); 168 } 169 170 static int sccnxp_update_best_err(int a, int b, int *besterr) 171 { 172 int err = abs(a - b); 173 174 if ((*besterr < 0) || (*besterr > err)) { 175 *besterr = err; 176 return 0; 177 } 178 179 return 1; 180 } 181 182 struct baud_table { 183 u8 csr; 184 u8 acr; 185 u8 mr0; 186 int baud; 187 }; 188 189 const struct baud_table baud_std[] = { 190 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 191 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 192 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 193 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 194 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 195 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 196 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 197 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 198 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 199 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 200 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 201 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 202 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 203 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 204 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 205 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 206 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 207 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 208 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 209 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 210 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 211 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 212 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 213 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 214 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 215 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 216 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 217 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 218 { 0, 0, 0, 0 } 219 }; 220 221 static int sccnxp_set_baud(struct uart_port *port, int baud) 222 { 223 struct sccnxp_port *s = dev_get_drvdata(port->dev); 224 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 225 u8 i, acr = 0, csr = 0, mr0 = 0; 226 227 /* Find best baud from table */ 228 for (i = 0; baud_std[i].baud && besterr; i++) { 229 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 230 continue; 231 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 232 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 233 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 234 acr = baud_std[i].acr; 235 csr = baud_std[i].csr; 236 mr0 = baud_std[i].mr0; 237 bestbaud = tmp_baud; 238 } 239 } 240 241 if (s->flags & SCCNXP_HAVE_MR0) { 242 /* Enable FIFO, set half level for TX */ 243 mr0 |= MR0_FIFO | MR0_TXLVL; 244 /* Update MR0 */ 245 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 246 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 247 } 248 249 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 250 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 251 252 if (baud != bestbaud) 253 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 254 baud, bestbaud); 255 256 return bestbaud; 257 } 258 259 static void sccnxp_enable_irq(struct uart_port *port, int mask) 260 { 261 struct sccnxp_port *s = dev_get_drvdata(port->dev); 262 263 s->imr |= mask << (port->line * 4); 264 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 265 } 266 267 static void sccnxp_disable_irq(struct uart_port *port, int mask) 268 { 269 struct sccnxp_port *s = dev_get_drvdata(port->dev); 270 271 s->imr &= ~(mask << (port->line * 4)); 272 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 273 } 274 275 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 276 { 277 u8 bitmask; 278 struct sccnxp_port *s = dev_get_drvdata(port->dev); 279 280 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 281 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 282 if (state) 283 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 284 else 285 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 286 } 287 } 288 289 static void sccnxp_handle_rx(struct uart_port *port) 290 { 291 u8 sr; 292 unsigned int ch, flag; 293 294 for (;;) { 295 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 296 if (!(sr & SR_RXRDY)) 297 break; 298 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 299 300 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 301 302 port->icount.rx++; 303 flag = TTY_NORMAL; 304 305 if (unlikely(sr)) { 306 if (sr & SR_BRK) { 307 port->icount.brk++; 308 sccnxp_port_write(port, SCCNXP_CR_REG, 309 CR_CMD_BREAK_RESET); 310 if (uart_handle_break(port)) 311 continue; 312 } else if (sr & SR_PE) 313 port->icount.parity++; 314 else if (sr & SR_FE) 315 port->icount.frame++; 316 else if (sr & SR_OVR) { 317 port->icount.overrun++; 318 sccnxp_port_write(port, SCCNXP_CR_REG, 319 CR_CMD_STATUS_RESET); 320 } 321 322 sr &= port->read_status_mask; 323 if (sr & SR_BRK) 324 flag = TTY_BREAK; 325 else if (sr & SR_PE) 326 flag = TTY_PARITY; 327 else if (sr & SR_FE) 328 flag = TTY_FRAME; 329 else if (sr & SR_OVR) 330 flag = TTY_OVERRUN; 331 } 332 333 if (uart_handle_sysrq_char(port, ch)) 334 continue; 335 336 if (sr & port->ignore_status_mask) 337 continue; 338 339 uart_insert_char(port, sr, SR_OVR, ch, flag); 340 } 341 342 tty_flip_buffer_push(&port->state->port); 343 } 344 345 static void sccnxp_handle_tx(struct uart_port *port) 346 { 347 u8 sr; 348 struct circ_buf *xmit = &port->state->xmit; 349 struct sccnxp_port *s = dev_get_drvdata(port->dev); 350 351 if (unlikely(port->x_char)) { 352 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 353 port->icount.tx++; 354 port->x_char = 0; 355 return; 356 } 357 358 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 359 /* Disable TX if FIFO is empty */ 360 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 361 sccnxp_disable_irq(port, IMR_TXRDY); 362 363 /* Set direction to input */ 364 if (s->flags & SCCNXP_HAVE_IO) 365 sccnxp_set_bit(port, DIR_OP, 0); 366 } 367 return; 368 } 369 370 while (!uart_circ_empty(xmit)) { 371 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 372 if (!(sr & SR_TXRDY)) 373 break; 374 375 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 376 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 377 port->icount.tx++; 378 } 379 380 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 381 uart_write_wakeup(port); 382 } 383 384 static void sccnxp_handle_events(struct sccnxp_port *s) 385 { 386 int i; 387 u8 isr; 388 389 do { 390 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 391 isr &= s->imr; 392 if (!isr) 393 break; 394 395 for (i = 0; i < s->uart.nr; i++) { 396 if (s->opened[i] && (isr & ISR_RXRDY(i))) 397 sccnxp_handle_rx(&s->port[i]); 398 if (s->opened[i] && (isr & ISR_TXRDY(i))) 399 sccnxp_handle_tx(&s->port[i]); 400 } 401 } while (1); 402 } 403 404 static void sccnxp_timer(unsigned long data) 405 { 406 struct sccnxp_port *s = (struct sccnxp_port *)data; 407 unsigned long flags; 408 409 spin_lock_irqsave(&s->lock, flags); 410 sccnxp_handle_events(s); 411 spin_unlock_irqrestore(&s->lock, flags); 412 413 if (!timer_pending(&s->timer)) 414 mod_timer(&s->timer, jiffies + 415 usecs_to_jiffies(s->pdata.poll_time_us)); 416 } 417 418 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 419 { 420 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 421 unsigned long flags; 422 423 spin_lock_irqsave(&s->lock, flags); 424 sccnxp_handle_events(s); 425 spin_unlock_irqrestore(&s->lock, flags); 426 427 return IRQ_HANDLED; 428 } 429 430 static void sccnxp_start_tx(struct uart_port *port) 431 { 432 struct sccnxp_port *s = dev_get_drvdata(port->dev); 433 unsigned long flags; 434 435 spin_lock_irqsave(&s->lock, flags); 436 437 /* Set direction to output */ 438 if (s->flags & SCCNXP_HAVE_IO) 439 sccnxp_set_bit(port, DIR_OP, 1); 440 441 sccnxp_enable_irq(port, IMR_TXRDY); 442 443 spin_unlock_irqrestore(&s->lock, flags); 444 } 445 446 static void sccnxp_stop_tx(struct uart_port *port) 447 { 448 /* Do nothing */ 449 } 450 451 static void sccnxp_stop_rx(struct uart_port *port) 452 { 453 struct sccnxp_port *s = dev_get_drvdata(port->dev); 454 unsigned long flags; 455 456 spin_lock_irqsave(&s->lock, flags); 457 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 458 spin_unlock_irqrestore(&s->lock, flags); 459 } 460 461 static unsigned int sccnxp_tx_empty(struct uart_port *port) 462 { 463 u8 val; 464 unsigned long flags; 465 struct sccnxp_port *s = dev_get_drvdata(port->dev); 466 467 spin_lock_irqsave(&s->lock, flags); 468 val = sccnxp_port_read(port, SCCNXP_SR_REG); 469 spin_unlock_irqrestore(&s->lock, flags); 470 471 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 472 } 473 474 static void sccnxp_enable_ms(struct uart_port *port) 475 { 476 /* Do nothing */ 477 } 478 479 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 480 { 481 struct sccnxp_port *s = dev_get_drvdata(port->dev); 482 unsigned long flags; 483 484 if (!(s->flags & SCCNXP_HAVE_IO)) 485 return; 486 487 spin_lock_irqsave(&s->lock, flags); 488 489 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 490 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 491 492 spin_unlock_irqrestore(&s->lock, flags); 493 } 494 495 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 496 { 497 u8 bitmask, ipr; 498 unsigned long flags; 499 struct sccnxp_port *s = dev_get_drvdata(port->dev); 500 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 501 502 if (!(s->flags & SCCNXP_HAVE_IO)) 503 return mctrl; 504 505 spin_lock_irqsave(&s->lock, flags); 506 507 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 508 509 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 510 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 511 DSR_IP); 512 mctrl &= ~TIOCM_DSR; 513 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 514 } 515 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 516 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 517 CTS_IP); 518 mctrl &= ~TIOCM_CTS; 519 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 520 } 521 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 522 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 523 DCD_IP); 524 mctrl &= ~TIOCM_CAR; 525 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 526 } 527 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 528 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 529 RNG_IP); 530 mctrl &= ~TIOCM_RNG; 531 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 532 } 533 534 spin_unlock_irqrestore(&s->lock, flags); 535 536 return mctrl; 537 } 538 539 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 540 { 541 struct sccnxp_port *s = dev_get_drvdata(port->dev); 542 unsigned long flags; 543 544 spin_lock_irqsave(&s->lock, flags); 545 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 546 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 547 spin_unlock_irqrestore(&s->lock, flags); 548 } 549 550 static void sccnxp_set_termios(struct uart_port *port, 551 struct ktermios *termios, struct ktermios *old) 552 { 553 struct sccnxp_port *s = dev_get_drvdata(port->dev); 554 unsigned long flags; 555 u8 mr1, mr2; 556 int baud; 557 558 spin_lock_irqsave(&s->lock, flags); 559 560 /* Mask termios capabilities we don't support */ 561 termios->c_cflag &= ~CMSPAR; 562 563 /* Disable RX & TX, reset break condition, status and FIFOs */ 564 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 565 CR_RX_DISABLE | CR_TX_DISABLE); 566 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 567 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 568 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 569 570 /* Word size */ 571 switch (termios->c_cflag & CSIZE) { 572 case CS5: 573 mr1 = MR1_BITS_5; 574 break; 575 case CS6: 576 mr1 = MR1_BITS_6; 577 break; 578 case CS7: 579 mr1 = MR1_BITS_7; 580 break; 581 case CS8: 582 default: 583 mr1 = MR1_BITS_8; 584 break; 585 } 586 587 /* Parity */ 588 if (termios->c_cflag & PARENB) { 589 if (termios->c_cflag & PARODD) 590 mr1 |= MR1_PAR_ODD; 591 } else 592 mr1 |= MR1_PAR_NO; 593 594 /* Stop bits */ 595 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 596 597 /* Update desired format */ 598 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 599 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 600 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 601 602 /* Set read status mask */ 603 port->read_status_mask = SR_OVR; 604 if (termios->c_iflag & INPCK) 605 port->read_status_mask |= SR_PE | SR_FE; 606 if (termios->c_iflag & (BRKINT | PARMRK)) 607 port->read_status_mask |= SR_BRK; 608 609 /* Set status ignore mask */ 610 port->ignore_status_mask = 0; 611 if (termios->c_iflag & IGNBRK) 612 port->ignore_status_mask |= SR_BRK; 613 if (!(termios->c_cflag & CREAD)) 614 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 615 616 /* Setup baudrate */ 617 baud = uart_get_baud_rate(port, termios, old, 50, 618 (s->flags & SCCNXP_HAVE_MR0) ? 619 230400 : 38400); 620 baud = sccnxp_set_baud(port, baud); 621 622 /* Update timeout according to new baud rate */ 623 uart_update_timeout(port, termios->c_cflag, baud); 624 625 /* Report actual baudrate back to core */ 626 if (tty_termios_baud_rate(termios)) 627 tty_termios_encode_baud_rate(termios, baud, baud); 628 629 /* Enable RX & TX */ 630 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 631 632 spin_unlock_irqrestore(&s->lock, flags); 633 } 634 635 static int sccnxp_startup(struct uart_port *port) 636 { 637 struct sccnxp_port *s = dev_get_drvdata(port->dev); 638 unsigned long flags; 639 640 spin_lock_irqsave(&s->lock, flags); 641 642 if (s->flags & SCCNXP_HAVE_IO) { 643 /* Outputs are controlled manually */ 644 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 645 } 646 647 /* Reset break condition, status and FIFOs */ 648 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 649 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 650 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 651 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 652 653 /* Enable RX & TX */ 654 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 655 656 /* Enable RX interrupt */ 657 sccnxp_enable_irq(port, IMR_RXRDY); 658 659 s->opened[port->line] = 1; 660 661 spin_unlock_irqrestore(&s->lock, flags); 662 663 return 0; 664 } 665 666 static void sccnxp_shutdown(struct uart_port *port) 667 { 668 struct sccnxp_port *s = dev_get_drvdata(port->dev); 669 unsigned long flags; 670 671 spin_lock_irqsave(&s->lock, flags); 672 673 s->opened[port->line] = 0; 674 675 /* Disable interrupts */ 676 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 677 678 /* Disable TX & RX */ 679 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 680 681 /* Leave direction to input */ 682 if (s->flags & SCCNXP_HAVE_IO) 683 sccnxp_set_bit(port, DIR_OP, 0); 684 685 spin_unlock_irqrestore(&s->lock, flags); 686 } 687 688 static const char *sccnxp_type(struct uart_port *port) 689 { 690 struct sccnxp_port *s = dev_get_drvdata(port->dev); 691 692 return (port->type == PORT_SC26XX) ? s->name : NULL; 693 } 694 695 static void sccnxp_release_port(struct uart_port *port) 696 { 697 /* Do nothing */ 698 } 699 700 static int sccnxp_request_port(struct uart_port *port) 701 { 702 /* Do nothing */ 703 return 0; 704 } 705 706 static void sccnxp_config_port(struct uart_port *port, int flags) 707 { 708 if (flags & UART_CONFIG_TYPE) 709 port->type = PORT_SC26XX; 710 } 711 712 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 713 { 714 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 715 return 0; 716 if (s->irq == port->irq) 717 return 0; 718 719 return -EINVAL; 720 } 721 722 static const struct uart_ops sccnxp_ops = { 723 .tx_empty = sccnxp_tx_empty, 724 .set_mctrl = sccnxp_set_mctrl, 725 .get_mctrl = sccnxp_get_mctrl, 726 .stop_tx = sccnxp_stop_tx, 727 .start_tx = sccnxp_start_tx, 728 .stop_rx = sccnxp_stop_rx, 729 .enable_ms = sccnxp_enable_ms, 730 .break_ctl = sccnxp_break_ctl, 731 .startup = sccnxp_startup, 732 .shutdown = sccnxp_shutdown, 733 .set_termios = sccnxp_set_termios, 734 .type = sccnxp_type, 735 .release_port = sccnxp_release_port, 736 .request_port = sccnxp_request_port, 737 .config_port = sccnxp_config_port, 738 .verify_port = sccnxp_verify_port, 739 }; 740 741 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 742 static void sccnxp_console_putchar(struct uart_port *port, int c) 743 { 744 int tryes = 100000; 745 746 while (tryes--) { 747 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 748 sccnxp_port_write(port, SCCNXP_THR_REG, c); 749 break; 750 } 751 barrier(); 752 } 753 } 754 755 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 756 { 757 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 758 struct uart_port *port = &s->port[co->index]; 759 unsigned long flags; 760 761 spin_lock_irqsave(&s->lock, flags); 762 uart_console_write(port, c, n, sccnxp_console_putchar); 763 spin_unlock_irqrestore(&s->lock, flags); 764 } 765 766 static int sccnxp_console_setup(struct console *co, char *options) 767 { 768 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 769 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 770 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 771 772 if (options) 773 uart_parse_options(options, &baud, &parity, &bits, &flow); 774 775 return uart_set_options(port, co, baud, parity, bits, flow); 776 } 777 #endif 778 779 static int sccnxp_probe(struct platform_device *pdev) 780 { 781 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 782 int chiptype = pdev->id_entry->driver_data; 783 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 784 int i, ret, fifosize, freq_min, freq_max; 785 struct sccnxp_port *s; 786 void __iomem *membase; 787 788 if (!res) { 789 dev_err(&pdev->dev, "Missing memory resource data\n"); 790 return -EADDRNOTAVAIL; 791 } 792 793 dev_set_name(&pdev->dev, SCCNXP_NAME); 794 795 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 796 if (!s) { 797 dev_err(&pdev->dev, "Error allocating port structure\n"); 798 return -ENOMEM; 799 } 800 platform_set_drvdata(pdev, s); 801 802 spin_lock_init(&s->lock); 803 804 /* Individual chip settings */ 805 switch (chiptype) { 806 case SCCNXP_TYPE_SC2681: 807 s->name = "SC2681"; 808 s->uart.nr = 2; 809 s->freq_std = 3686400; 810 s->addr_mask = 0x0f; 811 s->flags = SCCNXP_HAVE_IO; 812 fifosize = 3; 813 freq_min = 1000000; 814 freq_max = 4000000; 815 break; 816 case SCCNXP_TYPE_SC2691: 817 s->name = "SC2691"; 818 s->uart.nr = 1; 819 s->freq_std = 3686400; 820 s->addr_mask = 0x07; 821 s->flags = 0; 822 fifosize = 3; 823 freq_min = 1000000; 824 freq_max = 4000000; 825 break; 826 case SCCNXP_TYPE_SC2692: 827 s->name = "SC2692"; 828 s->uart.nr = 2; 829 s->freq_std = 3686400; 830 s->addr_mask = 0x0f; 831 s->flags = SCCNXP_HAVE_IO; 832 fifosize = 3; 833 freq_min = 1000000; 834 freq_max = 4000000; 835 break; 836 case SCCNXP_TYPE_SC2891: 837 s->name = "SC2891"; 838 s->uart.nr = 1; 839 s->freq_std = 3686400; 840 s->addr_mask = 0x0f; 841 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 842 fifosize = 16; 843 freq_min = 100000; 844 freq_max = 8000000; 845 break; 846 case SCCNXP_TYPE_SC2892: 847 s->name = "SC2892"; 848 s->uart.nr = 2; 849 s->freq_std = 3686400; 850 s->addr_mask = 0x0f; 851 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 852 fifosize = 16; 853 freq_min = 100000; 854 freq_max = 8000000; 855 break; 856 case SCCNXP_TYPE_SC28202: 857 s->name = "SC28202"; 858 s->uart.nr = 2; 859 s->freq_std = 14745600; 860 s->addr_mask = 0x7f; 861 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 862 fifosize = 256; 863 freq_min = 1000000; 864 freq_max = 50000000; 865 break; 866 case SCCNXP_TYPE_SC68681: 867 s->name = "SC68681"; 868 s->uart.nr = 2; 869 s->freq_std = 3686400; 870 s->addr_mask = 0x0f; 871 s->flags = SCCNXP_HAVE_IO; 872 fifosize = 3; 873 freq_min = 1000000; 874 freq_max = 4000000; 875 break; 876 case SCCNXP_TYPE_SC68692: 877 s->name = "SC68692"; 878 s->uart.nr = 2; 879 s->freq_std = 3686400; 880 s->addr_mask = 0x0f; 881 s->flags = SCCNXP_HAVE_IO; 882 fifosize = 3; 883 freq_min = 1000000; 884 freq_max = 4000000; 885 break; 886 default: 887 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype); 888 ret = -ENOTSUPP; 889 goto err_out; 890 } 891 892 if (!pdata) { 893 dev_warn(&pdev->dev, 894 "No platform data supplied, using defaults\n"); 895 s->pdata.frequency = s->freq_std; 896 } else 897 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 898 899 if (s->pdata.poll_time_us) { 900 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 901 s->pdata.poll_time_us); 902 s->poll = 1; 903 } 904 905 if (!s->poll) { 906 s->irq = platform_get_irq(pdev, 0); 907 if (s->irq < 0) { 908 dev_err(&pdev->dev, "Missing irq resource data\n"); 909 ret = -ENXIO; 910 goto err_out; 911 } 912 } 913 914 /* Check input frequency */ 915 if ((s->pdata.frequency < freq_min) || 916 (s->pdata.frequency > freq_max)) { 917 dev_err(&pdev->dev, "Frequency out of bounds\n"); 918 ret = -EINVAL; 919 goto err_out; 920 } 921 922 membase = devm_request_and_ioremap(&pdev->dev, res); 923 if (!membase) { 924 dev_err(&pdev->dev, "Failed to ioremap\n"); 925 ret = -EIO; 926 goto err_out; 927 } 928 929 s->uart.owner = THIS_MODULE; 930 s->uart.dev_name = "ttySC"; 931 s->uart.major = SCCNXP_MAJOR; 932 s->uart.minor = SCCNXP_MINOR; 933 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 934 s->uart.cons = &s->console; 935 s->uart.cons->device = uart_console_device; 936 s->uart.cons->write = sccnxp_console_write; 937 s->uart.cons->setup = sccnxp_console_setup; 938 s->uart.cons->flags = CON_PRINTBUFFER; 939 s->uart.cons->index = -1; 940 s->uart.cons->data = s; 941 strcpy(s->uart.cons->name, "ttySC"); 942 #endif 943 ret = uart_register_driver(&s->uart); 944 if (ret) { 945 dev_err(&pdev->dev, "Registering UART driver failed\n"); 946 goto err_out; 947 } 948 949 for (i = 0; i < s->uart.nr; i++) { 950 s->port[i].line = i; 951 s->port[i].dev = &pdev->dev; 952 s->port[i].irq = s->irq; 953 s->port[i].type = PORT_SC26XX; 954 s->port[i].fifosize = fifosize; 955 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 956 s->port[i].iotype = UPIO_MEM; 957 s->port[i].mapbase = res->start; 958 s->port[i].membase = membase; 959 s->port[i].regshift = s->pdata.reg_shift; 960 s->port[i].uartclk = s->pdata.frequency; 961 s->port[i].ops = &sccnxp_ops; 962 uart_add_one_port(&s->uart, &s->port[i]); 963 /* Set direction to input */ 964 if (s->flags & SCCNXP_HAVE_IO) 965 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 966 } 967 968 /* Disable interrupts */ 969 s->imr = 0; 970 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 971 972 /* Board specific configure */ 973 if (s->pdata.init) 974 s->pdata.init(); 975 976 if (!s->poll) { 977 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 978 sccnxp_ist, 979 IRQF_TRIGGER_FALLING | 980 IRQF_ONESHOT, 981 dev_name(&pdev->dev), s); 982 if (!ret) 983 return 0; 984 985 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 986 } else { 987 init_timer(&s->timer); 988 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 989 mod_timer(&s->timer, jiffies + 990 usecs_to_jiffies(s->pdata.poll_time_us)); 991 return 0; 992 } 993 994 err_out: 995 platform_set_drvdata(pdev, NULL); 996 997 return ret; 998 } 999 1000 static int sccnxp_remove(struct platform_device *pdev) 1001 { 1002 int i; 1003 struct sccnxp_port *s = platform_get_drvdata(pdev); 1004 1005 if (!s->poll) 1006 devm_free_irq(&pdev->dev, s->irq, s); 1007 else 1008 del_timer_sync(&s->timer); 1009 1010 for (i = 0; i < s->uart.nr; i++) 1011 uart_remove_one_port(&s->uart, &s->port[i]); 1012 1013 uart_unregister_driver(&s->uart); 1014 platform_set_drvdata(pdev, NULL); 1015 1016 if (s->pdata.exit) 1017 s->pdata.exit(); 1018 1019 return 0; 1020 } 1021 1022 static const struct platform_device_id sccnxp_id_table[] = { 1023 { "sc2681", SCCNXP_TYPE_SC2681 }, 1024 { "sc2691", SCCNXP_TYPE_SC2691 }, 1025 { "sc2692", SCCNXP_TYPE_SC2692 }, 1026 { "sc2891", SCCNXP_TYPE_SC2891 }, 1027 { "sc2892", SCCNXP_TYPE_SC2892 }, 1028 { "sc28202", SCCNXP_TYPE_SC28202 }, 1029 { "sc68681", SCCNXP_TYPE_SC68681 }, 1030 { "sc68692", SCCNXP_TYPE_SC68692 }, 1031 { }, 1032 }; 1033 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 1034 1035 static struct platform_driver sccnxp_uart_driver = { 1036 .driver = { 1037 .name = SCCNXP_NAME, 1038 .owner = THIS_MODULE, 1039 }, 1040 .probe = sccnxp_probe, 1041 .remove = sccnxp_remove, 1042 .id_table = sccnxp_id_table, 1043 }; 1044 module_platform_driver(sccnxp_uart_driver); 1045 1046 MODULE_LICENSE("GPL v2"); 1047 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1048 MODULE_DESCRIPTION("SCCNXP serial driver"); 1049