1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/err.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/io.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/platform_device.h> 28 #include <linux/platform_data/sccnxp.h> 29 30 #define SCCNXP_NAME "uart-sccnxp" 31 #define SCCNXP_MAJOR 204 32 #define SCCNXP_MINOR 205 33 34 #define SCCNXP_MR_REG (0x00) 35 # define MR0_BAUD_NORMAL (0 << 0) 36 # define MR0_BAUD_EXT1 (1 << 0) 37 # define MR0_BAUD_EXT2 (5 << 0) 38 # define MR0_FIFO (1 << 3) 39 # define MR0_TXLVL (1 << 4) 40 # define MR1_BITS_5 (0 << 0) 41 # define MR1_BITS_6 (1 << 0) 42 # define MR1_BITS_7 (2 << 0) 43 # define MR1_BITS_8 (3 << 0) 44 # define MR1_PAR_EVN (0 << 2) 45 # define MR1_PAR_ODD (1 << 2) 46 # define MR1_PAR_NO (4 << 2) 47 # define MR2_STOP1 (7 << 0) 48 # define MR2_STOP2 (0xf << 0) 49 #define SCCNXP_SR_REG (0x01) 50 #define SCCNXP_CSR_REG SCCNXP_SR_REG 51 # define SR_RXRDY (1 << 0) 52 # define SR_FULL (1 << 1) 53 # define SR_TXRDY (1 << 2) 54 # define SR_TXEMT (1 << 3) 55 # define SR_OVR (1 << 4) 56 # define SR_PE (1 << 5) 57 # define SR_FE (1 << 6) 58 # define SR_BRK (1 << 7) 59 #define SCCNXP_CR_REG (0x02) 60 # define CR_RX_ENABLE (1 << 0) 61 # define CR_RX_DISABLE (1 << 1) 62 # define CR_TX_ENABLE (1 << 2) 63 # define CR_TX_DISABLE (1 << 3) 64 # define CR_CMD_MRPTR1 (0x01 << 4) 65 # define CR_CMD_RX_RESET (0x02 << 4) 66 # define CR_CMD_TX_RESET (0x03 << 4) 67 # define CR_CMD_STATUS_RESET (0x04 << 4) 68 # define CR_CMD_BREAK_RESET (0x05 << 4) 69 # define CR_CMD_START_BREAK (0x06 << 4) 70 # define CR_CMD_STOP_BREAK (0x07 << 4) 71 # define CR_CMD_MRPTR0 (0x0b << 4) 72 #define SCCNXP_RHR_REG (0x03) 73 #define SCCNXP_THR_REG SCCNXP_RHR_REG 74 #define SCCNXP_IPCR_REG (0x04) 75 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 76 # define ACR_BAUD0 (0 << 7) 77 # define ACR_BAUD1 (1 << 7) 78 # define ACR_TIMER_MODE (6 << 4) 79 #define SCCNXP_ISR_REG (0x05) 80 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 81 # define IMR_TXRDY (1 << 0) 82 # define IMR_RXRDY (1 << 1) 83 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 84 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 85 #define SCCNXP_IPR_REG (0x0d) 86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 87 #define SCCNXP_SOP_REG (0x0e) 88 #define SCCNXP_ROP_REG (0x0f) 89 90 /* Route helpers */ 91 #define MCTRL_MASK(sig) (0xf << (sig)) 92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 94 95 /* Supported chip types */ 96 enum { 97 SCCNXP_TYPE_SC2681 = 2681, 98 SCCNXP_TYPE_SC2691 = 2691, 99 SCCNXP_TYPE_SC2692 = 2692, 100 SCCNXP_TYPE_SC2891 = 2891, 101 SCCNXP_TYPE_SC2892 = 2892, 102 SCCNXP_TYPE_SC28202 = 28202, 103 SCCNXP_TYPE_SC68681 = 68681, 104 SCCNXP_TYPE_SC68692 = 68692, 105 }; 106 107 struct sccnxp_port { 108 struct uart_driver uart; 109 struct uart_port port[SCCNXP_MAX_UARTS]; 110 111 const char *name; 112 int irq; 113 114 u8 imr; 115 u8 addr_mask; 116 int freq_std; 117 118 int flags; 119 #define SCCNXP_HAVE_IO 0x00000001 120 #define SCCNXP_HAVE_MR0 0x00000002 121 122 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 123 struct console console; 124 #endif 125 126 struct mutex sccnxp_mutex; 127 128 struct sccnxp_pdata pdata; 129 }; 130 131 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 132 { 133 return readb(base + (reg << shift)); 134 } 135 136 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 137 { 138 writeb(v, base + (reg << shift)); 139 } 140 141 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 142 { 143 struct sccnxp_port *s = dev_get_drvdata(port->dev); 144 145 return sccnxp_raw_read(port->membase, reg & s->addr_mask, 146 port->regshift); 147 } 148 149 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 150 { 151 struct sccnxp_port *s = dev_get_drvdata(port->dev); 152 153 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v); 154 } 155 156 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 157 { 158 return sccnxp_read(port, (port->line << 3) + reg); 159 } 160 161 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 162 { 163 sccnxp_write(port, (port->line << 3) + reg, v); 164 } 165 166 static int sccnxp_update_best_err(int a, int b, int *besterr) 167 { 168 int err = abs(a - b); 169 170 if ((*besterr < 0) || (*besterr > err)) { 171 *besterr = err; 172 return 0; 173 } 174 175 return 1; 176 } 177 178 struct baud_table { 179 u8 csr; 180 u8 acr; 181 u8 mr0; 182 int baud; 183 }; 184 185 const struct baud_table baud_std[] = { 186 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 187 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 188 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 189 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 190 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 191 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 192 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 193 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 194 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 195 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 196 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 197 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 198 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 199 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 200 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 201 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 202 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 203 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 204 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 205 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 206 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 207 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 208 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 209 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 210 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 211 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 212 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 213 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 214 { 0, 0, 0, 0 } 215 }; 216 217 static int sccnxp_set_baud(struct uart_port *port, int baud) 218 { 219 struct sccnxp_port *s = dev_get_drvdata(port->dev); 220 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 221 u8 i, acr = 0, csr = 0, mr0 = 0; 222 223 /* Find best baud from table */ 224 for (i = 0; baud_std[i].baud && besterr; i++) { 225 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 226 continue; 227 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 228 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 229 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 230 acr = baud_std[i].acr; 231 csr = baud_std[i].csr; 232 mr0 = baud_std[i].mr0; 233 bestbaud = tmp_baud; 234 } 235 } 236 237 if (s->flags & SCCNXP_HAVE_MR0) { 238 /* Enable FIFO, set half level for TX */ 239 mr0 |= MR0_FIFO | MR0_TXLVL; 240 /* Update MR0 */ 241 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 242 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 243 } 244 245 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 246 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 247 248 if (baud != bestbaud) 249 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 250 baud, bestbaud); 251 252 return bestbaud; 253 } 254 255 static void sccnxp_enable_irq(struct uart_port *port, int mask) 256 { 257 struct sccnxp_port *s = dev_get_drvdata(port->dev); 258 259 s->imr |= mask << (port->line * 4); 260 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 261 } 262 263 static void sccnxp_disable_irq(struct uart_port *port, int mask) 264 { 265 struct sccnxp_port *s = dev_get_drvdata(port->dev); 266 267 s->imr &= ~(mask << (port->line * 4)); 268 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 269 } 270 271 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 272 { 273 u8 bitmask; 274 struct sccnxp_port *s = dev_get_drvdata(port->dev); 275 276 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 277 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 278 if (state) 279 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 280 else 281 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 282 } 283 } 284 285 static void sccnxp_handle_rx(struct uart_port *port) 286 { 287 u8 sr; 288 unsigned int ch, flag; 289 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 290 291 if (!tty) 292 return; 293 294 for (;;) { 295 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 296 if (!(sr & SR_RXRDY)) 297 break; 298 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 299 300 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 301 302 port->icount.rx++; 303 flag = TTY_NORMAL; 304 305 if (unlikely(sr)) { 306 if (sr & SR_BRK) { 307 port->icount.brk++; 308 if (uart_handle_break(port)) 309 continue; 310 } else if (sr & SR_PE) 311 port->icount.parity++; 312 else if (sr & SR_FE) 313 port->icount.frame++; 314 else if (sr & SR_OVR) 315 port->icount.overrun++; 316 317 sr &= port->read_status_mask; 318 if (sr & SR_BRK) 319 flag = TTY_BREAK; 320 else if (sr & SR_PE) 321 flag = TTY_PARITY; 322 else if (sr & SR_FE) 323 flag = TTY_FRAME; 324 else if (sr & SR_OVR) 325 flag = TTY_OVERRUN; 326 } 327 328 if (uart_handle_sysrq_char(port, ch)) 329 continue; 330 331 if (sr & port->ignore_status_mask) 332 continue; 333 334 uart_insert_char(port, sr, SR_OVR, ch, flag); 335 } 336 337 tty_flip_buffer_push(tty); 338 339 tty_kref_put(tty); 340 } 341 342 static void sccnxp_handle_tx(struct uart_port *port) 343 { 344 u8 sr; 345 struct circ_buf *xmit = &port->state->xmit; 346 struct sccnxp_port *s = dev_get_drvdata(port->dev); 347 348 if (unlikely(port->x_char)) { 349 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 350 port->icount.tx++; 351 port->x_char = 0; 352 return; 353 } 354 355 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 356 /* Disable TX if FIFO is empty */ 357 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 358 sccnxp_disable_irq(port, IMR_TXRDY); 359 360 /* Set direction to input */ 361 if (s->flags & SCCNXP_HAVE_IO) 362 sccnxp_set_bit(port, DIR_OP, 0); 363 } 364 return; 365 } 366 367 while (!uart_circ_empty(xmit)) { 368 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 369 if (!(sr & SR_TXRDY)) 370 break; 371 372 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 373 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 374 port->icount.tx++; 375 } 376 377 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 378 uart_write_wakeup(port); 379 } 380 381 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 382 { 383 int i; 384 u8 isr; 385 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 386 387 mutex_lock(&s->sccnxp_mutex); 388 389 for (;;) { 390 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 391 isr &= s->imr; 392 if (!isr) 393 break; 394 395 dev_dbg(s->port[0].dev, "IRQ status: 0x%02x\n", isr); 396 397 for (i = 0; i < s->uart.nr; i++) { 398 if (isr & ISR_RXRDY(i)) 399 sccnxp_handle_rx(&s->port[i]); 400 if (isr & ISR_TXRDY(i)) 401 sccnxp_handle_tx(&s->port[i]); 402 } 403 } 404 405 mutex_unlock(&s->sccnxp_mutex); 406 407 return IRQ_HANDLED; 408 } 409 410 static void sccnxp_start_tx(struct uart_port *port) 411 { 412 struct sccnxp_port *s = dev_get_drvdata(port->dev); 413 414 mutex_lock(&s->sccnxp_mutex); 415 416 /* Set direction to output */ 417 if (s->flags & SCCNXP_HAVE_IO) 418 sccnxp_set_bit(port, DIR_OP, 1); 419 420 sccnxp_enable_irq(port, IMR_TXRDY); 421 422 mutex_unlock(&s->sccnxp_mutex); 423 } 424 425 static void sccnxp_stop_tx(struct uart_port *port) 426 { 427 /* Do nothing */ 428 } 429 430 static void sccnxp_stop_rx(struct uart_port *port) 431 { 432 struct sccnxp_port *s = dev_get_drvdata(port->dev); 433 434 mutex_lock(&s->sccnxp_mutex); 435 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 436 mutex_unlock(&s->sccnxp_mutex); 437 } 438 439 static unsigned int sccnxp_tx_empty(struct uart_port *port) 440 { 441 u8 val; 442 struct sccnxp_port *s = dev_get_drvdata(port->dev); 443 444 mutex_lock(&s->sccnxp_mutex); 445 val = sccnxp_port_read(port, SCCNXP_SR_REG); 446 mutex_unlock(&s->sccnxp_mutex); 447 448 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 449 } 450 451 static void sccnxp_enable_ms(struct uart_port *port) 452 { 453 /* Do nothing */ 454 } 455 456 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 457 { 458 struct sccnxp_port *s = dev_get_drvdata(port->dev); 459 460 if (!(s->flags & SCCNXP_HAVE_IO)) 461 return; 462 463 mutex_lock(&s->sccnxp_mutex); 464 465 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 466 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 467 468 mutex_unlock(&s->sccnxp_mutex); 469 } 470 471 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 472 { 473 u8 bitmask, ipr; 474 struct sccnxp_port *s = dev_get_drvdata(port->dev); 475 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 476 477 if (!(s->flags & SCCNXP_HAVE_IO)) 478 return mctrl; 479 480 mutex_lock(&s->sccnxp_mutex); 481 482 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 483 484 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 485 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 486 DSR_IP); 487 mctrl &= ~TIOCM_DSR; 488 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 489 } 490 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 491 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 492 CTS_IP); 493 mctrl &= ~TIOCM_CTS; 494 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 495 } 496 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 497 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 498 DCD_IP); 499 mctrl &= ~TIOCM_CAR; 500 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 501 } 502 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 503 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 504 RNG_IP); 505 mctrl &= ~TIOCM_RNG; 506 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 507 } 508 509 mutex_unlock(&s->sccnxp_mutex); 510 511 return mctrl; 512 } 513 514 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 515 { 516 struct sccnxp_port *s = dev_get_drvdata(port->dev); 517 518 mutex_lock(&s->sccnxp_mutex); 519 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 520 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 521 mutex_unlock(&s->sccnxp_mutex); 522 } 523 524 static void sccnxp_set_termios(struct uart_port *port, 525 struct ktermios *termios, struct ktermios *old) 526 { 527 struct sccnxp_port *s = dev_get_drvdata(port->dev); 528 u8 mr1, mr2; 529 int baud; 530 531 mutex_lock(&s->sccnxp_mutex); 532 533 /* Mask termios capabilities we don't support */ 534 termios->c_cflag &= ~CMSPAR; 535 536 /* Disable RX & TX, reset break condition, status and FIFOs */ 537 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 538 CR_RX_DISABLE | CR_TX_DISABLE); 539 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 540 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 541 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 542 543 /* Word size */ 544 switch (termios->c_cflag & CSIZE) { 545 case CS5: 546 mr1 = MR1_BITS_5; 547 break; 548 case CS6: 549 mr1 = MR1_BITS_6; 550 break; 551 case CS7: 552 mr1 = MR1_BITS_7; 553 break; 554 case CS8: 555 default: 556 mr1 = MR1_BITS_8; 557 break; 558 } 559 560 /* Parity */ 561 if (termios->c_cflag & PARENB) { 562 if (termios->c_cflag & PARODD) 563 mr1 |= MR1_PAR_ODD; 564 } else 565 mr1 |= MR1_PAR_NO; 566 567 /* Stop bits */ 568 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 569 570 /* Update desired format */ 571 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 572 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 573 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 574 575 /* Set read status mask */ 576 port->read_status_mask = SR_OVR; 577 if (termios->c_iflag & INPCK) 578 port->read_status_mask |= SR_PE | SR_FE; 579 if (termios->c_iflag & (BRKINT | PARMRK)) 580 port->read_status_mask |= SR_BRK; 581 582 /* Set status ignore mask */ 583 port->ignore_status_mask = 0; 584 if (termios->c_iflag & IGNBRK) 585 port->ignore_status_mask |= SR_BRK; 586 if (!(termios->c_cflag & CREAD)) 587 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 588 589 /* Setup baudrate */ 590 baud = uart_get_baud_rate(port, termios, old, 50, 591 (s->flags & SCCNXP_HAVE_MR0) ? 592 230400 : 38400); 593 baud = sccnxp_set_baud(port, baud); 594 595 /* Update timeout according to new baud rate */ 596 uart_update_timeout(port, termios->c_cflag, baud); 597 598 if (tty_termios_baud_rate(termios)) 599 tty_termios_encode_baud_rate(termios, baud, baud); 600 601 /* Enable RX & TX */ 602 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 603 604 mutex_unlock(&s->sccnxp_mutex); 605 } 606 607 static int sccnxp_startup(struct uart_port *port) 608 { 609 struct sccnxp_port *s = dev_get_drvdata(port->dev); 610 611 mutex_lock(&s->sccnxp_mutex); 612 613 if (s->flags & SCCNXP_HAVE_IO) { 614 /* Outputs are controlled manually */ 615 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 616 } 617 618 /* Reset break condition, status and FIFOs */ 619 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 620 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 622 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 623 624 /* Enable RX & TX */ 625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 626 627 /* Enable RX interrupt */ 628 sccnxp_enable_irq(port, IMR_RXRDY); 629 630 mutex_unlock(&s->sccnxp_mutex); 631 632 return 0; 633 } 634 635 static void sccnxp_shutdown(struct uart_port *port) 636 { 637 struct sccnxp_port *s = dev_get_drvdata(port->dev); 638 639 mutex_lock(&s->sccnxp_mutex); 640 641 /* Disable interrupts */ 642 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 643 644 /* Disable TX & RX */ 645 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 646 647 /* Leave direction to input */ 648 if (s->flags & SCCNXP_HAVE_IO) 649 sccnxp_set_bit(port, DIR_OP, 0); 650 651 mutex_unlock(&s->sccnxp_mutex); 652 } 653 654 static const char *sccnxp_type(struct uart_port *port) 655 { 656 struct sccnxp_port *s = dev_get_drvdata(port->dev); 657 658 return (port->type == PORT_SC26XX) ? s->name : NULL; 659 } 660 661 static void sccnxp_release_port(struct uart_port *port) 662 { 663 /* Do nothing */ 664 } 665 666 static int sccnxp_request_port(struct uart_port *port) 667 { 668 /* Do nothing */ 669 return 0; 670 } 671 672 static void sccnxp_config_port(struct uart_port *port, int flags) 673 { 674 if (flags & UART_CONFIG_TYPE) 675 port->type = PORT_SC26XX; 676 } 677 678 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 679 { 680 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 681 return 0; 682 if (s->irq == port->irq) 683 return 0; 684 685 return -EINVAL; 686 } 687 688 static const struct uart_ops sccnxp_ops = { 689 .tx_empty = sccnxp_tx_empty, 690 .set_mctrl = sccnxp_set_mctrl, 691 .get_mctrl = sccnxp_get_mctrl, 692 .stop_tx = sccnxp_stop_tx, 693 .start_tx = sccnxp_start_tx, 694 .stop_rx = sccnxp_stop_rx, 695 .enable_ms = sccnxp_enable_ms, 696 .break_ctl = sccnxp_break_ctl, 697 .startup = sccnxp_startup, 698 .shutdown = sccnxp_shutdown, 699 .set_termios = sccnxp_set_termios, 700 .type = sccnxp_type, 701 .release_port = sccnxp_release_port, 702 .request_port = sccnxp_request_port, 703 .config_port = sccnxp_config_port, 704 .verify_port = sccnxp_verify_port, 705 }; 706 707 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 708 static void sccnxp_console_putchar(struct uart_port *port, int c) 709 { 710 int tryes = 100000; 711 712 while (tryes--) { 713 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 714 sccnxp_port_write(port, SCCNXP_THR_REG, c); 715 break; 716 } 717 barrier(); 718 } 719 } 720 721 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 722 { 723 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 724 struct uart_port *port = &s->port[co->index]; 725 726 mutex_lock(&s->sccnxp_mutex); 727 uart_console_write(port, c, n, sccnxp_console_putchar); 728 mutex_unlock(&s->sccnxp_mutex); 729 } 730 731 static int sccnxp_console_setup(struct console *co, char *options) 732 { 733 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 734 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 735 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 736 737 if (options) 738 uart_parse_options(options, &baud, &parity, &bits, &flow); 739 740 return uart_set_options(port, co, baud, parity, bits, flow); 741 } 742 #endif 743 744 static int sccnxp_probe(struct platform_device *pdev) 745 { 746 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 747 int chiptype = pdev->id_entry->driver_data; 748 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 749 int i, ret, fifosize, freq_min, freq_max; 750 struct sccnxp_port *s; 751 void __iomem *membase; 752 753 if (!res) { 754 dev_err(&pdev->dev, "Missing memory resource data\n"); 755 return -EADDRNOTAVAIL; 756 } 757 758 dev_set_name(&pdev->dev, SCCNXP_NAME); 759 760 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 761 if (!s) { 762 dev_err(&pdev->dev, "Error allocating port structure\n"); 763 return -ENOMEM; 764 } 765 platform_set_drvdata(pdev, s); 766 767 mutex_init(&s->sccnxp_mutex); 768 769 /* Individual chip settings */ 770 switch (chiptype) { 771 case SCCNXP_TYPE_SC2681: 772 s->name = "SC2681"; 773 s->uart.nr = 2; 774 s->freq_std = 3686400; 775 s->addr_mask = 0x0f; 776 s->flags = SCCNXP_HAVE_IO; 777 fifosize = 3; 778 freq_min = 1000000; 779 freq_max = 4000000; 780 break; 781 case SCCNXP_TYPE_SC2691: 782 s->name = "SC2691"; 783 s->uart.nr = 1; 784 s->freq_std = 3686400; 785 s->addr_mask = 0x07; 786 s->flags = 0; 787 fifosize = 3; 788 freq_min = 1000000; 789 freq_max = 4000000; 790 break; 791 case SCCNXP_TYPE_SC2692: 792 s->name = "SC2692"; 793 s->uart.nr = 2; 794 s->freq_std = 3686400; 795 s->addr_mask = 0x0f; 796 s->flags = SCCNXP_HAVE_IO; 797 fifosize = 3; 798 freq_min = 1000000; 799 freq_max = 4000000; 800 break; 801 case SCCNXP_TYPE_SC2891: 802 s->name = "SC2891"; 803 s->uart.nr = 1; 804 s->freq_std = 3686400; 805 s->addr_mask = 0x0f; 806 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 807 fifosize = 16; 808 freq_min = 100000; 809 freq_max = 8000000; 810 break; 811 case SCCNXP_TYPE_SC2892: 812 s->name = "SC2892"; 813 s->uart.nr = 2; 814 s->freq_std = 3686400; 815 s->addr_mask = 0x0f; 816 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 817 fifosize = 16; 818 freq_min = 100000; 819 freq_max = 8000000; 820 break; 821 case SCCNXP_TYPE_SC28202: 822 s->name = "SC28202"; 823 s->uart.nr = 2; 824 s->freq_std = 14745600; 825 s->addr_mask = 0x7f; 826 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 827 fifosize = 256; 828 freq_min = 1000000; 829 freq_max = 50000000; 830 break; 831 case SCCNXP_TYPE_SC68681: 832 s->name = "SC68681"; 833 s->uart.nr = 2; 834 s->freq_std = 3686400; 835 s->addr_mask = 0x0f; 836 s->flags = SCCNXP_HAVE_IO; 837 fifosize = 3; 838 freq_min = 1000000; 839 freq_max = 4000000; 840 break; 841 case SCCNXP_TYPE_SC68692: 842 s->name = "SC68692"; 843 s->uart.nr = 2; 844 s->freq_std = 3686400; 845 s->addr_mask = 0x0f; 846 s->flags = SCCNXP_HAVE_IO; 847 fifosize = 3; 848 freq_min = 1000000; 849 freq_max = 4000000; 850 break; 851 default: 852 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype); 853 ret = -ENOTSUPP; 854 goto err_out; 855 } 856 857 if (!pdata) { 858 dev_warn(&pdev->dev, 859 "No platform data supplied, using defaults\n"); 860 s->pdata.frequency = s->freq_std; 861 } else 862 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 863 864 s->irq = platform_get_irq(pdev, 0); 865 if (s->irq <= 0) { 866 dev_err(&pdev->dev, "Missing irq resource data\n"); 867 ret = -ENXIO; 868 goto err_out; 869 } 870 871 /* Check input frequency */ 872 if ((s->pdata.frequency < freq_min) || 873 (s->pdata.frequency > freq_max)) { 874 dev_err(&pdev->dev, "Frequency out of bounds\n"); 875 ret = -EINVAL; 876 goto err_out; 877 } 878 879 membase = devm_ioremap_resource(&pdev->dev, res); 880 if (IS_ERR(membase)) { 881 ret = PTR_ERR(membase); 882 goto err_out; 883 } 884 885 s->uart.owner = THIS_MODULE; 886 s->uart.dev_name = "ttySC"; 887 s->uart.major = SCCNXP_MAJOR; 888 s->uart.minor = SCCNXP_MINOR; 889 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 890 s->uart.cons = &s->console; 891 s->uart.cons->device = uart_console_device; 892 s->uart.cons->write = sccnxp_console_write; 893 s->uart.cons->setup = sccnxp_console_setup; 894 s->uart.cons->flags = CON_PRINTBUFFER; 895 s->uart.cons->index = -1; 896 s->uart.cons->data = s; 897 strcpy(s->uart.cons->name, "ttySC"); 898 #endif 899 ret = uart_register_driver(&s->uart); 900 if (ret) { 901 dev_err(&pdev->dev, "Registering UART driver failed\n"); 902 goto err_out; 903 } 904 905 for (i = 0; i < s->uart.nr; i++) { 906 s->port[i].line = i; 907 s->port[i].dev = &pdev->dev; 908 s->port[i].irq = s->irq; 909 s->port[i].type = PORT_SC26XX; 910 s->port[i].fifosize = fifosize; 911 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 912 s->port[i].iotype = UPIO_MEM; 913 s->port[i].mapbase = res->start; 914 s->port[i].membase = membase; 915 s->port[i].regshift = s->pdata.reg_shift; 916 s->port[i].uartclk = s->pdata.frequency; 917 s->port[i].ops = &sccnxp_ops; 918 uart_add_one_port(&s->uart, &s->port[i]); 919 /* Set direction to input */ 920 if (s->flags & SCCNXP_HAVE_IO) 921 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 922 } 923 924 /* Disable interrupts */ 925 s->imr = 0; 926 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 927 928 /* Board specific configure */ 929 if (s->pdata.init) 930 s->pdata.init(); 931 932 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, sccnxp_ist, 933 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 934 dev_name(&pdev->dev), s); 935 if (!ret) 936 return 0; 937 938 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 939 940 err_out: 941 platform_set_drvdata(pdev, NULL); 942 943 return ret; 944 } 945 946 static int sccnxp_remove(struct platform_device *pdev) 947 { 948 int i; 949 struct sccnxp_port *s = platform_get_drvdata(pdev); 950 951 devm_free_irq(&pdev->dev, s->irq, s); 952 953 for (i = 0; i < s->uart.nr; i++) 954 uart_remove_one_port(&s->uart, &s->port[i]); 955 956 uart_unregister_driver(&s->uart); 957 platform_set_drvdata(pdev, NULL); 958 959 if (s->pdata.exit) 960 s->pdata.exit(); 961 962 return 0; 963 } 964 965 static const struct platform_device_id sccnxp_id_table[] = { 966 { "sc2681", SCCNXP_TYPE_SC2681 }, 967 { "sc2691", SCCNXP_TYPE_SC2691 }, 968 { "sc2692", SCCNXP_TYPE_SC2692 }, 969 { "sc2891", SCCNXP_TYPE_SC2891 }, 970 { "sc2892", SCCNXP_TYPE_SC2892 }, 971 { "sc28202", SCCNXP_TYPE_SC28202 }, 972 { "sc68681", SCCNXP_TYPE_SC68681 }, 973 { "sc68692", SCCNXP_TYPE_SC68692 }, 974 { }, 975 }; 976 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 977 978 static struct platform_driver sccnxp_uart_driver = { 979 .driver = { 980 .name = SCCNXP_NAME, 981 .owner = THIS_MODULE, 982 }, 983 .probe = sccnxp_probe, 984 .remove = sccnxp_remove, 985 .id_table = sccnxp_id_table, 986 }; 987 module_platform_driver(sccnxp_uart_driver); 988 989 MODULE_LICENSE("GPL v2"); 990 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 991 MODULE_DESCRIPTION("SCCNXP serial driver"); 992