1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/err.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/io.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/spinlock.h> 28 #include <linux/platform_device.h> 29 #include <linux/platform_data/serial-sccnxp.h> 30 #include <linux/regulator/consumer.h> 31 32 #define SCCNXP_NAME "uart-sccnxp" 33 #define SCCNXP_MAJOR 204 34 #define SCCNXP_MINOR 205 35 36 #define SCCNXP_MR_REG (0x00) 37 # define MR0_BAUD_NORMAL (0 << 0) 38 # define MR0_BAUD_EXT1 (1 << 0) 39 # define MR0_BAUD_EXT2 (5 << 0) 40 # define MR0_FIFO (1 << 3) 41 # define MR0_TXLVL (1 << 4) 42 # define MR1_BITS_5 (0 << 0) 43 # define MR1_BITS_6 (1 << 0) 44 # define MR1_BITS_7 (2 << 0) 45 # define MR1_BITS_8 (3 << 0) 46 # define MR1_PAR_EVN (0 << 2) 47 # define MR1_PAR_ODD (1 << 2) 48 # define MR1_PAR_NO (4 << 2) 49 # define MR2_STOP1 (7 << 0) 50 # define MR2_STOP2 (0xf << 0) 51 #define SCCNXP_SR_REG (0x01) 52 #define SCCNXP_CSR_REG SCCNXP_SR_REG 53 # define SR_RXRDY (1 << 0) 54 # define SR_FULL (1 << 1) 55 # define SR_TXRDY (1 << 2) 56 # define SR_TXEMT (1 << 3) 57 # define SR_OVR (1 << 4) 58 # define SR_PE (1 << 5) 59 # define SR_FE (1 << 6) 60 # define SR_BRK (1 << 7) 61 #define SCCNXP_CR_REG (0x02) 62 # define CR_RX_ENABLE (1 << 0) 63 # define CR_RX_DISABLE (1 << 1) 64 # define CR_TX_ENABLE (1 << 2) 65 # define CR_TX_DISABLE (1 << 3) 66 # define CR_CMD_MRPTR1 (0x01 << 4) 67 # define CR_CMD_RX_RESET (0x02 << 4) 68 # define CR_CMD_TX_RESET (0x03 << 4) 69 # define CR_CMD_STATUS_RESET (0x04 << 4) 70 # define CR_CMD_BREAK_RESET (0x05 << 4) 71 # define CR_CMD_START_BREAK (0x06 << 4) 72 # define CR_CMD_STOP_BREAK (0x07 << 4) 73 # define CR_CMD_MRPTR0 (0x0b << 4) 74 #define SCCNXP_RHR_REG (0x03) 75 #define SCCNXP_THR_REG SCCNXP_RHR_REG 76 #define SCCNXP_IPCR_REG (0x04) 77 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 78 # define ACR_BAUD0 (0 << 7) 79 # define ACR_BAUD1 (1 << 7) 80 # define ACR_TIMER_MODE (6 << 4) 81 #define SCCNXP_ISR_REG (0x05) 82 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 83 # define IMR_TXRDY (1 << 0) 84 # define IMR_RXRDY (1 << 1) 85 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 86 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 87 #define SCCNXP_IPR_REG (0x0d) 88 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 89 #define SCCNXP_SOP_REG (0x0e) 90 #define SCCNXP_ROP_REG (0x0f) 91 92 /* Route helpers */ 93 #define MCTRL_MASK(sig) (0xf << (sig)) 94 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 95 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 96 97 /* Supported chip types */ 98 enum { 99 SCCNXP_TYPE_SC2681 = 2681, 100 SCCNXP_TYPE_SC2691 = 2691, 101 SCCNXP_TYPE_SC2692 = 2692, 102 SCCNXP_TYPE_SC2891 = 2891, 103 SCCNXP_TYPE_SC2892 = 2892, 104 SCCNXP_TYPE_SC28202 = 28202, 105 SCCNXP_TYPE_SC68681 = 68681, 106 SCCNXP_TYPE_SC68692 = 68692, 107 }; 108 109 struct sccnxp_port { 110 struct uart_driver uart; 111 struct uart_port port[SCCNXP_MAX_UARTS]; 112 bool opened[SCCNXP_MAX_UARTS]; 113 114 const char *name; 115 int irq; 116 117 u8 imr; 118 u8 addr_mask; 119 int freq_std; 120 121 int flags; 122 #define SCCNXP_HAVE_IO 0x00000001 123 #define SCCNXP_HAVE_MR0 0x00000002 124 125 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 126 struct console console; 127 #endif 128 129 spinlock_t lock; 130 131 bool poll; 132 struct timer_list timer; 133 134 struct sccnxp_pdata pdata; 135 136 struct regulator *regulator; 137 }; 138 139 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 140 { 141 return readb(base + (reg << shift)); 142 } 143 144 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 145 { 146 writeb(v, base + (reg << shift)); 147 } 148 149 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 150 { 151 struct sccnxp_port *s = dev_get_drvdata(port->dev); 152 153 return sccnxp_raw_read(port->membase, reg & s->addr_mask, 154 port->regshift); 155 } 156 157 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 158 { 159 struct sccnxp_port *s = dev_get_drvdata(port->dev); 160 161 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v); 162 } 163 164 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 165 { 166 return sccnxp_read(port, (port->line << 3) + reg); 167 } 168 169 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 170 { 171 sccnxp_write(port, (port->line << 3) + reg, v); 172 } 173 174 static int sccnxp_update_best_err(int a, int b, int *besterr) 175 { 176 int err = abs(a - b); 177 178 if ((*besterr < 0) || (*besterr > err)) { 179 *besterr = err; 180 return 0; 181 } 182 183 return 1; 184 } 185 186 static const struct { 187 u8 csr; 188 u8 acr; 189 u8 mr0; 190 int baud; 191 } baud_std[] = { 192 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 193 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 194 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 195 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 196 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 197 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 198 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 199 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 200 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 201 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 202 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 203 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 204 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 205 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 206 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 207 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 208 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 209 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 210 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 211 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 212 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 213 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 214 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 215 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 216 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 217 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 218 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 219 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 220 { 0, 0, 0, 0 } 221 }; 222 223 static int sccnxp_set_baud(struct uart_port *port, int baud) 224 { 225 struct sccnxp_port *s = dev_get_drvdata(port->dev); 226 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 227 u8 i, acr = 0, csr = 0, mr0 = 0; 228 229 /* Find best baud from table */ 230 for (i = 0; baud_std[i].baud && besterr; i++) { 231 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 232 continue; 233 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 234 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 235 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 236 acr = baud_std[i].acr; 237 csr = baud_std[i].csr; 238 mr0 = baud_std[i].mr0; 239 bestbaud = tmp_baud; 240 } 241 } 242 243 if (s->flags & SCCNXP_HAVE_MR0) { 244 /* Enable FIFO, set half level for TX */ 245 mr0 |= MR0_FIFO | MR0_TXLVL; 246 /* Update MR0 */ 247 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 248 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 249 } 250 251 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 252 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 253 254 if (baud != bestbaud) 255 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 256 baud, bestbaud); 257 258 return bestbaud; 259 } 260 261 static void sccnxp_enable_irq(struct uart_port *port, int mask) 262 { 263 struct sccnxp_port *s = dev_get_drvdata(port->dev); 264 265 s->imr |= mask << (port->line * 4); 266 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 267 } 268 269 static void sccnxp_disable_irq(struct uart_port *port, int mask) 270 { 271 struct sccnxp_port *s = dev_get_drvdata(port->dev); 272 273 s->imr &= ~(mask << (port->line * 4)); 274 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 275 } 276 277 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 278 { 279 u8 bitmask; 280 struct sccnxp_port *s = dev_get_drvdata(port->dev); 281 282 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 283 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 284 if (state) 285 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 286 else 287 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 288 } 289 } 290 291 static void sccnxp_handle_rx(struct uart_port *port) 292 { 293 u8 sr; 294 unsigned int ch, flag; 295 296 for (;;) { 297 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 298 if (!(sr & SR_RXRDY)) 299 break; 300 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 301 302 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 303 304 port->icount.rx++; 305 flag = TTY_NORMAL; 306 307 if (unlikely(sr)) { 308 if (sr & SR_BRK) { 309 port->icount.brk++; 310 sccnxp_port_write(port, SCCNXP_CR_REG, 311 CR_CMD_BREAK_RESET); 312 if (uart_handle_break(port)) 313 continue; 314 } else if (sr & SR_PE) 315 port->icount.parity++; 316 else if (sr & SR_FE) 317 port->icount.frame++; 318 else if (sr & SR_OVR) { 319 port->icount.overrun++; 320 sccnxp_port_write(port, SCCNXP_CR_REG, 321 CR_CMD_STATUS_RESET); 322 } 323 324 sr &= port->read_status_mask; 325 if (sr & SR_BRK) 326 flag = TTY_BREAK; 327 else if (sr & SR_PE) 328 flag = TTY_PARITY; 329 else if (sr & SR_FE) 330 flag = TTY_FRAME; 331 else if (sr & SR_OVR) 332 flag = TTY_OVERRUN; 333 } 334 335 if (uart_handle_sysrq_char(port, ch)) 336 continue; 337 338 if (sr & port->ignore_status_mask) 339 continue; 340 341 uart_insert_char(port, sr, SR_OVR, ch, flag); 342 } 343 344 tty_flip_buffer_push(&port->state->port); 345 } 346 347 static void sccnxp_handle_tx(struct uart_port *port) 348 { 349 u8 sr; 350 struct circ_buf *xmit = &port->state->xmit; 351 struct sccnxp_port *s = dev_get_drvdata(port->dev); 352 353 if (unlikely(port->x_char)) { 354 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 355 port->icount.tx++; 356 port->x_char = 0; 357 return; 358 } 359 360 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 361 /* Disable TX if FIFO is empty */ 362 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 363 sccnxp_disable_irq(port, IMR_TXRDY); 364 365 /* Set direction to input */ 366 if (s->flags & SCCNXP_HAVE_IO) 367 sccnxp_set_bit(port, DIR_OP, 0); 368 } 369 return; 370 } 371 372 while (!uart_circ_empty(xmit)) { 373 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 374 if (!(sr & SR_TXRDY)) 375 break; 376 377 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 379 port->icount.tx++; 380 } 381 382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 383 uart_write_wakeup(port); 384 } 385 386 static void sccnxp_handle_events(struct sccnxp_port *s) 387 { 388 int i; 389 u8 isr; 390 391 do { 392 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 393 isr &= s->imr; 394 if (!isr) 395 break; 396 397 for (i = 0; i < s->uart.nr; i++) { 398 if (s->opened[i] && (isr & ISR_RXRDY(i))) 399 sccnxp_handle_rx(&s->port[i]); 400 if (s->opened[i] && (isr & ISR_TXRDY(i))) 401 sccnxp_handle_tx(&s->port[i]); 402 } 403 } while (1); 404 } 405 406 static void sccnxp_timer(unsigned long data) 407 { 408 struct sccnxp_port *s = (struct sccnxp_port *)data; 409 unsigned long flags; 410 411 spin_lock_irqsave(&s->lock, flags); 412 sccnxp_handle_events(s); 413 spin_unlock_irqrestore(&s->lock, flags); 414 415 if (!timer_pending(&s->timer)) 416 mod_timer(&s->timer, jiffies + 417 usecs_to_jiffies(s->pdata.poll_time_us)); 418 } 419 420 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 421 { 422 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 423 unsigned long flags; 424 425 spin_lock_irqsave(&s->lock, flags); 426 sccnxp_handle_events(s); 427 spin_unlock_irqrestore(&s->lock, flags); 428 429 return IRQ_HANDLED; 430 } 431 432 static void sccnxp_start_tx(struct uart_port *port) 433 { 434 struct sccnxp_port *s = dev_get_drvdata(port->dev); 435 unsigned long flags; 436 437 spin_lock_irqsave(&s->lock, flags); 438 439 /* Set direction to output */ 440 if (s->flags & SCCNXP_HAVE_IO) 441 sccnxp_set_bit(port, DIR_OP, 1); 442 443 sccnxp_enable_irq(port, IMR_TXRDY); 444 445 spin_unlock_irqrestore(&s->lock, flags); 446 } 447 448 static void sccnxp_stop_tx(struct uart_port *port) 449 { 450 /* Do nothing */ 451 } 452 453 static void sccnxp_stop_rx(struct uart_port *port) 454 { 455 struct sccnxp_port *s = dev_get_drvdata(port->dev); 456 unsigned long flags; 457 458 spin_lock_irqsave(&s->lock, flags); 459 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 460 spin_unlock_irqrestore(&s->lock, flags); 461 } 462 463 static unsigned int sccnxp_tx_empty(struct uart_port *port) 464 { 465 u8 val; 466 unsigned long flags; 467 struct sccnxp_port *s = dev_get_drvdata(port->dev); 468 469 spin_lock_irqsave(&s->lock, flags); 470 val = sccnxp_port_read(port, SCCNXP_SR_REG); 471 spin_unlock_irqrestore(&s->lock, flags); 472 473 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 474 } 475 476 static void sccnxp_enable_ms(struct uart_port *port) 477 { 478 /* Do nothing */ 479 } 480 481 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 482 { 483 struct sccnxp_port *s = dev_get_drvdata(port->dev); 484 unsigned long flags; 485 486 if (!(s->flags & SCCNXP_HAVE_IO)) 487 return; 488 489 spin_lock_irqsave(&s->lock, flags); 490 491 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 492 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 493 494 spin_unlock_irqrestore(&s->lock, flags); 495 } 496 497 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 498 { 499 u8 bitmask, ipr; 500 unsigned long flags; 501 struct sccnxp_port *s = dev_get_drvdata(port->dev); 502 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 503 504 if (!(s->flags & SCCNXP_HAVE_IO)) 505 return mctrl; 506 507 spin_lock_irqsave(&s->lock, flags); 508 509 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 510 511 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 512 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 513 DSR_IP); 514 mctrl &= ~TIOCM_DSR; 515 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 516 } 517 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 518 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 519 CTS_IP); 520 mctrl &= ~TIOCM_CTS; 521 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 522 } 523 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 524 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 525 DCD_IP); 526 mctrl &= ~TIOCM_CAR; 527 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 528 } 529 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 530 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 531 RNG_IP); 532 mctrl &= ~TIOCM_RNG; 533 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 534 } 535 536 spin_unlock_irqrestore(&s->lock, flags); 537 538 return mctrl; 539 } 540 541 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 542 { 543 struct sccnxp_port *s = dev_get_drvdata(port->dev); 544 unsigned long flags; 545 546 spin_lock_irqsave(&s->lock, flags); 547 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 548 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 549 spin_unlock_irqrestore(&s->lock, flags); 550 } 551 552 static void sccnxp_set_termios(struct uart_port *port, 553 struct ktermios *termios, struct ktermios *old) 554 { 555 struct sccnxp_port *s = dev_get_drvdata(port->dev); 556 unsigned long flags; 557 u8 mr1, mr2; 558 int baud; 559 560 spin_lock_irqsave(&s->lock, flags); 561 562 /* Mask termios capabilities we don't support */ 563 termios->c_cflag &= ~CMSPAR; 564 565 /* Disable RX & TX, reset break condition, status and FIFOs */ 566 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 567 CR_RX_DISABLE | CR_TX_DISABLE); 568 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 569 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 570 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 571 572 /* Word size */ 573 switch (termios->c_cflag & CSIZE) { 574 case CS5: 575 mr1 = MR1_BITS_5; 576 break; 577 case CS6: 578 mr1 = MR1_BITS_6; 579 break; 580 case CS7: 581 mr1 = MR1_BITS_7; 582 break; 583 case CS8: 584 default: 585 mr1 = MR1_BITS_8; 586 break; 587 } 588 589 /* Parity */ 590 if (termios->c_cflag & PARENB) { 591 if (termios->c_cflag & PARODD) 592 mr1 |= MR1_PAR_ODD; 593 } else 594 mr1 |= MR1_PAR_NO; 595 596 /* Stop bits */ 597 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 598 599 /* Update desired format */ 600 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 601 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 602 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 603 604 /* Set read status mask */ 605 port->read_status_mask = SR_OVR; 606 if (termios->c_iflag & INPCK) 607 port->read_status_mask |= SR_PE | SR_FE; 608 if (termios->c_iflag & (BRKINT | PARMRK)) 609 port->read_status_mask |= SR_BRK; 610 611 /* Set status ignore mask */ 612 port->ignore_status_mask = 0; 613 if (termios->c_iflag & IGNBRK) 614 port->ignore_status_mask |= SR_BRK; 615 if (!(termios->c_cflag & CREAD)) 616 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 617 618 /* Setup baudrate */ 619 baud = uart_get_baud_rate(port, termios, old, 50, 620 (s->flags & SCCNXP_HAVE_MR0) ? 621 230400 : 38400); 622 baud = sccnxp_set_baud(port, baud); 623 624 /* Update timeout according to new baud rate */ 625 uart_update_timeout(port, termios->c_cflag, baud); 626 627 /* Report actual baudrate back to core */ 628 if (tty_termios_baud_rate(termios)) 629 tty_termios_encode_baud_rate(termios, baud, baud); 630 631 /* Enable RX & TX */ 632 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 633 634 spin_unlock_irqrestore(&s->lock, flags); 635 } 636 637 static int sccnxp_startup(struct uart_port *port) 638 { 639 struct sccnxp_port *s = dev_get_drvdata(port->dev); 640 unsigned long flags; 641 642 spin_lock_irqsave(&s->lock, flags); 643 644 if (s->flags & SCCNXP_HAVE_IO) { 645 /* Outputs are controlled manually */ 646 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 647 } 648 649 /* Reset break condition, status and FIFOs */ 650 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 651 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 652 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 653 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 654 655 /* Enable RX & TX */ 656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 657 658 /* Enable RX interrupt */ 659 sccnxp_enable_irq(port, IMR_RXRDY); 660 661 s->opened[port->line] = 1; 662 663 spin_unlock_irqrestore(&s->lock, flags); 664 665 return 0; 666 } 667 668 static void sccnxp_shutdown(struct uart_port *port) 669 { 670 struct sccnxp_port *s = dev_get_drvdata(port->dev); 671 unsigned long flags; 672 673 spin_lock_irqsave(&s->lock, flags); 674 675 s->opened[port->line] = 0; 676 677 /* Disable interrupts */ 678 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 679 680 /* Disable TX & RX */ 681 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 682 683 /* Leave direction to input */ 684 if (s->flags & SCCNXP_HAVE_IO) 685 sccnxp_set_bit(port, DIR_OP, 0); 686 687 spin_unlock_irqrestore(&s->lock, flags); 688 } 689 690 static const char *sccnxp_type(struct uart_port *port) 691 { 692 struct sccnxp_port *s = dev_get_drvdata(port->dev); 693 694 return (port->type == PORT_SC26XX) ? s->name : NULL; 695 } 696 697 static void sccnxp_release_port(struct uart_port *port) 698 { 699 /* Do nothing */ 700 } 701 702 static int sccnxp_request_port(struct uart_port *port) 703 { 704 /* Do nothing */ 705 return 0; 706 } 707 708 static void sccnxp_config_port(struct uart_port *port, int flags) 709 { 710 if (flags & UART_CONFIG_TYPE) 711 port->type = PORT_SC26XX; 712 } 713 714 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 715 { 716 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 717 return 0; 718 if (s->irq == port->irq) 719 return 0; 720 721 return -EINVAL; 722 } 723 724 static const struct uart_ops sccnxp_ops = { 725 .tx_empty = sccnxp_tx_empty, 726 .set_mctrl = sccnxp_set_mctrl, 727 .get_mctrl = sccnxp_get_mctrl, 728 .stop_tx = sccnxp_stop_tx, 729 .start_tx = sccnxp_start_tx, 730 .stop_rx = sccnxp_stop_rx, 731 .enable_ms = sccnxp_enable_ms, 732 .break_ctl = sccnxp_break_ctl, 733 .startup = sccnxp_startup, 734 .shutdown = sccnxp_shutdown, 735 .set_termios = sccnxp_set_termios, 736 .type = sccnxp_type, 737 .release_port = sccnxp_release_port, 738 .request_port = sccnxp_request_port, 739 .config_port = sccnxp_config_port, 740 .verify_port = sccnxp_verify_port, 741 }; 742 743 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 744 static void sccnxp_console_putchar(struct uart_port *port, int c) 745 { 746 int tryes = 100000; 747 748 while (tryes--) { 749 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 750 sccnxp_port_write(port, SCCNXP_THR_REG, c); 751 break; 752 } 753 barrier(); 754 } 755 } 756 757 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 758 { 759 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 760 struct uart_port *port = &s->port[co->index]; 761 unsigned long flags; 762 763 spin_lock_irqsave(&s->lock, flags); 764 uart_console_write(port, c, n, sccnxp_console_putchar); 765 spin_unlock_irqrestore(&s->lock, flags); 766 } 767 768 static int sccnxp_console_setup(struct console *co, char *options) 769 { 770 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 771 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 772 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 773 774 if (options) 775 uart_parse_options(options, &baud, &parity, &bits, &flow); 776 777 return uart_set_options(port, co, baud, parity, bits, flow); 778 } 779 #endif 780 781 static int sccnxp_probe(struct platform_device *pdev) 782 { 783 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 784 int chiptype = pdev->id_entry->driver_data; 785 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 786 int i, ret, fifosize, freq_min, freq_max; 787 struct sccnxp_port *s; 788 void __iomem *membase; 789 790 membase = devm_ioremap_resource(&pdev->dev, res); 791 if (IS_ERR(membase)) 792 return PTR_ERR(membase); 793 794 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 795 if (!s) { 796 dev_err(&pdev->dev, "Error allocating port structure\n"); 797 return -ENOMEM; 798 } 799 platform_set_drvdata(pdev, s); 800 801 spin_lock_init(&s->lock); 802 803 /* Individual chip settings */ 804 switch (chiptype) { 805 case SCCNXP_TYPE_SC2681: 806 s->name = "SC2681"; 807 s->uart.nr = 2; 808 s->freq_std = 3686400; 809 s->addr_mask = 0x0f; 810 s->flags = SCCNXP_HAVE_IO; 811 fifosize = 3; 812 freq_min = 1000000; 813 freq_max = 4000000; 814 break; 815 case SCCNXP_TYPE_SC2691: 816 s->name = "SC2691"; 817 s->uart.nr = 1; 818 s->freq_std = 3686400; 819 s->addr_mask = 0x07; 820 s->flags = 0; 821 fifosize = 3; 822 freq_min = 1000000; 823 freq_max = 4000000; 824 break; 825 case SCCNXP_TYPE_SC2692: 826 s->name = "SC2692"; 827 s->uart.nr = 2; 828 s->freq_std = 3686400; 829 s->addr_mask = 0x0f; 830 s->flags = SCCNXP_HAVE_IO; 831 fifosize = 3; 832 freq_min = 1000000; 833 freq_max = 4000000; 834 break; 835 case SCCNXP_TYPE_SC2891: 836 s->name = "SC2891"; 837 s->uart.nr = 1; 838 s->freq_std = 3686400; 839 s->addr_mask = 0x0f; 840 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 841 fifosize = 16; 842 freq_min = 100000; 843 freq_max = 8000000; 844 break; 845 case SCCNXP_TYPE_SC2892: 846 s->name = "SC2892"; 847 s->uart.nr = 2; 848 s->freq_std = 3686400; 849 s->addr_mask = 0x0f; 850 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 851 fifosize = 16; 852 freq_min = 100000; 853 freq_max = 8000000; 854 break; 855 case SCCNXP_TYPE_SC28202: 856 s->name = "SC28202"; 857 s->uart.nr = 2; 858 s->freq_std = 14745600; 859 s->addr_mask = 0x7f; 860 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 861 fifosize = 256; 862 freq_min = 1000000; 863 freq_max = 50000000; 864 break; 865 case SCCNXP_TYPE_SC68681: 866 s->name = "SC68681"; 867 s->uart.nr = 2; 868 s->freq_std = 3686400; 869 s->addr_mask = 0x0f; 870 s->flags = SCCNXP_HAVE_IO; 871 fifosize = 3; 872 freq_min = 1000000; 873 freq_max = 4000000; 874 break; 875 case SCCNXP_TYPE_SC68692: 876 s->name = "SC68692"; 877 s->uart.nr = 2; 878 s->freq_std = 3686400; 879 s->addr_mask = 0x0f; 880 s->flags = SCCNXP_HAVE_IO; 881 fifosize = 3; 882 freq_min = 1000000; 883 freq_max = 4000000; 884 break; 885 default: 886 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype); 887 return -ENOTSUPP; 888 } 889 890 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 891 if (!IS_ERR(s->regulator)) { 892 ret = regulator_enable(s->regulator); 893 if (ret) { 894 dev_err(&pdev->dev, 895 "Failed to enable regulator: %i\n", ret); 896 return ret; 897 } 898 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) 899 return -EPROBE_DEFER; 900 901 if (!pdata) { 902 dev_warn(&pdev->dev, 903 "No platform data supplied, using defaults\n"); 904 s->pdata.frequency = s->freq_std; 905 } else 906 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 907 908 if (s->pdata.poll_time_us) { 909 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 910 s->pdata.poll_time_us); 911 s->poll = 1; 912 } 913 914 if (!s->poll) { 915 s->irq = platform_get_irq(pdev, 0); 916 if (s->irq < 0) { 917 dev_err(&pdev->dev, "Missing irq resource data\n"); 918 ret = -ENXIO; 919 goto err_out; 920 } 921 } 922 923 /* Check input frequency */ 924 if ((s->pdata.frequency < freq_min) || 925 (s->pdata.frequency > freq_max)) { 926 dev_err(&pdev->dev, "Frequency out of bounds\n"); 927 ret = -EINVAL; 928 goto err_out; 929 } 930 931 s->uart.owner = THIS_MODULE; 932 s->uart.dev_name = "ttySC"; 933 s->uart.major = SCCNXP_MAJOR; 934 s->uart.minor = SCCNXP_MINOR; 935 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 936 s->uart.cons = &s->console; 937 s->uart.cons->device = uart_console_device; 938 s->uart.cons->write = sccnxp_console_write; 939 s->uart.cons->setup = sccnxp_console_setup; 940 s->uart.cons->flags = CON_PRINTBUFFER; 941 s->uart.cons->index = -1; 942 s->uart.cons->data = s; 943 strcpy(s->uart.cons->name, "ttySC"); 944 #endif 945 ret = uart_register_driver(&s->uart); 946 if (ret) { 947 dev_err(&pdev->dev, "Registering UART driver failed\n"); 948 goto err_out; 949 } 950 951 for (i = 0; i < s->uart.nr; i++) { 952 s->port[i].line = i; 953 s->port[i].dev = &pdev->dev; 954 s->port[i].irq = s->irq; 955 s->port[i].type = PORT_SC26XX; 956 s->port[i].fifosize = fifosize; 957 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 958 s->port[i].iotype = UPIO_MEM; 959 s->port[i].mapbase = res->start; 960 s->port[i].membase = membase; 961 s->port[i].regshift = s->pdata.reg_shift; 962 s->port[i].uartclk = s->pdata.frequency; 963 s->port[i].ops = &sccnxp_ops; 964 uart_add_one_port(&s->uart, &s->port[i]); 965 /* Set direction to input */ 966 if (s->flags & SCCNXP_HAVE_IO) 967 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 968 } 969 970 /* Disable interrupts */ 971 s->imr = 0; 972 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 973 974 if (!s->poll) { 975 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 976 sccnxp_ist, 977 IRQF_TRIGGER_FALLING | 978 IRQF_ONESHOT, 979 dev_name(&pdev->dev), s); 980 if (!ret) 981 return 0; 982 983 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 984 } else { 985 init_timer(&s->timer); 986 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 987 mod_timer(&s->timer, jiffies + 988 usecs_to_jiffies(s->pdata.poll_time_us)); 989 return 0; 990 } 991 992 err_out: 993 if (!IS_ERR(s->regulator)) 994 return regulator_disable(s->regulator); 995 996 return ret; 997 } 998 999 static int sccnxp_remove(struct platform_device *pdev) 1000 { 1001 int i; 1002 struct sccnxp_port *s = platform_get_drvdata(pdev); 1003 1004 if (!s->poll) 1005 devm_free_irq(&pdev->dev, s->irq, s); 1006 else 1007 del_timer_sync(&s->timer); 1008 1009 for (i = 0; i < s->uart.nr; i++) 1010 uart_remove_one_port(&s->uart, &s->port[i]); 1011 1012 uart_unregister_driver(&s->uart); 1013 1014 if (!IS_ERR(s->regulator)) 1015 return regulator_disable(s->regulator); 1016 1017 return 0; 1018 } 1019 1020 static const struct platform_device_id sccnxp_id_table[] = { 1021 { "sc2681", SCCNXP_TYPE_SC2681 }, 1022 { "sc2691", SCCNXP_TYPE_SC2691 }, 1023 { "sc2692", SCCNXP_TYPE_SC2692 }, 1024 { "sc2891", SCCNXP_TYPE_SC2891 }, 1025 { "sc2892", SCCNXP_TYPE_SC2892 }, 1026 { "sc28202", SCCNXP_TYPE_SC28202 }, 1027 { "sc68681", SCCNXP_TYPE_SC68681 }, 1028 { "sc68692", SCCNXP_TYPE_SC68692 }, 1029 { }, 1030 }; 1031 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 1032 1033 static struct platform_driver sccnxp_uart_driver = { 1034 .driver = { 1035 .name = SCCNXP_NAME, 1036 .owner = THIS_MODULE, 1037 }, 1038 .probe = sccnxp_probe, 1039 .remove = sccnxp_remove, 1040 .id_table = sccnxp_id_table, 1041 }; 1042 module_platform_driver(sccnxp_uart_driver); 1043 1044 MODULE_LICENSE("GPL v2"); 1045 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1046 MODULE_DESCRIPTION("SCCNXP serial driver"); 1047