xref: /openbmc/linux/drivers/tty/serial/sccnxp.c (revision ded1ffea)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  NXP (Philips) SCC+++(SCN+++) serial driver
4  *
5  *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6  *
7  *  Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/device.h>
16 #include <linux/console.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial.h>
19 #include <linux/io.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/serial-sccnxp.h>
25 #include <linux/regulator/consumer.h>
26 
27 #define SCCNXP_NAME			"uart-sccnxp"
28 #define SCCNXP_MAJOR			204
29 #define SCCNXP_MINOR			205
30 
31 #define SCCNXP_MR_REG			(0x00)
32 #	define MR0_BAUD_NORMAL		(0 << 0)
33 #	define MR0_BAUD_EXT1		(1 << 0)
34 #	define MR0_BAUD_EXT2		(5 << 0)
35 #	define MR0_FIFO			(1 << 3)
36 #	define MR0_TXLVL		(1 << 4)
37 #	define MR1_BITS_5		(0 << 0)
38 #	define MR1_BITS_6		(1 << 0)
39 #	define MR1_BITS_7		(2 << 0)
40 #	define MR1_BITS_8		(3 << 0)
41 #	define MR1_PAR_EVN		(0 << 2)
42 #	define MR1_PAR_ODD		(1 << 2)
43 #	define MR1_PAR_NO		(4 << 2)
44 #	define MR2_STOP1		(7 << 0)
45 #	define MR2_STOP2		(0xf << 0)
46 #define SCCNXP_SR_REG			(0x01)
47 #	define SR_RXRDY			(1 << 0)
48 #	define SR_FULL			(1 << 1)
49 #	define SR_TXRDY			(1 << 2)
50 #	define SR_TXEMT			(1 << 3)
51 #	define SR_OVR			(1 << 4)
52 #	define SR_PE			(1 << 5)
53 #	define SR_FE			(1 << 6)
54 #	define SR_BRK			(1 << 7)
55 #define SCCNXP_CSR_REG			(SCCNXP_SR_REG)
56 #	define CSR_TIMER_MODE		(0x0d)
57 #define SCCNXP_CR_REG			(0x02)
58 #	define CR_RX_ENABLE		(1 << 0)
59 #	define CR_RX_DISABLE		(1 << 1)
60 #	define CR_TX_ENABLE		(1 << 2)
61 #	define CR_TX_DISABLE		(1 << 3)
62 #	define CR_CMD_MRPTR1		(0x01 << 4)
63 #	define CR_CMD_RX_RESET		(0x02 << 4)
64 #	define CR_CMD_TX_RESET		(0x03 << 4)
65 #	define CR_CMD_STATUS_RESET	(0x04 << 4)
66 #	define CR_CMD_BREAK_RESET	(0x05 << 4)
67 #	define CR_CMD_START_BREAK	(0x06 << 4)
68 #	define CR_CMD_STOP_BREAK	(0x07 << 4)
69 #	define CR_CMD_MRPTR0		(0x0b << 4)
70 #define SCCNXP_RHR_REG			(0x03)
71 #define SCCNXP_THR_REG			SCCNXP_RHR_REG
72 #define SCCNXP_IPCR_REG			(0x04)
73 #define SCCNXP_ACR_REG			SCCNXP_IPCR_REG
74 #	define ACR_BAUD0		(0 << 7)
75 #	define ACR_BAUD1		(1 << 7)
76 #	define ACR_TIMER_MODE		(6 << 4)
77 #define SCCNXP_ISR_REG			(0x05)
78 #define SCCNXP_IMR_REG			SCCNXP_ISR_REG
79 #	define IMR_TXRDY		(1 << 0)
80 #	define IMR_RXRDY		(1 << 1)
81 #	define ISR_TXRDY(x)		(1 << ((x * 4) + 0))
82 #	define ISR_RXRDY(x)		(1 << ((x * 4) + 1))
83 #define SCCNXP_CTPU_REG			(0x06)
84 #define SCCNXP_CTPL_REG			(0x07)
85 #define SCCNXP_IPR_REG			(0x0d)
86 #define SCCNXP_OPCR_REG			SCCNXP_IPR_REG
87 #define SCCNXP_SOP_REG			(0x0e)
88 #define SCCNXP_START_COUNTER_REG	SCCNXP_SOP_REG
89 #define SCCNXP_ROP_REG			(0x0f)
90 
91 /* Route helpers */
92 #define MCTRL_MASK(sig)			(0xf << (sig))
93 #define MCTRL_IBIT(cfg, sig)		((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig)		((((cfg) >> (sig)) & 0xf) - LINE_OP0)
95 
96 #define SCCNXP_HAVE_IO		0x00000001
97 #define SCCNXP_HAVE_MR0		0x00000002
98 
99 struct sccnxp_chip {
100 	const char		*name;
101 	unsigned int		nr;
102 	unsigned long		freq_min;
103 	unsigned long		freq_std;
104 	unsigned long		freq_max;
105 	unsigned int		flags;
106 	unsigned int		fifosize;
107 	/* Time between read/write cycles */
108 	unsigned int		trwd;
109 };
110 
111 struct sccnxp_port {
112 	struct uart_driver	uart;
113 	struct uart_port	port[SCCNXP_MAX_UARTS];
114 	bool			opened[SCCNXP_MAX_UARTS];
115 
116 	int			irq;
117 	u8			imr;
118 
119 	struct sccnxp_chip	*chip;
120 
121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
122 	struct console		console;
123 #endif
124 
125 	spinlock_t		lock;
126 
127 	bool			poll;
128 	struct timer_list	timer;
129 
130 	struct sccnxp_pdata	pdata;
131 
132 	struct regulator	*regulator;
133 };
134 
135 static const struct sccnxp_chip sc2681 = {
136 	.name		= "SC2681",
137 	.nr		= 2,
138 	.freq_min	= 1000000,
139 	.freq_std	= 3686400,
140 	.freq_max	= 4000000,
141 	.flags		= SCCNXP_HAVE_IO,
142 	.fifosize	= 3,
143 	.trwd		= 200,
144 };
145 
146 static const struct sccnxp_chip sc2691 = {
147 	.name		= "SC2691",
148 	.nr		= 1,
149 	.freq_min	= 1000000,
150 	.freq_std	= 3686400,
151 	.freq_max	= 4000000,
152 	.flags		= 0,
153 	.fifosize	= 3,
154 	.trwd		= 150,
155 };
156 
157 static const struct sccnxp_chip sc2692 = {
158 	.name		= "SC2692",
159 	.nr		= 2,
160 	.freq_min	= 1000000,
161 	.freq_std	= 3686400,
162 	.freq_max	= 4000000,
163 	.flags		= SCCNXP_HAVE_IO,
164 	.fifosize	= 3,
165 	.trwd		= 30,
166 };
167 
168 static const struct sccnxp_chip sc2891 = {
169 	.name		= "SC2891",
170 	.nr		= 1,
171 	.freq_min	= 100000,
172 	.freq_std	= 3686400,
173 	.freq_max	= 8000000,
174 	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
175 	.fifosize	= 16,
176 	.trwd		= 27,
177 };
178 
179 static const struct sccnxp_chip sc2892 = {
180 	.name		= "SC2892",
181 	.nr		= 2,
182 	.freq_min	= 100000,
183 	.freq_std	= 3686400,
184 	.freq_max	= 8000000,
185 	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
186 	.fifosize	= 16,
187 	.trwd		= 17,
188 };
189 
190 static const struct sccnxp_chip sc28202 = {
191 	.name		= "SC28202",
192 	.nr		= 2,
193 	.freq_min	= 1000000,
194 	.freq_std	= 14745600,
195 	.freq_max	= 50000000,
196 	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
197 	.fifosize	= 256,
198 	.trwd		= 10,
199 };
200 
201 static const struct sccnxp_chip sc68681 = {
202 	.name		= "SC68681",
203 	.nr		= 2,
204 	.freq_min	= 1000000,
205 	.freq_std	= 3686400,
206 	.freq_max	= 4000000,
207 	.flags		= SCCNXP_HAVE_IO,
208 	.fifosize	= 3,
209 	.trwd		= 200,
210 };
211 
212 static const struct sccnxp_chip sc68692 = {
213 	.name		= "SC68692",
214 	.nr		= 2,
215 	.freq_min	= 1000000,
216 	.freq_std	= 3686400,
217 	.freq_max	= 4000000,
218 	.flags		= SCCNXP_HAVE_IO,
219 	.fifosize	= 3,
220 	.trwd		= 200,
221 };
222 
223 static u8 sccnxp_read(struct uart_port *port, u8 reg)
224 {
225 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
226 	u8 ret;
227 
228 	ret = readb(port->membase + (reg << port->regshift));
229 
230 	ndelay(s->chip->trwd);
231 
232 	return ret;
233 }
234 
235 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
236 {
237 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
238 
239 	writeb(v, port->membase + (reg << port->regshift));
240 
241 	ndelay(s->chip->trwd);
242 }
243 
244 static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
245 {
246 	return sccnxp_read(port, (port->line << 3) + reg);
247 }
248 
249 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
250 {
251 	sccnxp_write(port, (port->line << 3) + reg, v);
252 }
253 
254 static int sccnxp_update_best_err(int a, int b, int *besterr)
255 {
256 	int err = abs(a - b);
257 
258 	if (*besterr > err) {
259 		*besterr = err;
260 		return 0;
261 	}
262 
263 	return 1;
264 }
265 
266 static const struct {
267 	u8	csr;
268 	u8	acr;
269 	u8	mr0;
270 	int	baud;
271 } baud_std[] = {
272 	{ 0,	ACR_BAUD0,	MR0_BAUD_NORMAL,	50, },
273 	{ 0,	ACR_BAUD1,	MR0_BAUD_NORMAL,	75, },
274 	{ 1,	ACR_BAUD0,	MR0_BAUD_NORMAL,	110, },
275 	{ 2,	ACR_BAUD0,	MR0_BAUD_NORMAL,	134, },
276 	{ 3,	ACR_BAUD1,	MR0_BAUD_NORMAL,	150, },
277 	{ 3,	ACR_BAUD0,	MR0_BAUD_NORMAL,	200, },
278 	{ 4,	ACR_BAUD0,	MR0_BAUD_NORMAL,	300, },
279 	{ 0,	ACR_BAUD1,	MR0_BAUD_EXT1,		450, },
280 	{ 1,	ACR_BAUD0,	MR0_BAUD_EXT2,		880, },
281 	{ 3,	ACR_BAUD1,	MR0_BAUD_EXT1,		900, },
282 	{ 5,	ACR_BAUD0,	MR0_BAUD_NORMAL,	600, },
283 	{ 7,	ACR_BAUD0,	MR0_BAUD_NORMAL,	1050, },
284 	{ 2,	ACR_BAUD0,	MR0_BAUD_EXT2,		1076, },
285 	{ 6,	ACR_BAUD0,	MR0_BAUD_NORMAL,	1200, },
286 	{ 10,	ACR_BAUD1,	MR0_BAUD_NORMAL,	1800, },
287 	{ 7,	ACR_BAUD1,	MR0_BAUD_NORMAL,	2000, },
288 	{ 8,	ACR_BAUD0,	MR0_BAUD_NORMAL,	2400, },
289 	{ 5,	ACR_BAUD1,	MR0_BAUD_EXT1,		3600, },
290 	{ 9,	ACR_BAUD0,	MR0_BAUD_NORMAL,	4800, },
291 	{ 10,	ACR_BAUD0,	MR0_BAUD_NORMAL,	7200, },
292 	{ 11,	ACR_BAUD0,	MR0_BAUD_NORMAL,	9600, },
293 	{ 8,	ACR_BAUD0,	MR0_BAUD_EXT1,		14400, },
294 	{ 12,	ACR_BAUD1,	MR0_BAUD_NORMAL,	19200, },
295 	{ 9,	ACR_BAUD0,	MR0_BAUD_EXT1,		28800, },
296 	{ 12,	ACR_BAUD0,	MR0_BAUD_NORMAL,	38400, },
297 	{ 11,	ACR_BAUD0,	MR0_BAUD_EXT1,		57600, },
298 	{ 12,	ACR_BAUD1,	MR0_BAUD_EXT1,		115200, },
299 	{ 12,	ACR_BAUD0,	MR0_BAUD_EXT1,		230400, },
300 	{ 0, 0, 0, 0 }
301 };
302 
303 static int sccnxp_set_baud(struct uart_port *port, int baud)
304 {
305 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
306 	int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
307 	struct sccnxp_chip *chip = s->chip;
308 	u8 i, acr = 0, csr = 0, mr0 = 0;
309 
310 	/* Find divisor to load to the timer preset registers */
311 	div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
312 	if ((div_std >= 2) && (div_std <= 0xffff)) {
313 		bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
314 		sccnxp_update_best_err(baud, bestbaud, &besterr);
315 		csr = CSR_TIMER_MODE;
316 		sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
317 		sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
318 		/* Issue start timer/counter command */
319 		sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
320 	}
321 
322 	/* Find best baud from table */
323 	for (i = 0; baud_std[i].baud && besterr; i++) {
324 		if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
325 			continue;
326 		div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
327 		tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
328 		if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
329 			acr = baud_std[i].acr;
330 			csr = baud_std[i].csr;
331 			mr0 = baud_std[i].mr0;
332 			bestbaud = tmp_baud;
333 		}
334 	}
335 
336 	if (chip->flags & SCCNXP_HAVE_MR0) {
337 		/* Enable FIFO, set half level for TX */
338 		mr0 |= MR0_FIFO | MR0_TXLVL;
339 		/* Update MR0 */
340 		sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
341 		sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
342 	}
343 
344 	sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
345 	sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
346 
347 	if (baud != bestbaud)
348 		dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
349 			baud, bestbaud);
350 
351 	return bestbaud;
352 }
353 
354 static void sccnxp_enable_irq(struct uart_port *port, int mask)
355 {
356 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
357 
358 	s->imr |= mask << (port->line * 4);
359 	sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
360 }
361 
362 static void sccnxp_disable_irq(struct uart_port *port, int mask)
363 {
364 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
365 
366 	s->imr &= ~(mask << (port->line * 4));
367 	sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
368 }
369 
370 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
371 {
372 	u8 bitmask;
373 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
374 
375 	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
376 		bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
377 		if (state)
378 			sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
379 		else
380 			sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
381 	}
382 }
383 
384 static void sccnxp_handle_rx(struct uart_port *port)
385 {
386 	u8 sr, ch, flag;
387 
388 	for (;;) {
389 		sr = sccnxp_port_read(port, SCCNXP_SR_REG);
390 		if (!(sr & SR_RXRDY))
391 			break;
392 		sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
393 
394 		ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
395 
396 		port->icount.rx++;
397 		flag = TTY_NORMAL;
398 
399 		if (unlikely(sr)) {
400 			if (sr & SR_BRK) {
401 				port->icount.brk++;
402 				sccnxp_port_write(port, SCCNXP_CR_REG,
403 						  CR_CMD_BREAK_RESET);
404 				if (uart_handle_break(port))
405 					continue;
406 			} else if (sr & SR_PE)
407 				port->icount.parity++;
408 			else if (sr & SR_FE)
409 				port->icount.frame++;
410 			else if (sr & SR_OVR) {
411 				port->icount.overrun++;
412 				sccnxp_port_write(port, SCCNXP_CR_REG,
413 						  CR_CMD_STATUS_RESET);
414 			}
415 
416 			sr &= port->read_status_mask;
417 			if (sr & SR_BRK)
418 				flag = TTY_BREAK;
419 			else if (sr & SR_PE)
420 				flag = TTY_PARITY;
421 			else if (sr & SR_FE)
422 				flag = TTY_FRAME;
423 			else if (sr & SR_OVR)
424 				flag = TTY_OVERRUN;
425 		}
426 
427 		if (uart_handle_sysrq_char(port, ch))
428 			continue;
429 
430 		if (sr & port->ignore_status_mask)
431 			continue;
432 
433 		uart_insert_char(port, sr, SR_OVR, ch, flag);
434 	}
435 
436 	tty_flip_buffer_push(&port->state->port);
437 }
438 
439 static void sccnxp_handle_tx(struct uart_port *port)
440 {
441 	u8 sr;
442 	struct circ_buf *xmit = &port->state->xmit;
443 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
444 
445 	if (unlikely(port->x_char)) {
446 		sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
447 		port->icount.tx++;
448 		port->x_char = 0;
449 		return;
450 	}
451 
452 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
453 		/* Disable TX if FIFO is empty */
454 		if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
455 			sccnxp_disable_irq(port, IMR_TXRDY);
456 
457 			/* Set direction to input */
458 			if (s->chip->flags & SCCNXP_HAVE_IO)
459 				sccnxp_set_bit(port, DIR_OP, 0);
460 		}
461 		return;
462 	}
463 
464 	while (!uart_circ_empty(xmit)) {
465 		sr = sccnxp_port_read(port, SCCNXP_SR_REG);
466 		if (!(sr & SR_TXRDY))
467 			break;
468 
469 		sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
470 		uart_xmit_advance(port, 1);
471 	}
472 
473 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
474 		uart_write_wakeup(port);
475 }
476 
477 static void sccnxp_handle_events(struct sccnxp_port *s)
478 {
479 	int i;
480 	u8 isr;
481 
482 	do {
483 		isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
484 		isr &= s->imr;
485 		if (!isr)
486 			break;
487 
488 		for (i = 0; i < s->uart.nr; i++) {
489 			if (s->opened[i] && (isr & ISR_RXRDY(i)))
490 				sccnxp_handle_rx(&s->port[i]);
491 			if (s->opened[i] && (isr & ISR_TXRDY(i)))
492 				sccnxp_handle_tx(&s->port[i]);
493 		}
494 	} while (1);
495 }
496 
497 static void sccnxp_timer(struct timer_list *t)
498 {
499 	struct sccnxp_port *s = from_timer(s, t, timer);
500 	unsigned long flags;
501 
502 	spin_lock_irqsave(&s->lock, flags);
503 	sccnxp_handle_events(s);
504 	spin_unlock_irqrestore(&s->lock, flags);
505 
506 	mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
507 }
508 
509 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
510 {
511 	struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
512 	unsigned long flags;
513 
514 	spin_lock_irqsave(&s->lock, flags);
515 	sccnxp_handle_events(s);
516 	spin_unlock_irqrestore(&s->lock, flags);
517 
518 	return IRQ_HANDLED;
519 }
520 
521 static void sccnxp_start_tx(struct uart_port *port)
522 {
523 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
524 	unsigned long flags;
525 
526 	spin_lock_irqsave(&s->lock, flags);
527 
528 	/* Set direction to output */
529 	if (s->chip->flags & SCCNXP_HAVE_IO)
530 		sccnxp_set_bit(port, DIR_OP, 1);
531 
532 	sccnxp_enable_irq(port, IMR_TXRDY);
533 
534 	spin_unlock_irqrestore(&s->lock, flags);
535 }
536 
537 static void sccnxp_stop_tx(struct uart_port *port)
538 {
539 	/* Do nothing */
540 }
541 
542 static void sccnxp_stop_rx(struct uart_port *port)
543 {
544 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
545 	unsigned long flags;
546 
547 	spin_lock_irqsave(&s->lock, flags);
548 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
549 	spin_unlock_irqrestore(&s->lock, flags);
550 }
551 
552 static unsigned int sccnxp_tx_empty(struct uart_port *port)
553 {
554 	u8 val;
555 	unsigned long flags;
556 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
557 
558 	spin_lock_irqsave(&s->lock, flags);
559 	val = sccnxp_port_read(port, SCCNXP_SR_REG);
560 	spin_unlock_irqrestore(&s->lock, flags);
561 
562 	return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
563 }
564 
565 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
566 {
567 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
568 	unsigned long flags;
569 
570 	if (!(s->chip->flags & SCCNXP_HAVE_IO))
571 		return;
572 
573 	spin_lock_irqsave(&s->lock, flags);
574 
575 	sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
576 	sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
577 
578 	spin_unlock_irqrestore(&s->lock, flags);
579 }
580 
581 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
582 {
583 	u8 bitmask, ipr;
584 	unsigned long flags;
585 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
586 	unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
587 
588 	if (!(s->chip->flags & SCCNXP_HAVE_IO))
589 		return mctrl;
590 
591 	spin_lock_irqsave(&s->lock, flags);
592 
593 	ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
594 
595 	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
596 		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
597 					  DSR_IP);
598 		mctrl &= ~TIOCM_DSR;
599 		mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
600 	}
601 	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
602 		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
603 					  CTS_IP);
604 		mctrl &= ~TIOCM_CTS;
605 		mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
606 	}
607 	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
608 		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
609 					  DCD_IP);
610 		mctrl &= ~TIOCM_CAR;
611 		mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
612 	}
613 	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
614 		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
615 					  RNG_IP);
616 		mctrl &= ~TIOCM_RNG;
617 		mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
618 	}
619 
620 	spin_unlock_irqrestore(&s->lock, flags);
621 
622 	return mctrl;
623 }
624 
625 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
626 {
627 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
628 	unsigned long flags;
629 
630 	spin_lock_irqsave(&s->lock, flags);
631 	sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
632 			  CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
633 	spin_unlock_irqrestore(&s->lock, flags);
634 }
635 
636 static void sccnxp_set_termios(struct uart_port *port,
637 			       struct ktermios *termios,
638 			       const struct ktermios *old)
639 {
640 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
641 	unsigned long flags;
642 	u8 mr1, mr2;
643 	int baud;
644 
645 	spin_lock_irqsave(&s->lock, flags);
646 
647 	/* Mask termios capabilities we don't support */
648 	termios->c_cflag &= ~CMSPAR;
649 
650 	/* Disable RX & TX, reset break condition, status and FIFOs */
651 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
652 					       CR_RX_DISABLE | CR_TX_DISABLE);
653 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
654 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
655 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
656 
657 	/* Word size */
658 	switch (termios->c_cflag & CSIZE) {
659 	case CS5:
660 		mr1 = MR1_BITS_5;
661 		break;
662 	case CS6:
663 		mr1 = MR1_BITS_6;
664 		break;
665 	case CS7:
666 		mr1 = MR1_BITS_7;
667 		break;
668 	case CS8:
669 	default:
670 		mr1 = MR1_BITS_8;
671 		break;
672 	}
673 
674 	/* Parity */
675 	if (termios->c_cflag & PARENB) {
676 		if (termios->c_cflag & PARODD)
677 			mr1 |= MR1_PAR_ODD;
678 	} else
679 		mr1 |= MR1_PAR_NO;
680 
681 	/* Stop bits */
682 	mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
683 
684 	/* Update desired format */
685 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
686 	sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
687 	sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
688 
689 	/* Set read status mask */
690 	port->read_status_mask = SR_OVR;
691 	if (termios->c_iflag & INPCK)
692 		port->read_status_mask |= SR_PE | SR_FE;
693 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
694 		port->read_status_mask |= SR_BRK;
695 
696 	/* Set status ignore mask */
697 	port->ignore_status_mask = 0;
698 	if (termios->c_iflag & IGNBRK)
699 		port->ignore_status_mask |= SR_BRK;
700 	if (termios->c_iflag & IGNPAR)
701 		port->ignore_status_mask |= SR_PE;
702 	if (!(termios->c_cflag & CREAD))
703 		port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
704 
705 	/* Setup baudrate */
706 	baud = uart_get_baud_rate(port, termios, old, 50,
707 				  (s->chip->flags & SCCNXP_HAVE_MR0) ?
708 				  230400 : 38400);
709 	baud = sccnxp_set_baud(port, baud);
710 
711 	/* Update timeout according to new baud rate */
712 	uart_update_timeout(port, termios->c_cflag, baud);
713 
714 	/* Report actual baudrate back to core */
715 	if (tty_termios_baud_rate(termios))
716 		tty_termios_encode_baud_rate(termios, baud, baud);
717 
718 	/* Enable RX & TX */
719 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
720 
721 	spin_unlock_irqrestore(&s->lock, flags);
722 }
723 
724 static int sccnxp_startup(struct uart_port *port)
725 {
726 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
727 	unsigned long flags;
728 
729 	spin_lock_irqsave(&s->lock, flags);
730 
731 	if (s->chip->flags & SCCNXP_HAVE_IO) {
732 		/* Outputs are controlled manually */
733 		sccnxp_write(port, SCCNXP_OPCR_REG, 0);
734 	}
735 
736 	/* Reset break condition, status and FIFOs */
737 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
738 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
739 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
740 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
741 
742 	/* Enable RX & TX */
743 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
744 
745 	/* Enable RX interrupt */
746 	sccnxp_enable_irq(port, IMR_RXRDY);
747 
748 	s->opened[port->line] = 1;
749 
750 	spin_unlock_irqrestore(&s->lock, flags);
751 
752 	return 0;
753 }
754 
755 static void sccnxp_shutdown(struct uart_port *port)
756 {
757 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
758 	unsigned long flags;
759 
760 	spin_lock_irqsave(&s->lock, flags);
761 
762 	s->opened[port->line] = 0;
763 
764 	/* Disable interrupts */
765 	sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
766 
767 	/* Disable TX & RX */
768 	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
769 
770 	/* Leave direction to input */
771 	if (s->chip->flags & SCCNXP_HAVE_IO)
772 		sccnxp_set_bit(port, DIR_OP, 0);
773 
774 	spin_unlock_irqrestore(&s->lock, flags);
775 }
776 
777 static const char *sccnxp_type(struct uart_port *port)
778 {
779 	struct sccnxp_port *s = dev_get_drvdata(port->dev);
780 
781 	return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
782 }
783 
784 static void sccnxp_release_port(struct uart_port *port)
785 {
786 	/* Do nothing */
787 }
788 
789 static int sccnxp_request_port(struct uart_port *port)
790 {
791 	/* Do nothing */
792 	return 0;
793 }
794 
795 static void sccnxp_config_port(struct uart_port *port, int flags)
796 {
797 	if (flags & UART_CONFIG_TYPE)
798 		port->type = PORT_SC26XX;
799 }
800 
801 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
802 {
803 	if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
804 		return 0;
805 	if (s->irq == port->irq)
806 		return 0;
807 
808 	return -EINVAL;
809 }
810 
811 static const struct uart_ops sccnxp_ops = {
812 	.tx_empty	= sccnxp_tx_empty,
813 	.set_mctrl	= sccnxp_set_mctrl,
814 	.get_mctrl	= sccnxp_get_mctrl,
815 	.stop_tx	= sccnxp_stop_tx,
816 	.start_tx	= sccnxp_start_tx,
817 	.stop_rx	= sccnxp_stop_rx,
818 	.break_ctl	= sccnxp_break_ctl,
819 	.startup	= sccnxp_startup,
820 	.shutdown	= sccnxp_shutdown,
821 	.set_termios	= sccnxp_set_termios,
822 	.type		= sccnxp_type,
823 	.release_port	= sccnxp_release_port,
824 	.request_port	= sccnxp_request_port,
825 	.config_port	= sccnxp_config_port,
826 	.verify_port	= sccnxp_verify_port,
827 };
828 
829 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
830 static void sccnxp_console_putchar(struct uart_port *port, unsigned char c)
831 {
832 	int tryes = 100000;
833 
834 	while (tryes--) {
835 		if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
836 			sccnxp_port_write(port, SCCNXP_THR_REG, c);
837 			break;
838 		}
839 		barrier();
840 	}
841 }
842 
843 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
844 {
845 	struct sccnxp_port *s = (struct sccnxp_port *)co->data;
846 	struct uart_port *port = &s->port[co->index];
847 	unsigned long flags;
848 
849 	spin_lock_irqsave(&s->lock, flags);
850 	uart_console_write(port, c, n, sccnxp_console_putchar);
851 	spin_unlock_irqrestore(&s->lock, flags);
852 }
853 
854 static int sccnxp_console_setup(struct console *co, char *options)
855 {
856 	struct sccnxp_port *s = (struct sccnxp_port *)co->data;
857 	struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
858 	int baud = 9600, bits = 8, parity = 'n', flow = 'n';
859 
860 	if (options)
861 		uart_parse_options(options, &baud, &parity, &bits, &flow);
862 
863 	return uart_set_options(port, co, baud, parity, bits, flow);
864 }
865 #endif
866 
867 static const struct platform_device_id sccnxp_id_table[] = {
868 	{ .name = "sc2681",	.driver_data = (kernel_ulong_t)&sc2681, },
869 	{ .name = "sc2691",	.driver_data = (kernel_ulong_t)&sc2691, },
870 	{ .name = "sc2692",	.driver_data = (kernel_ulong_t)&sc2692, },
871 	{ .name = "sc2891",	.driver_data = (kernel_ulong_t)&sc2891, },
872 	{ .name = "sc2892",	.driver_data = (kernel_ulong_t)&sc2892, },
873 	{ .name = "sc28202",	.driver_data = (kernel_ulong_t)&sc28202, },
874 	{ .name = "sc68681",	.driver_data = (kernel_ulong_t)&sc68681, },
875 	{ .name = "sc68692",	.driver_data = (kernel_ulong_t)&sc68692, },
876 	{ }
877 };
878 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
879 
880 static int sccnxp_probe(struct platform_device *pdev)
881 {
882 	struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
883 	struct resource *res;
884 	int i, ret, uartclk;
885 	struct sccnxp_port *s;
886 	void __iomem *membase;
887 	struct clk *clk;
888 
889 	membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
890 	if (IS_ERR(membase))
891 		return PTR_ERR(membase);
892 
893 	s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
894 	if (!s) {
895 		dev_err(&pdev->dev, "Error allocating port structure\n");
896 		return -ENOMEM;
897 	}
898 	platform_set_drvdata(pdev, s);
899 
900 	spin_lock_init(&s->lock);
901 
902 	s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
903 
904 	s->regulator = devm_regulator_get(&pdev->dev, "vcc");
905 	if (!IS_ERR(s->regulator)) {
906 		ret = regulator_enable(s->regulator);
907 		if (ret) {
908 			dev_err(&pdev->dev,
909 				"Failed to enable regulator: %i\n", ret);
910 			return ret;
911 		}
912 	} else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
913 		return -EPROBE_DEFER;
914 
915 	clk = devm_clk_get_enabled(&pdev->dev, NULL);
916 	if (IS_ERR(clk)) {
917 		ret = PTR_ERR(clk);
918 		if (ret == -EPROBE_DEFER)
919 			goto err_out;
920 		uartclk = 0;
921 	} else {
922 		uartclk = clk_get_rate(clk);
923 	}
924 
925 	if (!uartclk) {
926 		dev_notice(&pdev->dev, "Using default clock frequency\n");
927 		uartclk = s->chip->freq_std;
928 	}
929 
930 	/* Check input frequency */
931 	if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
932 		dev_err(&pdev->dev, "Frequency out of bounds\n");
933 		ret = -EINVAL;
934 		goto err_out;
935 	}
936 
937 	if (pdata)
938 		memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
939 
940 	if (s->pdata.poll_time_us) {
941 		dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
942 			 s->pdata.poll_time_us);
943 		s->poll = 1;
944 	}
945 
946 	if (!s->poll) {
947 		s->irq = platform_get_irq(pdev, 0);
948 		if (s->irq < 0) {
949 			ret = -ENXIO;
950 			goto err_out;
951 		}
952 	}
953 
954 	s->uart.owner		= THIS_MODULE;
955 	s->uart.dev_name	= "ttySC";
956 	s->uart.major		= SCCNXP_MAJOR;
957 	s->uart.minor		= SCCNXP_MINOR;
958 	s->uart.nr		= s->chip->nr;
959 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
960 	s->uart.cons		= &s->console;
961 	s->uart.cons->device	= uart_console_device;
962 	s->uart.cons->write	= sccnxp_console_write;
963 	s->uart.cons->setup	= sccnxp_console_setup;
964 	s->uart.cons->flags	= CON_PRINTBUFFER;
965 	s->uart.cons->index	= -1;
966 	s->uart.cons->data	= s;
967 	strcpy(s->uart.cons->name, "ttySC");
968 #endif
969 	ret = uart_register_driver(&s->uart);
970 	if (ret) {
971 		dev_err(&pdev->dev, "Registering UART driver failed\n");
972 		goto err_out;
973 	}
974 
975 	for (i = 0; i < s->uart.nr; i++) {
976 		s->port[i].line		= i;
977 		s->port[i].dev		= &pdev->dev;
978 		s->port[i].irq		= s->irq;
979 		s->port[i].type		= PORT_SC26XX;
980 		s->port[i].fifosize	= s->chip->fifosize;
981 		s->port[i].flags	= UPF_SKIP_TEST | UPF_FIXED_TYPE;
982 		s->port[i].iotype	= UPIO_MEM;
983 		s->port[i].mapbase	= res->start;
984 		s->port[i].membase	= membase;
985 		s->port[i].regshift	= s->pdata.reg_shift;
986 		s->port[i].uartclk	= uartclk;
987 		s->port[i].ops		= &sccnxp_ops;
988 		s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE);
989 		uart_add_one_port(&s->uart, &s->port[i]);
990 		/* Set direction to input */
991 		if (s->chip->flags & SCCNXP_HAVE_IO)
992 			sccnxp_set_bit(&s->port[i], DIR_OP, 0);
993 	}
994 
995 	/* Disable interrupts */
996 	s->imr = 0;
997 	sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
998 
999 	if (!s->poll) {
1000 		ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1001 						sccnxp_ist,
1002 						IRQF_TRIGGER_FALLING |
1003 						IRQF_ONESHOT,
1004 						dev_name(&pdev->dev), s);
1005 		if (!ret)
1006 			return 0;
1007 
1008 		dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1009 	} else {
1010 		timer_setup(&s->timer, sccnxp_timer, 0);
1011 		mod_timer(&s->timer, jiffies +
1012 			  usecs_to_jiffies(s->pdata.poll_time_us));
1013 		return 0;
1014 	}
1015 
1016 	uart_unregister_driver(&s->uart);
1017 err_out:
1018 	if (!IS_ERR(s->regulator))
1019 		regulator_disable(s->regulator);
1020 
1021 	return ret;
1022 }
1023 
1024 static int sccnxp_remove(struct platform_device *pdev)
1025 {
1026 	int i;
1027 	struct sccnxp_port *s = platform_get_drvdata(pdev);
1028 
1029 	if (!s->poll)
1030 		devm_free_irq(&pdev->dev, s->irq, s);
1031 	else
1032 		del_timer_sync(&s->timer);
1033 
1034 	for (i = 0; i < s->uart.nr; i++)
1035 		uart_remove_one_port(&s->uart, &s->port[i]);
1036 
1037 	uart_unregister_driver(&s->uart);
1038 
1039 	if (!IS_ERR(s->regulator))
1040 		return regulator_disable(s->regulator);
1041 
1042 	return 0;
1043 }
1044 
1045 static struct platform_driver sccnxp_uart_driver = {
1046 	.driver = {
1047 		.name	= SCCNXP_NAME,
1048 	},
1049 	.probe		= sccnxp_probe,
1050 	.remove		= sccnxp_remove,
1051 	.id_table	= sccnxp_id_table,
1052 };
1053 module_platform_driver(sccnxp_uart_driver);
1054 
1055 MODULE_LICENSE("GPL v2");
1056 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1057 MODULE_DESCRIPTION("SCCNXP serial driver");
1058