1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/console.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/io.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/platform_data/serial-sccnxp.h> 29 30 #define SCCNXP_NAME "uart-sccnxp" 31 #define SCCNXP_MAJOR 204 32 #define SCCNXP_MINOR 205 33 34 #define SCCNXP_MR_REG (0x00) 35 # define MR0_BAUD_NORMAL (0 << 0) 36 # define MR0_BAUD_EXT1 (1 << 0) 37 # define MR0_BAUD_EXT2 (5 << 0) 38 # define MR0_FIFO (1 << 3) 39 # define MR0_TXLVL (1 << 4) 40 # define MR1_BITS_5 (0 << 0) 41 # define MR1_BITS_6 (1 << 0) 42 # define MR1_BITS_7 (2 << 0) 43 # define MR1_BITS_8 (3 << 0) 44 # define MR1_PAR_EVN (0 << 2) 45 # define MR1_PAR_ODD (1 << 2) 46 # define MR1_PAR_NO (4 << 2) 47 # define MR2_STOP1 (7 << 0) 48 # define MR2_STOP2 (0xf << 0) 49 #define SCCNXP_SR_REG (0x01) 50 #define SCCNXP_CSR_REG SCCNXP_SR_REG 51 # define SR_RXRDY (1 << 0) 52 # define SR_FULL (1 << 1) 53 # define SR_TXRDY (1 << 2) 54 # define SR_TXEMT (1 << 3) 55 # define SR_OVR (1 << 4) 56 # define SR_PE (1 << 5) 57 # define SR_FE (1 << 6) 58 # define SR_BRK (1 << 7) 59 #define SCCNXP_CR_REG (0x02) 60 # define CR_RX_ENABLE (1 << 0) 61 # define CR_RX_DISABLE (1 << 1) 62 # define CR_TX_ENABLE (1 << 2) 63 # define CR_TX_DISABLE (1 << 3) 64 # define CR_CMD_MRPTR1 (0x01 << 4) 65 # define CR_CMD_RX_RESET (0x02 << 4) 66 # define CR_CMD_TX_RESET (0x03 << 4) 67 # define CR_CMD_STATUS_RESET (0x04 << 4) 68 # define CR_CMD_BREAK_RESET (0x05 << 4) 69 # define CR_CMD_START_BREAK (0x06 << 4) 70 # define CR_CMD_STOP_BREAK (0x07 << 4) 71 # define CR_CMD_MRPTR0 (0x0b << 4) 72 #define SCCNXP_RHR_REG (0x03) 73 #define SCCNXP_THR_REG SCCNXP_RHR_REG 74 #define SCCNXP_IPCR_REG (0x04) 75 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 76 # define ACR_BAUD0 (0 << 7) 77 # define ACR_BAUD1 (1 << 7) 78 # define ACR_TIMER_MODE (6 << 4) 79 #define SCCNXP_ISR_REG (0x05) 80 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 81 # define IMR_TXRDY (1 << 0) 82 # define IMR_RXRDY (1 << 1) 83 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 84 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 85 #define SCCNXP_IPR_REG (0x0d) 86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 87 #define SCCNXP_SOP_REG (0x0e) 88 #define SCCNXP_ROP_REG (0x0f) 89 90 /* Route helpers */ 91 #define MCTRL_MASK(sig) (0xf << (sig)) 92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 94 95 /* Supported chip types */ 96 enum { 97 SCCNXP_TYPE_SC2681 = 2681, 98 SCCNXP_TYPE_SC2691 = 2691, 99 SCCNXP_TYPE_SC2692 = 2692, 100 SCCNXP_TYPE_SC2891 = 2891, 101 SCCNXP_TYPE_SC2892 = 2892, 102 SCCNXP_TYPE_SC28202 = 28202, 103 SCCNXP_TYPE_SC68681 = 68681, 104 SCCNXP_TYPE_SC68692 = 68692, 105 }; 106 107 struct sccnxp_port { 108 struct uart_driver uart; 109 struct uart_port port[SCCNXP_MAX_UARTS]; 110 bool opened[SCCNXP_MAX_UARTS]; 111 112 const char *name; 113 int irq; 114 115 u8 imr; 116 u8 addr_mask; 117 int freq_std; 118 119 int flags; 120 #define SCCNXP_HAVE_IO 0x00000001 121 #define SCCNXP_HAVE_MR0 0x00000002 122 123 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 124 struct console console; 125 #endif 126 127 spinlock_t lock; 128 129 bool poll; 130 struct timer_list timer; 131 132 struct sccnxp_pdata pdata; 133 }; 134 135 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 136 { 137 return readb(base + (reg << shift)); 138 } 139 140 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 141 { 142 writeb(v, base + (reg << shift)); 143 } 144 145 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 146 { 147 struct sccnxp_port *s = dev_get_drvdata(port->dev); 148 149 return sccnxp_raw_read(port->membase, reg & s->addr_mask, 150 port->regshift); 151 } 152 153 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 154 { 155 struct sccnxp_port *s = dev_get_drvdata(port->dev); 156 157 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v); 158 } 159 160 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 161 { 162 return sccnxp_read(port, (port->line << 3) + reg); 163 } 164 165 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 166 { 167 sccnxp_write(port, (port->line << 3) + reg, v); 168 } 169 170 static int sccnxp_update_best_err(int a, int b, int *besterr) 171 { 172 int err = abs(a - b); 173 174 if ((*besterr < 0) || (*besterr > err)) { 175 *besterr = err; 176 return 0; 177 } 178 179 return 1; 180 } 181 182 struct baud_table { 183 u8 csr; 184 u8 acr; 185 u8 mr0; 186 int baud; 187 }; 188 189 const struct baud_table baud_std[] = { 190 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 191 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 192 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 193 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 194 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 195 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 196 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 197 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 198 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 199 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 200 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 201 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 202 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 203 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 204 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 205 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 206 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 207 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 208 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 209 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 210 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 211 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 212 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 213 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 214 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 215 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 216 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 217 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 218 { 0, 0, 0, 0 } 219 }; 220 221 static int sccnxp_set_baud(struct uart_port *port, int baud) 222 { 223 struct sccnxp_port *s = dev_get_drvdata(port->dev); 224 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 225 u8 i, acr = 0, csr = 0, mr0 = 0; 226 227 /* Find best baud from table */ 228 for (i = 0; baud_std[i].baud && besterr; i++) { 229 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 230 continue; 231 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 232 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 233 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 234 acr = baud_std[i].acr; 235 csr = baud_std[i].csr; 236 mr0 = baud_std[i].mr0; 237 bestbaud = tmp_baud; 238 } 239 } 240 241 if (s->flags & SCCNXP_HAVE_MR0) { 242 /* Enable FIFO, set half level for TX */ 243 mr0 |= MR0_FIFO | MR0_TXLVL; 244 /* Update MR0 */ 245 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 246 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 247 } 248 249 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 250 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 251 252 if (baud != bestbaud) 253 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 254 baud, bestbaud); 255 256 return bestbaud; 257 } 258 259 static void sccnxp_enable_irq(struct uart_port *port, int mask) 260 { 261 struct sccnxp_port *s = dev_get_drvdata(port->dev); 262 263 s->imr |= mask << (port->line * 4); 264 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 265 } 266 267 static void sccnxp_disable_irq(struct uart_port *port, int mask) 268 { 269 struct sccnxp_port *s = dev_get_drvdata(port->dev); 270 271 s->imr &= ~(mask << (port->line * 4)); 272 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 273 } 274 275 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 276 { 277 u8 bitmask; 278 struct sccnxp_port *s = dev_get_drvdata(port->dev); 279 280 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 281 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 282 if (state) 283 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 284 else 285 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 286 } 287 } 288 289 static void sccnxp_handle_rx(struct uart_port *port) 290 { 291 u8 sr; 292 unsigned int ch, flag; 293 294 for (;;) { 295 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 296 if (!(sr & SR_RXRDY)) 297 break; 298 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 299 300 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 301 302 port->icount.rx++; 303 flag = TTY_NORMAL; 304 305 if (unlikely(sr)) { 306 if (sr & SR_BRK) { 307 port->icount.brk++; 308 if (uart_handle_break(port)) 309 continue; 310 } else if (sr & SR_PE) 311 port->icount.parity++; 312 else if (sr & SR_FE) 313 port->icount.frame++; 314 else if (sr & SR_OVR) 315 port->icount.overrun++; 316 317 sr &= port->read_status_mask; 318 if (sr & SR_BRK) 319 flag = TTY_BREAK; 320 else if (sr & SR_PE) 321 flag = TTY_PARITY; 322 else if (sr & SR_FE) 323 flag = TTY_FRAME; 324 else if (sr & SR_OVR) 325 flag = TTY_OVERRUN; 326 } 327 328 if (uart_handle_sysrq_char(port, ch)) 329 continue; 330 331 if (sr & port->ignore_status_mask) 332 continue; 333 334 uart_insert_char(port, sr, SR_OVR, ch, flag); 335 } 336 337 tty_flip_buffer_push(&port->state->port); 338 } 339 340 static void sccnxp_handle_tx(struct uart_port *port) 341 { 342 u8 sr; 343 struct circ_buf *xmit = &port->state->xmit; 344 struct sccnxp_port *s = dev_get_drvdata(port->dev); 345 346 if (unlikely(port->x_char)) { 347 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 348 port->icount.tx++; 349 port->x_char = 0; 350 return; 351 } 352 353 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 354 /* Disable TX if FIFO is empty */ 355 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 356 sccnxp_disable_irq(port, IMR_TXRDY); 357 358 /* Set direction to input */ 359 if (s->flags & SCCNXP_HAVE_IO) 360 sccnxp_set_bit(port, DIR_OP, 0); 361 } 362 return; 363 } 364 365 while (!uart_circ_empty(xmit)) { 366 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 367 if (!(sr & SR_TXRDY)) 368 break; 369 370 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 371 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 372 port->icount.tx++; 373 } 374 375 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 376 uart_write_wakeup(port); 377 } 378 379 static void sccnxp_handle_events(struct sccnxp_port *s) 380 { 381 int i; 382 u8 isr; 383 384 do { 385 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 386 isr &= s->imr; 387 if (!isr) 388 break; 389 390 for (i = 0; i < s->uart.nr; i++) { 391 if (s->opened[i] && (isr & ISR_RXRDY(i))) 392 sccnxp_handle_rx(&s->port[i]); 393 if (s->opened[i] && (isr & ISR_TXRDY(i))) 394 sccnxp_handle_tx(&s->port[i]); 395 } 396 } while (1); 397 } 398 399 static void sccnxp_timer(unsigned long data) 400 { 401 struct sccnxp_port *s = (struct sccnxp_port *)data; 402 unsigned long flags; 403 404 spin_lock_irqsave(&s->lock, flags); 405 sccnxp_handle_events(s); 406 spin_unlock_irqrestore(&s->lock, flags); 407 408 if (!timer_pending(&s->timer)) 409 mod_timer(&s->timer, jiffies + 410 usecs_to_jiffies(s->pdata.poll_time_us)); 411 } 412 413 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 414 { 415 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 416 unsigned long flags; 417 418 spin_lock_irqsave(&s->lock, flags); 419 sccnxp_handle_events(s); 420 spin_unlock_irqrestore(&s->lock, flags); 421 422 return IRQ_HANDLED; 423 } 424 425 static void sccnxp_start_tx(struct uart_port *port) 426 { 427 struct sccnxp_port *s = dev_get_drvdata(port->dev); 428 unsigned long flags; 429 430 spin_lock_irqsave(&s->lock, flags); 431 432 /* Set direction to output */ 433 if (s->flags & SCCNXP_HAVE_IO) 434 sccnxp_set_bit(port, DIR_OP, 1); 435 436 sccnxp_enable_irq(port, IMR_TXRDY); 437 438 spin_unlock_irqrestore(&s->lock, flags); 439 } 440 441 static void sccnxp_stop_tx(struct uart_port *port) 442 { 443 /* Do nothing */ 444 } 445 446 static void sccnxp_stop_rx(struct uart_port *port) 447 { 448 struct sccnxp_port *s = dev_get_drvdata(port->dev); 449 unsigned long flags; 450 451 spin_lock_irqsave(&s->lock, flags); 452 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 453 spin_unlock_irqrestore(&s->lock, flags); 454 } 455 456 static unsigned int sccnxp_tx_empty(struct uart_port *port) 457 { 458 u8 val; 459 unsigned long flags; 460 struct sccnxp_port *s = dev_get_drvdata(port->dev); 461 462 spin_lock_irqsave(&s->lock, flags); 463 val = sccnxp_port_read(port, SCCNXP_SR_REG); 464 spin_unlock_irqrestore(&s->lock, flags); 465 466 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 467 } 468 469 static void sccnxp_enable_ms(struct uart_port *port) 470 { 471 /* Do nothing */ 472 } 473 474 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 475 { 476 struct sccnxp_port *s = dev_get_drvdata(port->dev); 477 unsigned long flags; 478 479 if (!(s->flags & SCCNXP_HAVE_IO)) 480 return; 481 482 spin_lock_irqsave(&s->lock, flags); 483 484 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 485 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 486 487 spin_unlock_irqrestore(&s->lock, flags); 488 } 489 490 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 491 { 492 u8 bitmask, ipr; 493 unsigned long flags; 494 struct sccnxp_port *s = dev_get_drvdata(port->dev); 495 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 496 497 if (!(s->flags & SCCNXP_HAVE_IO)) 498 return mctrl; 499 500 spin_lock_irqsave(&s->lock, flags); 501 502 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 503 504 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 505 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 506 DSR_IP); 507 mctrl &= ~TIOCM_DSR; 508 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 509 } 510 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 511 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 512 CTS_IP); 513 mctrl &= ~TIOCM_CTS; 514 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 515 } 516 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 517 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 518 DCD_IP); 519 mctrl &= ~TIOCM_CAR; 520 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 521 } 522 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 523 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 524 RNG_IP); 525 mctrl &= ~TIOCM_RNG; 526 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 527 } 528 529 spin_unlock_irqrestore(&s->lock, flags); 530 531 return mctrl; 532 } 533 534 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 535 { 536 struct sccnxp_port *s = dev_get_drvdata(port->dev); 537 unsigned long flags; 538 539 spin_lock_irqsave(&s->lock, flags); 540 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 541 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 542 spin_unlock_irqrestore(&s->lock, flags); 543 } 544 545 static void sccnxp_set_termios(struct uart_port *port, 546 struct ktermios *termios, struct ktermios *old) 547 { 548 struct sccnxp_port *s = dev_get_drvdata(port->dev); 549 unsigned long flags; 550 u8 mr1, mr2; 551 int baud; 552 553 spin_lock_irqsave(&s->lock, flags); 554 555 /* Mask termios capabilities we don't support */ 556 termios->c_cflag &= ~CMSPAR; 557 558 /* Disable RX & TX, reset break condition, status and FIFOs */ 559 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 560 CR_RX_DISABLE | CR_TX_DISABLE); 561 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 562 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 563 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 564 565 /* Word size */ 566 switch (termios->c_cflag & CSIZE) { 567 case CS5: 568 mr1 = MR1_BITS_5; 569 break; 570 case CS6: 571 mr1 = MR1_BITS_6; 572 break; 573 case CS7: 574 mr1 = MR1_BITS_7; 575 break; 576 case CS8: 577 default: 578 mr1 = MR1_BITS_8; 579 break; 580 } 581 582 /* Parity */ 583 if (termios->c_cflag & PARENB) { 584 if (termios->c_cflag & PARODD) 585 mr1 |= MR1_PAR_ODD; 586 } else 587 mr1 |= MR1_PAR_NO; 588 589 /* Stop bits */ 590 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 591 592 /* Update desired format */ 593 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 594 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 595 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 596 597 /* Set read status mask */ 598 port->read_status_mask = SR_OVR; 599 if (termios->c_iflag & INPCK) 600 port->read_status_mask |= SR_PE | SR_FE; 601 if (termios->c_iflag & (BRKINT | PARMRK)) 602 port->read_status_mask |= SR_BRK; 603 604 /* Set status ignore mask */ 605 port->ignore_status_mask = 0; 606 if (termios->c_iflag & IGNBRK) 607 port->ignore_status_mask |= SR_BRK; 608 if (!(termios->c_cflag & CREAD)) 609 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 610 611 /* Setup baudrate */ 612 baud = uart_get_baud_rate(port, termios, old, 50, 613 (s->flags & SCCNXP_HAVE_MR0) ? 614 230400 : 38400); 615 baud = sccnxp_set_baud(port, baud); 616 617 /* Update timeout according to new baud rate */ 618 uart_update_timeout(port, termios->c_cflag, baud); 619 620 /* Report actual baudrate back to core */ 621 if (tty_termios_baud_rate(termios)) 622 tty_termios_encode_baud_rate(termios, baud, baud); 623 624 /* Enable RX & TX */ 625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 626 627 spin_unlock_irqrestore(&s->lock, flags); 628 } 629 630 static int sccnxp_startup(struct uart_port *port) 631 { 632 struct sccnxp_port *s = dev_get_drvdata(port->dev); 633 unsigned long flags; 634 635 spin_lock_irqsave(&s->lock, flags); 636 637 if (s->flags & SCCNXP_HAVE_IO) { 638 /* Outputs are controlled manually */ 639 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 640 } 641 642 /* Reset break condition, status and FIFOs */ 643 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 644 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 645 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 646 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 647 648 /* Enable RX & TX */ 649 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 650 651 /* Enable RX interrupt */ 652 sccnxp_enable_irq(port, IMR_RXRDY); 653 654 s->opened[port->line] = 1; 655 656 spin_unlock_irqrestore(&s->lock, flags); 657 658 return 0; 659 } 660 661 static void sccnxp_shutdown(struct uart_port *port) 662 { 663 struct sccnxp_port *s = dev_get_drvdata(port->dev); 664 unsigned long flags; 665 666 spin_lock_irqsave(&s->lock, flags); 667 668 s->opened[port->line] = 0; 669 670 /* Disable interrupts */ 671 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 672 673 /* Disable TX & RX */ 674 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 675 676 /* Leave direction to input */ 677 if (s->flags & SCCNXP_HAVE_IO) 678 sccnxp_set_bit(port, DIR_OP, 0); 679 680 spin_unlock_irqrestore(&s->lock, flags); 681 } 682 683 static const char *sccnxp_type(struct uart_port *port) 684 { 685 struct sccnxp_port *s = dev_get_drvdata(port->dev); 686 687 return (port->type == PORT_SC26XX) ? s->name : NULL; 688 } 689 690 static void sccnxp_release_port(struct uart_port *port) 691 { 692 /* Do nothing */ 693 } 694 695 static int sccnxp_request_port(struct uart_port *port) 696 { 697 /* Do nothing */ 698 return 0; 699 } 700 701 static void sccnxp_config_port(struct uart_port *port, int flags) 702 { 703 if (flags & UART_CONFIG_TYPE) 704 port->type = PORT_SC26XX; 705 } 706 707 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 708 { 709 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 710 return 0; 711 if (s->irq == port->irq) 712 return 0; 713 714 return -EINVAL; 715 } 716 717 static const struct uart_ops sccnxp_ops = { 718 .tx_empty = sccnxp_tx_empty, 719 .set_mctrl = sccnxp_set_mctrl, 720 .get_mctrl = sccnxp_get_mctrl, 721 .stop_tx = sccnxp_stop_tx, 722 .start_tx = sccnxp_start_tx, 723 .stop_rx = sccnxp_stop_rx, 724 .enable_ms = sccnxp_enable_ms, 725 .break_ctl = sccnxp_break_ctl, 726 .startup = sccnxp_startup, 727 .shutdown = sccnxp_shutdown, 728 .set_termios = sccnxp_set_termios, 729 .type = sccnxp_type, 730 .release_port = sccnxp_release_port, 731 .request_port = sccnxp_request_port, 732 .config_port = sccnxp_config_port, 733 .verify_port = sccnxp_verify_port, 734 }; 735 736 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 737 static void sccnxp_console_putchar(struct uart_port *port, int c) 738 { 739 int tryes = 100000; 740 741 while (tryes--) { 742 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 743 sccnxp_port_write(port, SCCNXP_THR_REG, c); 744 break; 745 } 746 barrier(); 747 } 748 } 749 750 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 751 { 752 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 753 struct uart_port *port = &s->port[co->index]; 754 unsigned long flags; 755 756 spin_lock_irqsave(&s->lock, flags); 757 uart_console_write(port, c, n, sccnxp_console_putchar); 758 spin_unlock_irqrestore(&s->lock, flags); 759 } 760 761 static int sccnxp_console_setup(struct console *co, char *options) 762 { 763 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 764 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 765 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 766 767 if (options) 768 uart_parse_options(options, &baud, &parity, &bits, &flow); 769 770 return uart_set_options(port, co, baud, parity, bits, flow); 771 } 772 #endif 773 774 static int sccnxp_probe(struct platform_device *pdev) 775 { 776 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 777 int chiptype = pdev->id_entry->driver_data; 778 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 779 int i, ret, fifosize, freq_min, freq_max; 780 struct sccnxp_port *s; 781 void __iomem *membase; 782 783 if (!res) { 784 dev_err(&pdev->dev, "Missing memory resource data\n"); 785 return -EADDRNOTAVAIL; 786 } 787 788 dev_set_name(&pdev->dev, SCCNXP_NAME); 789 790 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 791 if (!s) { 792 dev_err(&pdev->dev, "Error allocating port structure\n"); 793 return -ENOMEM; 794 } 795 platform_set_drvdata(pdev, s); 796 797 spin_lock_init(&s->lock); 798 799 /* Individual chip settings */ 800 switch (chiptype) { 801 case SCCNXP_TYPE_SC2681: 802 s->name = "SC2681"; 803 s->uart.nr = 2; 804 s->freq_std = 3686400; 805 s->addr_mask = 0x0f; 806 s->flags = SCCNXP_HAVE_IO; 807 fifosize = 3; 808 freq_min = 1000000; 809 freq_max = 4000000; 810 break; 811 case SCCNXP_TYPE_SC2691: 812 s->name = "SC2691"; 813 s->uart.nr = 1; 814 s->freq_std = 3686400; 815 s->addr_mask = 0x07; 816 s->flags = 0; 817 fifosize = 3; 818 freq_min = 1000000; 819 freq_max = 4000000; 820 break; 821 case SCCNXP_TYPE_SC2692: 822 s->name = "SC2692"; 823 s->uart.nr = 2; 824 s->freq_std = 3686400; 825 s->addr_mask = 0x0f; 826 s->flags = SCCNXP_HAVE_IO; 827 fifosize = 3; 828 freq_min = 1000000; 829 freq_max = 4000000; 830 break; 831 case SCCNXP_TYPE_SC2891: 832 s->name = "SC2891"; 833 s->uart.nr = 1; 834 s->freq_std = 3686400; 835 s->addr_mask = 0x0f; 836 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 837 fifosize = 16; 838 freq_min = 100000; 839 freq_max = 8000000; 840 break; 841 case SCCNXP_TYPE_SC2892: 842 s->name = "SC2892"; 843 s->uart.nr = 2; 844 s->freq_std = 3686400; 845 s->addr_mask = 0x0f; 846 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 847 fifosize = 16; 848 freq_min = 100000; 849 freq_max = 8000000; 850 break; 851 case SCCNXP_TYPE_SC28202: 852 s->name = "SC28202"; 853 s->uart.nr = 2; 854 s->freq_std = 14745600; 855 s->addr_mask = 0x7f; 856 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 857 fifosize = 256; 858 freq_min = 1000000; 859 freq_max = 50000000; 860 break; 861 case SCCNXP_TYPE_SC68681: 862 s->name = "SC68681"; 863 s->uart.nr = 2; 864 s->freq_std = 3686400; 865 s->addr_mask = 0x0f; 866 s->flags = SCCNXP_HAVE_IO; 867 fifosize = 3; 868 freq_min = 1000000; 869 freq_max = 4000000; 870 break; 871 case SCCNXP_TYPE_SC68692: 872 s->name = "SC68692"; 873 s->uart.nr = 2; 874 s->freq_std = 3686400; 875 s->addr_mask = 0x0f; 876 s->flags = SCCNXP_HAVE_IO; 877 fifosize = 3; 878 freq_min = 1000000; 879 freq_max = 4000000; 880 break; 881 default: 882 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype); 883 ret = -ENOTSUPP; 884 goto err_out; 885 } 886 887 if (!pdata) { 888 dev_warn(&pdev->dev, 889 "No platform data supplied, using defaults\n"); 890 s->pdata.frequency = s->freq_std; 891 } else 892 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 893 894 if (s->pdata.poll_time_us) { 895 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 896 s->pdata.poll_time_us); 897 s->poll = 1; 898 } 899 900 if (!s->poll) { 901 s->irq = platform_get_irq(pdev, 0); 902 if (s->irq < 0) { 903 dev_err(&pdev->dev, "Missing irq resource data\n"); 904 ret = -ENXIO; 905 goto err_out; 906 } 907 } 908 909 /* Check input frequency */ 910 if ((s->pdata.frequency < freq_min) || 911 (s->pdata.frequency > freq_max)) { 912 dev_err(&pdev->dev, "Frequency out of bounds\n"); 913 ret = -EINVAL; 914 goto err_out; 915 } 916 917 membase = devm_request_and_ioremap(&pdev->dev, res); 918 if (!membase) { 919 dev_err(&pdev->dev, "Failed to ioremap\n"); 920 ret = -EIO; 921 goto err_out; 922 } 923 924 s->uart.owner = THIS_MODULE; 925 s->uart.dev_name = "ttySC"; 926 s->uart.major = SCCNXP_MAJOR; 927 s->uart.minor = SCCNXP_MINOR; 928 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 929 s->uart.cons = &s->console; 930 s->uart.cons->device = uart_console_device; 931 s->uart.cons->write = sccnxp_console_write; 932 s->uart.cons->setup = sccnxp_console_setup; 933 s->uart.cons->flags = CON_PRINTBUFFER; 934 s->uart.cons->index = -1; 935 s->uart.cons->data = s; 936 strcpy(s->uart.cons->name, "ttySC"); 937 #endif 938 ret = uart_register_driver(&s->uart); 939 if (ret) { 940 dev_err(&pdev->dev, "Registering UART driver failed\n"); 941 goto err_out; 942 } 943 944 for (i = 0; i < s->uart.nr; i++) { 945 s->port[i].line = i; 946 s->port[i].dev = &pdev->dev; 947 s->port[i].irq = s->irq; 948 s->port[i].type = PORT_SC26XX; 949 s->port[i].fifosize = fifosize; 950 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 951 s->port[i].iotype = UPIO_MEM; 952 s->port[i].mapbase = res->start; 953 s->port[i].membase = membase; 954 s->port[i].regshift = s->pdata.reg_shift; 955 s->port[i].uartclk = s->pdata.frequency; 956 s->port[i].ops = &sccnxp_ops; 957 uart_add_one_port(&s->uart, &s->port[i]); 958 /* Set direction to input */ 959 if (s->flags & SCCNXP_HAVE_IO) 960 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 961 } 962 963 /* Disable interrupts */ 964 s->imr = 0; 965 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 966 967 /* Board specific configure */ 968 if (s->pdata.init) 969 s->pdata.init(); 970 971 if (!s->poll) { 972 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 973 sccnxp_ist, 974 IRQF_TRIGGER_FALLING | 975 IRQF_ONESHOT, 976 dev_name(&pdev->dev), s); 977 if (!ret) 978 return 0; 979 980 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 981 } else { 982 init_timer(&s->timer); 983 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 984 mod_timer(&s->timer, jiffies + 985 usecs_to_jiffies(s->pdata.poll_time_us)); 986 return 0; 987 } 988 989 err_out: 990 platform_set_drvdata(pdev, NULL); 991 992 return ret; 993 } 994 995 static int sccnxp_remove(struct platform_device *pdev) 996 { 997 int i; 998 struct sccnxp_port *s = platform_get_drvdata(pdev); 999 1000 if (!s->poll) 1001 devm_free_irq(&pdev->dev, s->irq, s); 1002 else 1003 del_timer_sync(&s->timer); 1004 1005 for (i = 0; i < s->uart.nr; i++) 1006 uart_remove_one_port(&s->uart, &s->port[i]); 1007 1008 uart_unregister_driver(&s->uart); 1009 platform_set_drvdata(pdev, NULL); 1010 1011 if (s->pdata.exit) 1012 s->pdata.exit(); 1013 1014 return 0; 1015 } 1016 1017 static const struct platform_device_id sccnxp_id_table[] = { 1018 { "sc2681", SCCNXP_TYPE_SC2681 }, 1019 { "sc2691", SCCNXP_TYPE_SC2691 }, 1020 { "sc2692", SCCNXP_TYPE_SC2692 }, 1021 { "sc2891", SCCNXP_TYPE_SC2891 }, 1022 { "sc2892", SCCNXP_TYPE_SC2892 }, 1023 { "sc28202", SCCNXP_TYPE_SC28202 }, 1024 { "sc68681", SCCNXP_TYPE_SC68681 }, 1025 { "sc68692", SCCNXP_TYPE_SC68692 }, 1026 { }, 1027 }; 1028 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 1029 1030 static struct platform_driver sccnxp_uart_driver = { 1031 .driver = { 1032 .name = SCCNXP_NAME, 1033 .owner = THIS_MODULE, 1034 }, 1035 .probe = sccnxp_probe, 1036 .remove = sccnxp_remove, 1037 .id_table = sccnxp_id_table, 1038 }; 1039 module_platform_driver(sccnxp_uart_driver); 1040 1041 MODULE_LICENSE("GPL v2"); 1042 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1043 MODULE_DESCRIPTION("SCCNXP serial driver"); 1044