1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/err.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/io.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/spinlock.h> 28 #include <linux/platform_device.h> 29 #include <linux/platform_data/serial-sccnxp.h> 30 31 #define SCCNXP_NAME "uart-sccnxp" 32 #define SCCNXP_MAJOR 204 33 #define SCCNXP_MINOR 205 34 35 #define SCCNXP_MR_REG (0x00) 36 # define MR0_BAUD_NORMAL (0 << 0) 37 # define MR0_BAUD_EXT1 (1 << 0) 38 # define MR0_BAUD_EXT2 (5 << 0) 39 # define MR0_FIFO (1 << 3) 40 # define MR0_TXLVL (1 << 4) 41 # define MR1_BITS_5 (0 << 0) 42 # define MR1_BITS_6 (1 << 0) 43 # define MR1_BITS_7 (2 << 0) 44 # define MR1_BITS_8 (3 << 0) 45 # define MR1_PAR_EVN (0 << 2) 46 # define MR1_PAR_ODD (1 << 2) 47 # define MR1_PAR_NO (4 << 2) 48 # define MR2_STOP1 (7 << 0) 49 # define MR2_STOP2 (0xf << 0) 50 #define SCCNXP_SR_REG (0x01) 51 #define SCCNXP_CSR_REG SCCNXP_SR_REG 52 # define SR_RXRDY (1 << 0) 53 # define SR_FULL (1 << 1) 54 # define SR_TXRDY (1 << 2) 55 # define SR_TXEMT (1 << 3) 56 # define SR_OVR (1 << 4) 57 # define SR_PE (1 << 5) 58 # define SR_FE (1 << 6) 59 # define SR_BRK (1 << 7) 60 #define SCCNXP_CR_REG (0x02) 61 # define CR_RX_ENABLE (1 << 0) 62 # define CR_RX_DISABLE (1 << 1) 63 # define CR_TX_ENABLE (1 << 2) 64 # define CR_TX_DISABLE (1 << 3) 65 # define CR_CMD_MRPTR1 (0x01 << 4) 66 # define CR_CMD_RX_RESET (0x02 << 4) 67 # define CR_CMD_TX_RESET (0x03 << 4) 68 # define CR_CMD_STATUS_RESET (0x04 << 4) 69 # define CR_CMD_BREAK_RESET (0x05 << 4) 70 # define CR_CMD_START_BREAK (0x06 << 4) 71 # define CR_CMD_STOP_BREAK (0x07 << 4) 72 # define CR_CMD_MRPTR0 (0x0b << 4) 73 #define SCCNXP_RHR_REG (0x03) 74 #define SCCNXP_THR_REG SCCNXP_RHR_REG 75 #define SCCNXP_IPCR_REG (0x04) 76 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 77 # define ACR_BAUD0 (0 << 7) 78 # define ACR_BAUD1 (1 << 7) 79 # define ACR_TIMER_MODE (6 << 4) 80 #define SCCNXP_ISR_REG (0x05) 81 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 82 # define IMR_TXRDY (1 << 0) 83 # define IMR_RXRDY (1 << 1) 84 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 85 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 86 #define SCCNXP_IPR_REG (0x0d) 87 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 88 #define SCCNXP_SOP_REG (0x0e) 89 #define SCCNXP_ROP_REG (0x0f) 90 91 /* Route helpers */ 92 #define MCTRL_MASK(sig) (0xf << (sig)) 93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 95 96 /* Supported chip types */ 97 enum { 98 SCCNXP_TYPE_SC2681 = 2681, 99 SCCNXP_TYPE_SC2691 = 2691, 100 SCCNXP_TYPE_SC2692 = 2692, 101 SCCNXP_TYPE_SC2891 = 2891, 102 SCCNXP_TYPE_SC2892 = 2892, 103 SCCNXP_TYPE_SC28202 = 28202, 104 SCCNXP_TYPE_SC68681 = 68681, 105 SCCNXP_TYPE_SC68692 = 68692, 106 }; 107 108 struct sccnxp_port { 109 struct uart_driver uart; 110 struct uart_port port[SCCNXP_MAX_UARTS]; 111 bool opened[SCCNXP_MAX_UARTS]; 112 113 const char *name; 114 int irq; 115 116 u8 imr; 117 u8 addr_mask; 118 int freq_std; 119 120 int flags; 121 #define SCCNXP_HAVE_IO 0x00000001 122 #define SCCNXP_HAVE_MR0 0x00000002 123 124 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 125 struct console console; 126 #endif 127 128 spinlock_t lock; 129 130 bool poll; 131 struct timer_list timer; 132 133 struct sccnxp_pdata pdata; 134 }; 135 136 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 137 { 138 return readb(base + (reg << shift)); 139 } 140 141 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 142 { 143 writeb(v, base + (reg << shift)); 144 } 145 146 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 147 { 148 struct sccnxp_port *s = dev_get_drvdata(port->dev); 149 150 return sccnxp_raw_read(port->membase, reg & s->addr_mask, 151 port->regshift); 152 } 153 154 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 155 { 156 struct sccnxp_port *s = dev_get_drvdata(port->dev); 157 158 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v); 159 } 160 161 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 162 { 163 return sccnxp_read(port, (port->line << 3) + reg); 164 } 165 166 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 167 { 168 sccnxp_write(port, (port->line << 3) + reg, v); 169 } 170 171 static int sccnxp_update_best_err(int a, int b, int *besterr) 172 { 173 int err = abs(a - b); 174 175 if ((*besterr < 0) || (*besterr > err)) { 176 *besterr = err; 177 return 0; 178 } 179 180 return 1; 181 } 182 183 static const struct { 184 u8 csr; 185 u8 acr; 186 u8 mr0; 187 int baud; 188 } baud_std[] = { 189 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 190 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 191 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 192 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 193 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 194 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 195 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 196 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 197 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 198 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 199 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 200 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 201 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 202 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 203 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 204 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 205 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 206 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 207 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 208 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 209 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 210 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 211 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 212 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 213 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 214 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 215 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 216 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 217 { 0, 0, 0, 0 } 218 }; 219 220 static int sccnxp_set_baud(struct uart_port *port, int baud) 221 { 222 struct sccnxp_port *s = dev_get_drvdata(port->dev); 223 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 224 u8 i, acr = 0, csr = 0, mr0 = 0; 225 226 /* Find best baud from table */ 227 for (i = 0; baud_std[i].baud && besterr; i++) { 228 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 229 continue; 230 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 231 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 232 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 233 acr = baud_std[i].acr; 234 csr = baud_std[i].csr; 235 mr0 = baud_std[i].mr0; 236 bestbaud = tmp_baud; 237 } 238 } 239 240 if (s->flags & SCCNXP_HAVE_MR0) { 241 /* Enable FIFO, set half level for TX */ 242 mr0 |= MR0_FIFO | MR0_TXLVL; 243 /* Update MR0 */ 244 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 245 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 246 } 247 248 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 249 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 250 251 if (baud != bestbaud) 252 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 253 baud, bestbaud); 254 255 return bestbaud; 256 } 257 258 static void sccnxp_enable_irq(struct uart_port *port, int mask) 259 { 260 struct sccnxp_port *s = dev_get_drvdata(port->dev); 261 262 s->imr |= mask << (port->line * 4); 263 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 264 } 265 266 static void sccnxp_disable_irq(struct uart_port *port, int mask) 267 { 268 struct sccnxp_port *s = dev_get_drvdata(port->dev); 269 270 s->imr &= ~(mask << (port->line * 4)); 271 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 272 } 273 274 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 275 { 276 u8 bitmask; 277 struct sccnxp_port *s = dev_get_drvdata(port->dev); 278 279 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 280 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 281 if (state) 282 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 283 else 284 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 285 } 286 } 287 288 static void sccnxp_handle_rx(struct uart_port *port) 289 { 290 u8 sr; 291 unsigned int ch, flag; 292 293 for (;;) { 294 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 295 if (!(sr & SR_RXRDY)) 296 break; 297 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 298 299 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 300 301 port->icount.rx++; 302 flag = TTY_NORMAL; 303 304 if (unlikely(sr)) { 305 if (sr & SR_BRK) { 306 port->icount.brk++; 307 sccnxp_port_write(port, SCCNXP_CR_REG, 308 CR_CMD_BREAK_RESET); 309 if (uart_handle_break(port)) 310 continue; 311 } else if (sr & SR_PE) 312 port->icount.parity++; 313 else if (sr & SR_FE) 314 port->icount.frame++; 315 else if (sr & SR_OVR) { 316 port->icount.overrun++; 317 sccnxp_port_write(port, SCCNXP_CR_REG, 318 CR_CMD_STATUS_RESET); 319 } 320 321 sr &= port->read_status_mask; 322 if (sr & SR_BRK) 323 flag = TTY_BREAK; 324 else if (sr & SR_PE) 325 flag = TTY_PARITY; 326 else if (sr & SR_FE) 327 flag = TTY_FRAME; 328 else if (sr & SR_OVR) 329 flag = TTY_OVERRUN; 330 } 331 332 if (uart_handle_sysrq_char(port, ch)) 333 continue; 334 335 if (sr & port->ignore_status_mask) 336 continue; 337 338 uart_insert_char(port, sr, SR_OVR, ch, flag); 339 } 340 341 tty_flip_buffer_push(&port->state->port); 342 } 343 344 static void sccnxp_handle_tx(struct uart_port *port) 345 { 346 u8 sr; 347 struct circ_buf *xmit = &port->state->xmit; 348 struct sccnxp_port *s = dev_get_drvdata(port->dev); 349 350 if (unlikely(port->x_char)) { 351 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 352 port->icount.tx++; 353 port->x_char = 0; 354 return; 355 } 356 357 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 358 /* Disable TX if FIFO is empty */ 359 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 360 sccnxp_disable_irq(port, IMR_TXRDY); 361 362 /* Set direction to input */ 363 if (s->flags & SCCNXP_HAVE_IO) 364 sccnxp_set_bit(port, DIR_OP, 0); 365 } 366 return; 367 } 368 369 while (!uart_circ_empty(xmit)) { 370 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 371 if (!(sr & SR_TXRDY)) 372 break; 373 374 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 375 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 376 port->icount.tx++; 377 } 378 379 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 380 uart_write_wakeup(port); 381 } 382 383 static void sccnxp_handle_events(struct sccnxp_port *s) 384 { 385 int i; 386 u8 isr; 387 388 do { 389 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 390 isr &= s->imr; 391 if (!isr) 392 break; 393 394 for (i = 0; i < s->uart.nr; i++) { 395 if (s->opened[i] && (isr & ISR_RXRDY(i))) 396 sccnxp_handle_rx(&s->port[i]); 397 if (s->opened[i] && (isr & ISR_TXRDY(i))) 398 sccnxp_handle_tx(&s->port[i]); 399 } 400 } while (1); 401 } 402 403 static void sccnxp_timer(unsigned long data) 404 { 405 struct sccnxp_port *s = (struct sccnxp_port *)data; 406 unsigned long flags; 407 408 spin_lock_irqsave(&s->lock, flags); 409 sccnxp_handle_events(s); 410 spin_unlock_irqrestore(&s->lock, flags); 411 412 if (!timer_pending(&s->timer)) 413 mod_timer(&s->timer, jiffies + 414 usecs_to_jiffies(s->pdata.poll_time_us)); 415 } 416 417 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 418 { 419 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 420 unsigned long flags; 421 422 spin_lock_irqsave(&s->lock, flags); 423 sccnxp_handle_events(s); 424 spin_unlock_irqrestore(&s->lock, flags); 425 426 return IRQ_HANDLED; 427 } 428 429 static void sccnxp_start_tx(struct uart_port *port) 430 { 431 struct sccnxp_port *s = dev_get_drvdata(port->dev); 432 unsigned long flags; 433 434 spin_lock_irqsave(&s->lock, flags); 435 436 /* Set direction to output */ 437 if (s->flags & SCCNXP_HAVE_IO) 438 sccnxp_set_bit(port, DIR_OP, 1); 439 440 sccnxp_enable_irq(port, IMR_TXRDY); 441 442 spin_unlock_irqrestore(&s->lock, flags); 443 } 444 445 static void sccnxp_stop_tx(struct uart_port *port) 446 { 447 /* Do nothing */ 448 } 449 450 static void sccnxp_stop_rx(struct uart_port *port) 451 { 452 struct sccnxp_port *s = dev_get_drvdata(port->dev); 453 unsigned long flags; 454 455 spin_lock_irqsave(&s->lock, flags); 456 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 457 spin_unlock_irqrestore(&s->lock, flags); 458 } 459 460 static unsigned int sccnxp_tx_empty(struct uart_port *port) 461 { 462 u8 val; 463 unsigned long flags; 464 struct sccnxp_port *s = dev_get_drvdata(port->dev); 465 466 spin_lock_irqsave(&s->lock, flags); 467 val = sccnxp_port_read(port, SCCNXP_SR_REG); 468 spin_unlock_irqrestore(&s->lock, flags); 469 470 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 471 } 472 473 static void sccnxp_enable_ms(struct uart_port *port) 474 { 475 /* Do nothing */ 476 } 477 478 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 479 { 480 struct sccnxp_port *s = dev_get_drvdata(port->dev); 481 unsigned long flags; 482 483 if (!(s->flags & SCCNXP_HAVE_IO)) 484 return; 485 486 spin_lock_irqsave(&s->lock, flags); 487 488 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 489 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 490 491 spin_unlock_irqrestore(&s->lock, flags); 492 } 493 494 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 495 { 496 u8 bitmask, ipr; 497 unsigned long flags; 498 struct sccnxp_port *s = dev_get_drvdata(port->dev); 499 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 500 501 if (!(s->flags & SCCNXP_HAVE_IO)) 502 return mctrl; 503 504 spin_lock_irqsave(&s->lock, flags); 505 506 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 507 508 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 509 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 510 DSR_IP); 511 mctrl &= ~TIOCM_DSR; 512 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 513 } 514 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 515 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 516 CTS_IP); 517 mctrl &= ~TIOCM_CTS; 518 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 519 } 520 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 521 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 522 DCD_IP); 523 mctrl &= ~TIOCM_CAR; 524 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 525 } 526 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 527 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 528 RNG_IP); 529 mctrl &= ~TIOCM_RNG; 530 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 531 } 532 533 spin_unlock_irqrestore(&s->lock, flags); 534 535 return mctrl; 536 } 537 538 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 539 { 540 struct sccnxp_port *s = dev_get_drvdata(port->dev); 541 unsigned long flags; 542 543 spin_lock_irqsave(&s->lock, flags); 544 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 545 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 546 spin_unlock_irqrestore(&s->lock, flags); 547 } 548 549 static void sccnxp_set_termios(struct uart_port *port, 550 struct ktermios *termios, struct ktermios *old) 551 { 552 struct sccnxp_port *s = dev_get_drvdata(port->dev); 553 unsigned long flags; 554 u8 mr1, mr2; 555 int baud; 556 557 spin_lock_irqsave(&s->lock, flags); 558 559 /* Mask termios capabilities we don't support */ 560 termios->c_cflag &= ~CMSPAR; 561 562 /* Disable RX & TX, reset break condition, status and FIFOs */ 563 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 564 CR_RX_DISABLE | CR_TX_DISABLE); 565 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 566 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 567 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 568 569 /* Word size */ 570 switch (termios->c_cflag & CSIZE) { 571 case CS5: 572 mr1 = MR1_BITS_5; 573 break; 574 case CS6: 575 mr1 = MR1_BITS_6; 576 break; 577 case CS7: 578 mr1 = MR1_BITS_7; 579 break; 580 case CS8: 581 default: 582 mr1 = MR1_BITS_8; 583 break; 584 } 585 586 /* Parity */ 587 if (termios->c_cflag & PARENB) { 588 if (termios->c_cflag & PARODD) 589 mr1 |= MR1_PAR_ODD; 590 } else 591 mr1 |= MR1_PAR_NO; 592 593 /* Stop bits */ 594 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 595 596 /* Update desired format */ 597 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 598 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 599 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 600 601 /* Set read status mask */ 602 port->read_status_mask = SR_OVR; 603 if (termios->c_iflag & INPCK) 604 port->read_status_mask |= SR_PE | SR_FE; 605 if (termios->c_iflag & (BRKINT | PARMRK)) 606 port->read_status_mask |= SR_BRK; 607 608 /* Set status ignore mask */ 609 port->ignore_status_mask = 0; 610 if (termios->c_iflag & IGNBRK) 611 port->ignore_status_mask |= SR_BRK; 612 if (!(termios->c_cflag & CREAD)) 613 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 614 615 /* Setup baudrate */ 616 baud = uart_get_baud_rate(port, termios, old, 50, 617 (s->flags & SCCNXP_HAVE_MR0) ? 618 230400 : 38400); 619 baud = sccnxp_set_baud(port, baud); 620 621 /* Update timeout according to new baud rate */ 622 uart_update_timeout(port, termios->c_cflag, baud); 623 624 /* Report actual baudrate back to core */ 625 if (tty_termios_baud_rate(termios)) 626 tty_termios_encode_baud_rate(termios, baud, baud); 627 628 /* Enable RX & TX */ 629 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 630 631 spin_unlock_irqrestore(&s->lock, flags); 632 } 633 634 static int sccnxp_startup(struct uart_port *port) 635 { 636 struct sccnxp_port *s = dev_get_drvdata(port->dev); 637 unsigned long flags; 638 639 spin_lock_irqsave(&s->lock, flags); 640 641 if (s->flags & SCCNXP_HAVE_IO) { 642 /* Outputs are controlled manually */ 643 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 644 } 645 646 /* Reset break condition, status and FIFOs */ 647 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 648 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 649 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 650 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 651 652 /* Enable RX & TX */ 653 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 654 655 /* Enable RX interrupt */ 656 sccnxp_enable_irq(port, IMR_RXRDY); 657 658 s->opened[port->line] = 1; 659 660 spin_unlock_irqrestore(&s->lock, flags); 661 662 return 0; 663 } 664 665 static void sccnxp_shutdown(struct uart_port *port) 666 { 667 struct sccnxp_port *s = dev_get_drvdata(port->dev); 668 unsigned long flags; 669 670 spin_lock_irqsave(&s->lock, flags); 671 672 s->opened[port->line] = 0; 673 674 /* Disable interrupts */ 675 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 676 677 /* Disable TX & RX */ 678 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 679 680 /* Leave direction to input */ 681 if (s->flags & SCCNXP_HAVE_IO) 682 sccnxp_set_bit(port, DIR_OP, 0); 683 684 spin_unlock_irqrestore(&s->lock, flags); 685 } 686 687 static const char *sccnxp_type(struct uart_port *port) 688 { 689 struct sccnxp_port *s = dev_get_drvdata(port->dev); 690 691 return (port->type == PORT_SC26XX) ? s->name : NULL; 692 } 693 694 static void sccnxp_release_port(struct uart_port *port) 695 { 696 /* Do nothing */ 697 } 698 699 static int sccnxp_request_port(struct uart_port *port) 700 { 701 /* Do nothing */ 702 return 0; 703 } 704 705 static void sccnxp_config_port(struct uart_port *port, int flags) 706 { 707 if (flags & UART_CONFIG_TYPE) 708 port->type = PORT_SC26XX; 709 } 710 711 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 712 { 713 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 714 return 0; 715 if (s->irq == port->irq) 716 return 0; 717 718 return -EINVAL; 719 } 720 721 static const struct uart_ops sccnxp_ops = { 722 .tx_empty = sccnxp_tx_empty, 723 .set_mctrl = sccnxp_set_mctrl, 724 .get_mctrl = sccnxp_get_mctrl, 725 .stop_tx = sccnxp_stop_tx, 726 .start_tx = sccnxp_start_tx, 727 .stop_rx = sccnxp_stop_rx, 728 .enable_ms = sccnxp_enable_ms, 729 .break_ctl = sccnxp_break_ctl, 730 .startup = sccnxp_startup, 731 .shutdown = sccnxp_shutdown, 732 .set_termios = sccnxp_set_termios, 733 .type = sccnxp_type, 734 .release_port = sccnxp_release_port, 735 .request_port = sccnxp_request_port, 736 .config_port = sccnxp_config_port, 737 .verify_port = sccnxp_verify_port, 738 }; 739 740 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 741 static void sccnxp_console_putchar(struct uart_port *port, int c) 742 { 743 int tryes = 100000; 744 745 while (tryes--) { 746 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 747 sccnxp_port_write(port, SCCNXP_THR_REG, c); 748 break; 749 } 750 barrier(); 751 } 752 } 753 754 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 755 { 756 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 757 struct uart_port *port = &s->port[co->index]; 758 unsigned long flags; 759 760 spin_lock_irqsave(&s->lock, flags); 761 uart_console_write(port, c, n, sccnxp_console_putchar); 762 spin_unlock_irqrestore(&s->lock, flags); 763 } 764 765 static int sccnxp_console_setup(struct console *co, char *options) 766 { 767 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 768 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 769 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 770 771 if (options) 772 uart_parse_options(options, &baud, &parity, &bits, &flow); 773 774 return uart_set_options(port, co, baud, parity, bits, flow); 775 } 776 #endif 777 778 static int sccnxp_probe(struct platform_device *pdev) 779 { 780 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 781 int chiptype = pdev->id_entry->driver_data; 782 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 783 int i, ret, fifosize, freq_min, freq_max; 784 struct sccnxp_port *s; 785 void __iomem *membase; 786 787 if (!res) { 788 dev_err(&pdev->dev, "Missing memory resource data\n"); 789 return -EADDRNOTAVAIL; 790 } 791 792 dev_set_name(&pdev->dev, SCCNXP_NAME); 793 794 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 795 if (!s) { 796 dev_err(&pdev->dev, "Error allocating port structure\n"); 797 return -ENOMEM; 798 } 799 platform_set_drvdata(pdev, s); 800 801 spin_lock_init(&s->lock); 802 803 /* Individual chip settings */ 804 switch (chiptype) { 805 case SCCNXP_TYPE_SC2681: 806 s->name = "SC2681"; 807 s->uart.nr = 2; 808 s->freq_std = 3686400; 809 s->addr_mask = 0x0f; 810 s->flags = SCCNXP_HAVE_IO; 811 fifosize = 3; 812 freq_min = 1000000; 813 freq_max = 4000000; 814 break; 815 case SCCNXP_TYPE_SC2691: 816 s->name = "SC2691"; 817 s->uart.nr = 1; 818 s->freq_std = 3686400; 819 s->addr_mask = 0x07; 820 s->flags = 0; 821 fifosize = 3; 822 freq_min = 1000000; 823 freq_max = 4000000; 824 break; 825 case SCCNXP_TYPE_SC2692: 826 s->name = "SC2692"; 827 s->uart.nr = 2; 828 s->freq_std = 3686400; 829 s->addr_mask = 0x0f; 830 s->flags = SCCNXP_HAVE_IO; 831 fifosize = 3; 832 freq_min = 1000000; 833 freq_max = 4000000; 834 break; 835 case SCCNXP_TYPE_SC2891: 836 s->name = "SC2891"; 837 s->uart.nr = 1; 838 s->freq_std = 3686400; 839 s->addr_mask = 0x0f; 840 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 841 fifosize = 16; 842 freq_min = 100000; 843 freq_max = 8000000; 844 break; 845 case SCCNXP_TYPE_SC2892: 846 s->name = "SC2892"; 847 s->uart.nr = 2; 848 s->freq_std = 3686400; 849 s->addr_mask = 0x0f; 850 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 851 fifosize = 16; 852 freq_min = 100000; 853 freq_max = 8000000; 854 break; 855 case SCCNXP_TYPE_SC28202: 856 s->name = "SC28202"; 857 s->uart.nr = 2; 858 s->freq_std = 14745600; 859 s->addr_mask = 0x7f; 860 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 861 fifosize = 256; 862 freq_min = 1000000; 863 freq_max = 50000000; 864 break; 865 case SCCNXP_TYPE_SC68681: 866 s->name = "SC68681"; 867 s->uart.nr = 2; 868 s->freq_std = 3686400; 869 s->addr_mask = 0x0f; 870 s->flags = SCCNXP_HAVE_IO; 871 fifosize = 3; 872 freq_min = 1000000; 873 freq_max = 4000000; 874 break; 875 case SCCNXP_TYPE_SC68692: 876 s->name = "SC68692"; 877 s->uart.nr = 2; 878 s->freq_std = 3686400; 879 s->addr_mask = 0x0f; 880 s->flags = SCCNXP_HAVE_IO; 881 fifosize = 3; 882 freq_min = 1000000; 883 freq_max = 4000000; 884 break; 885 default: 886 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype); 887 ret = -ENOTSUPP; 888 goto err_out; 889 } 890 891 if (!pdata) { 892 dev_warn(&pdev->dev, 893 "No platform data supplied, using defaults\n"); 894 s->pdata.frequency = s->freq_std; 895 } else 896 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 897 898 if (s->pdata.poll_time_us) { 899 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 900 s->pdata.poll_time_us); 901 s->poll = 1; 902 } 903 904 if (!s->poll) { 905 s->irq = platform_get_irq(pdev, 0); 906 if (s->irq < 0) { 907 dev_err(&pdev->dev, "Missing irq resource data\n"); 908 ret = -ENXIO; 909 goto err_out; 910 } 911 } 912 913 /* Check input frequency */ 914 if ((s->pdata.frequency < freq_min) || 915 (s->pdata.frequency > freq_max)) { 916 dev_err(&pdev->dev, "Frequency out of bounds\n"); 917 ret = -EINVAL; 918 goto err_out; 919 } 920 921 membase = devm_ioremap_resource(&pdev->dev, res); 922 if (IS_ERR(membase)) { 923 ret = PTR_ERR(membase); 924 goto err_out; 925 } 926 927 s->uart.owner = THIS_MODULE; 928 s->uart.dev_name = "ttySC"; 929 s->uart.major = SCCNXP_MAJOR; 930 s->uart.minor = SCCNXP_MINOR; 931 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 932 s->uart.cons = &s->console; 933 s->uart.cons->device = uart_console_device; 934 s->uart.cons->write = sccnxp_console_write; 935 s->uart.cons->setup = sccnxp_console_setup; 936 s->uart.cons->flags = CON_PRINTBUFFER; 937 s->uart.cons->index = -1; 938 s->uart.cons->data = s; 939 strcpy(s->uart.cons->name, "ttySC"); 940 #endif 941 ret = uart_register_driver(&s->uart); 942 if (ret) { 943 dev_err(&pdev->dev, "Registering UART driver failed\n"); 944 goto err_out; 945 } 946 947 for (i = 0; i < s->uart.nr; i++) { 948 s->port[i].line = i; 949 s->port[i].dev = &pdev->dev; 950 s->port[i].irq = s->irq; 951 s->port[i].type = PORT_SC26XX; 952 s->port[i].fifosize = fifosize; 953 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 954 s->port[i].iotype = UPIO_MEM; 955 s->port[i].mapbase = res->start; 956 s->port[i].membase = membase; 957 s->port[i].regshift = s->pdata.reg_shift; 958 s->port[i].uartclk = s->pdata.frequency; 959 s->port[i].ops = &sccnxp_ops; 960 uart_add_one_port(&s->uart, &s->port[i]); 961 /* Set direction to input */ 962 if (s->flags & SCCNXP_HAVE_IO) 963 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 964 } 965 966 /* Disable interrupts */ 967 s->imr = 0; 968 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 969 970 /* Board specific configure */ 971 if (s->pdata.init) 972 s->pdata.init(); 973 974 if (!s->poll) { 975 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 976 sccnxp_ist, 977 IRQF_TRIGGER_FALLING | 978 IRQF_ONESHOT, 979 dev_name(&pdev->dev), s); 980 if (!ret) 981 return 0; 982 983 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 984 } else { 985 init_timer(&s->timer); 986 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 987 mod_timer(&s->timer, jiffies + 988 usecs_to_jiffies(s->pdata.poll_time_us)); 989 return 0; 990 } 991 992 err_out: 993 platform_set_drvdata(pdev, NULL); 994 995 return ret; 996 } 997 998 static int sccnxp_remove(struct platform_device *pdev) 999 { 1000 int i; 1001 struct sccnxp_port *s = platform_get_drvdata(pdev); 1002 1003 if (!s->poll) 1004 devm_free_irq(&pdev->dev, s->irq, s); 1005 else 1006 del_timer_sync(&s->timer); 1007 1008 for (i = 0; i < s->uart.nr; i++) 1009 uart_remove_one_port(&s->uart, &s->port[i]); 1010 1011 uart_unregister_driver(&s->uart); 1012 platform_set_drvdata(pdev, NULL); 1013 1014 if (s->pdata.exit) 1015 s->pdata.exit(); 1016 1017 return 0; 1018 } 1019 1020 static const struct platform_device_id sccnxp_id_table[] = { 1021 { "sc2681", SCCNXP_TYPE_SC2681 }, 1022 { "sc2691", SCCNXP_TYPE_SC2691 }, 1023 { "sc2692", SCCNXP_TYPE_SC2692 }, 1024 { "sc2891", SCCNXP_TYPE_SC2891 }, 1025 { "sc2892", SCCNXP_TYPE_SC2892 }, 1026 { "sc28202", SCCNXP_TYPE_SC28202 }, 1027 { "sc68681", SCCNXP_TYPE_SC68681 }, 1028 { "sc68692", SCCNXP_TYPE_SC68692 }, 1029 { }, 1030 }; 1031 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 1032 1033 static struct platform_driver sccnxp_uart_driver = { 1034 .driver = { 1035 .name = SCCNXP_NAME, 1036 .owner = THIS_MODULE, 1037 }, 1038 .probe = sccnxp_probe, 1039 .remove = sccnxp_remove, 1040 .id_table = sccnxp_id_table, 1041 }; 1042 module_platform_driver(sccnxp_uart_driver); 1043 1044 MODULE_LICENSE("GPL v2"); 1045 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1046 MODULE_DESCRIPTION("SCCNXP serial driver"); 1047