1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NXP (Philips) SCC+++(SCN+++) serial driver 4 * 5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 8 */ 9 10 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 11 #define SUPPORT_SYSRQ 12 #endif 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/device.h> 20 #include <linux/console.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/io.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/platform_data/serial-sccnxp.h> 29 #include <linux/regulator/consumer.h> 30 31 #define SCCNXP_NAME "uart-sccnxp" 32 #define SCCNXP_MAJOR 204 33 #define SCCNXP_MINOR 205 34 35 #define SCCNXP_MR_REG (0x00) 36 # define MR0_BAUD_NORMAL (0 << 0) 37 # define MR0_BAUD_EXT1 (1 << 0) 38 # define MR0_BAUD_EXT2 (5 << 0) 39 # define MR0_FIFO (1 << 3) 40 # define MR0_TXLVL (1 << 4) 41 # define MR1_BITS_5 (0 << 0) 42 # define MR1_BITS_6 (1 << 0) 43 # define MR1_BITS_7 (2 << 0) 44 # define MR1_BITS_8 (3 << 0) 45 # define MR1_PAR_EVN (0 << 2) 46 # define MR1_PAR_ODD (1 << 2) 47 # define MR1_PAR_NO (4 << 2) 48 # define MR2_STOP1 (7 << 0) 49 # define MR2_STOP2 (0xf << 0) 50 #define SCCNXP_SR_REG (0x01) 51 #define SCCNXP_CSR_REG SCCNXP_SR_REG 52 # define SR_RXRDY (1 << 0) 53 # define SR_FULL (1 << 1) 54 # define SR_TXRDY (1 << 2) 55 # define SR_TXEMT (1 << 3) 56 # define SR_OVR (1 << 4) 57 # define SR_PE (1 << 5) 58 # define SR_FE (1 << 6) 59 # define SR_BRK (1 << 7) 60 #define SCCNXP_CR_REG (0x02) 61 # define CR_RX_ENABLE (1 << 0) 62 # define CR_RX_DISABLE (1 << 1) 63 # define CR_TX_ENABLE (1 << 2) 64 # define CR_TX_DISABLE (1 << 3) 65 # define CR_CMD_MRPTR1 (0x01 << 4) 66 # define CR_CMD_RX_RESET (0x02 << 4) 67 # define CR_CMD_TX_RESET (0x03 << 4) 68 # define CR_CMD_STATUS_RESET (0x04 << 4) 69 # define CR_CMD_BREAK_RESET (0x05 << 4) 70 # define CR_CMD_START_BREAK (0x06 << 4) 71 # define CR_CMD_STOP_BREAK (0x07 << 4) 72 # define CR_CMD_MRPTR0 (0x0b << 4) 73 #define SCCNXP_RHR_REG (0x03) 74 #define SCCNXP_THR_REG SCCNXP_RHR_REG 75 #define SCCNXP_IPCR_REG (0x04) 76 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 77 # define ACR_BAUD0 (0 << 7) 78 # define ACR_BAUD1 (1 << 7) 79 # define ACR_TIMER_MODE (6 << 4) 80 #define SCCNXP_ISR_REG (0x05) 81 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 82 # define IMR_TXRDY (1 << 0) 83 # define IMR_RXRDY (1 << 1) 84 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 85 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 86 #define SCCNXP_IPR_REG (0x0d) 87 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 88 #define SCCNXP_SOP_REG (0x0e) 89 #define SCCNXP_ROP_REG (0x0f) 90 91 /* Route helpers */ 92 #define MCTRL_MASK(sig) (0xf << (sig)) 93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 95 96 #define SCCNXP_HAVE_IO 0x00000001 97 #define SCCNXP_HAVE_MR0 0x00000002 98 99 struct sccnxp_chip { 100 const char *name; 101 unsigned int nr; 102 unsigned long freq_min; 103 unsigned long freq_std; 104 unsigned long freq_max; 105 unsigned int flags; 106 unsigned int fifosize; 107 /* Time between read/write cycles */ 108 unsigned int trwd; 109 }; 110 111 struct sccnxp_port { 112 struct uart_driver uart; 113 struct uart_port port[SCCNXP_MAX_UARTS]; 114 bool opened[SCCNXP_MAX_UARTS]; 115 116 int irq; 117 u8 imr; 118 119 struct sccnxp_chip *chip; 120 121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 122 struct console console; 123 #endif 124 125 spinlock_t lock; 126 127 bool poll; 128 struct timer_list timer; 129 130 struct sccnxp_pdata pdata; 131 132 struct regulator *regulator; 133 }; 134 135 static const struct sccnxp_chip sc2681 = { 136 .name = "SC2681", 137 .nr = 2, 138 .freq_min = 1000000, 139 .freq_std = 3686400, 140 .freq_max = 4000000, 141 .flags = SCCNXP_HAVE_IO, 142 .fifosize = 3, 143 .trwd = 200, 144 }; 145 146 static const struct sccnxp_chip sc2691 = { 147 .name = "SC2691", 148 .nr = 1, 149 .freq_min = 1000000, 150 .freq_std = 3686400, 151 .freq_max = 4000000, 152 .flags = 0, 153 .fifosize = 3, 154 .trwd = 150, 155 }; 156 157 static const struct sccnxp_chip sc2692 = { 158 .name = "SC2692", 159 .nr = 2, 160 .freq_min = 1000000, 161 .freq_std = 3686400, 162 .freq_max = 4000000, 163 .flags = SCCNXP_HAVE_IO, 164 .fifosize = 3, 165 .trwd = 30, 166 }; 167 168 static const struct sccnxp_chip sc2891 = { 169 .name = "SC2891", 170 .nr = 1, 171 .freq_min = 100000, 172 .freq_std = 3686400, 173 .freq_max = 8000000, 174 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 175 .fifosize = 16, 176 .trwd = 27, 177 }; 178 179 static const struct sccnxp_chip sc2892 = { 180 .name = "SC2892", 181 .nr = 2, 182 .freq_min = 100000, 183 .freq_std = 3686400, 184 .freq_max = 8000000, 185 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 186 .fifosize = 16, 187 .trwd = 17, 188 }; 189 190 static const struct sccnxp_chip sc28202 = { 191 .name = "SC28202", 192 .nr = 2, 193 .freq_min = 1000000, 194 .freq_std = 14745600, 195 .freq_max = 50000000, 196 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 197 .fifosize = 256, 198 .trwd = 10, 199 }; 200 201 static const struct sccnxp_chip sc68681 = { 202 .name = "SC68681", 203 .nr = 2, 204 .freq_min = 1000000, 205 .freq_std = 3686400, 206 .freq_max = 4000000, 207 .flags = SCCNXP_HAVE_IO, 208 .fifosize = 3, 209 .trwd = 200, 210 }; 211 212 static const struct sccnxp_chip sc68692 = { 213 .name = "SC68692", 214 .nr = 2, 215 .freq_min = 1000000, 216 .freq_std = 3686400, 217 .freq_max = 4000000, 218 .flags = SCCNXP_HAVE_IO, 219 .fifosize = 3, 220 .trwd = 200, 221 }; 222 223 static u8 sccnxp_read(struct uart_port *port, u8 reg) 224 { 225 struct sccnxp_port *s = dev_get_drvdata(port->dev); 226 u8 ret; 227 228 ret = readb(port->membase + (reg << port->regshift)); 229 230 ndelay(s->chip->trwd); 231 232 return ret; 233 } 234 235 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 236 { 237 struct sccnxp_port *s = dev_get_drvdata(port->dev); 238 239 writeb(v, port->membase + (reg << port->regshift)); 240 241 ndelay(s->chip->trwd); 242 } 243 244 static u8 sccnxp_port_read(struct uart_port *port, u8 reg) 245 { 246 return sccnxp_read(port, (port->line << 3) + reg); 247 } 248 249 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 250 { 251 sccnxp_write(port, (port->line << 3) + reg, v); 252 } 253 254 static int sccnxp_update_best_err(int a, int b, int *besterr) 255 { 256 int err = abs(a - b); 257 258 if ((*besterr < 0) || (*besterr > err)) { 259 *besterr = err; 260 return 0; 261 } 262 263 return 1; 264 } 265 266 static const struct { 267 u8 csr; 268 u8 acr; 269 u8 mr0; 270 int baud; 271 } baud_std[] = { 272 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 273 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 274 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 275 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 276 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 277 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 278 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 279 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 280 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 281 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 282 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 283 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 284 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 285 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 286 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 287 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 288 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 289 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 290 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 291 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 292 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 293 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 294 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 295 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 296 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 297 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 298 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 299 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 300 { 0, 0, 0, 0 } 301 }; 302 303 static int sccnxp_set_baud(struct uart_port *port, int baud) 304 { 305 struct sccnxp_port *s = dev_get_drvdata(port->dev); 306 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 307 struct sccnxp_chip *chip = s->chip; 308 u8 i, acr = 0, csr = 0, mr0 = 0; 309 310 /* Find best baud from table */ 311 for (i = 0; baud_std[i].baud && besterr; i++) { 312 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0)) 313 continue; 314 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud); 315 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 316 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 317 acr = baud_std[i].acr; 318 csr = baud_std[i].csr; 319 mr0 = baud_std[i].mr0; 320 bestbaud = tmp_baud; 321 } 322 } 323 324 if (chip->flags & SCCNXP_HAVE_MR0) { 325 /* Enable FIFO, set half level for TX */ 326 mr0 |= MR0_FIFO | MR0_TXLVL; 327 /* Update MR0 */ 328 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 329 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 330 } 331 332 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 333 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 334 335 if (baud != bestbaud) 336 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 337 baud, bestbaud); 338 339 return bestbaud; 340 } 341 342 static void sccnxp_enable_irq(struct uart_port *port, int mask) 343 { 344 struct sccnxp_port *s = dev_get_drvdata(port->dev); 345 346 s->imr |= mask << (port->line * 4); 347 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 348 } 349 350 static void sccnxp_disable_irq(struct uart_port *port, int mask) 351 { 352 struct sccnxp_port *s = dev_get_drvdata(port->dev); 353 354 s->imr &= ~(mask << (port->line * 4)); 355 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 356 } 357 358 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 359 { 360 u8 bitmask; 361 struct sccnxp_port *s = dev_get_drvdata(port->dev); 362 363 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 364 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 365 if (state) 366 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 367 else 368 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 369 } 370 } 371 372 static void sccnxp_handle_rx(struct uart_port *port) 373 { 374 u8 sr; 375 unsigned int ch, flag; 376 377 for (;;) { 378 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 379 if (!(sr & SR_RXRDY)) 380 break; 381 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 382 383 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 384 385 port->icount.rx++; 386 flag = TTY_NORMAL; 387 388 if (unlikely(sr)) { 389 if (sr & SR_BRK) { 390 port->icount.brk++; 391 sccnxp_port_write(port, SCCNXP_CR_REG, 392 CR_CMD_BREAK_RESET); 393 if (uart_handle_break(port)) 394 continue; 395 } else if (sr & SR_PE) 396 port->icount.parity++; 397 else if (sr & SR_FE) 398 port->icount.frame++; 399 else if (sr & SR_OVR) { 400 port->icount.overrun++; 401 sccnxp_port_write(port, SCCNXP_CR_REG, 402 CR_CMD_STATUS_RESET); 403 } 404 405 sr &= port->read_status_mask; 406 if (sr & SR_BRK) 407 flag = TTY_BREAK; 408 else if (sr & SR_PE) 409 flag = TTY_PARITY; 410 else if (sr & SR_FE) 411 flag = TTY_FRAME; 412 else if (sr & SR_OVR) 413 flag = TTY_OVERRUN; 414 } 415 416 if (uart_handle_sysrq_char(port, ch)) 417 continue; 418 419 if (sr & port->ignore_status_mask) 420 continue; 421 422 uart_insert_char(port, sr, SR_OVR, ch, flag); 423 } 424 425 tty_flip_buffer_push(&port->state->port); 426 } 427 428 static void sccnxp_handle_tx(struct uart_port *port) 429 { 430 u8 sr; 431 struct circ_buf *xmit = &port->state->xmit; 432 struct sccnxp_port *s = dev_get_drvdata(port->dev); 433 434 if (unlikely(port->x_char)) { 435 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 436 port->icount.tx++; 437 port->x_char = 0; 438 return; 439 } 440 441 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 442 /* Disable TX if FIFO is empty */ 443 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 444 sccnxp_disable_irq(port, IMR_TXRDY); 445 446 /* Set direction to input */ 447 if (s->chip->flags & SCCNXP_HAVE_IO) 448 sccnxp_set_bit(port, DIR_OP, 0); 449 } 450 return; 451 } 452 453 while (!uart_circ_empty(xmit)) { 454 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 455 if (!(sr & SR_TXRDY)) 456 break; 457 458 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 459 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 460 port->icount.tx++; 461 } 462 463 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 464 uart_write_wakeup(port); 465 } 466 467 static void sccnxp_handle_events(struct sccnxp_port *s) 468 { 469 int i; 470 u8 isr; 471 472 do { 473 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 474 isr &= s->imr; 475 if (!isr) 476 break; 477 478 for (i = 0; i < s->uart.nr; i++) { 479 if (s->opened[i] && (isr & ISR_RXRDY(i))) 480 sccnxp_handle_rx(&s->port[i]); 481 if (s->opened[i] && (isr & ISR_TXRDY(i))) 482 sccnxp_handle_tx(&s->port[i]); 483 } 484 } while (1); 485 } 486 487 static void sccnxp_timer(struct timer_list *t) 488 { 489 struct sccnxp_port *s = from_timer(s, t, timer); 490 unsigned long flags; 491 492 spin_lock_irqsave(&s->lock, flags); 493 sccnxp_handle_events(s); 494 spin_unlock_irqrestore(&s->lock, flags); 495 496 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us)); 497 } 498 499 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 500 { 501 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 502 unsigned long flags; 503 504 spin_lock_irqsave(&s->lock, flags); 505 sccnxp_handle_events(s); 506 spin_unlock_irqrestore(&s->lock, flags); 507 508 return IRQ_HANDLED; 509 } 510 511 static void sccnxp_start_tx(struct uart_port *port) 512 { 513 struct sccnxp_port *s = dev_get_drvdata(port->dev); 514 unsigned long flags; 515 516 spin_lock_irqsave(&s->lock, flags); 517 518 /* Set direction to output */ 519 if (s->chip->flags & SCCNXP_HAVE_IO) 520 sccnxp_set_bit(port, DIR_OP, 1); 521 522 sccnxp_enable_irq(port, IMR_TXRDY); 523 524 spin_unlock_irqrestore(&s->lock, flags); 525 } 526 527 static void sccnxp_stop_tx(struct uart_port *port) 528 { 529 /* Do nothing */ 530 } 531 532 static void sccnxp_stop_rx(struct uart_port *port) 533 { 534 struct sccnxp_port *s = dev_get_drvdata(port->dev); 535 unsigned long flags; 536 537 spin_lock_irqsave(&s->lock, flags); 538 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 539 spin_unlock_irqrestore(&s->lock, flags); 540 } 541 542 static unsigned int sccnxp_tx_empty(struct uart_port *port) 543 { 544 u8 val; 545 unsigned long flags; 546 struct sccnxp_port *s = dev_get_drvdata(port->dev); 547 548 spin_lock_irqsave(&s->lock, flags); 549 val = sccnxp_port_read(port, SCCNXP_SR_REG); 550 spin_unlock_irqrestore(&s->lock, flags); 551 552 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 553 } 554 555 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 556 { 557 struct sccnxp_port *s = dev_get_drvdata(port->dev); 558 unsigned long flags; 559 560 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 561 return; 562 563 spin_lock_irqsave(&s->lock, flags); 564 565 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 566 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 567 568 spin_unlock_irqrestore(&s->lock, flags); 569 } 570 571 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 572 { 573 u8 bitmask, ipr; 574 unsigned long flags; 575 struct sccnxp_port *s = dev_get_drvdata(port->dev); 576 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 577 578 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 579 return mctrl; 580 581 spin_lock_irqsave(&s->lock, flags); 582 583 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 584 585 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 586 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 587 DSR_IP); 588 mctrl &= ~TIOCM_DSR; 589 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 590 } 591 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 592 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 593 CTS_IP); 594 mctrl &= ~TIOCM_CTS; 595 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 596 } 597 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 598 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 599 DCD_IP); 600 mctrl &= ~TIOCM_CAR; 601 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 602 } 603 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 604 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 605 RNG_IP); 606 mctrl &= ~TIOCM_RNG; 607 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 608 } 609 610 spin_unlock_irqrestore(&s->lock, flags); 611 612 return mctrl; 613 } 614 615 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 616 { 617 struct sccnxp_port *s = dev_get_drvdata(port->dev); 618 unsigned long flags; 619 620 spin_lock_irqsave(&s->lock, flags); 621 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 622 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 623 spin_unlock_irqrestore(&s->lock, flags); 624 } 625 626 static void sccnxp_set_termios(struct uart_port *port, 627 struct ktermios *termios, struct ktermios *old) 628 { 629 struct sccnxp_port *s = dev_get_drvdata(port->dev); 630 unsigned long flags; 631 u8 mr1, mr2; 632 int baud; 633 634 spin_lock_irqsave(&s->lock, flags); 635 636 /* Mask termios capabilities we don't support */ 637 termios->c_cflag &= ~CMSPAR; 638 639 /* Disable RX & TX, reset break condition, status and FIFOs */ 640 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 641 CR_RX_DISABLE | CR_TX_DISABLE); 642 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 643 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 644 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 645 646 /* Word size */ 647 switch (termios->c_cflag & CSIZE) { 648 case CS5: 649 mr1 = MR1_BITS_5; 650 break; 651 case CS6: 652 mr1 = MR1_BITS_6; 653 break; 654 case CS7: 655 mr1 = MR1_BITS_7; 656 break; 657 case CS8: 658 default: 659 mr1 = MR1_BITS_8; 660 break; 661 } 662 663 /* Parity */ 664 if (termios->c_cflag & PARENB) { 665 if (termios->c_cflag & PARODD) 666 mr1 |= MR1_PAR_ODD; 667 } else 668 mr1 |= MR1_PAR_NO; 669 670 /* Stop bits */ 671 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 672 673 /* Update desired format */ 674 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 675 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 676 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 677 678 /* Set read status mask */ 679 port->read_status_mask = SR_OVR; 680 if (termios->c_iflag & INPCK) 681 port->read_status_mask |= SR_PE | SR_FE; 682 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 683 port->read_status_mask |= SR_BRK; 684 685 /* Set status ignore mask */ 686 port->ignore_status_mask = 0; 687 if (termios->c_iflag & IGNBRK) 688 port->ignore_status_mask |= SR_BRK; 689 if (termios->c_iflag & IGNPAR) 690 port->ignore_status_mask |= SR_PE; 691 if (!(termios->c_cflag & CREAD)) 692 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 693 694 /* Setup baudrate */ 695 baud = uart_get_baud_rate(port, termios, old, 50, 696 (s->chip->flags & SCCNXP_HAVE_MR0) ? 697 230400 : 38400); 698 baud = sccnxp_set_baud(port, baud); 699 700 /* Update timeout according to new baud rate */ 701 uart_update_timeout(port, termios->c_cflag, baud); 702 703 /* Report actual baudrate back to core */ 704 if (tty_termios_baud_rate(termios)) 705 tty_termios_encode_baud_rate(termios, baud, baud); 706 707 /* Enable RX & TX */ 708 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 709 710 spin_unlock_irqrestore(&s->lock, flags); 711 } 712 713 static int sccnxp_startup(struct uart_port *port) 714 { 715 struct sccnxp_port *s = dev_get_drvdata(port->dev); 716 unsigned long flags; 717 718 spin_lock_irqsave(&s->lock, flags); 719 720 if (s->chip->flags & SCCNXP_HAVE_IO) { 721 /* Outputs are controlled manually */ 722 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 723 } 724 725 /* Reset break condition, status and FIFOs */ 726 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 727 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 728 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 729 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 730 731 /* Enable RX & TX */ 732 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 733 734 /* Enable RX interrupt */ 735 sccnxp_enable_irq(port, IMR_RXRDY); 736 737 s->opened[port->line] = 1; 738 739 spin_unlock_irqrestore(&s->lock, flags); 740 741 return 0; 742 } 743 744 static void sccnxp_shutdown(struct uart_port *port) 745 { 746 struct sccnxp_port *s = dev_get_drvdata(port->dev); 747 unsigned long flags; 748 749 spin_lock_irqsave(&s->lock, flags); 750 751 s->opened[port->line] = 0; 752 753 /* Disable interrupts */ 754 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 755 756 /* Disable TX & RX */ 757 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 758 759 /* Leave direction to input */ 760 if (s->chip->flags & SCCNXP_HAVE_IO) 761 sccnxp_set_bit(port, DIR_OP, 0); 762 763 spin_unlock_irqrestore(&s->lock, flags); 764 } 765 766 static const char *sccnxp_type(struct uart_port *port) 767 { 768 struct sccnxp_port *s = dev_get_drvdata(port->dev); 769 770 return (port->type == PORT_SC26XX) ? s->chip->name : NULL; 771 } 772 773 static void sccnxp_release_port(struct uart_port *port) 774 { 775 /* Do nothing */ 776 } 777 778 static int sccnxp_request_port(struct uart_port *port) 779 { 780 /* Do nothing */ 781 return 0; 782 } 783 784 static void sccnxp_config_port(struct uart_port *port, int flags) 785 { 786 if (flags & UART_CONFIG_TYPE) 787 port->type = PORT_SC26XX; 788 } 789 790 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 791 { 792 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 793 return 0; 794 if (s->irq == port->irq) 795 return 0; 796 797 return -EINVAL; 798 } 799 800 static const struct uart_ops sccnxp_ops = { 801 .tx_empty = sccnxp_tx_empty, 802 .set_mctrl = sccnxp_set_mctrl, 803 .get_mctrl = sccnxp_get_mctrl, 804 .stop_tx = sccnxp_stop_tx, 805 .start_tx = sccnxp_start_tx, 806 .stop_rx = sccnxp_stop_rx, 807 .break_ctl = sccnxp_break_ctl, 808 .startup = sccnxp_startup, 809 .shutdown = sccnxp_shutdown, 810 .set_termios = sccnxp_set_termios, 811 .type = sccnxp_type, 812 .release_port = sccnxp_release_port, 813 .request_port = sccnxp_request_port, 814 .config_port = sccnxp_config_port, 815 .verify_port = sccnxp_verify_port, 816 }; 817 818 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 819 static void sccnxp_console_putchar(struct uart_port *port, int c) 820 { 821 int tryes = 100000; 822 823 while (tryes--) { 824 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 825 sccnxp_port_write(port, SCCNXP_THR_REG, c); 826 break; 827 } 828 barrier(); 829 } 830 } 831 832 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 833 { 834 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 835 struct uart_port *port = &s->port[co->index]; 836 unsigned long flags; 837 838 spin_lock_irqsave(&s->lock, flags); 839 uart_console_write(port, c, n, sccnxp_console_putchar); 840 spin_unlock_irqrestore(&s->lock, flags); 841 } 842 843 static int sccnxp_console_setup(struct console *co, char *options) 844 { 845 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 846 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 847 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 848 849 if (options) 850 uart_parse_options(options, &baud, &parity, &bits, &flow); 851 852 return uart_set_options(port, co, baud, parity, bits, flow); 853 } 854 #endif 855 856 static const struct platform_device_id sccnxp_id_table[] = { 857 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, }, 858 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, }, 859 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, }, 860 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, }, 861 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, }, 862 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, }, 863 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, }, 864 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, }, 865 { } 866 }; 867 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 868 869 static int sccnxp_probe(struct platform_device *pdev) 870 { 871 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 872 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 873 int i, ret, uartclk; 874 struct sccnxp_port *s; 875 void __iomem *membase; 876 struct clk *clk; 877 878 membase = devm_ioremap_resource(&pdev->dev, res); 879 if (IS_ERR(membase)) 880 return PTR_ERR(membase); 881 882 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 883 if (!s) { 884 dev_err(&pdev->dev, "Error allocating port structure\n"); 885 return -ENOMEM; 886 } 887 platform_set_drvdata(pdev, s); 888 889 spin_lock_init(&s->lock); 890 891 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data; 892 893 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 894 if (!IS_ERR(s->regulator)) { 895 ret = regulator_enable(s->regulator); 896 if (ret) { 897 dev_err(&pdev->dev, 898 "Failed to enable regulator: %i\n", ret); 899 return ret; 900 } 901 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) 902 return -EPROBE_DEFER; 903 904 clk = devm_clk_get(&pdev->dev, NULL); 905 if (IS_ERR(clk)) { 906 ret = PTR_ERR(clk); 907 if (ret == -EPROBE_DEFER) 908 goto err_out; 909 uartclk = 0; 910 } else { 911 ret = clk_prepare_enable(clk); 912 if (ret) 913 goto err_out; 914 915 ret = devm_add_action_or_reset(&pdev->dev, 916 (void(*)(void *))clk_disable_unprepare, 917 clk); 918 if (ret) 919 goto err_out; 920 921 uartclk = clk_get_rate(clk); 922 } 923 924 if (!uartclk) { 925 dev_notice(&pdev->dev, "Using default clock frequency\n"); 926 uartclk = s->chip->freq_std; 927 } 928 929 /* Check input frequency */ 930 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { 931 dev_err(&pdev->dev, "Frequency out of bounds\n"); 932 ret = -EINVAL; 933 goto err_out; 934 } 935 936 if (pdata) 937 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 938 939 if (s->pdata.poll_time_us) { 940 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 941 s->pdata.poll_time_us); 942 s->poll = 1; 943 } 944 945 if (!s->poll) { 946 s->irq = platform_get_irq(pdev, 0); 947 if (s->irq < 0) { 948 dev_err(&pdev->dev, "Missing irq resource data\n"); 949 ret = -ENXIO; 950 goto err_out; 951 } 952 } 953 954 s->uart.owner = THIS_MODULE; 955 s->uart.dev_name = "ttySC"; 956 s->uart.major = SCCNXP_MAJOR; 957 s->uart.minor = SCCNXP_MINOR; 958 s->uart.nr = s->chip->nr; 959 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 960 s->uart.cons = &s->console; 961 s->uart.cons->device = uart_console_device; 962 s->uart.cons->write = sccnxp_console_write; 963 s->uart.cons->setup = sccnxp_console_setup; 964 s->uart.cons->flags = CON_PRINTBUFFER; 965 s->uart.cons->index = -1; 966 s->uart.cons->data = s; 967 strcpy(s->uart.cons->name, "ttySC"); 968 #endif 969 ret = uart_register_driver(&s->uart); 970 if (ret) { 971 dev_err(&pdev->dev, "Registering UART driver failed\n"); 972 goto err_out; 973 } 974 975 for (i = 0; i < s->uart.nr; i++) { 976 s->port[i].line = i; 977 s->port[i].dev = &pdev->dev; 978 s->port[i].irq = s->irq; 979 s->port[i].type = PORT_SC26XX; 980 s->port[i].fifosize = s->chip->fifosize; 981 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 982 s->port[i].iotype = UPIO_MEM; 983 s->port[i].mapbase = res->start; 984 s->port[i].membase = membase; 985 s->port[i].regshift = s->pdata.reg_shift; 986 s->port[i].uartclk = uartclk; 987 s->port[i].ops = &sccnxp_ops; 988 uart_add_one_port(&s->uart, &s->port[i]); 989 /* Set direction to input */ 990 if (s->chip->flags & SCCNXP_HAVE_IO) 991 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 992 } 993 994 /* Disable interrupts */ 995 s->imr = 0; 996 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 997 998 if (!s->poll) { 999 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 1000 sccnxp_ist, 1001 IRQF_TRIGGER_FALLING | 1002 IRQF_ONESHOT, 1003 dev_name(&pdev->dev), s); 1004 if (!ret) 1005 return 0; 1006 1007 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 1008 } else { 1009 timer_setup(&s->timer, sccnxp_timer, 0); 1010 mod_timer(&s->timer, jiffies + 1011 usecs_to_jiffies(s->pdata.poll_time_us)); 1012 return 0; 1013 } 1014 1015 uart_unregister_driver(&s->uart); 1016 err_out: 1017 if (!IS_ERR(s->regulator)) 1018 regulator_disable(s->regulator); 1019 1020 return ret; 1021 } 1022 1023 static int sccnxp_remove(struct platform_device *pdev) 1024 { 1025 int i; 1026 struct sccnxp_port *s = platform_get_drvdata(pdev); 1027 1028 if (!s->poll) 1029 devm_free_irq(&pdev->dev, s->irq, s); 1030 else 1031 del_timer_sync(&s->timer); 1032 1033 for (i = 0; i < s->uart.nr; i++) 1034 uart_remove_one_port(&s->uart, &s->port[i]); 1035 1036 uart_unregister_driver(&s->uart); 1037 1038 if (!IS_ERR(s->regulator)) 1039 return regulator_disable(s->regulator); 1040 1041 return 0; 1042 } 1043 1044 static struct platform_driver sccnxp_uart_driver = { 1045 .driver = { 1046 .name = SCCNXP_NAME, 1047 }, 1048 .probe = sccnxp_probe, 1049 .remove = sccnxp_remove, 1050 .id_table = sccnxp_id_table, 1051 }; 1052 module_platform_driver(sccnxp_uart_driver); 1053 1054 MODULE_LICENSE("GPL v2"); 1055 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1056 MODULE_DESCRIPTION("SCCNXP serial driver"); 1057