1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/console.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/io.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/platform_data/serial-sccnxp.h> 29 30 #define SCCNXP_NAME "uart-sccnxp" 31 #define SCCNXP_MAJOR 204 32 #define SCCNXP_MINOR 205 33 34 #define SCCNXP_MR_REG (0x00) 35 # define MR0_BAUD_NORMAL (0 << 0) 36 # define MR0_BAUD_EXT1 (1 << 0) 37 # define MR0_BAUD_EXT2 (5 << 0) 38 # define MR0_FIFO (1 << 3) 39 # define MR0_TXLVL (1 << 4) 40 # define MR1_BITS_5 (0 << 0) 41 # define MR1_BITS_6 (1 << 0) 42 # define MR1_BITS_7 (2 << 0) 43 # define MR1_BITS_8 (3 << 0) 44 # define MR1_PAR_EVN (0 << 2) 45 # define MR1_PAR_ODD (1 << 2) 46 # define MR1_PAR_NO (4 << 2) 47 # define MR2_STOP1 (7 << 0) 48 # define MR2_STOP2 (0xf << 0) 49 #define SCCNXP_SR_REG (0x01) 50 #define SCCNXP_CSR_REG SCCNXP_SR_REG 51 # define SR_RXRDY (1 << 0) 52 # define SR_FULL (1 << 1) 53 # define SR_TXRDY (1 << 2) 54 # define SR_TXEMT (1 << 3) 55 # define SR_OVR (1 << 4) 56 # define SR_PE (1 << 5) 57 # define SR_FE (1 << 6) 58 # define SR_BRK (1 << 7) 59 #define SCCNXP_CR_REG (0x02) 60 # define CR_RX_ENABLE (1 << 0) 61 # define CR_RX_DISABLE (1 << 1) 62 # define CR_TX_ENABLE (1 << 2) 63 # define CR_TX_DISABLE (1 << 3) 64 # define CR_CMD_MRPTR1 (0x01 << 4) 65 # define CR_CMD_RX_RESET (0x02 << 4) 66 # define CR_CMD_TX_RESET (0x03 << 4) 67 # define CR_CMD_STATUS_RESET (0x04 << 4) 68 # define CR_CMD_BREAK_RESET (0x05 << 4) 69 # define CR_CMD_START_BREAK (0x06 << 4) 70 # define CR_CMD_STOP_BREAK (0x07 << 4) 71 # define CR_CMD_MRPTR0 (0x0b << 4) 72 #define SCCNXP_RHR_REG (0x03) 73 #define SCCNXP_THR_REG SCCNXP_RHR_REG 74 #define SCCNXP_IPCR_REG (0x04) 75 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 76 # define ACR_BAUD0 (0 << 7) 77 # define ACR_BAUD1 (1 << 7) 78 # define ACR_TIMER_MODE (6 << 4) 79 #define SCCNXP_ISR_REG (0x05) 80 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 81 # define IMR_TXRDY (1 << 0) 82 # define IMR_RXRDY (1 << 1) 83 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 84 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 85 #define SCCNXP_IPR_REG (0x0d) 86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 87 #define SCCNXP_SOP_REG (0x0e) 88 #define SCCNXP_ROP_REG (0x0f) 89 90 /* Route helpers */ 91 #define MCTRL_MASK(sig) (0xf << (sig)) 92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 94 95 /* Supported chip types */ 96 enum { 97 SCCNXP_TYPE_SC2681 = 2681, 98 SCCNXP_TYPE_SC2691 = 2691, 99 SCCNXP_TYPE_SC2692 = 2692, 100 SCCNXP_TYPE_SC2891 = 2891, 101 SCCNXP_TYPE_SC2892 = 2892, 102 SCCNXP_TYPE_SC28202 = 28202, 103 SCCNXP_TYPE_SC68681 = 68681, 104 SCCNXP_TYPE_SC68692 = 68692, 105 }; 106 107 struct sccnxp_port { 108 struct uart_driver uart; 109 struct uart_port port[SCCNXP_MAX_UARTS]; 110 bool opened[SCCNXP_MAX_UARTS]; 111 112 const char *name; 113 int irq; 114 115 u8 imr; 116 u8 addr_mask; 117 int freq_std; 118 119 int flags; 120 #define SCCNXP_HAVE_IO 0x00000001 121 #define SCCNXP_HAVE_MR0 0x00000002 122 123 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 124 struct console console; 125 #endif 126 127 spinlock_t lock; 128 129 bool poll; 130 struct timer_list timer; 131 132 struct sccnxp_pdata pdata; 133 }; 134 135 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 136 { 137 return readb(base + (reg << shift)); 138 } 139 140 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 141 { 142 writeb(v, base + (reg << shift)); 143 } 144 145 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 146 { 147 struct sccnxp_port *s = dev_get_drvdata(port->dev); 148 149 return sccnxp_raw_read(port->membase, reg & s->addr_mask, 150 port->regshift); 151 } 152 153 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 154 { 155 struct sccnxp_port *s = dev_get_drvdata(port->dev); 156 157 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v); 158 } 159 160 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 161 { 162 return sccnxp_read(port, (port->line << 3) + reg); 163 } 164 165 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 166 { 167 sccnxp_write(port, (port->line << 3) + reg, v); 168 } 169 170 static int sccnxp_update_best_err(int a, int b, int *besterr) 171 { 172 int err = abs(a - b); 173 174 if ((*besterr < 0) || (*besterr > err)) { 175 *besterr = err; 176 return 0; 177 } 178 179 return 1; 180 } 181 182 static const struct { 183 u8 csr; 184 u8 acr; 185 u8 mr0; 186 int baud; 187 } baud_std[] = { 188 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 189 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 190 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 191 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 192 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 193 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 194 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 195 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 196 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 197 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 198 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 199 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 200 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 201 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 202 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 203 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 204 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 205 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 206 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 207 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 208 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 209 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 210 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 211 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 212 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 213 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 214 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 215 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 216 { 0, 0, 0, 0 } 217 }; 218 219 static int sccnxp_set_baud(struct uart_port *port, int baud) 220 { 221 struct sccnxp_port *s = dev_get_drvdata(port->dev); 222 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 223 u8 i, acr = 0, csr = 0, mr0 = 0; 224 225 /* Find best baud from table */ 226 for (i = 0; baud_std[i].baud && besterr; i++) { 227 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 228 continue; 229 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 230 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 231 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 232 acr = baud_std[i].acr; 233 csr = baud_std[i].csr; 234 mr0 = baud_std[i].mr0; 235 bestbaud = tmp_baud; 236 } 237 } 238 239 if (s->flags & SCCNXP_HAVE_MR0) { 240 /* Enable FIFO, set half level for TX */ 241 mr0 |= MR0_FIFO | MR0_TXLVL; 242 /* Update MR0 */ 243 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 244 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 245 } 246 247 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 248 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 249 250 if (baud != bestbaud) 251 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 252 baud, bestbaud); 253 254 return bestbaud; 255 } 256 257 static void sccnxp_enable_irq(struct uart_port *port, int mask) 258 { 259 struct sccnxp_port *s = dev_get_drvdata(port->dev); 260 261 s->imr |= mask << (port->line * 4); 262 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 263 } 264 265 static void sccnxp_disable_irq(struct uart_port *port, int mask) 266 { 267 struct sccnxp_port *s = dev_get_drvdata(port->dev); 268 269 s->imr &= ~(mask << (port->line * 4)); 270 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 271 } 272 273 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 274 { 275 u8 bitmask; 276 struct sccnxp_port *s = dev_get_drvdata(port->dev); 277 278 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 279 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 280 if (state) 281 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 282 else 283 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 284 } 285 } 286 287 static void sccnxp_handle_rx(struct uart_port *port) 288 { 289 u8 sr; 290 unsigned int ch, flag; 291 292 for (;;) { 293 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 294 if (!(sr & SR_RXRDY)) 295 break; 296 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 297 298 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 299 300 port->icount.rx++; 301 flag = TTY_NORMAL; 302 303 if (unlikely(sr)) { 304 if (sr & SR_BRK) { 305 port->icount.brk++; 306 sccnxp_port_write(port, SCCNXP_CR_REG, 307 CR_CMD_BREAK_RESET); 308 if (uart_handle_break(port)) 309 continue; 310 } else if (sr & SR_PE) 311 port->icount.parity++; 312 else if (sr & SR_FE) 313 port->icount.frame++; 314 else if (sr & SR_OVR) { 315 port->icount.overrun++; 316 sccnxp_port_write(port, SCCNXP_CR_REG, 317 CR_CMD_STATUS_RESET); 318 } 319 320 sr &= port->read_status_mask; 321 if (sr & SR_BRK) 322 flag = TTY_BREAK; 323 else if (sr & SR_PE) 324 flag = TTY_PARITY; 325 else if (sr & SR_FE) 326 flag = TTY_FRAME; 327 else if (sr & SR_OVR) 328 flag = TTY_OVERRUN; 329 } 330 331 if (uart_handle_sysrq_char(port, ch)) 332 continue; 333 334 if (sr & port->ignore_status_mask) 335 continue; 336 337 uart_insert_char(port, sr, SR_OVR, ch, flag); 338 } 339 340 tty_flip_buffer_push(&port->state->port); 341 } 342 343 static void sccnxp_handle_tx(struct uart_port *port) 344 { 345 u8 sr; 346 struct circ_buf *xmit = &port->state->xmit; 347 struct sccnxp_port *s = dev_get_drvdata(port->dev); 348 349 if (unlikely(port->x_char)) { 350 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 351 port->icount.tx++; 352 port->x_char = 0; 353 return; 354 } 355 356 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 357 /* Disable TX if FIFO is empty */ 358 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 359 sccnxp_disable_irq(port, IMR_TXRDY); 360 361 /* Set direction to input */ 362 if (s->flags & SCCNXP_HAVE_IO) 363 sccnxp_set_bit(port, DIR_OP, 0); 364 } 365 return; 366 } 367 368 while (!uart_circ_empty(xmit)) { 369 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 370 if (!(sr & SR_TXRDY)) 371 break; 372 373 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 374 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 375 port->icount.tx++; 376 } 377 378 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 379 uart_write_wakeup(port); 380 } 381 382 static void sccnxp_handle_events(struct sccnxp_port *s) 383 { 384 int i; 385 u8 isr; 386 387 do { 388 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 389 isr &= s->imr; 390 if (!isr) 391 break; 392 393 for (i = 0; i < s->uart.nr; i++) { 394 if (s->opened[i] && (isr & ISR_RXRDY(i))) 395 sccnxp_handle_rx(&s->port[i]); 396 if (s->opened[i] && (isr & ISR_TXRDY(i))) 397 sccnxp_handle_tx(&s->port[i]); 398 } 399 } while (1); 400 } 401 402 static void sccnxp_timer(unsigned long data) 403 { 404 struct sccnxp_port *s = (struct sccnxp_port *)data; 405 unsigned long flags; 406 407 spin_lock_irqsave(&s->lock, flags); 408 sccnxp_handle_events(s); 409 spin_unlock_irqrestore(&s->lock, flags); 410 411 if (!timer_pending(&s->timer)) 412 mod_timer(&s->timer, jiffies + 413 usecs_to_jiffies(s->pdata.poll_time_us)); 414 } 415 416 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 417 { 418 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 419 unsigned long flags; 420 421 spin_lock_irqsave(&s->lock, flags); 422 sccnxp_handle_events(s); 423 spin_unlock_irqrestore(&s->lock, flags); 424 425 return IRQ_HANDLED; 426 } 427 428 static void sccnxp_start_tx(struct uart_port *port) 429 { 430 struct sccnxp_port *s = dev_get_drvdata(port->dev); 431 unsigned long flags; 432 433 spin_lock_irqsave(&s->lock, flags); 434 435 /* Set direction to output */ 436 if (s->flags & SCCNXP_HAVE_IO) 437 sccnxp_set_bit(port, DIR_OP, 1); 438 439 sccnxp_enable_irq(port, IMR_TXRDY); 440 441 spin_unlock_irqrestore(&s->lock, flags); 442 } 443 444 static void sccnxp_stop_tx(struct uart_port *port) 445 { 446 /* Do nothing */ 447 } 448 449 static void sccnxp_stop_rx(struct uart_port *port) 450 { 451 struct sccnxp_port *s = dev_get_drvdata(port->dev); 452 unsigned long flags; 453 454 spin_lock_irqsave(&s->lock, flags); 455 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 456 spin_unlock_irqrestore(&s->lock, flags); 457 } 458 459 static unsigned int sccnxp_tx_empty(struct uart_port *port) 460 { 461 u8 val; 462 unsigned long flags; 463 struct sccnxp_port *s = dev_get_drvdata(port->dev); 464 465 spin_lock_irqsave(&s->lock, flags); 466 val = sccnxp_port_read(port, SCCNXP_SR_REG); 467 spin_unlock_irqrestore(&s->lock, flags); 468 469 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 470 } 471 472 static void sccnxp_enable_ms(struct uart_port *port) 473 { 474 /* Do nothing */ 475 } 476 477 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 478 { 479 struct sccnxp_port *s = dev_get_drvdata(port->dev); 480 unsigned long flags; 481 482 if (!(s->flags & SCCNXP_HAVE_IO)) 483 return; 484 485 spin_lock_irqsave(&s->lock, flags); 486 487 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 488 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 489 490 spin_unlock_irqrestore(&s->lock, flags); 491 } 492 493 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 494 { 495 u8 bitmask, ipr; 496 unsigned long flags; 497 struct sccnxp_port *s = dev_get_drvdata(port->dev); 498 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 499 500 if (!(s->flags & SCCNXP_HAVE_IO)) 501 return mctrl; 502 503 spin_lock_irqsave(&s->lock, flags); 504 505 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 506 507 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 508 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 509 DSR_IP); 510 mctrl &= ~TIOCM_DSR; 511 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 512 } 513 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 514 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 515 CTS_IP); 516 mctrl &= ~TIOCM_CTS; 517 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 518 } 519 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 520 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 521 DCD_IP); 522 mctrl &= ~TIOCM_CAR; 523 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 524 } 525 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 526 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 527 RNG_IP); 528 mctrl &= ~TIOCM_RNG; 529 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 530 } 531 532 spin_unlock_irqrestore(&s->lock, flags); 533 534 return mctrl; 535 } 536 537 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 538 { 539 struct sccnxp_port *s = dev_get_drvdata(port->dev); 540 unsigned long flags; 541 542 spin_lock_irqsave(&s->lock, flags); 543 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 544 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 545 spin_unlock_irqrestore(&s->lock, flags); 546 } 547 548 static void sccnxp_set_termios(struct uart_port *port, 549 struct ktermios *termios, struct ktermios *old) 550 { 551 struct sccnxp_port *s = dev_get_drvdata(port->dev); 552 unsigned long flags; 553 u8 mr1, mr2; 554 int baud; 555 556 spin_lock_irqsave(&s->lock, flags); 557 558 /* Mask termios capabilities we don't support */ 559 termios->c_cflag &= ~CMSPAR; 560 561 /* Disable RX & TX, reset break condition, status and FIFOs */ 562 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 563 CR_RX_DISABLE | CR_TX_DISABLE); 564 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 565 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 566 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 567 568 /* Word size */ 569 switch (termios->c_cflag & CSIZE) { 570 case CS5: 571 mr1 = MR1_BITS_5; 572 break; 573 case CS6: 574 mr1 = MR1_BITS_6; 575 break; 576 case CS7: 577 mr1 = MR1_BITS_7; 578 break; 579 case CS8: 580 default: 581 mr1 = MR1_BITS_8; 582 break; 583 } 584 585 /* Parity */ 586 if (termios->c_cflag & PARENB) { 587 if (termios->c_cflag & PARODD) 588 mr1 |= MR1_PAR_ODD; 589 } else 590 mr1 |= MR1_PAR_NO; 591 592 /* Stop bits */ 593 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 594 595 /* Update desired format */ 596 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 597 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 598 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 599 600 /* Set read status mask */ 601 port->read_status_mask = SR_OVR; 602 if (termios->c_iflag & INPCK) 603 port->read_status_mask |= SR_PE | SR_FE; 604 if (termios->c_iflag & (BRKINT | PARMRK)) 605 port->read_status_mask |= SR_BRK; 606 607 /* Set status ignore mask */ 608 port->ignore_status_mask = 0; 609 if (termios->c_iflag & IGNBRK) 610 port->ignore_status_mask |= SR_BRK; 611 if (!(termios->c_cflag & CREAD)) 612 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 613 614 /* Setup baudrate */ 615 baud = uart_get_baud_rate(port, termios, old, 50, 616 (s->flags & SCCNXP_HAVE_MR0) ? 617 230400 : 38400); 618 baud = sccnxp_set_baud(port, baud); 619 620 /* Update timeout according to new baud rate */ 621 uart_update_timeout(port, termios->c_cflag, baud); 622 623 /* Report actual baudrate back to core */ 624 if (tty_termios_baud_rate(termios)) 625 tty_termios_encode_baud_rate(termios, baud, baud); 626 627 /* Enable RX & TX */ 628 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 629 630 spin_unlock_irqrestore(&s->lock, flags); 631 } 632 633 static int sccnxp_startup(struct uart_port *port) 634 { 635 struct sccnxp_port *s = dev_get_drvdata(port->dev); 636 unsigned long flags; 637 638 spin_lock_irqsave(&s->lock, flags); 639 640 if (s->flags & SCCNXP_HAVE_IO) { 641 /* Outputs are controlled manually */ 642 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 643 } 644 645 /* Reset break condition, status and FIFOs */ 646 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 647 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 648 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 649 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 650 651 /* Enable RX & TX */ 652 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 653 654 /* Enable RX interrupt */ 655 sccnxp_enable_irq(port, IMR_RXRDY); 656 657 s->opened[port->line] = 1; 658 659 spin_unlock_irqrestore(&s->lock, flags); 660 661 return 0; 662 } 663 664 static void sccnxp_shutdown(struct uart_port *port) 665 { 666 struct sccnxp_port *s = dev_get_drvdata(port->dev); 667 unsigned long flags; 668 669 spin_lock_irqsave(&s->lock, flags); 670 671 s->opened[port->line] = 0; 672 673 /* Disable interrupts */ 674 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 675 676 /* Disable TX & RX */ 677 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 678 679 /* Leave direction to input */ 680 if (s->flags & SCCNXP_HAVE_IO) 681 sccnxp_set_bit(port, DIR_OP, 0); 682 683 spin_unlock_irqrestore(&s->lock, flags); 684 } 685 686 static const char *sccnxp_type(struct uart_port *port) 687 { 688 struct sccnxp_port *s = dev_get_drvdata(port->dev); 689 690 return (port->type == PORT_SC26XX) ? s->name : NULL; 691 } 692 693 static void sccnxp_release_port(struct uart_port *port) 694 { 695 /* Do nothing */ 696 } 697 698 static int sccnxp_request_port(struct uart_port *port) 699 { 700 /* Do nothing */ 701 return 0; 702 } 703 704 static void sccnxp_config_port(struct uart_port *port, int flags) 705 { 706 if (flags & UART_CONFIG_TYPE) 707 port->type = PORT_SC26XX; 708 } 709 710 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 711 { 712 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 713 return 0; 714 if (s->irq == port->irq) 715 return 0; 716 717 return -EINVAL; 718 } 719 720 static const struct uart_ops sccnxp_ops = { 721 .tx_empty = sccnxp_tx_empty, 722 .set_mctrl = sccnxp_set_mctrl, 723 .get_mctrl = sccnxp_get_mctrl, 724 .stop_tx = sccnxp_stop_tx, 725 .start_tx = sccnxp_start_tx, 726 .stop_rx = sccnxp_stop_rx, 727 .enable_ms = sccnxp_enable_ms, 728 .break_ctl = sccnxp_break_ctl, 729 .startup = sccnxp_startup, 730 .shutdown = sccnxp_shutdown, 731 .set_termios = sccnxp_set_termios, 732 .type = sccnxp_type, 733 .release_port = sccnxp_release_port, 734 .request_port = sccnxp_request_port, 735 .config_port = sccnxp_config_port, 736 .verify_port = sccnxp_verify_port, 737 }; 738 739 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 740 static void sccnxp_console_putchar(struct uart_port *port, int c) 741 { 742 int tryes = 100000; 743 744 while (tryes--) { 745 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 746 sccnxp_port_write(port, SCCNXP_THR_REG, c); 747 break; 748 } 749 barrier(); 750 } 751 } 752 753 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 754 { 755 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 756 struct uart_port *port = &s->port[co->index]; 757 unsigned long flags; 758 759 spin_lock_irqsave(&s->lock, flags); 760 uart_console_write(port, c, n, sccnxp_console_putchar); 761 spin_unlock_irqrestore(&s->lock, flags); 762 } 763 764 static int sccnxp_console_setup(struct console *co, char *options) 765 { 766 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 767 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 768 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 769 770 if (options) 771 uart_parse_options(options, &baud, &parity, &bits, &flow); 772 773 return uart_set_options(port, co, baud, parity, bits, flow); 774 } 775 #endif 776 777 static int sccnxp_probe(struct platform_device *pdev) 778 { 779 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 780 int chiptype = pdev->id_entry->driver_data; 781 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 782 int i, ret, fifosize, freq_min, freq_max; 783 struct sccnxp_port *s; 784 void __iomem *membase; 785 786 if (!res) { 787 dev_err(&pdev->dev, "Missing memory resource data\n"); 788 return -EADDRNOTAVAIL; 789 } 790 791 dev_set_name(&pdev->dev, SCCNXP_NAME); 792 793 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 794 if (!s) { 795 dev_err(&pdev->dev, "Error allocating port structure\n"); 796 return -ENOMEM; 797 } 798 platform_set_drvdata(pdev, s); 799 800 spin_lock_init(&s->lock); 801 802 /* Individual chip settings */ 803 switch (chiptype) { 804 case SCCNXP_TYPE_SC2681: 805 s->name = "SC2681"; 806 s->uart.nr = 2; 807 s->freq_std = 3686400; 808 s->addr_mask = 0x0f; 809 s->flags = SCCNXP_HAVE_IO; 810 fifosize = 3; 811 freq_min = 1000000; 812 freq_max = 4000000; 813 break; 814 case SCCNXP_TYPE_SC2691: 815 s->name = "SC2691"; 816 s->uart.nr = 1; 817 s->freq_std = 3686400; 818 s->addr_mask = 0x07; 819 s->flags = 0; 820 fifosize = 3; 821 freq_min = 1000000; 822 freq_max = 4000000; 823 break; 824 case SCCNXP_TYPE_SC2692: 825 s->name = "SC2692"; 826 s->uart.nr = 2; 827 s->freq_std = 3686400; 828 s->addr_mask = 0x0f; 829 s->flags = SCCNXP_HAVE_IO; 830 fifosize = 3; 831 freq_min = 1000000; 832 freq_max = 4000000; 833 break; 834 case SCCNXP_TYPE_SC2891: 835 s->name = "SC2891"; 836 s->uart.nr = 1; 837 s->freq_std = 3686400; 838 s->addr_mask = 0x0f; 839 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 840 fifosize = 16; 841 freq_min = 100000; 842 freq_max = 8000000; 843 break; 844 case SCCNXP_TYPE_SC2892: 845 s->name = "SC2892"; 846 s->uart.nr = 2; 847 s->freq_std = 3686400; 848 s->addr_mask = 0x0f; 849 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 850 fifosize = 16; 851 freq_min = 100000; 852 freq_max = 8000000; 853 break; 854 case SCCNXP_TYPE_SC28202: 855 s->name = "SC28202"; 856 s->uart.nr = 2; 857 s->freq_std = 14745600; 858 s->addr_mask = 0x7f; 859 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0; 860 fifosize = 256; 861 freq_min = 1000000; 862 freq_max = 50000000; 863 break; 864 case SCCNXP_TYPE_SC68681: 865 s->name = "SC68681"; 866 s->uart.nr = 2; 867 s->freq_std = 3686400; 868 s->addr_mask = 0x0f; 869 s->flags = SCCNXP_HAVE_IO; 870 fifosize = 3; 871 freq_min = 1000000; 872 freq_max = 4000000; 873 break; 874 case SCCNXP_TYPE_SC68692: 875 s->name = "SC68692"; 876 s->uart.nr = 2; 877 s->freq_std = 3686400; 878 s->addr_mask = 0x0f; 879 s->flags = SCCNXP_HAVE_IO; 880 fifosize = 3; 881 freq_min = 1000000; 882 freq_max = 4000000; 883 break; 884 default: 885 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype); 886 ret = -ENOTSUPP; 887 goto err_out; 888 } 889 890 if (!pdata) { 891 dev_warn(&pdev->dev, 892 "No platform data supplied, using defaults\n"); 893 s->pdata.frequency = s->freq_std; 894 } else 895 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 896 897 if (s->pdata.poll_time_us) { 898 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 899 s->pdata.poll_time_us); 900 s->poll = 1; 901 } 902 903 if (!s->poll) { 904 s->irq = platform_get_irq(pdev, 0); 905 if (s->irq < 0) { 906 dev_err(&pdev->dev, "Missing irq resource data\n"); 907 ret = -ENXIO; 908 goto err_out; 909 } 910 } 911 912 /* Check input frequency */ 913 if ((s->pdata.frequency < freq_min) || 914 (s->pdata.frequency > freq_max)) { 915 dev_err(&pdev->dev, "Frequency out of bounds\n"); 916 ret = -EINVAL; 917 goto err_out; 918 } 919 920 membase = devm_request_and_ioremap(&pdev->dev, res); 921 if (!membase) { 922 dev_err(&pdev->dev, "Failed to ioremap\n"); 923 ret = -EIO; 924 goto err_out; 925 } 926 927 s->uart.owner = THIS_MODULE; 928 s->uart.dev_name = "ttySC"; 929 s->uart.major = SCCNXP_MAJOR; 930 s->uart.minor = SCCNXP_MINOR; 931 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 932 s->uart.cons = &s->console; 933 s->uart.cons->device = uart_console_device; 934 s->uart.cons->write = sccnxp_console_write; 935 s->uart.cons->setup = sccnxp_console_setup; 936 s->uart.cons->flags = CON_PRINTBUFFER; 937 s->uart.cons->index = -1; 938 s->uart.cons->data = s; 939 strcpy(s->uart.cons->name, "ttySC"); 940 #endif 941 ret = uart_register_driver(&s->uart); 942 if (ret) { 943 dev_err(&pdev->dev, "Registering UART driver failed\n"); 944 goto err_out; 945 } 946 947 for (i = 0; i < s->uart.nr; i++) { 948 s->port[i].line = i; 949 s->port[i].dev = &pdev->dev; 950 s->port[i].irq = s->irq; 951 s->port[i].type = PORT_SC26XX; 952 s->port[i].fifosize = fifosize; 953 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 954 s->port[i].iotype = UPIO_MEM; 955 s->port[i].mapbase = res->start; 956 s->port[i].membase = membase; 957 s->port[i].regshift = s->pdata.reg_shift; 958 s->port[i].uartclk = s->pdata.frequency; 959 s->port[i].ops = &sccnxp_ops; 960 uart_add_one_port(&s->uart, &s->port[i]); 961 /* Set direction to input */ 962 if (s->flags & SCCNXP_HAVE_IO) 963 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 964 } 965 966 /* Disable interrupts */ 967 s->imr = 0; 968 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 969 970 /* Board specific configure */ 971 if (s->pdata.init) 972 s->pdata.init(); 973 974 if (!s->poll) { 975 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 976 sccnxp_ist, 977 IRQF_TRIGGER_FALLING | 978 IRQF_ONESHOT, 979 dev_name(&pdev->dev), s); 980 if (!ret) 981 return 0; 982 983 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 984 } else { 985 init_timer(&s->timer); 986 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 987 mod_timer(&s->timer, jiffies + 988 usecs_to_jiffies(s->pdata.poll_time_us)); 989 return 0; 990 } 991 992 err_out: 993 platform_set_drvdata(pdev, NULL); 994 995 return ret; 996 } 997 998 static int sccnxp_remove(struct platform_device *pdev) 999 { 1000 int i; 1001 struct sccnxp_port *s = platform_get_drvdata(pdev); 1002 1003 if (!s->poll) 1004 devm_free_irq(&pdev->dev, s->irq, s); 1005 else 1006 del_timer_sync(&s->timer); 1007 1008 for (i = 0; i < s->uart.nr; i++) 1009 uart_remove_one_port(&s->uart, &s->port[i]); 1010 1011 uart_unregister_driver(&s->uart); 1012 platform_set_drvdata(pdev, NULL); 1013 1014 if (s->pdata.exit) 1015 s->pdata.exit(); 1016 1017 return 0; 1018 } 1019 1020 static const struct platform_device_id sccnxp_id_table[] = { 1021 { "sc2681", SCCNXP_TYPE_SC2681 }, 1022 { "sc2691", SCCNXP_TYPE_SC2691 }, 1023 { "sc2692", SCCNXP_TYPE_SC2692 }, 1024 { "sc2891", SCCNXP_TYPE_SC2891 }, 1025 { "sc2892", SCCNXP_TYPE_SC2892 }, 1026 { "sc28202", SCCNXP_TYPE_SC28202 }, 1027 { "sc68681", SCCNXP_TYPE_SC68681 }, 1028 { "sc68692", SCCNXP_TYPE_SC68692 }, 1029 { }, 1030 }; 1031 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 1032 1033 static struct platform_driver sccnxp_uart_driver = { 1034 .driver = { 1035 .name = SCCNXP_NAME, 1036 .owner = THIS_MODULE, 1037 }, 1038 .probe = sccnxp_probe, 1039 .remove = sccnxp_remove, 1040 .id_table = sccnxp_id_table, 1041 }; 1042 module_platform_driver(sccnxp_uart_driver); 1043 1044 MODULE_LICENSE("GPL v2"); 1045 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1046 MODULE_DESCRIPTION("SCCNXP serial driver"); 1047