1 /* 2 * NXP (Philips) SCC+++(SCN+++) serial driver 3 * 4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 15 #define SUPPORT_SYSRQ 16 #endif 17 18 #include <linux/clk.h> 19 #include <linux/err.h> 20 #include <linux/module.h> 21 #include <linux/device.h> 22 #include <linux/console.h> 23 #include <linux/serial_core.h> 24 #include <linux/serial.h> 25 #include <linux/io.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/spinlock.h> 29 #include <linux/platform_device.h> 30 #include <linux/platform_data/serial-sccnxp.h> 31 #include <linux/regulator/consumer.h> 32 33 #define SCCNXP_NAME "uart-sccnxp" 34 #define SCCNXP_MAJOR 204 35 #define SCCNXP_MINOR 205 36 37 #define SCCNXP_MR_REG (0x00) 38 # define MR0_BAUD_NORMAL (0 << 0) 39 # define MR0_BAUD_EXT1 (1 << 0) 40 # define MR0_BAUD_EXT2 (5 << 0) 41 # define MR0_FIFO (1 << 3) 42 # define MR0_TXLVL (1 << 4) 43 # define MR1_BITS_5 (0 << 0) 44 # define MR1_BITS_6 (1 << 0) 45 # define MR1_BITS_7 (2 << 0) 46 # define MR1_BITS_8 (3 << 0) 47 # define MR1_PAR_EVN (0 << 2) 48 # define MR1_PAR_ODD (1 << 2) 49 # define MR1_PAR_NO (4 << 2) 50 # define MR2_STOP1 (7 << 0) 51 # define MR2_STOP2 (0xf << 0) 52 #define SCCNXP_SR_REG (0x01) 53 #define SCCNXP_CSR_REG SCCNXP_SR_REG 54 # define SR_RXRDY (1 << 0) 55 # define SR_FULL (1 << 1) 56 # define SR_TXRDY (1 << 2) 57 # define SR_TXEMT (1 << 3) 58 # define SR_OVR (1 << 4) 59 # define SR_PE (1 << 5) 60 # define SR_FE (1 << 6) 61 # define SR_BRK (1 << 7) 62 #define SCCNXP_CR_REG (0x02) 63 # define CR_RX_ENABLE (1 << 0) 64 # define CR_RX_DISABLE (1 << 1) 65 # define CR_TX_ENABLE (1 << 2) 66 # define CR_TX_DISABLE (1 << 3) 67 # define CR_CMD_MRPTR1 (0x01 << 4) 68 # define CR_CMD_RX_RESET (0x02 << 4) 69 # define CR_CMD_TX_RESET (0x03 << 4) 70 # define CR_CMD_STATUS_RESET (0x04 << 4) 71 # define CR_CMD_BREAK_RESET (0x05 << 4) 72 # define CR_CMD_START_BREAK (0x06 << 4) 73 # define CR_CMD_STOP_BREAK (0x07 << 4) 74 # define CR_CMD_MRPTR0 (0x0b << 4) 75 #define SCCNXP_RHR_REG (0x03) 76 #define SCCNXP_THR_REG SCCNXP_RHR_REG 77 #define SCCNXP_IPCR_REG (0x04) 78 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 79 # define ACR_BAUD0 (0 << 7) 80 # define ACR_BAUD1 (1 << 7) 81 # define ACR_TIMER_MODE (6 << 4) 82 #define SCCNXP_ISR_REG (0x05) 83 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 84 # define IMR_TXRDY (1 << 0) 85 # define IMR_RXRDY (1 << 1) 86 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 87 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 88 #define SCCNXP_IPR_REG (0x0d) 89 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 90 #define SCCNXP_SOP_REG (0x0e) 91 #define SCCNXP_ROP_REG (0x0f) 92 93 /* Route helpers */ 94 #define MCTRL_MASK(sig) (0xf << (sig)) 95 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 96 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 97 98 #define SCCNXP_HAVE_IO 0x00000001 99 #define SCCNXP_HAVE_MR0 0x00000002 100 101 struct sccnxp_chip { 102 const char *name; 103 unsigned int nr; 104 unsigned long freq_min; 105 unsigned long freq_std; 106 unsigned long freq_max; 107 unsigned int flags; 108 unsigned int fifosize; 109 }; 110 111 struct sccnxp_port { 112 struct uart_driver uart; 113 struct uart_port port[SCCNXP_MAX_UARTS]; 114 bool opened[SCCNXP_MAX_UARTS]; 115 116 int irq; 117 u8 imr; 118 119 struct sccnxp_chip *chip; 120 121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 122 struct console console; 123 #endif 124 125 spinlock_t lock; 126 127 bool poll; 128 struct timer_list timer; 129 130 struct sccnxp_pdata pdata; 131 132 struct regulator *regulator; 133 }; 134 135 static const struct sccnxp_chip sc2681 = { 136 .name = "SC2681", 137 .nr = 2, 138 .freq_min = 1000000, 139 .freq_std = 3686400, 140 .freq_max = 4000000, 141 .flags = SCCNXP_HAVE_IO, 142 .fifosize = 3, 143 }; 144 145 static const struct sccnxp_chip sc2691 = { 146 .name = "SC2691", 147 .nr = 1, 148 .freq_min = 1000000, 149 .freq_std = 3686400, 150 .freq_max = 4000000, 151 .flags = 0, 152 .fifosize = 3, 153 }; 154 155 static const struct sccnxp_chip sc2692 = { 156 .name = "SC2692", 157 .nr = 2, 158 .freq_min = 1000000, 159 .freq_std = 3686400, 160 .freq_max = 4000000, 161 .flags = SCCNXP_HAVE_IO, 162 .fifosize = 3, 163 }; 164 165 static const struct sccnxp_chip sc2891 = { 166 .name = "SC2891", 167 .nr = 1, 168 .freq_min = 100000, 169 .freq_std = 3686400, 170 .freq_max = 8000000, 171 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 172 .fifosize = 16, 173 }; 174 175 static const struct sccnxp_chip sc2892 = { 176 .name = "SC2892", 177 .nr = 2, 178 .freq_min = 100000, 179 .freq_std = 3686400, 180 .freq_max = 8000000, 181 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 182 .fifosize = 16, 183 }; 184 185 static const struct sccnxp_chip sc28202 = { 186 .name = "SC28202", 187 .nr = 2, 188 .freq_min = 1000000, 189 .freq_std = 14745600, 190 .freq_max = 50000000, 191 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 192 .fifosize = 256, 193 }; 194 195 static const struct sccnxp_chip sc68681 = { 196 .name = "SC68681", 197 .nr = 2, 198 .freq_min = 1000000, 199 .freq_std = 3686400, 200 .freq_max = 4000000, 201 .flags = SCCNXP_HAVE_IO, 202 .fifosize = 3, 203 }; 204 205 static const struct sccnxp_chip sc68692 = { 206 .name = "SC68692", 207 .nr = 2, 208 .freq_min = 1000000, 209 .freq_std = 3686400, 210 .freq_max = 4000000, 211 .flags = SCCNXP_HAVE_IO, 212 .fifosize = 3, 213 }; 214 215 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 216 { 217 return readb(port->membase + (reg << port->regshift)); 218 } 219 220 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 221 { 222 writeb(v, port->membase + (reg << port->regshift)); 223 } 224 225 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 226 { 227 return sccnxp_read(port, (port->line << 3) + reg); 228 } 229 230 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 231 { 232 sccnxp_write(port, (port->line << 3) + reg, v); 233 } 234 235 static int sccnxp_update_best_err(int a, int b, int *besterr) 236 { 237 int err = abs(a - b); 238 239 if ((*besterr < 0) || (*besterr > err)) { 240 *besterr = err; 241 return 0; 242 } 243 244 return 1; 245 } 246 247 static const struct { 248 u8 csr; 249 u8 acr; 250 u8 mr0; 251 int baud; 252 } baud_std[] = { 253 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 254 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 255 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 256 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 257 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 258 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 259 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 260 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 261 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 262 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 263 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 264 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 265 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 266 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 267 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 268 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 269 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 270 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 271 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 272 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 273 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 274 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 275 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 276 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 277 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 278 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 279 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 280 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 281 { 0, 0, 0, 0 } 282 }; 283 284 static int sccnxp_set_baud(struct uart_port *port, int baud) 285 { 286 struct sccnxp_port *s = dev_get_drvdata(port->dev); 287 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 288 struct sccnxp_chip *chip = s->chip; 289 u8 i, acr = 0, csr = 0, mr0 = 0; 290 291 /* Find best baud from table */ 292 for (i = 0; baud_std[i].baud && besterr; i++) { 293 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0)) 294 continue; 295 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud); 296 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 297 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 298 acr = baud_std[i].acr; 299 csr = baud_std[i].csr; 300 mr0 = baud_std[i].mr0; 301 bestbaud = tmp_baud; 302 } 303 } 304 305 if (chip->flags & SCCNXP_HAVE_MR0) { 306 /* Enable FIFO, set half level for TX */ 307 mr0 |= MR0_FIFO | MR0_TXLVL; 308 /* Update MR0 */ 309 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 310 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 311 } 312 313 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 314 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 315 316 if (baud != bestbaud) 317 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 318 baud, bestbaud); 319 320 return bestbaud; 321 } 322 323 static void sccnxp_enable_irq(struct uart_port *port, int mask) 324 { 325 struct sccnxp_port *s = dev_get_drvdata(port->dev); 326 327 s->imr |= mask << (port->line * 4); 328 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 329 } 330 331 static void sccnxp_disable_irq(struct uart_port *port, int mask) 332 { 333 struct sccnxp_port *s = dev_get_drvdata(port->dev); 334 335 s->imr &= ~(mask << (port->line * 4)); 336 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 337 } 338 339 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 340 { 341 u8 bitmask; 342 struct sccnxp_port *s = dev_get_drvdata(port->dev); 343 344 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 345 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 346 if (state) 347 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 348 else 349 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 350 } 351 } 352 353 static void sccnxp_handle_rx(struct uart_port *port) 354 { 355 u8 sr; 356 unsigned int ch, flag; 357 358 for (;;) { 359 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 360 if (!(sr & SR_RXRDY)) 361 break; 362 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 363 364 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 365 366 port->icount.rx++; 367 flag = TTY_NORMAL; 368 369 if (unlikely(sr)) { 370 if (sr & SR_BRK) { 371 port->icount.brk++; 372 sccnxp_port_write(port, SCCNXP_CR_REG, 373 CR_CMD_BREAK_RESET); 374 if (uart_handle_break(port)) 375 continue; 376 } else if (sr & SR_PE) 377 port->icount.parity++; 378 else if (sr & SR_FE) 379 port->icount.frame++; 380 else if (sr & SR_OVR) { 381 port->icount.overrun++; 382 sccnxp_port_write(port, SCCNXP_CR_REG, 383 CR_CMD_STATUS_RESET); 384 } 385 386 sr &= port->read_status_mask; 387 if (sr & SR_BRK) 388 flag = TTY_BREAK; 389 else if (sr & SR_PE) 390 flag = TTY_PARITY; 391 else if (sr & SR_FE) 392 flag = TTY_FRAME; 393 else if (sr & SR_OVR) 394 flag = TTY_OVERRUN; 395 } 396 397 if (uart_handle_sysrq_char(port, ch)) 398 continue; 399 400 if (sr & port->ignore_status_mask) 401 continue; 402 403 uart_insert_char(port, sr, SR_OVR, ch, flag); 404 } 405 406 tty_flip_buffer_push(&port->state->port); 407 } 408 409 static void sccnxp_handle_tx(struct uart_port *port) 410 { 411 u8 sr; 412 struct circ_buf *xmit = &port->state->xmit; 413 struct sccnxp_port *s = dev_get_drvdata(port->dev); 414 415 if (unlikely(port->x_char)) { 416 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 417 port->icount.tx++; 418 port->x_char = 0; 419 return; 420 } 421 422 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 423 /* Disable TX if FIFO is empty */ 424 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 425 sccnxp_disable_irq(port, IMR_TXRDY); 426 427 /* Set direction to input */ 428 if (s->chip->flags & SCCNXP_HAVE_IO) 429 sccnxp_set_bit(port, DIR_OP, 0); 430 } 431 return; 432 } 433 434 while (!uart_circ_empty(xmit)) { 435 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 436 if (!(sr & SR_TXRDY)) 437 break; 438 439 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 441 port->icount.tx++; 442 } 443 444 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 445 uart_write_wakeup(port); 446 } 447 448 static void sccnxp_handle_events(struct sccnxp_port *s) 449 { 450 int i; 451 u8 isr; 452 453 do { 454 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 455 isr &= s->imr; 456 if (!isr) 457 break; 458 459 for (i = 0; i < s->uart.nr; i++) { 460 if (s->opened[i] && (isr & ISR_RXRDY(i))) 461 sccnxp_handle_rx(&s->port[i]); 462 if (s->opened[i] && (isr & ISR_TXRDY(i))) 463 sccnxp_handle_tx(&s->port[i]); 464 } 465 } while (1); 466 } 467 468 static void sccnxp_timer(unsigned long data) 469 { 470 struct sccnxp_port *s = (struct sccnxp_port *)data; 471 unsigned long flags; 472 473 spin_lock_irqsave(&s->lock, flags); 474 sccnxp_handle_events(s); 475 spin_unlock_irqrestore(&s->lock, flags); 476 477 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us)); 478 } 479 480 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 481 { 482 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 483 unsigned long flags; 484 485 spin_lock_irqsave(&s->lock, flags); 486 sccnxp_handle_events(s); 487 spin_unlock_irqrestore(&s->lock, flags); 488 489 return IRQ_HANDLED; 490 } 491 492 static void sccnxp_start_tx(struct uart_port *port) 493 { 494 struct sccnxp_port *s = dev_get_drvdata(port->dev); 495 unsigned long flags; 496 497 spin_lock_irqsave(&s->lock, flags); 498 499 /* Set direction to output */ 500 if (s->chip->flags & SCCNXP_HAVE_IO) 501 sccnxp_set_bit(port, DIR_OP, 1); 502 503 sccnxp_enable_irq(port, IMR_TXRDY); 504 505 spin_unlock_irqrestore(&s->lock, flags); 506 } 507 508 static void sccnxp_stop_tx(struct uart_port *port) 509 { 510 /* Do nothing */ 511 } 512 513 static void sccnxp_stop_rx(struct uart_port *port) 514 { 515 struct sccnxp_port *s = dev_get_drvdata(port->dev); 516 unsigned long flags; 517 518 spin_lock_irqsave(&s->lock, flags); 519 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 520 spin_unlock_irqrestore(&s->lock, flags); 521 } 522 523 static unsigned int sccnxp_tx_empty(struct uart_port *port) 524 { 525 u8 val; 526 unsigned long flags; 527 struct sccnxp_port *s = dev_get_drvdata(port->dev); 528 529 spin_lock_irqsave(&s->lock, flags); 530 val = sccnxp_port_read(port, SCCNXP_SR_REG); 531 spin_unlock_irqrestore(&s->lock, flags); 532 533 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 534 } 535 536 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 537 { 538 struct sccnxp_port *s = dev_get_drvdata(port->dev); 539 unsigned long flags; 540 541 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 542 return; 543 544 spin_lock_irqsave(&s->lock, flags); 545 546 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 547 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 548 549 spin_unlock_irqrestore(&s->lock, flags); 550 } 551 552 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 553 { 554 u8 bitmask, ipr; 555 unsigned long flags; 556 struct sccnxp_port *s = dev_get_drvdata(port->dev); 557 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 558 559 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 560 return mctrl; 561 562 spin_lock_irqsave(&s->lock, flags); 563 564 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 565 566 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 567 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 568 DSR_IP); 569 mctrl &= ~TIOCM_DSR; 570 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 571 } 572 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 573 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 574 CTS_IP); 575 mctrl &= ~TIOCM_CTS; 576 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 577 } 578 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 579 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 580 DCD_IP); 581 mctrl &= ~TIOCM_CAR; 582 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 583 } 584 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 585 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 586 RNG_IP); 587 mctrl &= ~TIOCM_RNG; 588 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 589 } 590 591 spin_unlock_irqrestore(&s->lock, flags); 592 593 return mctrl; 594 } 595 596 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 597 { 598 struct sccnxp_port *s = dev_get_drvdata(port->dev); 599 unsigned long flags; 600 601 spin_lock_irqsave(&s->lock, flags); 602 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 603 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 604 spin_unlock_irqrestore(&s->lock, flags); 605 } 606 607 static void sccnxp_set_termios(struct uart_port *port, 608 struct ktermios *termios, struct ktermios *old) 609 { 610 struct sccnxp_port *s = dev_get_drvdata(port->dev); 611 unsigned long flags; 612 u8 mr1, mr2; 613 int baud; 614 615 spin_lock_irqsave(&s->lock, flags); 616 617 /* Mask termios capabilities we don't support */ 618 termios->c_cflag &= ~CMSPAR; 619 620 /* Disable RX & TX, reset break condition, status and FIFOs */ 621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 622 CR_RX_DISABLE | CR_TX_DISABLE); 623 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 624 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 626 627 /* Word size */ 628 switch (termios->c_cflag & CSIZE) { 629 case CS5: 630 mr1 = MR1_BITS_5; 631 break; 632 case CS6: 633 mr1 = MR1_BITS_6; 634 break; 635 case CS7: 636 mr1 = MR1_BITS_7; 637 break; 638 case CS8: 639 default: 640 mr1 = MR1_BITS_8; 641 break; 642 } 643 644 /* Parity */ 645 if (termios->c_cflag & PARENB) { 646 if (termios->c_cflag & PARODD) 647 mr1 |= MR1_PAR_ODD; 648 } else 649 mr1 |= MR1_PAR_NO; 650 651 /* Stop bits */ 652 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 653 654 /* Update desired format */ 655 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 656 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 657 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 658 659 /* Set read status mask */ 660 port->read_status_mask = SR_OVR; 661 if (termios->c_iflag & INPCK) 662 port->read_status_mask |= SR_PE | SR_FE; 663 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 664 port->read_status_mask |= SR_BRK; 665 666 /* Set status ignore mask */ 667 port->ignore_status_mask = 0; 668 if (termios->c_iflag & IGNBRK) 669 port->ignore_status_mask |= SR_BRK; 670 if (termios->c_iflag & IGNPAR) 671 port->ignore_status_mask |= SR_PE; 672 if (!(termios->c_cflag & CREAD)) 673 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 674 675 /* Setup baudrate */ 676 baud = uart_get_baud_rate(port, termios, old, 50, 677 (s->chip->flags & SCCNXP_HAVE_MR0) ? 678 230400 : 38400); 679 baud = sccnxp_set_baud(port, baud); 680 681 /* Update timeout according to new baud rate */ 682 uart_update_timeout(port, termios->c_cflag, baud); 683 684 /* Report actual baudrate back to core */ 685 if (tty_termios_baud_rate(termios)) 686 tty_termios_encode_baud_rate(termios, baud, baud); 687 688 /* Enable RX & TX */ 689 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 690 691 spin_unlock_irqrestore(&s->lock, flags); 692 } 693 694 static int sccnxp_startup(struct uart_port *port) 695 { 696 struct sccnxp_port *s = dev_get_drvdata(port->dev); 697 unsigned long flags; 698 699 spin_lock_irqsave(&s->lock, flags); 700 701 if (s->chip->flags & SCCNXP_HAVE_IO) { 702 /* Outputs are controlled manually */ 703 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 704 } 705 706 /* Reset break condition, status and FIFOs */ 707 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 708 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 709 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 710 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 711 712 /* Enable RX & TX */ 713 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 714 715 /* Enable RX interrupt */ 716 sccnxp_enable_irq(port, IMR_RXRDY); 717 718 s->opened[port->line] = 1; 719 720 spin_unlock_irqrestore(&s->lock, flags); 721 722 return 0; 723 } 724 725 static void sccnxp_shutdown(struct uart_port *port) 726 { 727 struct sccnxp_port *s = dev_get_drvdata(port->dev); 728 unsigned long flags; 729 730 spin_lock_irqsave(&s->lock, flags); 731 732 s->opened[port->line] = 0; 733 734 /* Disable interrupts */ 735 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 736 737 /* Disable TX & RX */ 738 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 739 740 /* Leave direction to input */ 741 if (s->chip->flags & SCCNXP_HAVE_IO) 742 sccnxp_set_bit(port, DIR_OP, 0); 743 744 spin_unlock_irqrestore(&s->lock, flags); 745 } 746 747 static const char *sccnxp_type(struct uart_port *port) 748 { 749 struct sccnxp_port *s = dev_get_drvdata(port->dev); 750 751 return (port->type == PORT_SC26XX) ? s->chip->name : NULL; 752 } 753 754 static void sccnxp_release_port(struct uart_port *port) 755 { 756 /* Do nothing */ 757 } 758 759 static int sccnxp_request_port(struct uart_port *port) 760 { 761 /* Do nothing */ 762 return 0; 763 } 764 765 static void sccnxp_config_port(struct uart_port *port, int flags) 766 { 767 if (flags & UART_CONFIG_TYPE) 768 port->type = PORT_SC26XX; 769 } 770 771 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 772 { 773 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 774 return 0; 775 if (s->irq == port->irq) 776 return 0; 777 778 return -EINVAL; 779 } 780 781 static const struct uart_ops sccnxp_ops = { 782 .tx_empty = sccnxp_tx_empty, 783 .set_mctrl = sccnxp_set_mctrl, 784 .get_mctrl = sccnxp_get_mctrl, 785 .stop_tx = sccnxp_stop_tx, 786 .start_tx = sccnxp_start_tx, 787 .stop_rx = sccnxp_stop_rx, 788 .break_ctl = sccnxp_break_ctl, 789 .startup = sccnxp_startup, 790 .shutdown = sccnxp_shutdown, 791 .set_termios = sccnxp_set_termios, 792 .type = sccnxp_type, 793 .release_port = sccnxp_release_port, 794 .request_port = sccnxp_request_port, 795 .config_port = sccnxp_config_port, 796 .verify_port = sccnxp_verify_port, 797 }; 798 799 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 800 static void sccnxp_console_putchar(struct uart_port *port, int c) 801 { 802 int tryes = 100000; 803 804 while (tryes--) { 805 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 806 sccnxp_port_write(port, SCCNXP_THR_REG, c); 807 break; 808 } 809 barrier(); 810 } 811 } 812 813 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 814 { 815 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 816 struct uart_port *port = &s->port[co->index]; 817 unsigned long flags; 818 819 spin_lock_irqsave(&s->lock, flags); 820 uart_console_write(port, c, n, sccnxp_console_putchar); 821 spin_unlock_irqrestore(&s->lock, flags); 822 } 823 824 static int sccnxp_console_setup(struct console *co, char *options) 825 { 826 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 827 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 828 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 829 830 if (options) 831 uart_parse_options(options, &baud, &parity, &bits, &flow); 832 833 return uart_set_options(port, co, baud, parity, bits, flow); 834 } 835 #endif 836 837 static const struct platform_device_id sccnxp_id_table[] = { 838 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, }, 839 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, }, 840 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, }, 841 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, }, 842 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, }, 843 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, }, 844 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, }, 845 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, }, 846 { } 847 }; 848 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 849 850 static int sccnxp_probe(struct platform_device *pdev) 851 { 852 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 853 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 854 int i, ret, uartclk; 855 struct sccnxp_port *s; 856 void __iomem *membase; 857 struct clk *clk; 858 859 membase = devm_ioremap_resource(&pdev->dev, res); 860 if (IS_ERR(membase)) 861 return PTR_ERR(membase); 862 863 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 864 if (!s) { 865 dev_err(&pdev->dev, "Error allocating port structure\n"); 866 return -ENOMEM; 867 } 868 platform_set_drvdata(pdev, s); 869 870 spin_lock_init(&s->lock); 871 872 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data; 873 874 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 875 if (!IS_ERR(s->regulator)) { 876 ret = regulator_enable(s->regulator); 877 if (ret) { 878 dev_err(&pdev->dev, 879 "Failed to enable regulator: %i\n", ret); 880 return ret; 881 } 882 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) 883 return -EPROBE_DEFER; 884 885 clk = devm_clk_get(&pdev->dev, NULL); 886 if (IS_ERR(clk)) { 887 if (PTR_ERR(clk) == -EPROBE_DEFER) { 888 ret = -EPROBE_DEFER; 889 goto err_out; 890 } 891 dev_notice(&pdev->dev, "Using default clock frequency\n"); 892 uartclk = s->chip->freq_std; 893 } else 894 uartclk = clk_get_rate(clk); 895 896 /* Check input frequency */ 897 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { 898 dev_err(&pdev->dev, "Frequency out of bounds\n"); 899 ret = -EINVAL; 900 goto err_out; 901 } 902 903 if (pdata) 904 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 905 906 if (s->pdata.poll_time_us) { 907 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 908 s->pdata.poll_time_us); 909 s->poll = 1; 910 } 911 912 if (!s->poll) { 913 s->irq = platform_get_irq(pdev, 0); 914 if (s->irq < 0) { 915 dev_err(&pdev->dev, "Missing irq resource data\n"); 916 ret = -ENXIO; 917 goto err_out; 918 } 919 } 920 921 s->uart.owner = THIS_MODULE; 922 s->uart.dev_name = "ttySC"; 923 s->uart.major = SCCNXP_MAJOR; 924 s->uart.minor = SCCNXP_MINOR; 925 s->uart.nr = s->chip->nr; 926 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 927 s->uart.cons = &s->console; 928 s->uart.cons->device = uart_console_device; 929 s->uart.cons->write = sccnxp_console_write; 930 s->uart.cons->setup = sccnxp_console_setup; 931 s->uart.cons->flags = CON_PRINTBUFFER; 932 s->uart.cons->index = -1; 933 s->uart.cons->data = s; 934 strcpy(s->uart.cons->name, "ttySC"); 935 #endif 936 ret = uart_register_driver(&s->uart); 937 if (ret) { 938 dev_err(&pdev->dev, "Registering UART driver failed\n"); 939 goto err_out; 940 } 941 942 for (i = 0; i < s->uart.nr; i++) { 943 s->port[i].line = i; 944 s->port[i].dev = &pdev->dev; 945 s->port[i].irq = s->irq; 946 s->port[i].type = PORT_SC26XX; 947 s->port[i].fifosize = s->chip->fifosize; 948 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 949 s->port[i].iotype = UPIO_MEM; 950 s->port[i].mapbase = res->start; 951 s->port[i].membase = membase; 952 s->port[i].regshift = s->pdata.reg_shift; 953 s->port[i].uartclk = uartclk; 954 s->port[i].ops = &sccnxp_ops; 955 uart_add_one_port(&s->uart, &s->port[i]); 956 /* Set direction to input */ 957 if (s->chip->flags & SCCNXP_HAVE_IO) 958 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 959 } 960 961 /* Disable interrupts */ 962 s->imr = 0; 963 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 964 965 if (!s->poll) { 966 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 967 sccnxp_ist, 968 IRQF_TRIGGER_FALLING | 969 IRQF_ONESHOT, 970 dev_name(&pdev->dev), s); 971 if (!ret) 972 return 0; 973 974 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 975 } else { 976 init_timer(&s->timer); 977 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 978 mod_timer(&s->timer, jiffies + 979 usecs_to_jiffies(s->pdata.poll_time_us)); 980 return 0; 981 } 982 983 uart_unregister_driver(&s->uart); 984 err_out: 985 if (!IS_ERR(s->regulator)) 986 return regulator_disable(s->regulator); 987 988 return ret; 989 } 990 991 static int sccnxp_remove(struct platform_device *pdev) 992 { 993 int i; 994 struct sccnxp_port *s = platform_get_drvdata(pdev); 995 996 if (!s->poll) 997 devm_free_irq(&pdev->dev, s->irq, s); 998 else 999 del_timer_sync(&s->timer); 1000 1001 for (i = 0; i < s->uart.nr; i++) 1002 uart_remove_one_port(&s->uart, &s->port[i]); 1003 1004 uart_unregister_driver(&s->uart); 1005 1006 if (!IS_ERR(s->regulator)) 1007 return regulator_disable(s->regulator); 1008 1009 return 0; 1010 } 1011 1012 static struct platform_driver sccnxp_uart_driver = { 1013 .driver = { 1014 .name = SCCNXP_NAME, 1015 }, 1016 .probe = sccnxp_probe, 1017 .remove = sccnxp_remove, 1018 .id_table = sccnxp_id_table, 1019 }; 1020 module_platform_driver(sccnxp_uart_driver); 1021 1022 MODULE_LICENSE("GPL v2"); 1023 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1024 MODULE_DESCRIPTION("SCCNXP serial driver"); 1025