1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/sched.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 #include <linux/units.h> 29 30 #define SC16IS7XX_NAME "sc16is7xx" 31 #define SC16IS7XX_MAX_DEVS 8 32 33 /* SC16IS7XX register definitions */ 34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 47 * - only on 75x/76x 48 */ 49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 50 * - only on 75x/76x 51 */ 52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 53 * - only on 75x/76x 54 */ 55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 56 * - only on 75x/76x 57 */ 58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 59 60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 63 64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 67 68 /* Enhanced Register set: Only if (LCR == 0xBF) */ 69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 74 75 /* IER register bits */ 76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 78 * interrupt */ 79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 80 * interrupt */ 81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 82 * interrupt */ 83 84 /* IER register bits - write only if (EFR[4] == 1) */ 85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 89 90 /* FCR register bits */ 91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 96 97 /* FCR register bits - write only if (EFR[4] == 1) */ 98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 100 101 /* IIR register bits */ 102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 109 * - only on 75x/76x 110 */ 111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 112 * - only on 75x/76x 113 */ 114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 116 * from active (LOW) 117 * to inactive (HIGH) 118 */ 119 /* LCR register bits */ 120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 122 * 123 * Word length bits table: 124 * 00 -> 5 bit words 125 * 01 -> 6 bit words 126 * 10 -> 7 bit words 127 * 11 -> 8 bit words 128 */ 129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 130 * 131 * STOP length bit table: 132 * 0 -> 1 stop bit 133 * 1 -> 1-1.5 stop bits if 134 * word length is 5, 135 * 2 stop bits otherwise 136 */ 137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 147 * reg set */ 148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 149 * reg set */ 150 151 /* MCR register bits */ 152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 153 * - only on 75x/76x 154 */ 155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 159 * - write enabled 160 * if (EFR[4] == 1) 161 */ 162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 171 /* LSR register bits */ 172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 181 182 /* MSR register bits */ 183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 185 * or (IO4) 186 * - only on 75x/76x 187 */ 188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 189 * or (IO7) 190 * - only on 75x/76x 191 */ 192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 193 * or (IO6) 194 * - only on 75x/76x 195 */ 196 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 197 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 198 * - only on 75x/76x 199 */ 200 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 201 * - only on 75x/76x 202 */ 203 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 204 * - only on 75x/76x 205 */ 206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 207 208 /* 209 * TCR register bits 210 * TCR trigger levels are available from 0 to 60 characters with a granularity 211 * of four. 212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 213 * no built-in hardware check to make sure this condition is met. Also, the TCR 214 * must be programmed with this condition before auto RTS or software flow 215 * control is enabled to avoid spurious operation of the device. 216 */ 217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 219 220 /* 221 * TLR register bits 222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 224 * trigger levels. Trigger levels from 4 characters to 60 characters are 225 * available with a granularity of four. 226 * 227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 229 * the trigger level defined in FCR is discarded. This applies to both transmit 230 * FIFO and receive FIFO trigger level setting. 231 * 232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 233 * default state, that is, '00'. 234 */ 235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 237 238 /* IOControl register bits (Only 750/760) */ 239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 240 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 241 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 242 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 243 244 /* EFCR register bits */ 245 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 246 * mode (RS485) */ 247 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 248 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 249 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 250 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 251 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 252 * 0 = rate upto 115.2 kbit/s 253 * - Only 750/760 254 * 1 = rate upto 1.152 Mbit/s 255 * - Only 760 256 */ 257 258 /* EFR register bits */ 259 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 260 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 261 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 262 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 263 * and writing to IER[7:4], 264 * FCR[5:4], MCR[7:5] 265 */ 266 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 267 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 268 * 269 * SWFLOW bits 3 & 2 table: 270 * 00 -> no transmitter flow 271 * control 272 * 01 -> transmitter generates 273 * XON2 and XOFF2 274 * 10 -> transmitter generates 275 * XON1 and XOFF1 276 * 11 -> transmitter generates 277 * XON1, XON2, XOFF1 and 278 * XOFF2 279 */ 280 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 281 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 282 * 283 * SWFLOW bits 3 & 2 table: 284 * 00 -> no received flow 285 * control 286 * 01 -> receiver compares 287 * XON2 and XOFF2 288 * 10 -> receiver compares 289 * XON1 and XOFF1 290 * 11 -> receiver compares 291 * XON1, XON2, XOFF1 and 292 * XOFF2 293 */ 294 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 295 SC16IS7XX_EFR_AUTOCTS_BIT | \ 296 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 297 SC16IS7XX_EFR_SWFLOW3_BIT | \ 298 SC16IS7XX_EFR_SWFLOW2_BIT | \ 299 SC16IS7XX_EFR_SWFLOW1_BIT | \ 300 SC16IS7XX_EFR_SWFLOW0_BIT) 301 302 303 /* Misc definitions */ 304 #define SC16IS7XX_SPI_READ_BIT BIT(7) 305 #define SC16IS7XX_FIFO_SIZE (64) 306 #define SC16IS7XX_GPIOS_PER_BANK 4 307 308 struct sc16is7xx_devtype { 309 char name[10]; 310 int nr_gpio; 311 int nr_uart; 312 }; 313 314 #define SC16IS7XX_RECONF_MD (1 << 0) 315 #define SC16IS7XX_RECONF_IER (1 << 1) 316 #define SC16IS7XX_RECONF_RS485 (1 << 2) 317 318 struct sc16is7xx_one_config { 319 unsigned int flags; 320 u8 ier_mask; 321 u8 ier_val; 322 }; 323 324 struct sc16is7xx_one { 325 struct uart_port port; 326 struct regmap *regmap; 327 struct mutex efr_lock; /* EFR registers access */ 328 struct kthread_work tx_work; 329 struct kthread_work reg_work; 330 struct kthread_delayed_work ms_work; 331 struct sc16is7xx_one_config config; 332 bool irda_mode; 333 unsigned int old_mctrl; 334 }; 335 336 struct sc16is7xx_port { 337 const struct sc16is7xx_devtype *devtype; 338 struct clk *clk; 339 #ifdef CONFIG_GPIOLIB 340 struct gpio_chip gpio; 341 unsigned long gpio_valid_mask; 342 #endif 343 u8 mctrl_mask; 344 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 345 struct kthread_worker kworker; 346 struct task_struct *kworker_task; 347 struct sc16is7xx_one p[]; 348 }; 349 350 static unsigned long sc16is7xx_lines; 351 352 static struct uart_driver sc16is7xx_uart = { 353 .owner = THIS_MODULE, 354 .dev_name = "ttySC", 355 .nr = SC16IS7XX_MAX_DEVS, 356 }; 357 358 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 359 static void sc16is7xx_stop_tx(struct uart_port *port); 360 361 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 362 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 363 364 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 365 { 366 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 367 unsigned int val = 0; 368 369 regmap_read(one->regmap, reg, &val); 370 371 return val; 372 } 373 374 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 375 { 376 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 377 378 regmap_write(one->regmap, reg, val); 379 } 380 381 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 382 { 383 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 384 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 385 386 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, s->buf, rxlen); 387 } 388 389 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 390 { 391 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 392 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 393 394 /* 395 * Don't send zero-length data, at least on SPI it confuses the chip 396 * delivering wrong TXLVL data. 397 */ 398 if (unlikely(!to_send)) 399 return; 400 401 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, s->buf, to_send); 402 } 403 404 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 405 u8 mask, u8 val) 406 { 407 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 408 409 regmap_update_bits(one->regmap, reg, mask, val); 410 } 411 412 static void sc16is7xx_power(struct uart_port *port, int on) 413 { 414 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 415 SC16IS7XX_IER_SLEEP_BIT, 416 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 417 } 418 419 static const struct sc16is7xx_devtype sc16is74x_devtype = { 420 .name = "SC16IS74X", 421 .nr_gpio = 0, 422 .nr_uart = 1, 423 }; 424 425 static const struct sc16is7xx_devtype sc16is750_devtype = { 426 .name = "SC16IS750", 427 .nr_gpio = 8, 428 .nr_uart = 1, 429 }; 430 431 static const struct sc16is7xx_devtype sc16is752_devtype = { 432 .name = "SC16IS752", 433 .nr_gpio = 8, 434 .nr_uart = 2, 435 }; 436 437 static const struct sc16is7xx_devtype sc16is760_devtype = { 438 .name = "SC16IS760", 439 .nr_gpio = 8, 440 .nr_uart = 1, 441 }; 442 443 static const struct sc16is7xx_devtype sc16is762_devtype = { 444 .name = "SC16IS762", 445 .nr_gpio = 8, 446 .nr_uart = 2, 447 }; 448 449 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 450 { 451 switch (reg) { 452 case SC16IS7XX_RHR_REG: 453 case SC16IS7XX_IIR_REG: 454 case SC16IS7XX_LSR_REG: 455 case SC16IS7XX_MSR_REG: 456 case SC16IS7XX_TXLVL_REG: 457 case SC16IS7XX_RXLVL_REG: 458 case SC16IS7XX_IOSTATE_REG: 459 case SC16IS7XX_IOCONTROL_REG: 460 return true; 461 default: 462 break; 463 } 464 465 return false; 466 } 467 468 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 469 { 470 switch (reg) { 471 case SC16IS7XX_RHR_REG: 472 return true; 473 default: 474 break; 475 } 476 477 return false; 478 } 479 480 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 481 { 482 return reg == SC16IS7XX_RHR_REG; 483 } 484 485 /* 486 * Configure programmable baud rate generator (divisor) according to the 487 * desired baud rate. 488 * 489 * From the datasheet, the divisor is computed according to: 490 * 491 * XTAL1 input frequency 492 * ----------------------- 493 * prescaler 494 * divisor = --------------------------- 495 * baud-rate x sampling-rate 496 */ 497 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 498 { 499 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 500 u8 lcr; 501 unsigned int prescaler = 1; 502 unsigned long clk = port->uartclk, div = clk / 16 / baud; 503 504 if (div >= BIT(16)) { 505 prescaler = 4; 506 div /= prescaler; 507 } 508 509 /* In an amazing feat of design, the Enhanced Features Register shares 510 * the address of the Interrupt Identification Register, and is 511 * switched in by writing a magic value (0xbf) to the Line Control 512 * Register. Any interrupt firing during this time will see the EFR 513 * where it expects the IIR to be, leading to "Unexpected interrupt" 514 * messages. 515 * 516 * Prevent this possibility by claiming a mutex while accessing the 517 * EFR, and claiming the same mutex from within the interrupt handler. 518 * This is similar to disabling the interrupt, but that doesn't work 519 * because the bulk of the interrupt processing is run as a workqueue 520 * job in thread context. 521 */ 522 mutex_lock(&one->efr_lock); 523 524 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 525 526 /* Open the LCR divisors for configuration */ 527 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 528 SC16IS7XX_LCR_CONF_MODE_B); 529 530 /* Enable enhanced features */ 531 regcache_cache_bypass(one->regmap, true); 532 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 533 SC16IS7XX_EFR_ENABLE_BIT, 534 SC16IS7XX_EFR_ENABLE_BIT); 535 536 regcache_cache_bypass(one->regmap, false); 537 538 /* Put LCR back to the normal mode */ 539 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 540 541 mutex_unlock(&one->efr_lock); 542 543 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */ 544 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 545 SC16IS7XX_MCR_CLKSEL_BIT, 546 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT); 547 548 mutex_lock(&one->efr_lock); 549 550 /* Open the LCR divisors for configuration */ 551 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 552 SC16IS7XX_LCR_CONF_MODE_A); 553 554 /* Write the new divisor */ 555 regcache_cache_bypass(one->regmap, true); 556 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 557 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 558 regcache_cache_bypass(one->regmap, false); 559 560 /* Put LCR back to the normal mode */ 561 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 562 563 mutex_unlock(&one->efr_lock); 564 565 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div); 566 } 567 568 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 569 unsigned int iir) 570 { 571 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 572 unsigned int lsr = 0, bytes_read, i; 573 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 574 u8 ch, flag; 575 576 if (unlikely(rxlen >= sizeof(s->buf))) { 577 dev_warn_ratelimited(port->dev, 578 "ttySC%i: Possible RX FIFO overrun: %d\n", 579 port->line, rxlen); 580 port->icount.buf_overrun++; 581 /* Ensure sanity of RX level */ 582 rxlen = sizeof(s->buf); 583 } 584 585 while (rxlen) { 586 /* Only read lsr if there are possible errors in FIFO */ 587 if (read_lsr) { 588 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 589 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 590 read_lsr = false; /* No errors left in FIFO */ 591 } else 592 lsr = 0; 593 594 if (read_lsr) { 595 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 596 bytes_read = 1; 597 } else { 598 sc16is7xx_fifo_read(port, rxlen); 599 bytes_read = rxlen; 600 } 601 602 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 603 604 port->icount.rx++; 605 flag = TTY_NORMAL; 606 607 if (unlikely(lsr)) { 608 if (lsr & SC16IS7XX_LSR_BI_BIT) { 609 port->icount.brk++; 610 if (uart_handle_break(port)) 611 continue; 612 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 613 port->icount.parity++; 614 else if (lsr & SC16IS7XX_LSR_FE_BIT) 615 port->icount.frame++; 616 else if (lsr & SC16IS7XX_LSR_OE_BIT) 617 port->icount.overrun++; 618 619 lsr &= port->read_status_mask; 620 if (lsr & SC16IS7XX_LSR_BI_BIT) 621 flag = TTY_BREAK; 622 else if (lsr & SC16IS7XX_LSR_PE_BIT) 623 flag = TTY_PARITY; 624 else if (lsr & SC16IS7XX_LSR_FE_BIT) 625 flag = TTY_FRAME; 626 else if (lsr & SC16IS7XX_LSR_OE_BIT) 627 flag = TTY_OVERRUN; 628 } 629 630 for (i = 0; i < bytes_read; ++i) { 631 ch = s->buf[i]; 632 if (uart_handle_sysrq_char(port, ch)) 633 continue; 634 635 if (lsr & port->ignore_status_mask) 636 continue; 637 638 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 639 flag); 640 } 641 rxlen -= bytes_read; 642 } 643 644 tty_flip_buffer_push(&port->state->port); 645 } 646 647 static void sc16is7xx_handle_tx(struct uart_port *port) 648 { 649 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 650 struct circ_buf *xmit = &port->state->xmit; 651 unsigned int txlen, to_send, i; 652 unsigned long flags; 653 654 if (unlikely(port->x_char)) { 655 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 656 port->icount.tx++; 657 port->x_char = 0; 658 return; 659 } 660 661 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 662 uart_port_lock_irqsave(port, &flags); 663 sc16is7xx_stop_tx(port); 664 uart_port_unlock_irqrestore(port, flags); 665 return; 666 } 667 668 /* Get length of data pending in circular buffer */ 669 to_send = uart_circ_chars_pending(xmit); 670 if (likely(to_send)) { 671 /* Limit to size of TX FIFO */ 672 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 673 if (txlen > SC16IS7XX_FIFO_SIZE) { 674 dev_err_ratelimited(port->dev, 675 "chip reports %d free bytes in TX fifo, but it only has %d", 676 txlen, SC16IS7XX_FIFO_SIZE); 677 txlen = 0; 678 } 679 to_send = (to_send > txlen) ? txlen : to_send; 680 681 /* Convert to linear buffer */ 682 for (i = 0; i < to_send; ++i) { 683 s->buf[i] = xmit->buf[xmit->tail]; 684 uart_xmit_advance(port, 1); 685 } 686 687 sc16is7xx_fifo_write(port, to_send); 688 } 689 690 uart_port_lock_irqsave(port, &flags); 691 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 692 uart_write_wakeup(port); 693 694 if (uart_circ_empty(xmit)) 695 sc16is7xx_stop_tx(port); 696 else 697 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 698 uart_port_unlock_irqrestore(port, flags); 699 } 700 701 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 702 { 703 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 704 unsigned int mctrl = 0; 705 706 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 707 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 708 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 709 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 710 return mctrl; 711 } 712 713 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 714 { 715 struct uart_port *port = &one->port; 716 unsigned long flags; 717 unsigned int status, changed; 718 719 lockdep_assert_held_once(&one->efr_lock); 720 721 status = sc16is7xx_get_hwmctrl(port); 722 changed = status ^ one->old_mctrl; 723 724 if (changed == 0) 725 return; 726 727 one->old_mctrl = status; 728 729 uart_port_lock_irqsave(port, &flags); 730 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 731 port->icount.rng++; 732 if (changed & TIOCM_DSR) 733 port->icount.dsr++; 734 if (changed & TIOCM_CAR) 735 uart_handle_dcd_change(port, status & TIOCM_CAR); 736 if (changed & TIOCM_CTS) 737 uart_handle_cts_change(port, status & TIOCM_CTS); 738 739 wake_up_interruptible(&port->state->port.delta_msr_wait); 740 uart_port_unlock_irqrestore(port, flags); 741 } 742 743 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 744 { 745 bool rc = true; 746 unsigned int iir, rxlen; 747 struct uart_port *port = &s->p[portno].port; 748 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 749 750 mutex_lock(&one->efr_lock); 751 752 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 753 if (iir & SC16IS7XX_IIR_NO_INT_BIT) { 754 rc = false; 755 goto out_port_irq; 756 } 757 758 iir &= SC16IS7XX_IIR_ID_MASK; 759 760 switch (iir) { 761 case SC16IS7XX_IIR_RDI_SRC: 762 case SC16IS7XX_IIR_RLSE_SRC: 763 case SC16IS7XX_IIR_RTOI_SRC: 764 case SC16IS7XX_IIR_XOFFI_SRC: 765 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 766 767 /* 768 * There is a silicon bug that makes the chip report a 769 * time-out interrupt but no data in the FIFO. This is 770 * described in errata section 18.1.4. 771 * 772 * When this happens, read one byte from the FIFO to 773 * clear the interrupt. 774 */ 775 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 776 rxlen = 1; 777 778 if (rxlen) 779 sc16is7xx_handle_rx(port, rxlen, iir); 780 break; 781 /* CTSRTS interrupt comes only when CTS goes inactive */ 782 case SC16IS7XX_IIR_CTSRTS_SRC: 783 case SC16IS7XX_IIR_MSI_SRC: 784 sc16is7xx_update_mlines(one); 785 break; 786 case SC16IS7XX_IIR_THRI_SRC: 787 sc16is7xx_handle_tx(port); 788 break; 789 default: 790 dev_err_ratelimited(port->dev, 791 "ttySC%i: Unexpected interrupt: %x", 792 port->line, iir); 793 break; 794 } 795 796 out_port_irq: 797 mutex_unlock(&one->efr_lock); 798 799 return rc; 800 } 801 802 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 803 { 804 bool keep_polling; 805 806 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 807 808 do { 809 int i; 810 811 keep_polling = false; 812 813 for (i = 0; i < s->devtype->nr_uart; ++i) 814 keep_polling |= sc16is7xx_port_irq(s, i); 815 } while (keep_polling); 816 817 return IRQ_HANDLED; 818 } 819 820 static void sc16is7xx_tx_proc(struct kthread_work *ws) 821 { 822 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 823 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 824 825 if ((port->rs485.flags & SER_RS485_ENABLED) && 826 (port->rs485.delay_rts_before_send > 0)) 827 msleep(port->rs485.delay_rts_before_send); 828 829 mutex_lock(&one->efr_lock); 830 sc16is7xx_handle_tx(port); 831 mutex_unlock(&one->efr_lock); 832 } 833 834 static void sc16is7xx_reconf_rs485(struct uart_port *port) 835 { 836 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 837 SC16IS7XX_EFCR_RTS_INVERT_BIT; 838 u32 efcr = 0; 839 struct serial_rs485 *rs485 = &port->rs485; 840 unsigned long irqflags; 841 842 uart_port_lock_irqsave(port, &irqflags); 843 if (rs485->flags & SER_RS485_ENABLED) { 844 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 845 846 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 847 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 848 } 849 uart_port_unlock_irqrestore(port, irqflags); 850 851 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 852 } 853 854 static void sc16is7xx_reg_proc(struct kthread_work *ws) 855 { 856 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 857 struct sc16is7xx_one_config config; 858 unsigned long irqflags; 859 860 uart_port_lock_irqsave(&one->port, &irqflags); 861 config = one->config; 862 memset(&one->config, 0, sizeof(one->config)); 863 uart_port_unlock_irqrestore(&one->port, irqflags); 864 865 if (config.flags & SC16IS7XX_RECONF_MD) { 866 u8 mcr = 0; 867 868 /* Device ignores RTS setting when hardware flow is enabled */ 869 if (one->port.mctrl & TIOCM_RTS) 870 mcr |= SC16IS7XX_MCR_RTS_BIT; 871 872 if (one->port.mctrl & TIOCM_DTR) 873 mcr |= SC16IS7XX_MCR_DTR_BIT; 874 875 if (one->port.mctrl & TIOCM_LOOP) 876 mcr |= SC16IS7XX_MCR_LOOP_BIT; 877 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 878 SC16IS7XX_MCR_RTS_BIT | 879 SC16IS7XX_MCR_DTR_BIT | 880 SC16IS7XX_MCR_LOOP_BIT, 881 mcr); 882 } 883 884 if (config.flags & SC16IS7XX_RECONF_IER) 885 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 886 config.ier_mask, config.ier_val); 887 888 if (config.flags & SC16IS7XX_RECONF_RS485) 889 sc16is7xx_reconf_rs485(&one->port); 890 } 891 892 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 893 { 894 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 895 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 896 897 lockdep_assert_held_once(&port->lock); 898 899 one->config.flags |= SC16IS7XX_RECONF_IER; 900 one->config.ier_mask |= bit; 901 one->config.ier_val &= ~bit; 902 kthread_queue_work(&s->kworker, &one->reg_work); 903 } 904 905 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 906 { 907 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 908 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 909 910 lockdep_assert_held_once(&port->lock); 911 912 one->config.flags |= SC16IS7XX_RECONF_IER; 913 one->config.ier_mask |= bit; 914 one->config.ier_val |= bit; 915 kthread_queue_work(&s->kworker, &one->reg_work); 916 } 917 918 static void sc16is7xx_stop_tx(struct uart_port *port) 919 { 920 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 921 } 922 923 static void sc16is7xx_stop_rx(struct uart_port *port) 924 { 925 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 926 } 927 928 static void sc16is7xx_ms_proc(struct kthread_work *ws) 929 { 930 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 931 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 932 933 if (one->port.state) { 934 mutex_lock(&one->efr_lock); 935 sc16is7xx_update_mlines(one); 936 mutex_unlock(&one->efr_lock); 937 938 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 939 } 940 } 941 942 static void sc16is7xx_enable_ms(struct uart_port *port) 943 { 944 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 945 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 946 947 lockdep_assert_held_once(&port->lock); 948 949 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 950 } 951 952 static void sc16is7xx_start_tx(struct uart_port *port) 953 { 954 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 955 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 956 957 kthread_queue_work(&s->kworker, &one->tx_work); 958 } 959 960 static void sc16is7xx_throttle(struct uart_port *port) 961 { 962 unsigned long flags; 963 964 /* 965 * Hardware flow control is enabled and thus the device ignores RTS 966 * value set in MCR register. Stop reading data from RX FIFO so the 967 * AutoRTS feature will de-activate RTS output. 968 */ 969 uart_port_lock_irqsave(port, &flags); 970 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 971 uart_port_unlock_irqrestore(port, flags); 972 } 973 974 static void sc16is7xx_unthrottle(struct uart_port *port) 975 { 976 unsigned long flags; 977 978 uart_port_lock_irqsave(port, &flags); 979 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 980 uart_port_unlock_irqrestore(port, flags); 981 } 982 983 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 984 { 985 unsigned int lsr; 986 987 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 988 989 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 990 } 991 992 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 993 { 994 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 995 996 /* Called with port lock taken so we can only return cached value */ 997 return one->old_mctrl; 998 } 999 1000 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 1001 { 1002 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1003 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1004 1005 one->config.flags |= SC16IS7XX_RECONF_MD; 1006 kthread_queue_work(&s->kworker, &one->reg_work); 1007 } 1008 1009 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1010 { 1011 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1012 SC16IS7XX_LCR_TXBREAK_BIT, 1013 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1014 } 1015 1016 static void sc16is7xx_set_termios(struct uart_port *port, 1017 struct ktermios *termios, 1018 const struct ktermios *old) 1019 { 1020 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1021 unsigned int lcr, flow = 0; 1022 int baud; 1023 unsigned long flags; 1024 1025 kthread_cancel_delayed_work_sync(&one->ms_work); 1026 1027 /* Mask termios capabilities we don't support */ 1028 termios->c_cflag &= ~CMSPAR; 1029 1030 /* Word size */ 1031 switch (termios->c_cflag & CSIZE) { 1032 case CS5: 1033 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1034 break; 1035 case CS6: 1036 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1037 break; 1038 case CS7: 1039 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1040 break; 1041 case CS8: 1042 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1043 break; 1044 default: 1045 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1046 termios->c_cflag &= ~CSIZE; 1047 termios->c_cflag |= CS8; 1048 break; 1049 } 1050 1051 /* Parity */ 1052 if (termios->c_cflag & PARENB) { 1053 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1054 if (!(termios->c_cflag & PARODD)) 1055 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1056 } 1057 1058 /* Stop bits */ 1059 if (termios->c_cflag & CSTOPB) 1060 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1061 1062 /* Set read status mask */ 1063 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1064 if (termios->c_iflag & INPCK) 1065 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1066 SC16IS7XX_LSR_FE_BIT; 1067 if (termios->c_iflag & (BRKINT | PARMRK)) 1068 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1069 1070 /* Set status ignore mask */ 1071 port->ignore_status_mask = 0; 1072 if (termios->c_iflag & IGNBRK) 1073 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1074 if (!(termios->c_cflag & CREAD)) 1075 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1076 1077 /* As above, claim the mutex while accessing the EFR. */ 1078 mutex_lock(&one->efr_lock); 1079 1080 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1081 SC16IS7XX_LCR_CONF_MODE_B); 1082 1083 /* Configure flow control */ 1084 regcache_cache_bypass(one->regmap, true); 1085 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1086 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1087 1088 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1089 if (termios->c_cflag & CRTSCTS) { 1090 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1091 SC16IS7XX_EFR_AUTORTS_BIT; 1092 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1093 } 1094 if (termios->c_iflag & IXON) 1095 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1096 if (termios->c_iflag & IXOFF) 1097 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1098 1099 sc16is7xx_port_update(port, 1100 SC16IS7XX_EFR_REG, 1101 SC16IS7XX_EFR_FLOWCTRL_BITS, 1102 flow); 1103 regcache_cache_bypass(one->regmap, false); 1104 1105 /* Update LCR register */ 1106 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1107 1108 mutex_unlock(&one->efr_lock); 1109 1110 /* Get baud rate generator configuration */ 1111 baud = uart_get_baud_rate(port, termios, old, 1112 port->uartclk / 16 / 4 / 0xffff, 1113 port->uartclk / 16); 1114 1115 /* Setup baudrate generator */ 1116 baud = sc16is7xx_set_baud(port, baud); 1117 1118 uart_port_lock_irqsave(port, &flags); 1119 1120 /* Update timeout according to new baud rate */ 1121 uart_update_timeout(port, termios->c_cflag, baud); 1122 1123 if (UART_ENABLE_MS(port, termios->c_cflag)) 1124 sc16is7xx_enable_ms(port); 1125 1126 uart_port_unlock_irqrestore(port, flags); 1127 } 1128 1129 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1130 struct serial_rs485 *rs485) 1131 { 1132 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1133 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1134 1135 if (rs485->flags & SER_RS485_ENABLED) { 1136 /* 1137 * RTS signal is handled by HW, it's timing can't be influenced. 1138 * However, it's sometimes useful to delay TX even without RTS 1139 * control therefore we try to handle .delay_rts_before_send. 1140 */ 1141 if (rs485->delay_rts_after_send) 1142 return -EINVAL; 1143 } 1144 1145 one->config.flags |= SC16IS7XX_RECONF_RS485; 1146 kthread_queue_work(&s->kworker, &one->reg_work); 1147 1148 return 0; 1149 } 1150 1151 static int sc16is7xx_startup(struct uart_port *port) 1152 { 1153 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1154 unsigned int val; 1155 unsigned long flags; 1156 1157 sc16is7xx_power(port, 1); 1158 1159 /* Reset FIFOs*/ 1160 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1161 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1162 udelay(5); 1163 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1164 SC16IS7XX_FCR_FIFO_BIT); 1165 1166 /* Enable EFR */ 1167 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1168 SC16IS7XX_LCR_CONF_MODE_B); 1169 1170 regcache_cache_bypass(one->regmap, true); 1171 1172 /* Enable write access to enhanced features and internal clock div */ 1173 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1174 SC16IS7XX_EFR_ENABLE_BIT, 1175 SC16IS7XX_EFR_ENABLE_BIT); 1176 1177 /* Enable TCR/TLR */ 1178 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1179 SC16IS7XX_MCR_TCRTLR_BIT, 1180 SC16IS7XX_MCR_TCRTLR_BIT); 1181 1182 /* Configure flow control levels */ 1183 /* Flow control halt level 48, resume level 24 */ 1184 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1185 SC16IS7XX_TCR_RX_RESUME(24) | 1186 SC16IS7XX_TCR_RX_HALT(48)); 1187 1188 regcache_cache_bypass(one->regmap, false); 1189 1190 /* Now, initialize the UART */ 1191 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1192 1193 /* Enable IrDA mode if requested in DT */ 1194 /* This bit must be written with LCR[7] = 0 */ 1195 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1196 SC16IS7XX_MCR_IRDA_BIT, 1197 one->irda_mode ? 1198 SC16IS7XX_MCR_IRDA_BIT : 0); 1199 1200 /* Enable the Rx and Tx FIFO */ 1201 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1202 SC16IS7XX_EFCR_RXDISABLE_BIT | 1203 SC16IS7XX_EFCR_TXDISABLE_BIT, 1204 0); 1205 1206 /* Enable RX, CTS change and modem lines interrupts */ 1207 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1208 SC16IS7XX_IER_MSI_BIT; 1209 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1210 1211 /* Enable modem status polling */ 1212 uart_port_lock_irqsave(port, &flags); 1213 sc16is7xx_enable_ms(port); 1214 uart_port_unlock_irqrestore(port, flags); 1215 1216 return 0; 1217 } 1218 1219 static void sc16is7xx_shutdown(struct uart_port *port) 1220 { 1221 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1222 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1223 1224 kthread_cancel_delayed_work_sync(&one->ms_work); 1225 1226 /* Disable all interrupts */ 1227 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1228 /* Disable TX/RX */ 1229 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1230 SC16IS7XX_EFCR_RXDISABLE_BIT | 1231 SC16IS7XX_EFCR_TXDISABLE_BIT, 1232 SC16IS7XX_EFCR_RXDISABLE_BIT | 1233 SC16IS7XX_EFCR_TXDISABLE_BIT); 1234 1235 sc16is7xx_power(port, 0); 1236 1237 kthread_flush_worker(&s->kworker); 1238 } 1239 1240 static const char *sc16is7xx_type(struct uart_port *port) 1241 { 1242 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1243 1244 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1245 } 1246 1247 static int sc16is7xx_request_port(struct uart_port *port) 1248 { 1249 /* Do nothing */ 1250 return 0; 1251 } 1252 1253 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1254 { 1255 if (flags & UART_CONFIG_TYPE) 1256 port->type = PORT_SC16IS7XX; 1257 } 1258 1259 static int sc16is7xx_verify_port(struct uart_port *port, 1260 struct serial_struct *s) 1261 { 1262 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1263 return -EINVAL; 1264 if (s->irq != port->irq) 1265 return -EINVAL; 1266 1267 return 0; 1268 } 1269 1270 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1271 unsigned int oldstate) 1272 { 1273 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1274 } 1275 1276 static void sc16is7xx_null_void(struct uart_port *port) 1277 { 1278 /* Do nothing */ 1279 } 1280 1281 static const struct uart_ops sc16is7xx_ops = { 1282 .tx_empty = sc16is7xx_tx_empty, 1283 .set_mctrl = sc16is7xx_set_mctrl, 1284 .get_mctrl = sc16is7xx_get_mctrl, 1285 .stop_tx = sc16is7xx_stop_tx, 1286 .start_tx = sc16is7xx_start_tx, 1287 .throttle = sc16is7xx_throttle, 1288 .unthrottle = sc16is7xx_unthrottle, 1289 .stop_rx = sc16is7xx_stop_rx, 1290 .enable_ms = sc16is7xx_enable_ms, 1291 .break_ctl = sc16is7xx_break_ctl, 1292 .startup = sc16is7xx_startup, 1293 .shutdown = sc16is7xx_shutdown, 1294 .set_termios = sc16is7xx_set_termios, 1295 .type = sc16is7xx_type, 1296 .request_port = sc16is7xx_request_port, 1297 .release_port = sc16is7xx_null_void, 1298 .config_port = sc16is7xx_config_port, 1299 .verify_port = sc16is7xx_verify_port, 1300 .pm = sc16is7xx_pm, 1301 }; 1302 1303 #ifdef CONFIG_GPIOLIB 1304 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1305 { 1306 unsigned int val; 1307 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1308 struct uart_port *port = &s->p[0].port; 1309 1310 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1311 1312 return !!(val & BIT(offset)); 1313 } 1314 1315 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1316 { 1317 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1318 struct uart_port *port = &s->p[0].port; 1319 1320 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1321 val ? BIT(offset) : 0); 1322 } 1323 1324 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1325 unsigned offset) 1326 { 1327 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1328 struct uart_port *port = &s->p[0].port; 1329 1330 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1331 1332 return 0; 1333 } 1334 1335 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1336 unsigned offset, int val) 1337 { 1338 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1339 struct uart_port *port = &s->p[0].port; 1340 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1341 1342 if (val) 1343 state |= BIT(offset); 1344 else 1345 state &= ~BIT(offset); 1346 1347 /* 1348 * If we write IOSTATE first, and then IODIR, the output value is not 1349 * transferred to the corresponding I/O pin. 1350 * The datasheet states that each register bit will be transferred to 1351 * the corresponding I/O pin programmed as output when writing to 1352 * IOSTATE. Therefore, configure direction first with IODIR, and then 1353 * set value after with IOSTATE. 1354 */ 1355 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1356 BIT(offset)); 1357 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1358 1359 return 0; 1360 } 1361 1362 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1363 unsigned long *valid_mask, 1364 unsigned int ngpios) 1365 { 1366 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1367 1368 *valid_mask = s->gpio_valid_mask; 1369 1370 return 0; 1371 } 1372 1373 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1374 { 1375 struct device *dev = s->p[0].port.dev; 1376 1377 if (!s->devtype->nr_gpio) 1378 return 0; 1379 1380 switch (s->mctrl_mask) { 1381 case 0: 1382 s->gpio_valid_mask = GENMASK(7, 0); 1383 break; 1384 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1385 s->gpio_valid_mask = GENMASK(3, 0); 1386 break; 1387 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1388 s->gpio_valid_mask = GENMASK(7, 4); 1389 break; 1390 default: 1391 break; 1392 } 1393 1394 if (s->gpio_valid_mask == 0) 1395 return 0; 1396 1397 s->gpio.owner = THIS_MODULE; 1398 s->gpio.parent = dev; 1399 s->gpio.label = dev_name(dev); 1400 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1401 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1402 s->gpio.get = sc16is7xx_gpio_get; 1403 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1404 s->gpio.set = sc16is7xx_gpio_set; 1405 s->gpio.base = -1; 1406 s->gpio.ngpio = s->devtype->nr_gpio; 1407 s->gpio.can_sleep = 1; 1408 1409 return gpiochip_add_data(&s->gpio, s); 1410 } 1411 #endif 1412 1413 /* 1414 * Configure ports designated to operate as modem control lines. 1415 */ 1416 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1417 struct regmap *regmap) 1418 { 1419 int i; 1420 int ret; 1421 int count; 1422 u32 mctrl_port[2]; 1423 struct device *dev = s->p[0].port.dev; 1424 1425 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1426 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1427 return 0; 1428 1429 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1430 mctrl_port, count); 1431 if (ret) 1432 return ret; 1433 1434 s->mctrl_mask = 0; 1435 1436 for (i = 0; i < count; i++) { 1437 /* Use GPIO lines as modem control lines */ 1438 if (mctrl_port[i] == 0) 1439 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1440 else if (mctrl_port[i] == 1) 1441 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1442 } 1443 1444 if (s->mctrl_mask) 1445 regmap_update_bits( 1446 regmap, 1447 SC16IS7XX_IOCONTROL_REG, 1448 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1449 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1450 1451 return 0; 1452 } 1453 1454 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1455 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1456 .delay_rts_before_send = 1, 1457 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1458 }; 1459 1460 static int sc16is7xx_probe(struct device *dev, 1461 const struct sc16is7xx_devtype *devtype, 1462 struct regmap *regmaps[], int irq) 1463 { 1464 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1465 unsigned int val; 1466 u32 uartclk = 0; 1467 int i, ret; 1468 struct sc16is7xx_port *s; 1469 1470 for (i = 0; i < devtype->nr_uart; i++) 1471 if (IS_ERR(regmaps[i])) 1472 return PTR_ERR(regmaps[i]); 1473 1474 /* 1475 * This device does not have an identification register that would 1476 * tell us if we are really connected to the correct device. 1477 * The best we can do is to check if communication is at all possible. 1478 * 1479 * Note: regmap[0] is used in the probe function to access registers 1480 * common to all channels/ports, as it is guaranteed to be present on 1481 * all variants. 1482 */ 1483 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1484 if (ret < 0) 1485 return -EPROBE_DEFER; 1486 1487 /* Alloc port structure */ 1488 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1489 if (!s) { 1490 dev_err(dev, "Error allocating port structure\n"); 1491 return -ENOMEM; 1492 } 1493 1494 /* Always ask for fixed clock rate from a property. */ 1495 device_property_read_u32(dev, "clock-frequency", &uartclk); 1496 1497 s->clk = devm_clk_get_optional(dev, NULL); 1498 if (IS_ERR(s->clk)) 1499 return PTR_ERR(s->clk); 1500 1501 ret = clk_prepare_enable(s->clk); 1502 if (ret) 1503 return ret; 1504 1505 freq = clk_get_rate(s->clk); 1506 if (freq == 0) { 1507 if (uartclk) 1508 freq = uartclk; 1509 if (pfreq) 1510 freq = *pfreq; 1511 if (freq) 1512 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1513 else 1514 return -EINVAL; 1515 } 1516 1517 s->devtype = devtype; 1518 dev_set_drvdata(dev, s); 1519 1520 kthread_init_worker(&s->kworker); 1521 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1522 "sc16is7xx"); 1523 if (IS_ERR(s->kworker_task)) { 1524 ret = PTR_ERR(s->kworker_task); 1525 goto out_clk; 1526 } 1527 sched_set_fifo(s->kworker_task); 1528 1529 /* reset device, purging any pending irq / data */ 1530 regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG, 1531 SC16IS7XX_IOCONTROL_SRESET_BIT); 1532 1533 for (i = 0; i < devtype->nr_uart; ++i) { 1534 s->p[i].port.line = find_first_zero_bit(&sc16is7xx_lines, 1535 SC16IS7XX_MAX_DEVS); 1536 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1537 ret = -ERANGE; 1538 goto out_ports; 1539 } 1540 1541 /* Initialize port data */ 1542 s->p[i].port.dev = dev; 1543 s->p[i].port.irq = irq; 1544 s->p[i].port.type = PORT_SC16IS7XX; 1545 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1546 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1547 s->p[i].port.iobase = i; 1548 /* 1549 * Use all ones as membase to make sure uart_configure_port() in 1550 * serial_core.c does not abort for SPI/I2C devices where the 1551 * membase address is not applicable. 1552 */ 1553 s->p[i].port.membase = (void __iomem *)~0; 1554 s->p[i].port.iotype = UPIO_PORT; 1555 s->p[i].port.uartclk = freq; 1556 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1557 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1558 s->p[i].port.ops = &sc16is7xx_ops; 1559 s->p[i].old_mctrl = 0; 1560 s->p[i].regmap = regmaps[i]; 1561 1562 mutex_init(&s->p[i].efr_lock); 1563 1564 ret = uart_get_rs485_mode(&s->p[i].port); 1565 if (ret) 1566 goto out_ports; 1567 1568 /* Disable all interrupts */ 1569 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1570 /* Disable TX/RX */ 1571 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1572 SC16IS7XX_EFCR_RXDISABLE_BIT | 1573 SC16IS7XX_EFCR_TXDISABLE_BIT); 1574 1575 /* Initialize kthread work structs */ 1576 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1577 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1578 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1579 1580 /* Register port */ 1581 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1582 if (ret) 1583 goto out_ports; 1584 1585 set_bit(s->p[i].port.line, &sc16is7xx_lines); 1586 1587 /* Enable EFR */ 1588 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1589 SC16IS7XX_LCR_CONF_MODE_B); 1590 1591 regcache_cache_bypass(regmaps[i], true); 1592 1593 /* Enable write access to enhanced features */ 1594 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1595 SC16IS7XX_EFR_ENABLE_BIT); 1596 1597 regcache_cache_bypass(regmaps[i], false); 1598 1599 /* Restore access to general registers */ 1600 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1601 1602 /* Go to suspend mode */ 1603 sc16is7xx_power(&s->p[i].port, 0); 1604 } 1605 1606 if (dev->of_node) { 1607 struct property *prop; 1608 const __be32 *p; 1609 u32 u; 1610 1611 of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1612 prop, p, u) 1613 if (u < devtype->nr_uart) 1614 s->p[u].irda_mode = true; 1615 } 1616 1617 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1618 if (ret) 1619 goto out_ports; 1620 1621 #ifdef CONFIG_GPIOLIB 1622 ret = sc16is7xx_setup_gpio_chip(s); 1623 if (ret) 1624 goto out_ports; 1625 #endif 1626 1627 /* 1628 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1629 * If that succeeds, we can allow sharing the interrupt as well. 1630 * In case the interrupt controller doesn't support that, we fall 1631 * back to a non-shared falling-edge trigger. 1632 */ 1633 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1634 IRQF_TRIGGER_LOW | IRQF_SHARED | 1635 IRQF_ONESHOT, 1636 dev_name(dev), s); 1637 if (!ret) 1638 return 0; 1639 1640 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1641 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1642 dev_name(dev), s); 1643 if (!ret) 1644 return 0; 1645 1646 #ifdef CONFIG_GPIOLIB 1647 if (s->gpio_valid_mask) 1648 gpiochip_remove(&s->gpio); 1649 #endif 1650 1651 out_ports: 1652 for (i = 0; i < devtype->nr_uart; i++) 1653 if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines)) 1654 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1655 1656 kthread_stop(s->kworker_task); 1657 1658 out_clk: 1659 clk_disable_unprepare(s->clk); 1660 1661 return ret; 1662 } 1663 1664 static void sc16is7xx_remove(struct device *dev) 1665 { 1666 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1667 int i; 1668 1669 #ifdef CONFIG_GPIOLIB 1670 if (s->gpio_valid_mask) 1671 gpiochip_remove(&s->gpio); 1672 #endif 1673 1674 for (i = 0; i < s->devtype->nr_uart; i++) { 1675 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1676 if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines)) 1677 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1678 sc16is7xx_power(&s->p[i].port, 0); 1679 } 1680 1681 kthread_flush_worker(&s->kworker); 1682 kthread_stop(s->kworker_task); 1683 1684 clk_disable_unprepare(s->clk); 1685 } 1686 1687 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1688 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1689 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1690 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1691 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1692 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1693 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1694 { } 1695 }; 1696 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1697 1698 static struct regmap_config regcfg = { 1699 .reg_bits = 5, 1700 .pad_bits = 3, 1701 .val_bits = 8, 1702 .cache_type = REGCACHE_RBTREE, 1703 .volatile_reg = sc16is7xx_regmap_volatile, 1704 .precious_reg = sc16is7xx_regmap_precious, 1705 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1706 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1707 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1708 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1709 .max_register = SC16IS7XX_EFCR_REG, 1710 }; 1711 1712 static const char *sc16is7xx_regmap_name(u8 port_id) 1713 { 1714 switch (port_id) { 1715 case 0: return "port0"; 1716 case 1: return "port1"; 1717 default: 1718 WARN_ON(true); 1719 return NULL; 1720 } 1721 } 1722 1723 static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1724 { 1725 /* CH1,CH0 are at bits 2:1. */ 1726 return port_id << 1; 1727 } 1728 1729 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1730 static int sc16is7xx_spi_probe(struct spi_device *spi) 1731 { 1732 const struct sc16is7xx_devtype *devtype; 1733 struct regmap *regmaps[2]; 1734 unsigned int i; 1735 int ret; 1736 1737 /* Setup SPI bus */ 1738 spi->bits_per_word = 8; 1739 /* For all variants, only mode 0 is supported */ 1740 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0) 1741 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n"); 1742 1743 spi->mode = spi->mode ? : SPI_MODE_0; 1744 spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ; 1745 ret = spi_setup(spi); 1746 if (ret) 1747 return ret; 1748 1749 if (spi->dev.of_node) { 1750 devtype = device_get_match_data(&spi->dev); 1751 if (!devtype) 1752 return -ENODEV; 1753 } else { 1754 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1755 1756 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1757 } 1758 1759 for (i = 0; i < devtype->nr_uart; i++) { 1760 regcfg.name = sc16is7xx_regmap_name(i); 1761 /* 1762 * If read_flag_mask is 0, the regmap code sets it to a default 1763 * of 0x80. Since we specify our own mask, we must add the READ 1764 * bit ourselves: 1765 */ 1766 regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i) | 1767 SC16IS7XX_SPI_READ_BIT; 1768 regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i); 1769 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1770 } 1771 1772 return sc16is7xx_probe(&spi->dev, devtype, regmaps, spi->irq); 1773 } 1774 1775 static void sc16is7xx_spi_remove(struct spi_device *spi) 1776 { 1777 sc16is7xx_remove(&spi->dev); 1778 } 1779 1780 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1781 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1782 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1783 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1784 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1785 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1786 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1787 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1788 { } 1789 }; 1790 1791 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1792 1793 static struct spi_driver sc16is7xx_spi_uart_driver = { 1794 .driver = { 1795 .name = SC16IS7XX_NAME, 1796 .of_match_table = sc16is7xx_dt_ids, 1797 }, 1798 .probe = sc16is7xx_spi_probe, 1799 .remove = sc16is7xx_spi_remove, 1800 .id_table = sc16is7xx_spi_id_table, 1801 }; 1802 1803 MODULE_ALIAS("spi:sc16is7xx"); 1804 #endif 1805 1806 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1807 static int sc16is7xx_i2c_probe(struct i2c_client *i2c) 1808 { 1809 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1810 const struct sc16is7xx_devtype *devtype; 1811 struct regmap *regmaps[2]; 1812 unsigned int i; 1813 1814 if (i2c->dev.of_node) { 1815 devtype = device_get_match_data(&i2c->dev); 1816 if (!devtype) 1817 return -ENODEV; 1818 } else { 1819 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1820 } 1821 1822 for (i = 0; i < devtype->nr_uart; i++) { 1823 regcfg.name = sc16is7xx_regmap_name(i); 1824 regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i); 1825 regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i); 1826 regmaps[i] = devm_regmap_init_i2c(i2c, ®cfg); 1827 } 1828 1829 return sc16is7xx_probe(&i2c->dev, devtype, regmaps, i2c->irq); 1830 } 1831 1832 static void sc16is7xx_i2c_remove(struct i2c_client *client) 1833 { 1834 sc16is7xx_remove(&client->dev); 1835 } 1836 1837 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1838 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1839 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1840 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1841 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1842 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1843 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1844 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1845 { } 1846 }; 1847 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1848 1849 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1850 .driver = { 1851 .name = SC16IS7XX_NAME, 1852 .of_match_table = sc16is7xx_dt_ids, 1853 }, 1854 .probe = sc16is7xx_i2c_probe, 1855 .remove = sc16is7xx_i2c_remove, 1856 .id_table = sc16is7xx_i2c_id_table, 1857 }; 1858 1859 #endif 1860 1861 static int __init sc16is7xx_init(void) 1862 { 1863 int ret; 1864 1865 ret = uart_register_driver(&sc16is7xx_uart); 1866 if (ret) { 1867 pr_err("Registering UART driver failed\n"); 1868 return ret; 1869 } 1870 1871 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1872 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1873 if (ret < 0) { 1874 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1875 goto err_i2c; 1876 } 1877 #endif 1878 1879 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1880 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1881 if (ret < 0) { 1882 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1883 goto err_spi; 1884 } 1885 #endif 1886 return ret; 1887 1888 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1889 err_spi: 1890 #endif 1891 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1892 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1893 err_i2c: 1894 #endif 1895 uart_unregister_driver(&sc16is7xx_uart); 1896 return ret; 1897 } 1898 module_init(sc16is7xx_init); 1899 1900 static void __exit sc16is7xx_exit(void) 1901 { 1902 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1903 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1904 #endif 1905 1906 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1907 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1908 #endif 1909 uart_unregister_driver(&sc16is7xx_uart); 1910 } 1911 module_exit(sc16is7xx_exit); 1912 1913 MODULE_LICENSE("GPL"); 1914 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1915 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1916