1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 #include <linux/units.h> 28 #include <uapi/linux/sched/types.h> 29 30 #define SC16IS7XX_NAME "sc16is7xx" 31 #define SC16IS7XX_MAX_DEVS 8 32 33 /* SC16IS7XX register definitions */ 34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 47 * - only on 75x/76x 48 */ 49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 50 * - only on 75x/76x 51 */ 52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 53 * - only on 75x/76x 54 */ 55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 56 * - only on 75x/76x 57 */ 58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 59 60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 63 64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 67 68 /* Enhanced Register set: Only if (LCR == 0xBF) */ 69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 74 75 /* IER register bits */ 76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 78 * interrupt */ 79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 80 * interrupt */ 81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 82 * interrupt */ 83 84 /* IER register bits - write only if (EFR[4] == 1) */ 85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 89 90 /* FCR register bits */ 91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 96 97 /* FCR register bits - write only if (EFR[4] == 1) */ 98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 100 101 /* IIR register bits */ 102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 109 * - only on 75x/76x 110 */ 111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 112 * - only on 75x/76x 113 */ 114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 116 * from active (LOW) 117 * to inactive (HIGH) 118 */ 119 /* LCR register bits */ 120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 122 * 123 * Word length bits table: 124 * 00 -> 5 bit words 125 * 01 -> 6 bit words 126 * 10 -> 7 bit words 127 * 11 -> 8 bit words 128 */ 129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 130 * 131 * STOP length bit table: 132 * 0 -> 1 stop bit 133 * 1 -> 1-1.5 stop bits if 134 * word length is 5, 135 * 2 stop bits otherwise 136 */ 137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 147 * reg set */ 148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 149 * reg set */ 150 151 /* MCR register bits */ 152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 153 * - only on 75x/76x 154 */ 155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 159 * - write enabled 160 * if (EFR[4] == 1) 161 */ 162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 171 /* LSR register bits */ 172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 181 182 /* MSR register bits */ 183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 185 * or (IO4) 186 * - only on 75x/76x 187 */ 188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 189 * or (IO7) 190 * - only on 75x/76x 191 */ 192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 193 * or (IO6) 194 * - only on 75x/76x 195 */ 196 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 197 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 198 * - only on 75x/76x 199 */ 200 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 201 * - only on 75x/76x 202 */ 203 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 204 * - only on 75x/76x 205 */ 206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 207 208 /* 209 * TCR register bits 210 * TCR trigger levels are available from 0 to 60 characters with a granularity 211 * of four. 212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 213 * no built-in hardware check to make sure this condition is met. Also, the TCR 214 * must be programmed with this condition before auto RTS or software flow 215 * control is enabled to avoid spurious operation of the device. 216 */ 217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 219 220 /* 221 * TLR register bits 222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 224 * trigger levels. Trigger levels from 4 characters to 60 characters are 225 * available with a granularity of four. 226 * 227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 229 * the trigger level defined in FCR is discarded. This applies to both transmit 230 * FIFO and receive FIFO trigger level setting. 231 * 232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 233 * default state, that is, '00'. 234 */ 235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 237 238 /* IOControl register bits (Only 750/760) */ 239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 240 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 241 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 242 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 243 244 /* EFCR register bits */ 245 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 246 * mode (RS485) */ 247 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 248 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 249 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 250 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 251 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 252 * 0 = rate upto 115.2 kbit/s 253 * - Only 750/760 254 * 1 = rate upto 1.152 Mbit/s 255 * - Only 760 256 */ 257 258 /* EFR register bits */ 259 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 260 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 261 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 262 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 263 * and writing to IER[7:4], 264 * FCR[5:4], MCR[7:5] 265 */ 266 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 267 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 268 * 269 * SWFLOW bits 3 & 2 table: 270 * 00 -> no transmitter flow 271 * control 272 * 01 -> transmitter generates 273 * XON2 and XOFF2 274 * 10 -> transmitter generates 275 * XON1 and XOFF1 276 * 11 -> transmitter generates 277 * XON1, XON2, XOFF1 and 278 * XOFF2 279 */ 280 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 281 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 282 * 283 * SWFLOW bits 3 & 2 table: 284 * 00 -> no received flow 285 * control 286 * 01 -> receiver compares 287 * XON2 and XOFF2 288 * 10 -> receiver compares 289 * XON1 and XOFF1 290 * 11 -> receiver compares 291 * XON1, XON2, XOFF1 and 292 * XOFF2 293 */ 294 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 295 SC16IS7XX_EFR_AUTOCTS_BIT | \ 296 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 297 SC16IS7XX_EFR_SWFLOW3_BIT | \ 298 SC16IS7XX_EFR_SWFLOW2_BIT | \ 299 SC16IS7XX_EFR_SWFLOW1_BIT | \ 300 SC16IS7XX_EFR_SWFLOW0_BIT) 301 302 303 /* Misc definitions */ 304 #define SC16IS7XX_FIFO_SIZE (64) 305 #define SC16IS7XX_REG_SHIFT 2 306 #define SC16IS7XX_GPIOS_PER_BANK 4 307 308 struct sc16is7xx_devtype { 309 char name[10]; 310 int nr_gpio; 311 int nr_uart; 312 }; 313 314 #define SC16IS7XX_RECONF_MD (1 << 0) 315 #define SC16IS7XX_RECONF_IER (1 << 1) 316 #define SC16IS7XX_RECONF_RS485 (1 << 2) 317 318 struct sc16is7xx_one_config { 319 unsigned int flags; 320 u8 ier_mask; 321 u8 ier_val; 322 }; 323 324 struct sc16is7xx_one { 325 struct uart_port port; 326 u8 line; 327 struct kthread_work tx_work; 328 struct kthread_work reg_work; 329 struct kthread_delayed_work ms_work; 330 struct sc16is7xx_one_config config; 331 bool irda_mode; 332 unsigned int old_mctrl; 333 }; 334 335 struct sc16is7xx_port { 336 const struct sc16is7xx_devtype *devtype; 337 struct regmap *regmap; 338 struct clk *clk; 339 #ifdef CONFIG_GPIOLIB 340 struct gpio_chip gpio; 341 unsigned long gpio_valid_mask; 342 #endif 343 u8 mctrl_mask; 344 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 345 struct kthread_worker kworker; 346 struct task_struct *kworker_task; 347 struct mutex efr_lock; 348 struct sc16is7xx_one p[]; 349 }; 350 351 static unsigned long sc16is7xx_lines; 352 353 static struct uart_driver sc16is7xx_uart = { 354 .owner = THIS_MODULE, 355 .dev_name = "ttySC", 356 .nr = SC16IS7XX_MAX_DEVS, 357 }; 358 359 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 360 static void sc16is7xx_stop_tx(struct uart_port *port); 361 362 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 363 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 364 365 static int sc16is7xx_line(struct uart_port *port) 366 { 367 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 368 369 return one->line; 370 } 371 372 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 373 { 374 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 375 unsigned int val = 0; 376 const u8 line = sc16is7xx_line(port); 377 378 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 379 380 return val; 381 } 382 383 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 384 { 385 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 386 const u8 line = sc16is7xx_line(port); 387 388 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 389 } 390 391 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 392 { 393 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 394 const u8 line = sc16is7xx_line(port); 395 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 396 397 regcache_cache_bypass(s->regmap, true); 398 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 399 regcache_cache_bypass(s->regmap, false); 400 } 401 402 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 403 { 404 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 405 const u8 line = sc16is7xx_line(port); 406 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 407 408 /* 409 * Don't send zero-length data, at least on SPI it confuses the chip 410 * delivering wrong TXLVL data. 411 */ 412 if (unlikely(!to_send)) 413 return; 414 415 regcache_cache_bypass(s->regmap, true); 416 regmap_raw_write(s->regmap, addr, s->buf, to_send); 417 regcache_cache_bypass(s->regmap, false); 418 } 419 420 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 421 u8 mask, u8 val) 422 { 423 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 424 const u8 line = sc16is7xx_line(port); 425 426 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 427 mask, val); 428 } 429 430 static int sc16is7xx_alloc_line(void) 431 { 432 int i; 433 434 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 435 436 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 437 if (!test_and_set_bit(i, &sc16is7xx_lines)) 438 break; 439 440 return i; 441 } 442 443 static void sc16is7xx_power(struct uart_port *port, int on) 444 { 445 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 446 SC16IS7XX_IER_SLEEP_BIT, 447 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 448 } 449 450 static const struct sc16is7xx_devtype sc16is74x_devtype = { 451 .name = "SC16IS74X", 452 .nr_gpio = 0, 453 .nr_uart = 1, 454 }; 455 456 static const struct sc16is7xx_devtype sc16is750_devtype = { 457 .name = "SC16IS750", 458 .nr_gpio = 8, 459 .nr_uart = 1, 460 }; 461 462 static const struct sc16is7xx_devtype sc16is752_devtype = { 463 .name = "SC16IS752", 464 .nr_gpio = 8, 465 .nr_uart = 2, 466 }; 467 468 static const struct sc16is7xx_devtype sc16is760_devtype = { 469 .name = "SC16IS760", 470 .nr_gpio = 8, 471 .nr_uart = 1, 472 }; 473 474 static const struct sc16is7xx_devtype sc16is762_devtype = { 475 .name = "SC16IS762", 476 .nr_gpio = 8, 477 .nr_uart = 2, 478 }; 479 480 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 481 { 482 switch (reg >> SC16IS7XX_REG_SHIFT) { 483 case SC16IS7XX_RHR_REG: 484 case SC16IS7XX_IIR_REG: 485 case SC16IS7XX_LSR_REG: 486 case SC16IS7XX_MSR_REG: 487 case SC16IS7XX_TXLVL_REG: 488 case SC16IS7XX_RXLVL_REG: 489 case SC16IS7XX_IOSTATE_REG: 490 case SC16IS7XX_IOCONTROL_REG: 491 return true; 492 default: 493 break; 494 } 495 496 return false; 497 } 498 499 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 500 { 501 switch (reg >> SC16IS7XX_REG_SHIFT) { 502 case SC16IS7XX_RHR_REG: 503 return true; 504 default: 505 break; 506 } 507 508 return false; 509 } 510 511 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 512 { 513 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 514 u8 lcr; 515 u8 prescaler = 0; 516 unsigned long clk = port->uartclk, div = clk / 16 / baud; 517 518 if (div > 0xffff) { 519 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 520 div /= 4; 521 } 522 523 /* In an amazing feat of design, the Enhanced Features Register shares 524 * the address of the Interrupt Identification Register, and is 525 * switched in by writing a magic value (0xbf) to the Line Control 526 * Register. Any interrupt firing during this time will see the EFR 527 * where it expects the IIR to be, leading to "Unexpected interrupt" 528 * messages. 529 * 530 * Prevent this possibility by claiming a mutex while accessing the 531 * EFR, and claiming the same mutex from within the interrupt handler. 532 * This is similar to disabling the interrupt, but that doesn't work 533 * because the bulk of the interrupt processing is run as a workqueue 534 * job in thread context. 535 */ 536 mutex_lock(&s->efr_lock); 537 538 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 539 540 /* Open the LCR divisors for configuration */ 541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 542 SC16IS7XX_LCR_CONF_MODE_B); 543 544 /* Enable enhanced features */ 545 regcache_cache_bypass(s->regmap, true); 546 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 547 SC16IS7XX_EFR_ENABLE_BIT, 548 SC16IS7XX_EFR_ENABLE_BIT); 549 550 regcache_cache_bypass(s->regmap, false); 551 552 /* Put LCR back to the normal mode */ 553 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 554 555 mutex_unlock(&s->efr_lock); 556 557 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 558 SC16IS7XX_MCR_CLKSEL_BIT, 559 prescaler); 560 561 /* Open the LCR divisors for configuration */ 562 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 563 SC16IS7XX_LCR_CONF_MODE_A); 564 565 /* Write the new divisor */ 566 regcache_cache_bypass(s->regmap, true); 567 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 568 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 569 regcache_cache_bypass(s->regmap, false); 570 571 /* Put LCR back to the normal mode */ 572 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 573 574 return DIV_ROUND_CLOSEST(clk / 16, div); 575 } 576 577 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 578 unsigned int iir) 579 { 580 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 581 unsigned int lsr = 0, bytes_read, i; 582 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 583 u8 ch, flag; 584 585 if (unlikely(rxlen >= sizeof(s->buf))) { 586 dev_warn_ratelimited(port->dev, 587 "ttySC%i: Possible RX FIFO overrun: %d\n", 588 port->line, rxlen); 589 port->icount.buf_overrun++; 590 /* Ensure sanity of RX level */ 591 rxlen = sizeof(s->buf); 592 } 593 594 while (rxlen) { 595 /* Only read lsr if there are possible errors in FIFO */ 596 if (read_lsr) { 597 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 598 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 599 read_lsr = false; /* No errors left in FIFO */ 600 } else 601 lsr = 0; 602 603 if (read_lsr) { 604 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 605 bytes_read = 1; 606 } else { 607 sc16is7xx_fifo_read(port, rxlen); 608 bytes_read = rxlen; 609 } 610 611 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 612 613 port->icount.rx++; 614 flag = TTY_NORMAL; 615 616 if (unlikely(lsr)) { 617 if (lsr & SC16IS7XX_LSR_BI_BIT) { 618 port->icount.brk++; 619 if (uart_handle_break(port)) 620 continue; 621 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 622 port->icount.parity++; 623 else if (lsr & SC16IS7XX_LSR_FE_BIT) 624 port->icount.frame++; 625 else if (lsr & SC16IS7XX_LSR_OE_BIT) 626 port->icount.overrun++; 627 628 lsr &= port->read_status_mask; 629 if (lsr & SC16IS7XX_LSR_BI_BIT) 630 flag = TTY_BREAK; 631 else if (lsr & SC16IS7XX_LSR_PE_BIT) 632 flag = TTY_PARITY; 633 else if (lsr & SC16IS7XX_LSR_FE_BIT) 634 flag = TTY_FRAME; 635 else if (lsr & SC16IS7XX_LSR_OE_BIT) 636 flag = TTY_OVERRUN; 637 } 638 639 for (i = 0; i < bytes_read; ++i) { 640 ch = s->buf[i]; 641 if (uart_handle_sysrq_char(port, ch)) 642 continue; 643 644 if (lsr & port->ignore_status_mask) 645 continue; 646 647 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 648 flag); 649 } 650 rxlen -= bytes_read; 651 } 652 653 tty_flip_buffer_push(&port->state->port); 654 } 655 656 static void sc16is7xx_handle_tx(struct uart_port *port) 657 { 658 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 659 struct circ_buf *xmit = &port->state->xmit; 660 unsigned int txlen, to_send, i; 661 unsigned long flags; 662 663 if (unlikely(port->x_char)) { 664 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 665 port->icount.tx++; 666 port->x_char = 0; 667 return; 668 } 669 670 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 671 spin_lock_irqsave(&port->lock, flags); 672 sc16is7xx_stop_tx(port); 673 spin_unlock_irqrestore(&port->lock, flags); 674 return; 675 } 676 677 /* Get length of data pending in circular buffer */ 678 to_send = uart_circ_chars_pending(xmit); 679 if (likely(to_send)) { 680 /* Limit to size of TX FIFO */ 681 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 682 if (txlen > SC16IS7XX_FIFO_SIZE) { 683 dev_err_ratelimited(port->dev, 684 "chip reports %d free bytes in TX fifo, but it only has %d", 685 txlen, SC16IS7XX_FIFO_SIZE); 686 txlen = 0; 687 } 688 to_send = (to_send > txlen) ? txlen : to_send; 689 690 /* Convert to linear buffer */ 691 for (i = 0; i < to_send; ++i) { 692 s->buf[i] = xmit->buf[xmit->tail]; 693 uart_xmit_advance(port, 1); 694 } 695 696 sc16is7xx_fifo_write(port, to_send); 697 } 698 699 spin_lock_irqsave(&port->lock, flags); 700 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 701 uart_write_wakeup(port); 702 703 if (uart_circ_empty(xmit)) 704 sc16is7xx_stop_tx(port); 705 spin_unlock_irqrestore(&port->lock, flags); 706 } 707 708 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 709 { 710 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 711 unsigned int mctrl = 0; 712 713 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 714 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 715 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 716 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 717 return mctrl; 718 } 719 720 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 721 { 722 struct uart_port *port = &one->port; 723 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 724 unsigned long flags; 725 unsigned int status, changed; 726 727 lockdep_assert_held_once(&s->efr_lock); 728 729 status = sc16is7xx_get_hwmctrl(port); 730 changed = status ^ one->old_mctrl; 731 732 if (changed == 0) 733 return; 734 735 one->old_mctrl = status; 736 737 spin_lock_irqsave(&port->lock, flags); 738 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 739 port->icount.rng++; 740 if (changed & TIOCM_DSR) 741 port->icount.dsr++; 742 if (changed & TIOCM_CAR) 743 uart_handle_dcd_change(port, status & TIOCM_CAR); 744 if (changed & TIOCM_CTS) 745 uart_handle_cts_change(port, status & TIOCM_CTS); 746 747 wake_up_interruptible(&port->state->port.delta_msr_wait); 748 spin_unlock_irqrestore(&port->lock, flags); 749 } 750 751 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 752 { 753 struct uart_port *port = &s->p[portno].port; 754 755 do { 756 unsigned int iir, rxlen; 757 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 758 759 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 760 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 761 return false; 762 763 iir &= SC16IS7XX_IIR_ID_MASK; 764 765 switch (iir) { 766 case SC16IS7XX_IIR_RDI_SRC: 767 case SC16IS7XX_IIR_RLSE_SRC: 768 case SC16IS7XX_IIR_RTOI_SRC: 769 case SC16IS7XX_IIR_XOFFI_SRC: 770 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 771 772 /* 773 * There is a silicon bug that makes the chip report a 774 * time-out interrupt but no data in the FIFO. This is 775 * described in errata section 18.1.4. 776 * 777 * When this happens, read one byte from the FIFO to 778 * clear the interrupt. 779 */ 780 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 781 rxlen = 1; 782 783 if (rxlen) 784 sc16is7xx_handle_rx(port, rxlen, iir); 785 break; 786 /* CTSRTS interrupt comes only when CTS goes inactive */ 787 case SC16IS7XX_IIR_CTSRTS_SRC: 788 case SC16IS7XX_IIR_MSI_SRC: 789 sc16is7xx_update_mlines(one); 790 break; 791 case SC16IS7XX_IIR_THRI_SRC: 792 sc16is7xx_handle_tx(port); 793 break; 794 default: 795 dev_err_ratelimited(port->dev, 796 "ttySC%i: Unexpected interrupt: %x", 797 port->line, iir); 798 break; 799 } 800 } while (0); 801 return true; 802 } 803 804 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 805 { 806 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 807 808 mutex_lock(&s->efr_lock); 809 810 while (1) { 811 bool keep_polling = false; 812 int i; 813 814 for (i = 0; i < s->devtype->nr_uart; ++i) 815 keep_polling |= sc16is7xx_port_irq(s, i); 816 if (!keep_polling) 817 break; 818 } 819 820 mutex_unlock(&s->efr_lock); 821 822 return IRQ_HANDLED; 823 } 824 825 static void sc16is7xx_tx_proc(struct kthread_work *ws) 826 { 827 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 828 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 829 unsigned long flags; 830 831 if ((port->rs485.flags & SER_RS485_ENABLED) && 832 (port->rs485.delay_rts_before_send > 0)) 833 msleep(port->rs485.delay_rts_before_send); 834 835 mutex_lock(&s->efr_lock); 836 sc16is7xx_handle_tx(port); 837 mutex_unlock(&s->efr_lock); 838 839 spin_lock_irqsave(&port->lock, flags); 840 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 841 spin_unlock_irqrestore(&port->lock, flags); 842 } 843 844 static void sc16is7xx_reconf_rs485(struct uart_port *port) 845 { 846 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 847 SC16IS7XX_EFCR_RTS_INVERT_BIT; 848 u32 efcr = 0; 849 struct serial_rs485 *rs485 = &port->rs485; 850 unsigned long irqflags; 851 852 spin_lock_irqsave(&port->lock, irqflags); 853 if (rs485->flags & SER_RS485_ENABLED) { 854 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 855 856 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 857 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 858 } 859 spin_unlock_irqrestore(&port->lock, irqflags); 860 861 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 862 } 863 864 static void sc16is7xx_reg_proc(struct kthread_work *ws) 865 { 866 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 867 struct sc16is7xx_one_config config; 868 unsigned long irqflags; 869 870 spin_lock_irqsave(&one->port.lock, irqflags); 871 config = one->config; 872 memset(&one->config, 0, sizeof(one->config)); 873 spin_unlock_irqrestore(&one->port.lock, irqflags); 874 875 if (config.flags & SC16IS7XX_RECONF_MD) { 876 u8 mcr = 0; 877 878 /* Device ignores RTS setting when hardware flow is enabled */ 879 if (one->port.mctrl & TIOCM_RTS) 880 mcr |= SC16IS7XX_MCR_RTS_BIT; 881 882 if (one->port.mctrl & TIOCM_DTR) 883 mcr |= SC16IS7XX_MCR_DTR_BIT; 884 885 if (one->port.mctrl & TIOCM_LOOP) 886 mcr |= SC16IS7XX_MCR_LOOP_BIT; 887 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 888 SC16IS7XX_MCR_RTS_BIT | 889 SC16IS7XX_MCR_DTR_BIT | 890 SC16IS7XX_MCR_LOOP_BIT, 891 mcr); 892 } 893 894 if (config.flags & SC16IS7XX_RECONF_IER) 895 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 896 config.ier_mask, config.ier_val); 897 898 if (config.flags & SC16IS7XX_RECONF_RS485) 899 sc16is7xx_reconf_rs485(&one->port); 900 } 901 902 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 903 { 904 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 905 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 906 907 lockdep_assert_held_once(&port->lock); 908 909 one->config.flags |= SC16IS7XX_RECONF_IER; 910 one->config.ier_mask |= bit; 911 one->config.ier_val &= ~bit; 912 kthread_queue_work(&s->kworker, &one->reg_work); 913 } 914 915 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 916 { 917 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 918 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 919 920 lockdep_assert_held_once(&port->lock); 921 922 one->config.flags |= SC16IS7XX_RECONF_IER; 923 one->config.ier_mask |= bit; 924 one->config.ier_val |= bit; 925 kthread_queue_work(&s->kworker, &one->reg_work); 926 } 927 928 static void sc16is7xx_stop_tx(struct uart_port *port) 929 { 930 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 931 } 932 933 static void sc16is7xx_stop_rx(struct uart_port *port) 934 { 935 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 936 } 937 938 static void sc16is7xx_ms_proc(struct kthread_work *ws) 939 { 940 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 941 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 942 943 if (one->port.state) { 944 mutex_lock(&s->efr_lock); 945 sc16is7xx_update_mlines(one); 946 mutex_unlock(&s->efr_lock); 947 948 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 949 } 950 } 951 952 static void sc16is7xx_enable_ms(struct uart_port *port) 953 { 954 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 955 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 956 957 lockdep_assert_held_once(&port->lock); 958 959 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 960 } 961 962 static void sc16is7xx_start_tx(struct uart_port *port) 963 { 964 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 965 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 966 967 kthread_queue_work(&s->kworker, &one->tx_work); 968 } 969 970 static void sc16is7xx_throttle(struct uart_port *port) 971 { 972 unsigned long flags; 973 974 /* 975 * Hardware flow control is enabled and thus the device ignores RTS 976 * value set in MCR register. Stop reading data from RX FIFO so the 977 * AutoRTS feature will de-activate RTS output. 978 */ 979 spin_lock_irqsave(&port->lock, flags); 980 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 981 spin_unlock_irqrestore(&port->lock, flags); 982 } 983 984 static void sc16is7xx_unthrottle(struct uart_port *port) 985 { 986 unsigned long flags; 987 988 spin_lock_irqsave(&port->lock, flags); 989 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 990 spin_unlock_irqrestore(&port->lock, flags); 991 } 992 993 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 994 { 995 unsigned int lsr; 996 997 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 998 999 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 1000 } 1001 1002 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 1003 { 1004 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1005 1006 /* Called with port lock taken so we can only return cached value */ 1007 return one->old_mctrl; 1008 } 1009 1010 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 1011 { 1012 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1013 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1014 1015 one->config.flags |= SC16IS7XX_RECONF_MD; 1016 kthread_queue_work(&s->kworker, &one->reg_work); 1017 } 1018 1019 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1020 { 1021 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1022 SC16IS7XX_LCR_TXBREAK_BIT, 1023 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1024 } 1025 1026 static void sc16is7xx_set_termios(struct uart_port *port, 1027 struct ktermios *termios, 1028 const struct ktermios *old) 1029 { 1030 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1031 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1032 unsigned int lcr, flow = 0; 1033 int baud; 1034 unsigned long flags; 1035 1036 kthread_cancel_delayed_work_sync(&one->ms_work); 1037 1038 /* Mask termios capabilities we don't support */ 1039 termios->c_cflag &= ~CMSPAR; 1040 1041 /* Word size */ 1042 switch (termios->c_cflag & CSIZE) { 1043 case CS5: 1044 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1045 break; 1046 case CS6: 1047 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1048 break; 1049 case CS7: 1050 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1051 break; 1052 case CS8: 1053 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1054 break; 1055 default: 1056 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1057 termios->c_cflag &= ~CSIZE; 1058 termios->c_cflag |= CS8; 1059 break; 1060 } 1061 1062 /* Parity */ 1063 if (termios->c_cflag & PARENB) { 1064 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1065 if (!(termios->c_cflag & PARODD)) 1066 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1067 } 1068 1069 /* Stop bits */ 1070 if (termios->c_cflag & CSTOPB) 1071 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1072 1073 /* Set read status mask */ 1074 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1075 if (termios->c_iflag & INPCK) 1076 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1077 SC16IS7XX_LSR_FE_BIT; 1078 if (termios->c_iflag & (BRKINT | PARMRK)) 1079 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1080 1081 /* Set status ignore mask */ 1082 port->ignore_status_mask = 0; 1083 if (termios->c_iflag & IGNBRK) 1084 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1085 if (!(termios->c_cflag & CREAD)) 1086 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1087 1088 /* As above, claim the mutex while accessing the EFR. */ 1089 mutex_lock(&s->efr_lock); 1090 1091 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1092 SC16IS7XX_LCR_CONF_MODE_B); 1093 1094 /* Configure flow control */ 1095 regcache_cache_bypass(s->regmap, true); 1096 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1097 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1098 1099 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1100 if (termios->c_cflag & CRTSCTS) { 1101 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1102 SC16IS7XX_EFR_AUTORTS_BIT; 1103 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1104 } 1105 if (termios->c_iflag & IXON) 1106 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1107 if (termios->c_iflag & IXOFF) 1108 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1109 1110 sc16is7xx_port_update(port, 1111 SC16IS7XX_EFR_REG, 1112 SC16IS7XX_EFR_FLOWCTRL_BITS, 1113 flow); 1114 regcache_cache_bypass(s->regmap, false); 1115 1116 /* Update LCR register */ 1117 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1118 1119 mutex_unlock(&s->efr_lock); 1120 1121 /* Get baud rate generator configuration */ 1122 baud = uart_get_baud_rate(port, termios, old, 1123 port->uartclk / 16 / 4 / 0xffff, 1124 port->uartclk / 16); 1125 1126 /* Setup baudrate generator */ 1127 baud = sc16is7xx_set_baud(port, baud); 1128 1129 spin_lock_irqsave(&port->lock, flags); 1130 1131 /* Update timeout according to new baud rate */ 1132 uart_update_timeout(port, termios->c_cflag, baud); 1133 1134 if (UART_ENABLE_MS(port, termios->c_cflag)) 1135 sc16is7xx_enable_ms(port); 1136 1137 spin_unlock_irqrestore(&port->lock, flags); 1138 } 1139 1140 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1141 struct serial_rs485 *rs485) 1142 { 1143 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1144 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1145 1146 if (rs485->flags & SER_RS485_ENABLED) { 1147 /* 1148 * RTS signal is handled by HW, it's timing can't be influenced. 1149 * However, it's sometimes useful to delay TX even without RTS 1150 * control therefore we try to handle .delay_rts_before_send. 1151 */ 1152 if (rs485->delay_rts_after_send) 1153 return -EINVAL; 1154 } 1155 1156 one->config.flags |= SC16IS7XX_RECONF_RS485; 1157 kthread_queue_work(&s->kworker, &one->reg_work); 1158 1159 return 0; 1160 } 1161 1162 static int sc16is7xx_startup(struct uart_port *port) 1163 { 1164 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1165 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1166 unsigned int val; 1167 unsigned long flags; 1168 1169 sc16is7xx_power(port, 1); 1170 1171 /* Reset FIFOs*/ 1172 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1173 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1174 udelay(5); 1175 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1176 SC16IS7XX_FCR_FIFO_BIT); 1177 1178 /* Enable EFR */ 1179 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1180 SC16IS7XX_LCR_CONF_MODE_B); 1181 1182 regcache_cache_bypass(s->regmap, true); 1183 1184 /* Enable write access to enhanced features and internal clock div */ 1185 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1186 SC16IS7XX_EFR_ENABLE_BIT, 1187 SC16IS7XX_EFR_ENABLE_BIT); 1188 1189 /* Enable TCR/TLR */ 1190 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1191 SC16IS7XX_MCR_TCRTLR_BIT, 1192 SC16IS7XX_MCR_TCRTLR_BIT); 1193 1194 /* Configure flow control levels */ 1195 /* Flow control halt level 48, resume level 24 */ 1196 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1197 SC16IS7XX_TCR_RX_RESUME(24) | 1198 SC16IS7XX_TCR_RX_HALT(48)); 1199 1200 regcache_cache_bypass(s->regmap, false); 1201 1202 /* Now, initialize the UART */ 1203 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1204 1205 /* Enable IrDA mode if requested in DT */ 1206 /* This bit must be written with LCR[7] = 0 */ 1207 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1208 SC16IS7XX_MCR_IRDA_BIT, 1209 one->irda_mode ? 1210 SC16IS7XX_MCR_IRDA_BIT : 0); 1211 1212 /* Enable the Rx and Tx FIFO */ 1213 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1214 SC16IS7XX_EFCR_RXDISABLE_BIT | 1215 SC16IS7XX_EFCR_TXDISABLE_BIT, 1216 0); 1217 1218 /* Enable RX, CTS change and modem lines interrupts */ 1219 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1220 SC16IS7XX_IER_MSI_BIT; 1221 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1222 1223 /* Enable modem status polling */ 1224 spin_lock_irqsave(&port->lock, flags); 1225 sc16is7xx_enable_ms(port); 1226 spin_unlock_irqrestore(&port->lock, flags); 1227 1228 return 0; 1229 } 1230 1231 static void sc16is7xx_shutdown(struct uart_port *port) 1232 { 1233 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1234 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1235 1236 kthread_cancel_delayed_work_sync(&one->ms_work); 1237 1238 /* Disable all interrupts */ 1239 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1240 /* Disable TX/RX */ 1241 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1242 SC16IS7XX_EFCR_RXDISABLE_BIT | 1243 SC16IS7XX_EFCR_TXDISABLE_BIT, 1244 SC16IS7XX_EFCR_RXDISABLE_BIT | 1245 SC16IS7XX_EFCR_TXDISABLE_BIT); 1246 1247 sc16is7xx_power(port, 0); 1248 1249 kthread_flush_worker(&s->kworker); 1250 } 1251 1252 static const char *sc16is7xx_type(struct uart_port *port) 1253 { 1254 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1255 1256 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1257 } 1258 1259 static int sc16is7xx_request_port(struct uart_port *port) 1260 { 1261 /* Do nothing */ 1262 return 0; 1263 } 1264 1265 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1266 { 1267 if (flags & UART_CONFIG_TYPE) 1268 port->type = PORT_SC16IS7XX; 1269 } 1270 1271 static int sc16is7xx_verify_port(struct uart_port *port, 1272 struct serial_struct *s) 1273 { 1274 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1275 return -EINVAL; 1276 if (s->irq != port->irq) 1277 return -EINVAL; 1278 1279 return 0; 1280 } 1281 1282 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1283 unsigned int oldstate) 1284 { 1285 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1286 } 1287 1288 static void sc16is7xx_null_void(struct uart_port *port) 1289 { 1290 /* Do nothing */ 1291 } 1292 1293 static const struct uart_ops sc16is7xx_ops = { 1294 .tx_empty = sc16is7xx_tx_empty, 1295 .set_mctrl = sc16is7xx_set_mctrl, 1296 .get_mctrl = sc16is7xx_get_mctrl, 1297 .stop_tx = sc16is7xx_stop_tx, 1298 .start_tx = sc16is7xx_start_tx, 1299 .throttle = sc16is7xx_throttle, 1300 .unthrottle = sc16is7xx_unthrottle, 1301 .stop_rx = sc16is7xx_stop_rx, 1302 .enable_ms = sc16is7xx_enable_ms, 1303 .break_ctl = sc16is7xx_break_ctl, 1304 .startup = sc16is7xx_startup, 1305 .shutdown = sc16is7xx_shutdown, 1306 .set_termios = sc16is7xx_set_termios, 1307 .type = sc16is7xx_type, 1308 .request_port = sc16is7xx_request_port, 1309 .release_port = sc16is7xx_null_void, 1310 .config_port = sc16is7xx_config_port, 1311 .verify_port = sc16is7xx_verify_port, 1312 .pm = sc16is7xx_pm, 1313 }; 1314 1315 #ifdef CONFIG_GPIOLIB 1316 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1317 { 1318 unsigned int val; 1319 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1320 struct uart_port *port = &s->p[0].port; 1321 1322 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1323 1324 return !!(val & BIT(offset)); 1325 } 1326 1327 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1328 { 1329 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1330 struct uart_port *port = &s->p[0].port; 1331 1332 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1333 val ? BIT(offset) : 0); 1334 } 1335 1336 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1337 unsigned offset) 1338 { 1339 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1340 struct uart_port *port = &s->p[0].port; 1341 1342 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1343 1344 return 0; 1345 } 1346 1347 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1348 unsigned offset, int val) 1349 { 1350 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1351 struct uart_port *port = &s->p[0].port; 1352 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1353 1354 if (val) 1355 state |= BIT(offset); 1356 else 1357 state &= ~BIT(offset); 1358 1359 /* 1360 * If we write IOSTATE first, and then IODIR, the output value is not 1361 * transferred to the corresponding I/O pin. 1362 * The datasheet states that each register bit will be transferred to 1363 * the corresponding I/O pin programmed as output when writing to 1364 * IOSTATE. Therefore, configure direction first with IODIR, and then 1365 * set value after with IOSTATE. 1366 */ 1367 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1368 BIT(offset)); 1369 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1370 1371 return 0; 1372 } 1373 1374 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1375 unsigned long *valid_mask, 1376 unsigned int ngpios) 1377 { 1378 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1379 1380 *valid_mask = s->gpio_valid_mask; 1381 1382 return 0; 1383 } 1384 1385 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1386 { 1387 struct device *dev = s->p[0].port.dev; 1388 1389 if (!s->devtype->nr_gpio) 1390 return 0; 1391 1392 switch (s->mctrl_mask) { 1393 case 0: 1394 s->gpio_valid_mask = GENMASK(7, 0); 1395 break; 1396 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1397 s->gpio_valid_mask = GENMASK(3, 0); 1398 break; 1399 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1400 s->gpio_valid_mask = GENMASK(7, 4); 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 if (s->gpio_valid_mask == 0) 1407 return 0; 1408 1409 s->gpio.owner = THIS_MODULE; 1410 s->gpio.parent = dev; 1411 s->gpio.label = dev_name(dev); 1412 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1413 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1414 s->gpio.get = sc16is7xx_gpio_get; 1415 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1416 s->gpio.set = sc16is7xx_gpio_set; 1417 s->gpio.base = -1; 1418 s->gpio.ngpio = s->devtype->nr_gpio; 1419 s->gpio.can_sleep = 1; 1420 1421 return gpiochip_add_data(&s->gpio, s); 1422 } 1423 #endif 1424 1425 /* 1426 * Configure ports designated to operate as modem control lines. 1427 */ 1428 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s) 1429 { 1430 int i; 1431 int ret; 1432 int count; 1433 u32 mctrl_port[2]; 1434 struct device *dev = s->p[0].port.dev; 1435 1436 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1437 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1438 return 0; 1439 1440 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1441 mctrl_port, count); 1442 if (ret) 1443 return ret; 1444 1445 s->mctrl_mask = 0; 1446 1447 for (i = 0; i < count; i++) { 1448 /* Use GPIO lines as modem control lines */ 1449 if (mctrl_port[i] == 0) 1450 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1451 else if (mctrl_port[i] == 1) 1452 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1453 } 1454 1455 if (s->mctrl_mask) 1456 regmap_update_bits( 1457 s->regmap, 1458 SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1459 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1460 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1461 1462 return 0; 1463 } 1464 1465 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1466 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1467 .delay_rts_before_send = 1, 1468 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1469 }; 1470 1471 static int sc16is7xx_probe(struct device *dev, 1472 const struct sc16is7xx_devtype *devtype, 1473 struct regmap *regmap, int irq) 1474 { 1475 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1476 unsigned int val; 1477 u32 uartclk = 0; 1478 int i, ret; 1479 struct sc16is7xx_port *s; 1480 1481 if (IS_ERR(regmap)) 1482 return PTR_ERR(regmap); 1483 1484 /* 1485 * This device does not have an identification register that would 1486 * tell us if we are really connected to the correct device. 1487 * The best we can do is to check if communication is at all possible. 1488 */ 1489 ret = regmap_read(regmap, 1490 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val); 1491 if (ret < 0) 1492 return -EPROBE_DEFER; 1493 1494 /* Alloc port structure */ 1495 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1496 if (!s) { 1497 dev_err(dev, "Error allocating port structure\n"); 1498 return -ENOMEM; 1499 } 1500 1501 /* Always ask for fixed clock rate from a property. */ 1502 device_property_read_u32(dev, "clock-frequency", &uartclk); 1503 1504 s->clk = devm_clk_get_optional(dev, NULL); 1505 if (IS_ERR(s->clk)) 1506 return PTR_ERR(s->clk); 1507 1508 ret = clk_prepare_enable(s->clk); 1509 if (ret) 1510 return ret; 1511 1512 freq = clk_get_rate(s->clk); 1513 if (freq == 0) { 1514 if (uartclk) 1515 freq = uartclk; 1516 if (pfreq) 1517 freq = *pfreq; 1518 if (freq) 1519 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1520 else 1521 return -EINVAL; 1522 } 1523 1524 s->regmap = regmap; 1525 s->devtype = devtype; 1526 dev_set_drvdata(dev, s); 1527 mutex_init(&s->efr_lock); 1528 1529 kthread_init_worker(&s->kworker); 1530 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1531 "sc16is7xx"); 1532 if (IS_ERR(s->kworker_task)) { 1533 ret = PTR_ERR(s->kworker_task); 1534 goto out_clk; 1535 } 1536 sched_set_fifo(s->kworker_task); 1537 1538 /* reset device, purging any pending irq / data */ 1539 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1540 SC16IS7XX_IOCONTROL_SRESET_BIT); 1541 1542 for (i = 0; i < devtype->nr_uart; ++i) { 1543 s->p[i].line = i; 1544 /* Initialize port data */ 1545 s->p[i].port.dev = dev; 1546 s->p[i].port.irq = irq; 1547 s->p[i].port.type = PORT_SC16IS7XX; 1548 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1549 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1550 s->p[i].port.iobase = i; 1551 /* 1552 * Use all ones as membase to make sure uart_configure_port() in 1553 * serial_core.c does not abort for SPI/I2C devices where the 1554 * membase address is not applicable. 1555 */ 1556 s->p[i].port.membase = (void __iomem *)~0; 1557 s->p[i].port.iotype = UPIO_PORT; 1558 s->p[i].port.uartclk = freq; 1559 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1560 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1561 s->p[i].port.ops = &sc16is7xx_ops; 1562 s->p[i].old_mctrl = 0; 1563 s->p[i].port.line = sc16is7xx_alloc_line(); 1564 1565 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1566 ret = -ENOMEM; 1567 goto out_ports; 1568 } 1569 1570 ret = uart_get_rs485_mode(&s->p[i].port); 1571 if (ret) 1572 goto out_ports; 1573 1574 /* Disable all interrupts */ 1575 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1576 /* Disable TX/RX */ 1577 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1578 SC16IS7XX_EFCR_RXDISABLE_BIT | 1579 SC16IS7XX_EFCR_TXDISABLE_BIT); 1580 1581 /* Initialize kthread work structs */ 1582 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1583 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1584 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1585 /* Register port */ 1586 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1587 1588 /* Enable EFR */ 1589 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1590 SC16IS7XX_LCR_CONF_MODE_B); 1591 1592 regcache_cache_bypass(s->regmap, true); 1593 1594 /* Enable write access to enhanced features */ 1595 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1596 SC16IS7XX_EFR_ENABLE_BIT); 1597 1598 regcache_cache_bypass(s->regmap, false); 1599 1600 /* Restore access to general registers */ 1601 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1602 1603 /* Go to suspend mode */ 1604 sc16is7xx_power(&s->p[i].port, 0); 1605 } 1606 1607 if (dev->of_node) { 1608 struct property *prop; 1609 const __be32 *p; 1610 u32 u; 1611 1612 of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1613 prop, p, u) 1614 if (u < devtype->nr_uart) 1615 s->p[u].irda_mode = true; 1616 } 1617 1618 ret = sc16is7xx_setup_mctrl_ports(s); 1619 if (ret) 1620 goto out_ports; 1621 1622 #ifdef CONFIG_GPIOLIB 1623 ret = sc16is7xx_setup_gpio_chip(s); 1624 if (ret) 1625 goto out_ports; 1626 #endif 1627 1628 /* 1629 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1630 * If that succeeds, we can allow sharing the interrupt as well. 1631 * In case the interrupt controller doesn't support that, we fall 1632 * back to a non-shared falling-edge trigger. 1633 */ 1634 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1635 IRQF_TRIGGER_LOW | IRQF_SHARED | 1636 IRQF_ONESHOT, 1637 dev_name(dev), s); 1638 if (!ret) 1639 return 0; 1640 1641 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1642 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1643 dev_name(dev), s); 1644 if (!ret) 1645 return 0; 1646 1647 #ifdef CONFIG_GPIOLIB 1648 if (s->gpio_valid_mask) 1649 gpiochip_remove(&s->gpio); 1650 #endif 1651 1652 out_ports: 1653 for (i--; i >= 0; i--) { 1654 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1655 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1656 } 1657 1658 kthread_stop(s->kworker_task); 1659 1660 out_clk: 1661 clk_disable_unprepare(s->clk); 1662 1663 return ret; 1664 } 1665 1666 static void sc16is7xx_remove(struct device *dev) 1667 { 1668 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1669 int i; 1670 1671 #ifdef CONFIG_GPIOLIB 1672 if (s->gpio_valid_mask) 1673 gpiochip_remove(&s->gpio); 1674 #endif 1675 1676 for (i = 0; i < s->devtype->nr_uart; i++) { 1677 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1678 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1679 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1680 sc16is7xx_power(&s->p[i].port, 0); 1681 } 1682 1683 kthread_flush_worker(&s->kworker); 1684 kthread_stop(s->kworker_task); 1685 1686 clk_disable_unprepare(s->clk); 1687 } 1688 1689 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1690 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1691 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1692 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1693 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1694 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1695 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1696 { } 1697 }; 1698 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1699 1700 static struct regmap_config regcfg = { 1701 .reg_bits = 7, 1702 .pad_bits = 1, 1703 .val_bits = 8, 1704 .cache_type = REGCACHE_RBTREE, 1705 .volatile_reg = sc16is7xx_regmap_volatile, 1706 .precious_reg = sc16is7xx_regmap_precious, 1707 }; 1708 1709 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1710 static int sc16is7xx_spi_probe(struct spi_device *spi) 1711 { 1712 const struct sc16is7xx_devtype *devtype; 1713 struct regmap *regmap; 1714 int ret; 1715 1716 /* Setup SPI bus */ 1717 spi->bits_per_word = 8; 1718 /* For all variants, only mode 0 is supported */ 1719 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0) 1720 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n"); 1721 1722 spi->mode = spi->mode ? : SPI_MODE_0; 1723 spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ; 1724 ret = spi_setup(spi); 1725 if (ret) 1726 return ret; 1727 1728 if (spi->dev.of_node) { 1729 devtype = device_get_match_data(&spi->dev); 1730 if (!devtype) 1731 return -ENODEV; 1732 } else { 1733 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1734 1735 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1736 } 1737 1738 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1739 (devtype->nr_uart - 1); 1740 regmap = devm_regmap_init_spi(spi, ®cfg); 1741 1742 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); 1743 } 1744 1745 static void sc16is7xx_spi_remove(struct spi_device *spi) 1746 { 1747 sc16is7xx_remove(&spi->dev); 1748 } 1749 1750 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1751 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1752 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1753 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1754 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1755 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1756 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1757 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1758 { } 1759 }; 1760 1761 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1762 1763 static struct spi_driver sc16is7xx_spi_uart_driver = { 1764 .driver = { 1765 .name = SC16IS7XX_NAME, 1766 .of_match_table = sc16is7xx_dt_ids, 1767 }, 1768 .probe = sc16is7xx_spi_probe, 1769 .remove = sc16is7xx_spi_remove, 1770 .id_table = sc16is7xx_spi_id_table, 1771 }; 1772 1773 MODULE_ALIAS("spi:sc16is7xx"); 1774 #endif 1775 1776 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1777 static int sc16is7xx_i2c_probe(struct i2c_client *i2c) 1778 { 1779 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1780 const struct sc16is7xx_devtype *devtype; 1781 struct regmap *regmap; 1782 1783 if (i2c->dev.of_node) { 1784 devtype = device_get_match_data(&i2c->dev); 1785 if (!devtype) 1786 return -ENODEV; 1787 } else { 1788 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1789 } 1790 1791 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1792 (devtype->nr_uart - 1); 1793 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1794 1795 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); 1796 } 1797 1798 static void sc16is7xx_i2c_remove(struct i2c_client *client) 1799 { 1800 sc16is7xx_remove(&client->dev); 1801 } 1802 1803 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1804 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1805 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1806 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1807 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1808 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1809 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1810 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1811 { } 1812 }; 1813 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1814 1815 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1816 .driver = { 1817 .name = SC16IS7XX_NAME, 1818 .of_match_table = sc16is7xx_dt_ids, 1819 }, 1820 .probe = sc16is7xx_i2c_probe, 1821 .remove = sc16is7xx_i2c_remove, 1822 .id_table = sc16is7xx_i2c_id_table, 1823 }; 1824 1825 #endif 1826 1827 static int __init sc16is7xx_init(void) 1828 { 1829 int ret; 1830 1831 ret = uart_register_driver(&sc16is7xx_uart); 1832 if (ret) { 1833 pr_err("Registering UART driver failed\n"); 1834 return ret; 1835 } 1836 1837 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1838 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1839 if (ret < 0) { 1840 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1841 goto err_i2c; 1842 } 1843 #endif 1844 1845 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1846 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1847 if (ret < 0) { 1848 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1849 goto err_spi; 1850 } 1851 #endif 1852 return ret; 1853 1854 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1855 err_spi: 1856 #endif 1857 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1858 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1859 err_i2c: 1860 #endif 1861 uart_unregister_driver(&sc16is7xx_uart); 1862 return ret; 1863 } 1864 module_init(sc16is7xx_init); 1865 1866 static void __exit sc16is7xx_exit(void) 1867 { 1868 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1869 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1870 #endif 1871 1872 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1873 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1874 #endif 1875 uart_unregister_driver(&sc16is7xx_uart); 1876 } 1877 module_exit(sc16is7xx_exit); 1878 1879 MODULE_LICENSE("GPL"); 1880 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1881 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1882