1 /* 2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 3 * Author: Jon Ringle <jringle@gridpoint.com> 4 * 5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/bitops.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/i2c.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 #include <linux/spi/spi.h> 31 #include <linux/uaccess.h> 32 #include <uapi/linux/sched/types.h> 33 34 #define SC16IS7XX_NAME "sc16is7xx" 35 #define SC16IS7XX_MAX_DEVS 8 36 37 /* SC16IS7XX register definitions */ 38 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 39 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 40 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 41 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 42 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 43 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 44 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 45 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 46 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 47 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 48 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 49 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 50 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 51 * - only on 75x/76x 52 */ 53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 54 * - only on 75x/76x 55 */ 56 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 57 * - only on 75x/76x 58 */ 59 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 60 * - only on 75x/76x 61 */ 62 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 63 64 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 65 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 66 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 67 68 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 69 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 70 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 71 72 /* Enhanced Register set: Only if (LCR == 0xBF) */ 73 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 74 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 75 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 76 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 77 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 78 79 /* IER register bits */ 80 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 81 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 82 * interrupt */ 83 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 84 * interrupt */ 85 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 86 * interrupt */ 87 88 /* IER register bits - write only if (EFR[4] == 1) */ 89 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 90 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 91 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 92 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 93 94 /* FCR register bits */ 95 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 96 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 97 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 98 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 99 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 100 101 /* FCR register bits - write only if (EFR[4] == 1) */ 102 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 103 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 104 105 /* IIR register bits */ 106 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 107 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 108 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 109 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 110 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 111 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 112 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 113 * - only on 75x/76x 114 */ 115 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 116 * - only on 75x/76x 117 */ 118 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 119 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 120 * from active (LOW) 121 * to inactive (HIGH) 122 */ 123 /* LCR register bits */ 124 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 125 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 126 * 127 * Word length bits table: 128 * 00 -> 5 bit words 129 * 01 -> 6 bit words 130 * 10 -> 7 bit words 131 * 11 -> 8 bit words 132 */ 133 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 134 * 135 * STOP length bit table: 136 * 0 -> 1 stop bit 137 * 1 -> 1-1.5 stop bits if 138 * word length is 5, 139 * 2 stop bits otherwise 140 */ 141 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 142 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 143 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 144 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 145 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 146 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 147 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 148 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 149 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 150 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 151 * reg set */ 152 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 153 * reg set */ 154 155 /* MCR register bits */ 156 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 157 * - only on 75x/76x 158 */ 159 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 160 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 161 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 162 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 171 * - write enabled 172 * if (EFR[4] == 1) 173 */ 174 175 /* LSR register bits */ 176 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 177 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 178 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 179 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 180 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 181 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 182 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 183 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 184 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 185 186 /* MSR register bits */ 187 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 188 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 189 * or (IO4) 190 * - only on 75x/76x 191 */ 192 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 193 * or (IO7) 194 * - only on 75x/76x 195 */ 196 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 197 * or (IO6) 198 * - only on 75x/76x 199 */ 200 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 201 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 202 * - only on 75x/76x 203 */ 204 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 205 * - only on 75x/76x 206 */ 207 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 208 * - only on 75x/76x 209 */ 210 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 211 212 /* 213 * TCR register bits 214 * TCR trigger levels are available from 0 to 60 characters with a granularity 215 * of four. 216 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 217 * no built-in hardware check to make sure this condition is met. Also, the TCR 218 * must be programmed with this condition before auto RTS or software flow 219 * control is enabled to avoid spurious operation of the device. 220 */ 221 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 222 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 223 224 /* 225 * TLR register bits 226 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 227 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 228 * trigger levels. Trigger levels from 4 characters to 60 characters are 229 * available with a granularity of four. 230 * 231 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 232 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 233 * the trigger level defined in FCR is discarded. This applies to both transmit 234 * FIFO and receive FIFO trigger level setting. 235 * 236 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 237 * default state, that is, '00'. 238 */ 239 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 240 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 241 242 /* IOControl register bits (Only 750/760) */ 243 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 244 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */ 245 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 246 247 /* EFCR register bits */ 248 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 249 * mode (RS485) */ 250 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 251 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 252 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 253 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 254 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 255 * 0 = rate upto 115.2 kbit/s 256 * - Only 750/760 257 * 1 = rate upto 1.152 Mbit/s 258 * - Only 760 259 */ 260 261 /* EFR register bits */ 262 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 263 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 264 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 265 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 266 * and writing to IER[7:4], 267 * FCR[5:4], MCR[7:5] 268 */ 269 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 270 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 271 * 272 * SWFLOW bits 3 & 2 table: 273 * 00 -> no transmitter flow 274 * control 275 * 01 -> transmitter generates 276 * XON2 and XOFF2 277 * 10 -> transmitter generates 278 * XON1 and XOFF1 279 * 11 -> transmitter generates 280 * XON1, XON2, XOFF1 and 281 * XOFF2 282 */ 283 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 284 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 285 * 286 * SWFLOW bits 3 & 2 table: 287 * 00 -> no received flow 288 * control 289 * 01 -> receiver compares 290 * XON2 and XOFF2 291 * 10 -> receiver compares 292 * XON1 and XOFF1 293 * 11 -> receiver compares 294 * XON1, XON2, XOFF1 and 295 * XOFF2 296 */ 297 298 /* Misc definitions */ 299 #define SC16IS7XX_FIFO_SIZE (64) 300 #define SC16IS7XX_REG_SHIFT 2 301 302 struct sc16is7xx_devtype { 303 char name[10]; 304 int nr_gpio; 305 int nr_uart; 306 }; 307 308 #define SC16IS7XX_RECONF_MD (1 << 0) 309 #define SC16IS7XX_RECONF_IER (1 << 1) 310 #define SC16IS7XX_RECONF_RS485 (1 << 2) 311 312 struct sc16is7xx_one_config { 313 unsigned int flags; 314 u8 ier_clear; 315 }; 316 317 struct sc16is7xx_one { 318 struct uart_port port; 319 u8 line; 320 struct kthread_work tx_work; 321 struct kthread_work reg_work; 322 struct sc16is7xx_one_config config; 323 }; 324 325 struct sc16is7xx_port { 326 const struct sc16is7xx_devtype *devtype; 327 struct regmap *regmap; 328 struct clk *clk; 329 #ifdef CONFIG_GPIOLIB 330 struct gpio_chip gpio; 331 #endif 332 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 333 struct kthread_worker kworker; 334 struct task_struct *kworker_task; 335 struct kthread_work irq_work; 336 struct sc16is7xx_one p[0]; 337 }; 338 339 static unsigned long sc16is7xx_lines; 340 341 static struct uart_driver sc16is7xx_uart = { 342 .owner = THIS_MODULE, 343 .dev_name = "ttySC", 344 .nr = SC16IS7XX_MAX_DEVS, 345 }; 346 347 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 348 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 349 350 static int sc16is7xx_line(struct uart_port *port) 351 { 352 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 353 354 return one->line; 355 } 356 357 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 358 { 359 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 360 unsigned int val = 0; 361 const u8 line = sc16is7xx_line(port); 362 363 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 364 365 return val; 366 } 367 368 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 369 { 370 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 371 const u8 line = sc16is7xx_line(port); 372 373 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 374 } 375 376 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 377 { 378 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 379 const u8 line = sc16is7xx_line(port); 380 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 381 382 regcache_cache_bypass(s->regmap, true); 383 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 384 regcache_cache_bypass(s->regmap, false); 385 } 386 387 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 388 { 389 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 390 const u8 line = sc16is7xx_line(port); 391 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 392 393 /* 394 * Don't send zero-length data, at least on SPI it confuses the chip 395 * delivering wrong TXLVL data. 396 */ 397 if (unlikely(!to_send)) 398 return; 399 400 regcache_cache_bypass(s->regmap, true); 401 regmap_raw_write(s->regmap, addr, s->buf, to_send); 402 regcache_cache_bypass(s->regmap, false); 403 } 404 405 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 406 u8 mask, u8 val) 407 { 408 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 409 const u8 line = sc16is7xx_line(port); 410 411 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 412 mask, val); 413 } 414 415 static int sc16is7xx_alloc_line(void) 416 { 417 int i; 418 419 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 420 421 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 422 if (!test_and_set_bit(i, &sc16is7xx_lines)) 423 break; 424 425 return i; 426 } 427 428 static void sc16is7xx_power(struct uart_port *port, int on) 429 { 430 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 431 SC16IS7XX_IER_SLEEP_BIT, 432 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 433 } 434 435 static const struct sc16is7xx_devtype sc16is74x_devtype = { 436 .name = "SC16IS74X", 437 .nr_gpio = 0, 438 .nr_uart = 1, 439 }; 440 441 static const struct sc16is7xx_devtype sc16is750_devtype = { 442 .name = "SC16IS750", 443 .nr_gpio = 8, 444 .nr_uart = 1, 445 }; 446 447 static const struct sc16is7xx_devtype sc16is752_devtype = { 448 .name = "SC16IS752", 449 .nr_gpio = 8, 450 .nr_uart = 2, 451 }; 452 453 static const struct sc16is7xx_devtype sc16is760_devtype = { 454 .name = "SC16IS760", 455 .nr_gpio = 8, 456 .nr_uart = 1, 457 }; 458 459 static const struct sc16is7xx_devtype sc16is762_devtype = { 460 .name = "SC16IS762", 461 .nr_gpio = 8, 462 .nr_uart = 2, 463 }; 464 465 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 466 { 467 switch (reg >> SC16IS7XX_REG_SHIFT) { 468 case SC16IS7XX_RHR_REG: 469 case SC16IS7XX_IIR_REG: 470 case SC16IS7XX_LSR_REG: 471 case SC16IS7XX_MSR_REG: 472 case SC16IS7XX_TXLVL_REG: 473 case SC16IS7XX_RXLVL_REG: 474 case SC16IS7XX_IOSTATE_REG: 475 return true; 476 default: 477 break; 478 } 479 480 return false; 481 } 482 483 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 484 { 485 switch (reg >> SC16IS7XX_REG_SHIFT) { 486 case SC16IS7XX_RHR_REG: 487 return true; 488 default: 489 break; 490 } 491 492 return false; 493 } 494 495 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 496 { 497 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 498 u8 lcr; 499 u8 prescaler = 0; 500 unsigned long clk = port->uartclk, div = clk / 16 / baud; 501 502 if (div > 0xffff) { 503 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 504 div /= 4; 505 } 506 507 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 508 509 /* Open the LCR divisors for configuration */ 510 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 511 SC16IS7XX_LCR_CONF_MODE_B); 512 513 /* Enable enhanced features */ 514 regcache_cache_bypass(s->regmap, true); 515 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 516 SC16IS7XX_EFR_ENABLE_BIT); 517 regcache_cache_bypass(s->regmap, false); 518 519 /* Put LCR back to the normal mode */ 520 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 521 522 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 523 SC16IS7XX_MCR_CLKSEL_BIT, 524 prescaler); 525 526 /* Open the LCR divisors for configuration */ 527 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 528 SC16IS7XX_LCR_CONF_MODE_A); 529 530 /* Write the new divisor */ 531 regcache_cache_bypass(s->regmap, true); 532 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 533 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 534 regcache_cache_bypass(s->regmap, false); 535 536 /* Put LCR back to the normal mode */ 537 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 538 539 return DIV_ROUND_CLOSEST(clk / 16, div); 540 } 541 542 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 543 unsigned int iir) 544 { 545 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 546 unsigned int lsr = 0, ch, flag, bytes_read, i; 547 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 548 549 if (unlikely(rxlen >= sizeof(s->buf))) { 550 dev_warn_ratelimited(port->dev, 551 "ttySC%i: Possible RX FIFO overrun: %d\n", 552 port->line, rxlen); 553 port->icount.buf_overrun++; 554 /* Ensure sanity of RX level */ 555 rxlen = sizeof(s->buf); 556 } 557 558 while (rxlen) { 559 /* Only read lsr if there are possible errors in FIFO */ 560 if (read_lsr) { 561 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 562 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 563 read_lsr = false; /* No errors left in FIFO */ 564 } else 565 lsr = 0; 566 567 if (read_lsr) { 568 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 569 bytes_read = 1; 570 } else { 571 sc16is7xx_fifo_read(port, rxlen); 572 bytes_read = rxlen; 573 } 574 575 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 576 577 port->icount.rx++; 578 flag = TTY_NORMAL; 579 580 if (unlikely(lsr)) { 581 if (lsr & SC16IS7XX_LSR_BI_BIT) { 582 port->icount.brk++; 583 if (uart_handle_break(port)) 584 continue; 585 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 586 port->icount.parity++; 587 else if (lsr & SC16IS7XX_LSR_FE_BIT) 588 port->icount.frame++; 589 else if (lsr & SC16IS7XX_LSR_OE_BIT) 590 port->icount.overrun++; 591 592 lsr &= port->read_status_mask; 593 if (lsr & SC16IS7XX_LSR_BI_BIT) 594 flag = TTY_BREAK; 595 else if (lsr & SC16IS7XX_LSR_PE_BIT) 596 flag = TTY_PARITY; 597 else if (lsr & SC16IS7XX_LSR_FE_BIT) 598 flag = TTY_FRAME; 599 else if (lsr & SC16IS7XX_LSR_OE_BIT) 600 flag = TTY_OVERRUN; 601 } 602 603 for (i = 0; i < bytes_read; ++i) { 604 ch = s->buf[i]; 605 if (uart_handle_sysrq_char(port, ch)) 606 continue; 607 608 if (lsr & port->ignore_status_mask) 609 continue; 610 611 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 612 flag); 613 } 614 rxlen -= bytes_read; 615 } 616 617 tty_flip_buffer_push(&port->state->port); 618 } 619 620 static void sc16is7xx_handle_tx(struct uart_port *port) 621 { 622 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 623 struct circ_buf *xmit = &port->state->xmit; 624 unsigned int txlen, to_send, i; 625 626 if (unlikely(port->x_char)) { 627 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 628 port->icount.tx++; 629 port->x_char = 0; 630 return; 631 } 632 633 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 634 return; 635 636 /* Get length of data pending in circular buffer */ 637 to_send = uart_circ_chars_pending(xmit); 638 if (likely(to_send)) { 639 /* Limit to size of TX FIFO */ 640 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 641 if (txlen > SC16IS7XX_FIFO_SIZE) { 642 dev_err_ratelimited(port->dev, 643 "chip reports %d free bytes in TX fifo, but it only has %d", 644 txlen, SC16IS7XX_FIFO_SIZE); 645 txlen = 0; 646 } 647 to_send = (to_send > txlen) ? txlen : to_send; 648 649 /* Add data to send */ 650 port->icount.tx += to_send; 651 652 /* Convert to linear buffer */ 653 for (i = 0; i < to_send; ++i) { 654 s->buf[i] = xmit->buf[xmit->tail]; 655 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 656 } 657 658 sc16is7xx_fifo_write(port, to_send); 659 } 660 661 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 662 uart_write_wakeup(port); 663 } 664 665 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 666 { 667 struct uart_port *port = &s->p[portno].port; 668 669 do { 670 unsigned int iir, rxlen; 671 672 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 673 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 674 break; 675 676 iir &= SC16IS7XX_IIR_ID_MASK; 677 678 switch (iir) { 679 case SC16IS7XX_IIR_RDI_SRC: 680 case SC16IS7XX_IIR_RLSE_SRC: 681 case SC16IS7XX_IIR_RTOI_SRC: 682 case SC16IS7XX_IIR_XOFFI_SRC: 683 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 684 if (rxlen) 685 sc16is7xx_handle_rx(port, rxlen, iir); 686 break; 687 case SC16IS7XX_IIR_THRI_SRC: 688 sc16is7xx_handle_tx(port); 689 break; 690 default: 691 dev_err_ratelimited(port->dev, 692 "ttySC%i: Unexpected interrupt: %x", 693 port->line, iir); 694 break; 695 } 696 } while (1); 697 } 698 699 static void sc16is7xx_ist(struct kthread_work *ws) 700 { 701 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work); 702 int i; 703 704 for (i = 0; i < s->devtype->nr_uart; ++i) 705 sc16is7xx_port_irq(s, i); 706 } 707 708 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 709 { 710 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 711 712 kthread_queue_work(&s->kworker, &s->irq_work); 713 714 return IRQ_HANDLED; 715 } 716 717 static void sc16is7xx_tx_proc(struct kthread_work *ws) 718 { 719 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 720 721 if ((port->rs485.flags & SER_RS485_ENABLED) && 722 (port->rs485.delay_rts_before_send > 0)) 723 msleep(port->rs485.delay_rts_before_send); 724 725 sc16is7xx_handle_tx(port); 726 } 727 728 static void sc16is7xx_reconf_rs485(struct uart_port *port) 729 { 730 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 731 SC16IS7XX_EFCR_RTS_INVERT_BIT; 732 u32 efcr = 0; 733 struct serial_rs485 *rs485 = &port->rs485; 734 unsigned long irqflags; 735 736 spin_lock_irqsave(&port->lock, irqflags); 737 if (rs485->flags & SER_RS485_ENABLED) { 738 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 739 740 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 741 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 742 } 743 spin_unlock_irqrestore(&port->lock, irqflags); 744 745 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 746 } 747 748 static void sc16is7xx_reg_proc(struct kthread_work *ws) 749 { 750 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 751 struct sc16is7xx_one_config config; 752 unsigned long irqflags; 753 754 spin_lock_irqsave(&one->port.lock, irqflags); 755 config = one->config; 756 memset(&one->config, 0, sizeof(one->config)); 757 spin_unlock_irqrestore(&one->port.lock, irqflags); 758 759 if (config.flags & SC16IS7XX_RECONF_MD) { 760 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 761 SC16IS7XX_MCR_LOOP_BIT, 762 (one->port.mctrl & TIOCM_LOOP) ? 763 SC16IS7XX_MCR_LOOP_BIT : 0); 764 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 765 SC16IS7XX_MCR_RTS_BIT, 766 (one->port.mctrl & TIOCM_RTS) ? 767 SC16IS7XX_MCR_RTS_BIT : 0); 768 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 769 SC16IS7XX_MCR_DTR_BIT, 770 (one->port.mctrl & TIOCM_DTR) ? 771 SC16IS7XX_MCR_DTR_BIT : 0); 772 } 773 if (config.flags & SC16IS7XX_RECONF_IER) 774 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 775 config.ier_clear, 0); 776 777 if (config.flags & SC16IS7XX_RECONF_RS485) 778 sc16is7xx_reconf_rs485(&one->port); 779 } 780 781 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 782 { 783 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 784 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 785 786 one->config.flags |= SC16IS7XX_RECONF_IER; 787 one->config.ier_clear |= bit; 788 kthread_queue_work(&s->kworker, &one->reg_work); 789 } 790 791 static void sc16is7xx_stop_tx(struct uart_port *port) 792 { 793 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 794 } 795 796 static void sc16is7xx_stop_rx(struct uart_port *port) 797 { 798 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 799 } 800 801 static void sc16is7xx_start_tx(struct uart_port *port) 802 { 803 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 804 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 805 806 kthread_queue_work(&s->kworker, &one->tx_work); 807 } 808 809 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 810 { 811 unsigned int lsr; 812 813 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 814 815 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 816 } 817 818 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 819 { 820 /* DCD and DSR are not wired and CTS/RTS is handled automatically 821 * so just indicate DSR and CAR asserted 822 */ 823 return TIOCM_DSR | TIOCM_CAR; 824 } 825 826 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 827 { 828 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 829 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 830 831 one->config.flags |= SC16IS7XX_RECONF_MD; 832 kthread_queue_work(&s->kworker, &one->reg_work); 833 } 834 835 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 836 { 837 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 838 SC16IS7XX_LCR_TXBREAK_BIT, 839 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 840 } 841 842 static void sc16is7xx_set_termios(struct uart_port *port, 843 struct ktermios *termios, 844 struct ktermios *old) 845 { 846 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 847 unsigned int lcr, flow = 0; 848 int baud; 849 850 /* Mask termios capabilities we don't support */ 851 termios->c_cflag &= ~CMSPAR; 852 853 /* Word size */ 854 switch (termios->c_cflag & CSIZE) { 855 case CS5: 856 lcr = SC16IS7XX_LCR_WORD_LEN_5; 857 break; 858 case CS6: 859 lcr = SC16IS7XX_LCR_WORD_LEN_6; 860 break; 861 case CS7: 862 lcr = SC16IS7XX_LCR_WORD_LEN_7; 863 break; 864 case CS8: 865 lcr = SC16IS7XX_LCR_WORD_LEN_8; 866 break; 867 default: 868 lcr = SC16IS7XX_LCR_WORD_LEN_8; 869 termios->c_cflag &= ~CSIZE; 870 termios->c_cflag |= CS8; 871 break; 872 } 873 874 /* Parity */ 875 if (termios->c_cflag & PARENB) { 876 lcr |= SC16IS7XX_LCR_PARITY_BIT; 877 if (!(termios->c_cflag & PARODD)) 878 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 879 } 880 881 /* Stop bits */ 882 if (termios->c_cflag & CSTOPB) 883 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 884 885 /* Set read status mask */ 886 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 887 if (termios->c_iflag & INPCK) 888 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 889 SC16IS7XX_LSR_FE_BIT; 890 if (termios->c_iflag & (BRKINT | PARMRK)) 891 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 892 893 /* Set status ignore mask */ 894 port->ignore_status_mask = 0; 895 if (termios->c_iflag & IGNBRK) 896 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 897 if (!(termios->c_cflag & CREAD)) 898 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 899 900 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 901 SC16IS7XX_LCR_CONF_MODE_B); 902 903 /* Configure flow control */ 904 regcache_cache_bypass(s->regmap, true); 905 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 906 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 907 if (termios->c_cflag & CRTSCTS) 908 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 909 SC16IS7XX_EFR_AUTORTS_BIT; 910 if (termios->c_iflag & IXON) 911 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 912 if (termios->c_iflag & IXOFF) 913 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 914 915 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow); 916 regcache_cache_bypass(s->regmap, false); 917 918 /* Update LCR register */ 919 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 920 921 /* Get baud rate generator configuration */ 922 baud = uart_get_baud_rate(port, termios, old, 923 port->uartclk / 16 / 4 / 0xffff, 924 port->uartclk / 16); 925 926 /* Setup baudrate generator */ 927 baud = sc16is7xx_set_baud(port, baud); 928 929 /* Update timeout according to new baud rate */ 930 uart_update_timeout(port, termios->c_cflag, baud); 931 } 932 933 static int sc16is7xx_config_rs485(struct uart_port *port, 934 struct serial_rs485 *rs485) 935 { 936 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 937 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 938 939 if (rs485->flags & SER_RS485_ENABLED) { 940 bool rts_during_rx, rts_during_tx; 941 942 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND; 943 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND; 944 945 if (rts_during_rx == rts_during_tx) 946 dev_err(port->dev, 947 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n", 948 rts_during_tx, rts_during_rx); 949 950 /* 951 * RTS signal is handled by HW, it's timing can't be influenced. 952 * However, it's sometimes useful to delay TX even without RTS 953 * control therefore we try to handle .delay_rts_before_send. 954 */ 955 if (rs485->delay_rts_after_send) 956 return -EINVAL; 957 } 958 959 port->rs485 = *rs485; 960 one->config.flags |= SC16IS7XX_RECONF_RS485; 961 kthread_queue_work(&s->kworker, &one->reg_work); 962 963 return 0; 964 } 965 966 static int sc16is7xx_startup(struct uart_port *port) 967 { 968 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 969 unsigned int val; 970 971 sc16is7xx_power(port, 1); 972 973 /* Reset FIFOs*/ 974 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 975 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 976 udelay(5); 977 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 978 SC16IS7XX_FCR_FIFO_BIT); 979 980 /* Enable EFR */ 981 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 982 SC16IS7XX_LCR_CONF_MODE_B); 983 984 regcache_cache_bypass(s->regmap, true); 985 986 /* Enable write access to enhanced features and internal clock div */ 987 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 988 SC16IS7XX_EFR_ENABLE_BIT); 989 990 /* Enable TCR/TLR */ 991 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 992 SC16IS7XX_MCR_TCRTLR_BIT, 993 SC16IS7XX_MCR_TCRTLR_BIT); 994 995 /* Configure flow control levels */ 996 /* Flow control halt level 48, resume level 24 */ 997 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 998 SC16IS7XX_TCR_RX_RESUME(24) | 999 SC16IS7XX_TCR_RX_HALT(48)); 1000 1001 regcache_cache_bypass(s->regmap, false); 1002 1003 /* Now, initialize the UART */ 1004 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1005 1006 /* Enable the Rx and Tx FIFO */ 1007 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1008 SC16IS7XX_EFCR_RXDISABLE_BIT | 1009 SC16IS7XX_EFCR_TXDISABLE_BIT, 1010 0); 1011 1012 /* Enable RX, TX interrupts */ 1013 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT; 1014 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1015 1016 return 0; 1017 } 1018 1019 static void sc16is7xx_shutdown(struct uart_port *port) 1020 { 1021 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1022 1023 /* Disable all interrupts */ 1024 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1025 /* Disable TX/RX */ 1026 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1027 SC16IS7XX_EFCR_RXDISABLE_BIT | 1028 SC16IS7XX_EFCR_TXDISABLE_BIT, 1029 SC16IS7XX_EFCR_RXDISABLE_BIT | 1030 SC16IS7XX_EFCR_TXDISABLE_BIT); 1031 1032 sc16is7xx_power(port, 0); 1033 1034 kthread_flush_worker(&s->kworker); 1035 } 1036 1037 static const char *sc16is7xx_type(struct uart_port *port) 1038 { 1039 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1040 1041 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1042 } 1043 1044 static int sc16is7xx_request_port(struct uart_port *port) 1045 { 1046 /* Do nothing */ 1047 return 0; 1048 } 1049 1050 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1051 { 1052 if (flags & UART_CONFIG_TYPE) 1053 port->type = PORT_SC16IS7XX; 1054 } 1055 1056 static int sc16is7xx_verify_port(struct uart_port *port, 1057 struct serial_struct *s) 1058 { 1059 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1060 return -EINVAL; 1061 if (s->irq != port->irq) 1062 return -EINVAL; 1063 1064 return 0; 1065 } 1066 1067 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1068 unsigned int oldstate) 1069 { 1070 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1071 } 1072 1073 static void sc16is7xx_null_void(struct uart_port *port) 1074 { 1075 /* Do nothing */ 1076 } 1077 1078 static const struct uart_ops sc16is7xx_ops = { 1079 .tx_empty = sc16is7xx_tx_empty, 1080 .set_mctrl = sc16is7xx_set_mctrl, 1081 .get_mctrl = sc16is7xx_get_mctrl, 1082 .stop_tx = sc16is7xx_stop_tx, 1083 .start_tx = sc16is7xx_start_tx, 1084 .stop_rx = sc16is7xx_stop_rx, 1085 .break_ctl = sc16is7xx_break_ctl, 1086 .startup = sc16is7xx_startup, 1087 .shutdown = sc16is7xx_shutdown, 1088 .set_termios = sc16is7xx_set_termios, 1089 .type = sc16is7xx_type, 1090 .request_port = sc16is7xx_request_port, 1091 .release_port = sc16is7xx_null_void, 1092 .config_port = sc16is7xx_config_port, 1093 .verify_port = sc16is7xx_verify_port, 1094 .pm = sc16is7xx_pm, 1095 }; 1096 1097 #ifdef CONFIG_GPIOLIB 1098 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1099 { 1100 unsigned int val; 1101 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1102 struct uart_port *port = &s->p[0].port; 1103 1104 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1105 1106 return !!(val & BIT(offset)); 1107 } 1108 1109 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1110 { 1111 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1112 struct uart_port *port = &s->p[0].port; 1113 1114 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1115 val ? BIT(offset) : 0); 1116 } 1117 1118 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1119 unsigned offset) 1120 { 1121 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1122 struct uart_port *port = &s->p[0].port; 1123 1124 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1125 1126 return 0; 1127 } 1128 1129 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1130 unsigned offset, int val) 1131 { 1132 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1133 struct uart_port *port = &s->p[0].port; 1134 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1135 1136 if (val) 1137 state |= BIT(offset); 1138 else 1139 state &= ~BIT(offset); 1140 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1141 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1142 BIT(offset)); 1143 1144 return 0; 1145 } 1146 #endif 1147 1148 static int sc16is7xx_probe(struct device *dev, 1149 const struct sc16is7xx_devtype *devtype, 1150 struct regmap *regmap, int irq, unsigned long flags) 1151 { 1152 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 }; 1153 unsigned long freq, *pfreq = dev_get_platdata(dev); 1154 int i, ret; 1155 struct sc16is7xx_port *s; 1156 1157 if (IS_ERR(regmap)) 1158 return PTR_ERR(regmap); 1159 1160 /* Alloc port structure */ 1161 s = devm_kzalloc(dev, sizeof(*s) + 1162 sizeof(struct sc16is7xx_one) * devtype->nr_uart, 1163 GFP_KERNEL); 1164 if (!s) { 1165 dev_err(dev, "Error allocating port structure\n"); 1166 return -ENOMEM; 1167 } 1168 1169 s->clk = devm_clk_get(dev, NULL); 1170 if (IS_ERR(s->clk)) { 1171 if (pfreq) 1172 freq = *pfreq; 1173 else 1174 return PTR_ERR(s->clk); 1175 } else { 1176 clk_prepare_enable(s->clk); 1177 freq = clk_get_rate(s->clk); 1178 } 1179 1180 s->regmap = regmap; 1181 s->devtype = devtype; 1182 dev_set_drvdata(dev, s); 1183 1184 kthread_init_worker(&s->kworker); 1185 kthread_init_work(&s->irq_work, sc16is7xx_ist); 1186 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1187 "sc16is7xx"); 1188 if (IS_ERR(s->kworker_task)) { 1189 ret = PTR_ERR(s->kworker_task); 1190 goto out_clk; 1191 } 1192 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param); 1193 1194 #ifdef CONFIG_GPIOLIB 1195 if (devtype->nr_gpio) { 1196 /* Setup GPIO cotroller */ 1197 s->gpio.owner = THIS_MODULE; 1198 s->gpio.parent = dev; 1199 s->gpio.label = dev_name(dev); 1200 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1201 s->gpio.get = sc16is7xx_gpio_get; 1202 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1203 s->gpio.set = sc16is7xx_gpio_set; 1204 s->gpio.base = -1; 1205 s->gpio.ngpio = devtype->nr_gpio; 1206 s->gpio.can_sleep = 1; 1207 ret = gpiochip_add_data(&s->gpio, s); 1208 if (ret) 1209 goto out_thread; 1210 } 1211 #endif 1212 1213 /* reset device, purging any pending irq / data */ 1214 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1215 SC16IS7XX_IOCONTROL_SRESET_BIT); 1216 1217 for (i = 0; i < devtype->nr_uart; ++i) { 1218 s->p[i].line = i; 1219 /* Initialize port data */ 1220 s->p[i].port.dev = dev; 1221 s->p[i].port.irq = irq; 1222 s->p[i].port.type = PORT_SC16IS7XX; 1223 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1224 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1225 s->p[i].port.iotype = UPIO_PORT; 1226 s->p[i].port.uartclk = freq; 1227 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1228 s->p[i].port.ops = &sc16is7xx_ops; 1229 s->p[i].port.line = sc16is7xx_alloc_line(); 1230 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1231 ret = -ENOMEM; 1232 goto out_ports; 1233 } 1234 1235 /* Disable all interrupts */ 1236 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1237 /* Disable TX/RX */ 1238 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1239 SC16IS7XX_EFCR_RXDISABLE_BIT | 1240 SC16IS7XX_EFCR_TXDISABLE_BIT); 1241 /* Initialize kthread work structs */ 1242 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1243 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1244 /* Register port */ 1245 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1246 1247 /* Enable EFR */ 1248 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1249 SC16IS7XX_LCR_CONF_MODE_B); 1250 1251 regcache_cache_bypass(s->regmap, true); 1252 1253 /* Enable write access to enhanced features */ 1254 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1255 SC16IS7XX_EFR_ENABLE_BIT); 1256 1257 regcache_cache_bypass(s->regmap, false); 1258 1259 /* Restore access to general registers */ 1260 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1261 1262 /* Go to suspend mode */ 1263 sc16is7xx_power(&s->p[i].port, 0); 1264 } 1265 1266 /* Setup interrupt */ 1267 ret = devm_request_irq(dev, irq, sc16is7xx_irq, 1268 flags, dev_name(dev), s); 1269 if (!ret) 1270 return 0; 1271 1272 out_ports: 1273 for (i--; i >= 0; i--) { 1274 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1275 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1276 } 1277 1278 #ifdef CONFIG_GPIOLIB 1279 if (devtype->nr_gpio) 1280 gpiochip_remove(&s->gpio); 1281 1282 out_thread: 1283 #endif 1284 kthread_stop(s->kworker_task); 1285 1286 out_clk: 1287 if (!IS_ERR(s->clk)) 1288 clk_disable_unprepare(s->clk); 1289 1290 return ret; 1291 } 1292 1293 static int sc16is7xx_remove(struct device *dev) 1294 { 1295 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1296 int i; 1297 1298 #ifdef CONFIG_GPIOLIB 1299 if (s->devtype->nr_gpio) 1300 gpiochip_remove(&s->gpio); 1301 #endif 1302 1303 for (i = 0; i < s->devtype->nr_uart; i++) { 1304 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1305 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1306 sc16is7xx_power(&s->p[i].port, 0); 1307 } 1308 1309 kthread_flush_worker(&s->kworker); 1310 kthread_stop(s->kworker_task); 1311 1312 if (!IS_ERR(s->clk)) 1313 clk_disable_unprepare(s->clk); 1314 1315 return 0; 1316 } 1317 1318 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1319 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1320 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1321 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1322 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1323 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1324 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1325 { } 1326 }; 1327 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1328 1329 static struct regmap_config regcfg = { 1330 .reg_bits = 7, 1331 .pad_bits = 1, 1332 .val_bits = 8, 1333 .cache_type = REGCACHE_RBTREE, 1334 .volatile_reg = sc16is7xx_regmap_volatile, 1335 .precious_reg = sc16is7xx_regmap_precious, 1336 }; 1337 1338 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1339 static int sc16is7xx_spi_probe(struct spi_device *spi) 1340 { 1341 const struct sc16is7xx_devtype *devtype; 1342 unsigned long flags = 0; 1343 struct regmap *regmap; 1344 int ret; 1345 1346 /* Setup SPI bus */ 1347 spi->bits_per_word = 8; 1348 /* only supports mode 0 on SC16IS762 */ 1349 spi->mode = spi->mode ? : SPI_MODE_0; 1350 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1351 ret = spi_setup(spi); 1352 if (ret) 1353 return ret; 1354 1355 if (spi->dev.of_node) { 1356 const struct of_device_id *of_id = 1357 of_match_device(sc16is7xx_dt_ids, &spi->dev); 1358 1359 if (!of_id) 1360 return -ENODEV; 1361 1362 devtype = (struct sc16is7xx_devtype *)of_id->data; 1363 } else { 1364 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1365 1366 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1367 flags = IRQF_TRIGGER_FALLING; 1368 } 1369 1370 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1371 (devtype->nr_uart - 1); 1372 regmap = devm_regmap_init_spi(spi, ®cfg); 1373 1374 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags); 1375 } 1376 1377 static int sc16is7xx_spi_remove(struct spi_device *spi) 1378 { 1379 return sc16is7xx_remove(&spi->dev); 1380 } 1381 1382 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1383 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1384 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1385 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1386 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1387 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1388 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1389 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1390 { } 1391 }; 1392 1393 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1394 1395 static struct spi_driver sc16is7xx_spi_uart_driver = { 1396 .driver = { 1397 .name = SC16IS7XX_NAME, 1398 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1399 }, 1400 .probe = sc16is7xx_spi_probe, 1401 .remove = sc16is7xx_spi_remove, 1402 .id_table = sc16is7xx_spi_id_table, 1403 }; 1404 1405 MODULE_ALIAS("spi:sc16is7xx"); 1406 #endif 1407 1408 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1409 static int sc16is7xx_i2c_probe(struct i2c_client *i2c, 1410 const struct i2c_device_id *id) 1411 { 1412 const struct sc16is7xx_devtype *devtype; 1413 unsigned long flags = 0; 1414 struct regmap *regmap; 1415 1416 if (i2c->dev.of_node) { 1417 const struct of_device_id *of_id = 1418 of_match_device(sc16is7xx_dt_ids, &i2c->dev); 1419 1420 if (!of_id) 1421 return -ENODEV; 1422 1423 devtype = (struct sc16is7xx_devtype *)of_id->data; 1424 } else { 1425 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1426 flags = IRQF_TRIGGER_FALLING; 1427 } 1428 1429 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1430 (devtype->nr_uart - 1); 1431 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1432 1433 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags); 1434 } 1435 1436 static int sc16is7xx_i2c_remove(struct i2c_client *client) 1437 { 1438 return sc16is7xx_remove(&client->dev); 1439 } 1440 1441 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1442 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1443 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1444 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1445 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1446 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1447 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1448 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1449 { } 1450 }; 1451 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1452 1453 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1454 .driver = { 1455 .name = SC16IS7XX_NAME, 1456 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1457 }, 1458 .probe = sc16is7xx_i2c_probe, 1459 .remove = sc16is7xx_i2c_remove, 1460 .id_table = sc16is7xx_i2c_id_table, 1461 }; 1462 1463 #endif 1464 1465 static int __init sc16is7xx_init(void) 1466 { 1467 int ret; 1468 1469 ret = uart_register_driver(&sc16is7xx_uart); 1470 if (ret) { 1471 pr_err("Registering UART driver failed\n"); 1472 return ret; 1473 } 1474 1475 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1476 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1477 if (ret < 0) { 1478 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1479 return ret; 1480 } 1481 #endif 1482 1483 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1484 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1485 if (ret < 0) { 1486 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1487 return ret; 1488 } 1489 #endif 1490 return ret; 1491 } 1492 module_init(sc16is7xx_init); 1493 1494 static void __exit sc16is7xx_exit(void) 1495 { 1496 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1497 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1498 #endif 1499 1500 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1501 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1502 #endif 1503 uart_unregister_driver(&sc16is7xx_uart); 1504 } 1505 module_exit(sc16is7xx_exit); 1506 1507 MODULE_LICENSE("GPL"); 1508 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1509 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1510