1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 #include <uapi/linux/sched/types.h> 28 29 #define SC16IS7XX_NAME "sc16is7xx" 30 #define SC16IS7XX_MAX_DEVS 8 31 32 /* SC16IS7XX register definitions */ 33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 46 * - only on 75x/76x 47 */ 48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 49 * - only on 75x/76x 50 */ 51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 58 59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 62 63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 66 67 /* Enhanced Register set: Only if (LCR == 0xBF) */ 68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 73 74 /* IER register bits */ 75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 77 * interrupt */ 78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 79 * interrupt */ 80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 81 * interrupt */ 82 83 /* IER register bits - write only if (EFR[4] == 1) */ 84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 88 89 /* FCR register bits */ 90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 95 96 /* FCR register bits - write only if (EFR[4] == 1) */ 97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 99 100 /* IIR register bits */ 101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 108 * - only on 75x/76x 109 */ 110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 111 * - only on 75x/76x 112 */ 113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 115 * from active (LOW) 116 * to inactive (HIGH) 117 */ 118 /* LCR register bits */ 119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 121 * 122 * Word length bits table: 123 * 00 -> 5 bit words 124 * 01 -> 6 bit words 125 * 10 -> 7 bit words 126 * 11 -> 8 bit words 127 */ 128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 129 * 130 * STOP length bit table: 131 * 0 -> 1 stop bit 132 * 1 -> 1-1.5 stop bits if 133 * word length is 5, 134 * 2 stop bits otherwise 135 */ 136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 146 * reg set */ 147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 148 * reg set */ 149 150 /* MCR register bits */ 151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 152 * - only on 75x/76x 153 */ 154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 158 * - write enabled 159 * if (EFR[4] == 1) 160 */ 161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 162 * - write enabled 163 * if (EFR[4] == 1) 164 */ 165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 166 * - write enabled 167 * if (EFR[4] == 1) 168 */ 169 170 /* LSR register bits */ 171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 180 181 /* MSR register bits */ 182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 184 * or (IO4) 185 * - only on 75x/76x 186 */ 187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 188 * or (IO7) 189 * - only on 75x/76x 190 */ 191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 192 * or (IO6) 193 * - only on 75x/76x 194 */ 195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 197 * - only on 75x/76x 198 */ 199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 200 * - only on 75x/76x 201 */ 202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 206 207 /* 208 * TCR register bits 209 * TCR trigger levels are available from 0 to 60 characters with a granularity 210 * of four. 211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 212 * no built-in hardware check to make sure this condition is met. Also, the TCR 213 * must be programmed with this condition before auto RTS or software flow 214 * control is enabled to avoid spurious operation of the device. 215 */ 216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 218 219 /* 220 * TLR register bits 221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 223 * trigger levels. Trigger levels from 4 characters to 60 characters are 224 * available with a granularity of four. 225 * 226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 228 * the trigger level defined in FCR is discarded. This applies to both transmit 229 * FIFO and receive FIFO trigger level setting. 230 * 231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 232 * default state, that is, '00'. 233 */ 234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 236 237 /* IOControl register bits (Only 750/760) */ 238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 239 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */ 240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 241 242 /* EFCR register bits */ 243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 244 * mode (RS485) */ 245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 250 * 0 = rate upto 115.2 kbit/s 251 * - Only 750/760 252 * 1 = rate upto 1.152 Mbit/s 253 * - Only 760 254 */ 255 256 /* EFR register bits */ 257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 261 * and writing to IER[7:4], 262 * FCR[5:4], MCR[7:5] 263 */ 264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 266 * 267 * SWFLOW bits 3 & 2 table: 268 * 00 -> no transmitter flow 269 * control 270 * 01 -> transmitter generates 271 * XON2 and XOFF2 272 * 10 -> transmitter generates 273 * XON1 and XOFF1 274 * 11 -> transmitter generates 275 * XON1, XON2, XOFF1 and 276 * XOFF2 277 */ 278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 280 * 281 * SWFLOW bits 3 & 2 table: 282 * 00 -> no received flow 283 * control 284 * 01 -> receiver compares 285 * XON2 and XOFF2 286 * 10 -> receiver compares 287 * XON1 and XOFF1 288 * 11 -> receiver compares 289 * XON1, XON2, XOFF1 and 290 * XOFF2 291 */ 292 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 293 SC16IS7XX_EFR_AUTOCTS_BIT | \ 294 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 295 SC16IS7XX_EFR_SWFLOW3_BIT | \ 296 SC16IS7XX_EFR_SWFLOW2_BIT | \ 297 SC16IS7XX_EFR_SWFLOW1_BIT | \ 298 SC16IS7XX_EFR_SWFLOW0_BIT) 299 300 301 /* Misc definitions */ 302 #define SC16IS7XX_FIFO_SIZE (64) 303 #define SC16IS7XX_REG_SHIFT 2 304 305 struct sc16is7xx_devtype { 306 char name[10]; 307 int nr_gpio; 308 int nr_uart; 309 int has_mctrl; 310 }; 311 312 #define SC16IS7XX_RECONF_MD (1 << 0) 313 #define SC16IS7XX_RECONF_IER (1 << 1) 314 #define SC16IS7XX_RECONF_RS485 (1 << 2) 315 316 struct sc16is7xx_one_config { 317 unsigned int flags; 318 u8 ier_mask; 319 u8 ier_val; 320 }; 321 322 struct sc16is7xx_one { 323 struct uart_port port; 324 u8 line; 325 struct kthread_work tx_work; 326 struct kthread_work reg_work; 327 struct kthread_delayed_work ms_work; 328 struct sc16is7xx_one_config config; 329 bool irda_mode; 330 unsigned int old_mctrl; 331 }; 332 333 struct sc16is7xx_port { 334 const struct sc16is7xx_devtype *devtype; 335 struct regmap *regmap; 336 struct clk *clk; 337 #ifdef CONFIG_GPIOLIB 338 struct gpio_chip gpio; 339 #endif 340 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 341 struct kthread_worker kworker; 342 struct task_struct *kworker_task; 343 struct mutex efr_lock; 344 struct sc16is7xx_one p[]; 345 }; 346 347 static unsigned long sc16is7xx_lines; 348 349 static struct uart_driver sc16is7xx_uart = { 350 .owner = THIS_MODULE, 351 .dev_name = "ttySC", 352 .nr = SC16IS7XX_MAX_DEVS, 353 }; 354 355 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 356 static void sc16is7xx_stop_tx(struct uart_port *port); 357 358 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 359 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 360 361 static int sc16is7xx_line(struct uart_port *port) 362 { 363 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 364 365 return one->line; 366 } 367 368 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 369 { 370 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 371 unsigned int val = 0; 372 const u8 line = sc16is7xx_line(port); 373 374 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 375 376 return val; 377 } 378 379 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 380 { 381 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 382 const u8 line = sc16is7xx_line(port); 383 384 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 385 } 386 387 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 388 { 389 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 390 const u8 line = sc16is7xx_line(port); 391 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 392 393 regcache_cache_bypass(s->regmap, true); 394 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 395 regcache_cache_bypass(s->regmap, false); 396 } 397 398 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 399 { 400 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 401 const u8 line = sc16is7xx_line(port); 402 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 403 404 /* 405 * Don't send zero-length data, at least on SPI it confuses the chip 406 * delivering wrong TXLVL data. 407 */ 408 if (unlikely(!to_send)) 409 return; 410 411 regcache_cache_bypass(s->regmap, true); 412 regmap_raw_write(s->regmap, addr, s->buf, to_send); 413 regcache_cache_bypass(s->regmap, false); 414 } 415 416 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 417 u8 mask, u8 val) 418 { 419 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 420 const u8 line = sc16is7xx_line(port); 421 422 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 423 mask, val); 424 } 425 426 static int sc16is7xx_alloc_line(void) 427 { 428 int i; 429 430 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 431 432 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 433 if (!test_and_set_bit(i, &sc16is7xx_lines)) 434 break; 435 436 return i; 437 } 438 439 static void sc16is7xx_power(struct uart_port *port, int on) 440 { 441 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 442 SC16IS7XX_IER_SLEEP_BIT, 443 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 444 } 445 446 static const struct sc16is7xx_devtype sc16is74x_devtype = { 447 .name = "SC16IS74X", 448 .nr_gpio = 0, 449 .nr_uart = 1, 450 .has_mctrl = 0, 451 }; 452 453 static const struct sc16is7xx_devtype sc16is750_devtype = { 454 .name = "SC16IS750", 455 .nr_gpio = 4, 456 .nr_uart = 1, 457 .has_mctrl = 1, 458 }; 459 460 static const struct sc16is7xx_devtype sc16is752_devtype = { 461 .name = "SC16IS752", 462 .nr_gpio = 0, 463 .nr_uart = 2, 464 .has_mctrl = 1, 465 }; 466 467 static const struct sc16is7xx_devtype sc16is760_devtype = { 468 .name = "SC16IS760", 469 .nr_gpio = 4, 470 .nr_uart = 1, 471 .has_mctrl = 1, 472 }; 473 474 static const struct sc16is7xx_devtype sc16is762_devtype = { 475 .name = "SC16IS762", 476 .nr_gpio = 0, 477 .nr_uart = 2, 478 .has_mctrl = 1, 479 }; 480 481 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 482 { 483 switch (reg >> SC16IS7XX_REG_SHIFT) { 484 case SC16IS7XX_RHR_REG: 485 case SC16IS7XX_IIR_REG: 486 case SC16IS7XX_LSR_REG: 487 case SC16IS7XX_MSR_REG: 488 case SC16IS7XX_TXLVL_REG: 489 case SC16IS7XX_RXLVL_REG: 490 case SC16IS7XX_IOSTATE_REG: 491 return true; 492 default: 493 break; 494 } 495 496 return false; 497 } 498 499 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 500 { 501 switch (reg >> SC16IS7XX_REG_SHIFT) { 502 case SC16IS7XX_RHR_REG: 503 return true; 504 default: 505 break; 506 } 507 508 return false; 509 } 510 511 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 512 { 513 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 514 u8 lcr; 515 u8 prescaler = 0; 516 unsigned long clk = port->uartclk, div = clk / 16 / baud; 517 518 if (div > 0xffff) { 519 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 520 div /= 4; 521 } 522 523 /* In an amazing feat of design, the Enhanced Features Register shares 524 * the address of the Interrupt Identification Register, and is 525 * switched in by writing a magic value (0xbf) to the Line Control 526 * Register. Any interrupt firing during this time will see the EFR 527 * where it expects the IIR to be, leading to "Unexpected interrupt" 528 * messages. 529 * 530 * Prevent this possibility by claiming a mutex while accessing the 531 * EFR, and claiming the same mutex from within the interrupt handler. 532 * This is similar to disabling the interrupt, but that doesn't work 533 * because the bulk of the interrupt processing is run as a workqueue 534 * job in thread context. 535 */ 536 mutex_lock(&s->efr_lock); 537 538 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 539 540 /* Open the LCR divisors for configuration */ 541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 542 SC16IS7XX_LCR_CONF_MODE_B); 543 544 /* Enable enhanced features */ 545 regcache_cache_bypass(s->regmap, true); 546 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 547 SC16IS7XX_EFR_ENABLE_BIT, 548 SC16IS7XX_EFR_ENABLE_BIT); 549 550 regcache_cache_bypass(s->regmap, false); 551 552 /* Put LCR back to the normal mode */ 553 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 554 555 mutex_unlock(&s->efr_lock); 556 557 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 558 SC16IS7XX_MCR_CLKSEL_BIT, 559 prescaler); 560 561 /* Open the LCR divisors for configuration */ 562 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 563 SC16IS7XX_LCR_CONF_MODE_A); 564 565 /* Write the new divisor */ 566 regcache_cache_bypass(s->regmap, true); 567 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 568 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 569 regcache_cache_bypass(s->regmap, false); 570 571 /* Put LCR back to the normal mode */ 572 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 573 574 return DIV_ROUND_CLOSEST(clk / 16, div); 575 } 576 577 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 578 unsigned int iir) 579 { 580 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 581 unsigned int lsr = 0, ch, flag, bytes_read, i; 582 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 583 584 if (unlikely(rxlen >= sizeof(s->buf))) { 585 dev_warn_ratelimited(port->dev, 586 "ttySC%i: Possible RX FIFO overrun: %d\n", 587 port->line, rxlen); 588 port->icount.buf_overrun++; 589 /* Ensure sanity of RX level */ 590 rxlen = sizeof(s->buf); 591 } 592 593 while (rxlen) { 594 /* Only read lsr if there are possible errors in FIFO */ 595 if (read_lsr) { 596 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 597 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 598 read_lsr = false; /* No errors left in FIFO */ 599 } else 600 lsr = 0; 601 602 if (read_lsr) { 603 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 604 bytes_read = 1; 605 } else { 606 sc16is7xx_fifo_read(port, rxlen); 607 bytes_read = rxlen; 608 } 609 610 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 611 612 port->icount.rx++; 613 flag = TTY_NORMAL; 614 615 if (unlikely(lsr)) { 616 if (lsr & SC16IS7XX_LSR_BI_BIT) { 617 port->icount.brk++; 618 if (uart_handle_break(port)) 619 continue; 620 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 621 port->icount.parity++; 622 else if (lsr & SC16IS7XX_LSR_FE_BIT) 623 port->icount.frame++; 624 else if (lsr & SC16IS7XX_LSR_OE_BIT) 625 port->icount.overrun++; 626 627 lsr &= port->read_status_mask; 628 if (lsr & SC16IS7XX_LSR_BI_BIT) 629 flag = TTY_BREAK; 630 else if (lsr & SC16IS7XX_LSR_PE_BIT) 631 flag = TTY_PARITY; 632 else if (lsr & SC16IS7XX_LSR_FE_BIT) 633 flag = TTY_FRAME; 634 else if (lsr & SC16IS7XX_LSR_OE_BIT) 635 flag = TTY_OVERRUN; 636 } 637 638 for (i = 0; i < bytes_read; ++i) { 639 ch = s->buf[i]; 640 if (uart_handle_sysrq_char(port, ch)) 641 continue; 642 643 if (lsr & port->ignore_status_mask) 644 continue; 645 646 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 647 flag); 648 } 649 rxlen -= bytes_read; 650 } 651 652 tty_flip_buffer_push(&port->state->port); 653 } 654 655 static void sc16is7xx_handle_tx(struct uart_port *port) 656 { 657 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 658 struct circ_buf *xmit = &port->state->xmit; 659 unsigned int txlen, to_send, i; 660 unsigned long flags; 661 662 if (unlikely(port->x_char)) { 663 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 664 port->icount.tx++; 665 port->x_char = 0; 666 return; 667 } 668 669 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 670 spin_lock_irqsave(&port->lock, flags); 671 sc16is7xx_stop_tx(port); 672 spin_unlock_irqrestore(&port->lock, flags); 673 return; 674 } 675 676 /* Get length of data pending in circular buffer */ 677 to_send = uart_circ_chars_pending(xmit); 678 if (likely(to_send)) { 679 /* Limit to size of TX FIFO */ 680 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 681 if (txlen > SC16IS7XX_FIFO_SIZE) { 682 dev_err_ratelimited(port->dev, 683 "chip reports %d free bytes in TX fifo, but it only has %d", 684 txlen, SC16IS7XX_FIFO_SIZE); 685 txlen = 0; 686 } 687 to_send = (to_send > txlen) ? txlen : to_send; 688 689 /* Convert to linear buffer */ 690 for (i = 0; i < to_send; ++i) { 691 s->buf[i] = xmit->buf[xmit->tail]; 692 uart_xmit_advance(port, 1); 693 } 694 695 sc16is7xx_fifo_write(port, to_send); 696 } 697 698 spin_lock_irqsave(&port->lock, flags); 699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 700 uart_write_wakeup(port); 701 702 if (uart_circ_empty(xmit)) 703 sc16is7xx_stop_tx(port); 704 spin_unlock_irqrestore(&port->lock, flags); 705 } 706 707 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 708 { 709 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 710 unsigned int mctrl = 0; 711 712 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 713 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 714 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 715 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 716 return mctrl; 717 } 718 719 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 720 { 721 struct uart_port *port = &one->port; 722 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 723 unsigned long flags; 724 unsigned int status, changed; 725 726 lockdep_assert_held_once(&s->efr_lock); 727 728 status = sc16is7xx_get_hwmctrl(port); 729 changed = status ^ one->old_mctrl; 730 731 if (changed == 0) 732 return; 733 734 one->old_mctrl = status; 735 736 spin_lock_irqsave(&port->lock, flags); 737 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 738 port->icount.rng++; 739 if (changed & TIOCM_DSR) 740 port->icount.dsr++; 741 if (changed & TIOCM_CAR) 742 uart_handle_dcd_change(port, status & TIOCM_CAR); 743 if (changed & TIOCM_CTS) 744 uart_handle_cts_change(port, status & TIOCM_CTS); 745 746 wake_up_interruptible(&port->state->port.delta_msr_wait); 747 spin_unlock_irqrestore(&port->lock, flags); 748 } 749 750 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 751 { 752 struct uart_port *port = &s->p[portno].port; 753 754 do { 755 unsigned int iir, rxlen; 756 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 757 758 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 759 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 760 return false; 761 762 iir &= SC16IS7XX_IIR_ID_MASK; 763 764 switch (iir) { 765 case SC16IS7XX_IIR_RDI_SRC: 766 case SC16IS7XX_IIR_RLSE_SRC: 767 case SC16IS7XX_IIR_RTOI_SRC: 768 case SC16IS7XX_IIR_XOFFI_SRC: 769 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 770 if (rxlen) 771 sc16is7xx_handle_rx(port, rxlen, iir); 772 break; 773 /* CTSRTS interrupt comes only when CTS goes inactive */ 774 case SC16IS7XX_IIR_CTSRTS_SRC: 775 case SC16IS7XX_IIR_MSI_SRC: 776 sc16is7xx_update_mlines(one); 777 break; 778 case SC16IS7XX_IIR_THRI_SRC: 779 sc16is7xx_handle_tx(port); 780 break; 781 default: 782 dev_err_ratelimited(port->dev, 783 "ttySC%i: Unexpected interrupt: %x", 784 port->line, iir); 785 break; 786 } 787 } while (0); 788 return true; 789 } 790 791 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 792 { 793 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 794 795 mutex_lock(&s->efr_lock); 796 797 while (1) { 798 bool keep_polling = false; 799 int i; 800 801 for (i = 0; i < s->devtype->nr_uart; ++i) 802 keep_polling |= sc16is7xx_port_irq(s, i); 803 if (!keep_polling) 804 break; 805 } 806 807 mutex_unlock(&s->efr_lock); 808 809 return IRQ_HANDLED; 810 } 811 812 static void sc16is7xx_tx_proc(struct kthread_work *ws) 813 { 814 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 815 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 816 unsigned long flags; 817 818 if ((port->rs485.flags & SER_RS485_ENABLED) && 819 (port->rs485.delay_rts_before_send > 0)) 820 msleep(port->rs485.delay_rts_before_send); 821 822 mutex_lock(&s->efr_lock); 823 sc16is7xx_handle_tx(port); 824 mutex_unlock(&s->efr_lock); 825 826 spin_lock_irqsave(&port->lock, flags); 827 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 828 spin_unlock_irqrestore(&port->lock, flags); 829 } 830 831 static void sc16is7xx_reconf_rs485(struct uart_port *port) 832 { 833 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 834 SC16IS7XX_EFCR_RTS_INVERT_BIT; 835 u32 efcr = 0; 836 struct serial_rs485 *rs485 = &port->rs485; 837 unsigned long irqflags; 838 839 spin_lock_irqsave(&port->lock, irqflags); 840 if (rs485->flags & SER_RS485_ENABLED) { 841 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 842 843 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 844 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 845 } 846 spin_unlock_irqrestore(&port->lock, irqflags); 847 848 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 849 } 850 851 static void sc16is7xx_reg_proc(struct kthread_work *ws) 852 { 853 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 854 struct sc16is7xx_one_config config; 855 unsigned long irqflags; 856 857 spin_lock_irqsave(&one->port.lock, irqflags); 858 config = one->config; 859 memset(&one->config, 0, sizeof(one->config)); 860 spin_unlock_irqrestore(&one->port.lock, irqflags); 861 862 if (config.flags & SC16IS7XX_RECONF_MD) { 863 u8 mcr = 0; 864 865 /* Device ignores RTS setting when hardware flow is enabled */ 866 if (one->port.mctrl & TIOCM_RTS) 867 mcr |= SC16IS7XX_MCR_RTS_BIT; 868 869 if (one->port.mctrl & TIOCM_DTR) 870 mcr |= SC16IS7XX_MCR_DTR_BIT; 871 872 if (one->port.mctrl & TIOCM_LOOP) 873 mcr |= SC16IS7XX_MCR_LOOP_BIT; 874 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 875 SC16IS7XX_MCR_RTS_BIT | 876 SC16IS7XX_MCR_DTR_BIT | 877 SC16IS7XX_MCR_LOOP_BIT, 878 mcr); 879 } 880 881 if (config.flags & SC16IS7XX_RECONF_IER) 882 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 883 config.ier_mask, config.ier_val); 884 885 if (config.flags & SC16IS7XX_RECONF_RS485) 886 sc16is7xx_reconf_rs485(&one->port); 887 } 888 889 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 890 { 891 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 892 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 893 894 lockdep_assert_held_once(&port->lock); 895 896 one->config.flags |= SC16IS7XX_RECONF_IER; 897 one->config.ier_mask |= bit; 898 one->config.ier_val &= ~bit; 899 kthread_queue_work(&s->kworker, &one->reg_work); 900 } 901 902 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 903 { 904 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 905 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 906 907 lockdep_assert_held_once(&port->lock); 908 909 one->config.flags |= SC16IS7XX_RECONF_IER; 910 one->config.ier_mask |= bit; 911 one->config.ier_val |= bit; 912 kthread_queue_work(&s->kworker, &one->reg_work); 913 } 914 915 static void sc16is7xx_stop_tx(struct uart_port *port) 916 { 917 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 918 } 919 920 static void sc16is7xx_stop_rx(struct uart_port *port) 921 { 922 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 923 } 924 925 static void sc16is7xx_ms_proc(struct kthread_work *ws) 926 { 927 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 928 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 929 930 if (one->port.state) { 931 mutex_lock(&s->efr_lock); 932 sc16is7xx_update_mlines(one); 933 mutex_unlock(&s->efr_lock); 934 935 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 936 } 937 } 938 939 static void sc16is7xx_enable_ms(struct uart_port *port) 940 { 941 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 942 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 943 944 lockdep_assert_held_once(&port->lock); 945 946 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 947 } 948 949 static void sc16is7xx_start_tx(struct uart_port *port) 950 { 951 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 952 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 953 954 kthread_queue_work(&s->kworker, &one->tx_work); 955 } 956 957 static void sc16is7xx_throttle(struct uart_port *port) 958 { 959 unsigned long flags; 960 961 /* 962 * Hardware flow control is enabled and thus the device ignores RTS 963 * value set in MCR register. Stop reading data from RX FIFO so the 964 * AutoRTS feature will de-activate RTS output. 965 */ 966 spin_lock_irqsave(&port->lock, flags); 967 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 968 spin_unlock_irqrestore(&port->lock, flags); 969 } 970 971 static void sc16is7xx_unthrottle(struct uart_port *port) 972 { 973 unsigned long flags; 974 975 spin_lock_irqsave(&port->lock, flags); 976 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 977 spin_unlock_irqrestore(&port->lock, flags); 978 } 979 980 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 981 { 982 unsigned int lsr; 983 984 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 985 986 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 987 } 988 989 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 990 { 991 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 992 993 /* Called with port lock taken so we can only return cached value */ 994 return one->old_mctrl; 995 } 996 997 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 998 { 999 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1000 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1001 1002 one->config.flags |= SC16IS7XX_RECONF_MD; 1003 kthread_queue_work(&s->kworker, &one->reg_work); 1004 } 1005 1006 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1007 { 1008 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1009 SC16IS7XX_LCR_TXBREAK_BIT, 1010 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1011 } 1012 1013 static void sc16is7xx_set_termios(struct uart_port *port, 1014 struct ktermios *termios, 1015 const struct ktermios *old) 1016 { 1017 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1018 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1019 unsigned int lcr, flow = 0; 1020 int baud; 1021 unsigned long flags; 1022 1023 kthread_cancel_delayed_work_sync(&one->ms_work); 1024 1025 /* Mask termios capabilities we don't support */ 1026 termios->c_cflag &= ~CMSPAR; 1027 1028 /* Word size */ 1029 switch (termios->c_cflag & CSIZE) { 1030 case CS5: 1031 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1032 break; 1033 case CS6: 1034 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1035 break; 1036 case CS7: 1037 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1038 break; 1039 case CS8: 1040 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1041 break; 1042 default: 1043 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1044 termios->c_cflag &= ~CSIZE; 1045 termios->c_cflag |= CS8; 1046 break; 1047 } 1048 1049 /* Parity */ 1050 if (termios->c_cflag & PARENB) { 1051 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1052 if (!(termios->c_cflag & PARODD)) 1053 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1054 } 1055 1056 /* Stop bits */ 1057 if (termios->c_cflag & CSTOPB) 1058 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1059 1060 /* Set read status mask */ 1061 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1062 if (termios->c_iflag & INPCK) 1063 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1064 SC16IS7XX_LSR_FE_BIT; 1065 if (termios->c_iflag & (BRKINT | PARMRK)) 1066 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1067 1068 /* Set status ignore mask */ 1069 port->ignore_status_mask = 0; 1070 if (termios->c_iflag & IGNBRK) 1071 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1072 if (!(termios->c_cflag & CREAD)) 1073 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1074 1075 /* As above, claim the mutex while accessing the EFR. */ 1076 mutex_lock(&s->efr_lock); 1077 1078 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1079 SC16IS7XX_LCR_CONF_MODE_B); 1080 1081 /* Configure flow control */ 1082 regcache_cache_bypass(s->regmap, true); 1083 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1084 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1085 1086 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1087 if (termios->c_cflag & CRTSCTS) { 1088 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1089 SC16IS7XX_EFR_AUTORTS_BIT; 1090 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1091 } 1092 if (termios->c_iflag & IXON) 1093 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1094 if (termios->c_iflag & IXOFF) 1095 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1096 1097 sc16is7xx_port_update(port, 1098 SC16IS7XX_EFR_REG, 1099 SC16IS7XX_EFR_FLOWCTRL_BITS, 1100 flow); 1101 regcache_cache_bypass(s->regmap, false); 1102 1103 /* Update LCR register */ 1104 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1105 1106 mutex_unlock(&s->efr_lock); 1107 1108 /* Get baud rate generator configuration */ 1109 baud = uart_get_baud_rate(port, termios, old, 1110 port->uartclk / 16 / 4 / 0xffff, 1111 port->uartclk / 16); 1112 1113 /* Setup baudrate generator */ 1114 baud = sc16is7xx_set_baud(port, baud); 1115 1116 spin_lock_irqsave(&port->lock, flags); 1117 1118 /* Update timeout according to new baud rate */ 1119 uart_update_timeout(port, termios->c_cflag, baud); 1120 1121 if (UART_ENABLE_MS(port, termios->c_cflag)) 1122 sc16is7xx_enable_ms(port); 1123 1124 spin_unlock_irqrestore(&port->lock, flags); 1125 } 1126 1127 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1128 struct serial_rs485 *rs485) 1129 { 1130 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1131 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1132 1133 if (rs485->flags & SER_RS485_ENABLED) { 1134 /* 1135 * RTS signal is handled by HW, it's timing can't be influenced. 1136 * However, it's sometimes useful to delay TX even without RTS 1137 * control therefore we try to handle .delay_rts_before_send. 1138 */ 1139 if (rs485->delay_rts_after_send) 1140 return -EINVAL; 1141 } 1142 1143 one->config.flags |= SC16IS7XX_RECONF_RS485; 1144 kthread_queue_work(&s->kworker, &one->reg_work); 1145 1146 return 0; 1147 } 1148 1149 static int sc16is7xx_startup(struct uart_port *port) 1150 { 1151 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1152 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1153 unsigned int val; 1154 unsigned long flags; 1155 1156 sc16is7xx_power(port, 1); 1157 1158 /* Reset FIFOs*/ 1159 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1160 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1161 udelay(5); 1162 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1163 SC16IS7XX_FCR_FIFO_BIT); 1164 1165 /* Enable EFR */ 1166 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1167 SC16IS7XX_LCR_CONF_MODE_B); 1168 1169 regcache_cache_bypass(s->regmap, true); 1170 1171 /* Enable write access to enhanced features and internal clock div */ 1172 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1173 SC16IS7XX_EFR_ENABLE_BIT, 1174 SC16IS7XX_EFR_ENABLE_BIT); 1175 1176 /* Enable TCR/TLR */ 1177 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1178 SC16IS7XX_MCR_TCRTLR_BIT, 1179 SC16IS7XX_MCR_TCRTLR_BIT); 1180 1181 /* Configure flow control levels */ 1182 /* Flow control halt level 48, resume level 24 */ 1183 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1184 SC16IS7XX_TCR_RX_RESUME(24) | 1185 SC16IS7XX_TCR_RX_HALT(48)); 1186 1187 regcache_cache_bypass(s->regmap, false); 1188 1189 /* Now, initialize the UART */ 1190 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1191 1192 /* Enable IrDA mode if requested in DT */ 1193 /* This bit must be written with LCR[7] = 0 */ 1194 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1195 SC16IS7XX_MCR_IRDA_BIT, 1196 one->irda_mode ? 1197 SC16IS7XX_MCR_IRDA_BIT : 0); 1198 1199 /* Enable the Rx and Tx FIFO */ 1200 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1201 SC16IS7XX_EFCR_RXDISABLE_BIT | 1202 SC16IS7XX_EFCR_TXDISABLE_BIT, 1203 0); 1204 1205 /* Enable RX, CTS change and modem lines interrupts */ 1206 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1207 SC16IS7XX_IER_MSI_BIT; 1208 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1209 1210 /* Enable modem status polling */ 1211 spin_lock_irqsave(&port->lock, flags); 1212 sc16is7xx_enable_ms(port); 1213 spin_unlock_irqrestore(&port->lock, flags); 1214 1215 return 0; 1216 } 1217 1218 static void sc16is7xx_shutdown(struct uart_port *port) 1219 { 1220 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1221 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1222 1223 kthread_cancel_delayed_work_sync(&one->ms_work); 1224 1225 /* Disable all interrupts */ 1226 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1227 /* Disable TX/RX */ 1228 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1229 SC16IS7XX_EFCR_RXDISABLE_BIT | 1230 SC16IS7XX_EFCR_TXDISABLE_BIT, 1231 SC16IS7XX_EFCR_RXDISABLE_BIT | 1232 SC16IS7XX_EFCR_TXDISABLE_BIT); 1233 1234 sc16is7xx_power(port, 0); 1235 1236 kthread_flush_worker(&s->kworker); 1237 } 1238 1239 static const char *sc16is7xx_type(struct uart_port *port) 1240 { 1241 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1242 1243 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1244 } 1245 1246 static int sc16is7xx_request_port(struct uart_port *port) 1247 { 1248 /* Do nothing */ 1249 return 0; 1250 } 1251 1252 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1253 { 1254 if (flags & UART_CONFIG_TYPE) 1255 port->type = PORT_SC16IS7XX; 1256 } 1257 1258 static int sc16is7xx_verify_port(struct uart_port *port, 1259 struct serial_struct *s) 1260 { 1261 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1262 return -EINVAL; 1263 if (s->irq != port->irq) 1264 return -EINVAL; 1265 1266 return 0; 1267 } 1268 1269 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1270 unsigned int oldstate) 1271 { 1272 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1273 } 1274 1275 static void sc16is7xx_null_void(struct uart_port *port) 1276 { 1277 /* Do nothing */ 1278 } 1279 1280 static const struct uart_ops sc16is7xx_ops = { 1281 .tx_empty = sc16is7xx_tx_empty, 1282 .set_mctrl = sc16is7xx_set_mctrl, 1283 .get_mctrl = sc16is7xx_get_mctrl, 1284 .stop_tx = sc16is7xx_stop_tx, 1285 .start_tx = sc16is7xx_start_tx, 1286 .throttle = sc16is7xx_throttle, 1287 .unthrottle = sc16is7xx_unthrottle, 1288 .stop_rx = sc16is7xx_stop_rx, 1289 .enable_ms = sc16is7xx_enable_ms, 1290 .break_ctl = sc16is7xx_break_ctl, 1291 .startup = sc16is7xx_startup, 1292 .shutdown = sc16is7xx_shutdown, 1293 .set_termios = sc16is7xx_set_termios, 1294 .type = sc16is7xx_type, 1295 .request_port = sc16is7xx_request_port, 1296 .release_port = sc16is7xx_null_void, 1297 .config_port = sc16is7xx_config_port, 1298 .verify_port = sc16is7xx_verify_port, 1299 .pm = sc16is7xx_pm, 1300 }; 1301 1302 #ifdef CONFIG_GPIOLIB 1303 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1304 { 1305 unsigned int val; 1306 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1307 struct uart_port *port = &s->p[0].port; 1308 1309 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1310 1311 return !!(val & BIT(offset)); 1312 } 1313 1314 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1315 { 1316 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1317 struct uart_port *port = &s->p[0].port; 1318 1319 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1320 val ? BIT(offset) : 0); 1321 } 1322 1323 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1324 unsigned offset) 1325 { 1326 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1327 struct uart_port *port = &s->p[0].port; 1328 1329 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1330 1331 return 0; 1332 } 1333 1334 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1335 unsigned offset, int val) 1336 { 1337 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1338 struct uart_port *port = &s->p[0].port; 1339 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1340 1341 if (val) 1342 state |= BIT(offset); 1343 else 1344 state &= ~BIT(offset); 1345 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1346 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1347 BIT(offset)); 1348 1349 return 0; 1350 } 1351 #endif 1352 1353 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1354 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1355 .delay_rts_before_send = 1, 1356 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1357 }; 1358 1359 static int sc16is7xx_probe(struct device *dev, 1360 const struct sc16is7xx_devtype *devtype, 1361 struct regmap *regmap, int irq) 1362 { 1363 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1364 unsigned int val; 1365 u32 uartclk = 0; 1366 int i, ret; 1367 struct sc16is7xx_port *s; 1368 1369 if (IS_ERR(regmap)) 1370 return PTR_ERR(regmap); 1371 1372 /* 1373 * This device does not have an identification register that would 1374 * tell us if we are really connected to the correct device. 1375 * The best we can do is to check if communication is at all possible. 1376 */ 1377 ret = regmap_read(regmap, 1378 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val); 1379 if (ret < 0) 1380 return -EPROBE_DEFER; 1381 1382 /* Alloc port structure */ 1383 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1384 if (!s) { 1385 dev_err(dev, "Error allocating port structure\n"); 1386 return -ENOMEM; 1387 } 1388 1389 /* Always ask for fixed clock rate from a property. */ 1390 device_property_read_u32(dev, "clock-frequency", &uartclk); 1391 1392 s->clk = devm_clk_get_optional(dev, NULL); 1393 if (IS_ERR(s->clk)) 1394 return PTR_ERR(s->clk); 1395 1396 ret = clk_prepare_enable(s->clk); 1397 if (ret) 1398 return ret; 1399 1400 freq = clk_get_rate(s->clk); 1401 if (freq == 0) { 1402 if (uartclk) 1403 freq = uartclk; 1404 if (pfreq) 1405 freq = *pfreq; 1406 if (freq) 1407 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1408 else 1409 return -EINVAL; 1410 } 1411 1412 s->regmap = regmap; 1413 s->devtype = devtype; 1414 dev_set_drvdata(dev, s); 1415 mutex_init(&s->efr_lock); 1416 1417 kthread_init_worker(&s->kworker); 1418 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1419 "sc16is7xx"); 1420 if (IS_ERR(s->kworker_task)) { 1421 ret = PTR_ERR(s->kworker_task); 1422 goto out_clk; 1423 } 1424 sched_set_fifo(s->kworker_task); 1425 1426 /* reset device, purging any pending irq / data */ 1427 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1428 SC16IS7XX_IOCONTROL_SRESET_BIT); 1429 1430 for (i = 0; i < devtype->nr_uart; ++i) { 1431 s->p[i].line = i; 1432 /* Initialize port data */ 1433 s->p[i].port.dev = dev; 1434 s->p[i].port.irq = irq; 1435 s->p[i].port.type = PORT_SC16IS7XX; 1436 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1437 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1438 s->p[i].port.iobase = i; 1439 s->p[i].port.iotype = UPIO_PORT; 1440 s->p[i].port.uartclk = freq; 1441 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1442 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1443 s->p[i].port.ops = &sc16is7xx_ops; 1444 s->p[i].old_mctrl = 0; 1445 s->p[i].port.line = sc16is7xx_alloc_line(); 1446 1447 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1448 ret = -ENOMEM; 1449 goto out_ports; 1450 } 1451 1452 /* Disable all interrupts */ 1453 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1454 /* Disable TX/RX */ 1455 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1456 SC16IS7XX_EFCR_RXDISABLE_BIT | 1457 SC16IS7XX_EFCR_TXDISABLE_BIT); 1458 1459 /* Use GPIO lines as modem status registers */ 1460 if (devtype->has_mctrl) 1461 sc16is7xx_port_write(&s->p[i].port, 1462 SC16IS7XX_IOCONTROL_REG, 1463 SC16IS7XX_IOCONTROL_MODEM_BIT); 1464 1465 /* Initialize kthread work structs */ 1466 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1467 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1468 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1469 /* Register port */ 1470 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1471 1472 /* Enable EFR */ 1473 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1474 SC16IS7XX_LCR_CONF_MODE_B); 1475 1476 regcache_cache_bypass(s->regmap, true); 1477 1478 /* Enable write access to enhanced features */ 1479 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1480 SC16IS7XX_EFR_ENABLE_BIT); 1481 1482 regcache_cache_bypass(s->regmap, false); 1483 1484 /* Restore access to general registers */ 1485 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1486 1487 /* Go to suspend mode */ 1488 sc16is7xx_power(&s->p[i].port, 0); 1489 } 1490 1491 if (dev->of_node) { 1492 struct property *prop; 1493 const __be32 *p; 1494 u32 u; 1495 1496 of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1497 prop, p, u) 1498 if (u < devtype->nr_uart) 1499 s->p[u].irda_mode = true; 1500 } 1501 1502 #ifdef CONFIG_GPIOLIB 1503 if (devtype->nr_gpio) { 1504 /* Setup GPIO cotroller */ 1505 s->gpio.owner = THIS_MODULE; 1506 s->gpio.parent = dev; 1507 s->gpio.label = dev_name(dev); 1508 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1509 s->gpio.get = sc16is7xx_gpio_get; 1510 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1511 s->gpio.set = sc16is7xx_gpio_set; 1512 s->gpio.base = -1; 1513 s->gpio.ngpio = devtype->nr_gpio; 1514 s->gpio.can_sleep = 1; 1515 ret = gpiochip_add_data(&s->gpio, s); 1516 if (ret) 1517 goto out_thread; 1518 } 1519 #endif 1520 1521 /* 1522 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1523 * If that succeeds, we can allow sharing the interrupt as well. 1524 * In case the interrupt controller doesn't support that, we fall 1525 * back to a non-shared falling-edge trigger. 1526 */ 1527 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1528 IRQF_TRIGGER_LOW | IRQF_SHARED | 1529 IRQF_ONESHOT, 1530 dev_name(dev), s); 1531 if (!ret) 1532 return 0; 1533 1534 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1535 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1536 dev_name(dev), s); 1537 if (!ret) 1538 return 0; 1539 1540 #ifdef CONFIG_GPIOLIB 1541 if (devtype->nr_gpio) 1542 gpiochip_remove(&s->gpio); 1543 1544 out_thread: 1545 #endif 1546 1547 out_ports: 1548 for (i--; i >= 0; i--) { 1549 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1550 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1551 } 1552 1553 kthread_stop(s->kworker_task); 1554 1555 out_clk: 1556 clk_disable_unprepare(s->clk); 1557 1558 return ret; 1559 } 1560 1561 static void sc16is7xx_remove(struct device *dev) 1562 { 1563 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1564 int i; 1565 1566 #ifdef CONFIG_GPIOLIB 1567 if (s->devtype->nr_gpio) 1568 gpiochip_remove(&s->gpio); 1569 #endif 1570 1571 for (i = 0; i < s->devtype->nr_uart; i++) { 1572 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1573 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1574 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1575 sc16is7xx_power(&s->p[i].port, 0); 1576 } 1577 1578 kthread_flush_worker(&s->kworker); 1579 kthread_stop(s->kworker_task); 1580 1581 clk_disable_unprepare(s->clk); 1582 } 1583 1584 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1585 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1586 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1587 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1588 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1589 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1590 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1591 { } 1592 }; 1593 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1594 1595 static struct regmap_config regcfg = { 1596 .reg_bits = 7, 1597 .pad_bits = 1, 1598 .val_bits = 8, 1599 .cache_type = REGCACHE_RBTREE, 1600 .volatile_reg = sc16is7xx_regmap_volatile, 1601 .precious_reg = sc16is7xx_regmap_precious, 1602 }; 1603 1604 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1605 static int sc16is7xx_spi_probe(struct spi_device *spi) 1606 { 1607 const struct sc16is7xx_devtype *devtype; 1608 struct regmap *regmap; 1609 int ret; 1610 1611 /* Setup SPI bus */ 1612 spi->bits_per_word = 8; 1613 /* only supports mode 0 on SC16IS762 */ 1614 spi->mode = spi->mode ? : SPI_MODE_0; 1615 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1616 ret = spi_setup(spi); 1617 if (ret) 1618 return ret; 1619 1620 if (spi->dev.of_node) { 1621 devtype = device_get_match_data(&spi->dev); 1622 if (!devtype) 1623 return -ENODEV; 1624 } else { 1625 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1626 1627 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1628 } 1629 1630 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1631 (devtype->nr_uart - 1); 1632 regmap = devm_regmap_init_spi(spi, ®cfg); 1633 1634 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); 1635 } 1636 1637 static void sc16is7xx_spi_remove(struct spi_device *spi) 1638 { 1639 sc16is7xx_remove(&spi->dev); 1640 } 1641 1642 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1643 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1644 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1645 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1646 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1647 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1648 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1649 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1650 { } 1651 }; 1652 1653 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1654 1655 static struct spi_driver sc16is7xx_spi_uart_driver = { 1656 .driver = { 1657 .name = SC16IS7XX_NAME, 1658 .of_match_table = sc16is7xx_dt_ids, 1659 }, 1660 .probe = sc16is7xx_spi_probe, 1661 .remove = sc16is7xx_spi_remove, 1662 .id_table = sc16is7xx_spi_id_table, 1663 }; 1664 1665 MODULE_ALIAS("spi:sc16is7xx"); 1666 #endif 1667 1668 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1669 static int sc16is7xx_i2c_probe(struct i2c_client *i2c) 1670 { 1671 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1672 const struct sc16is7xx_devtype *devtype; 1673 struct regmap *regmap; 1674 1675 if (i2c->dev.of_node) { 1676 devtype = device_get_match_data(&i2c->dev); 1677 if (!devtype) 1678 return -ENODEV; 1679 } else { 1680 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1681 } 1682 1683 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1684 (devtype->nr_uart - 1); 1685 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1686 1687 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); 1688 } 1689 1690 static void sc16is7xx_i2c_remove(struct i2c_client *client) 1691 { 1692 sc16is7xx_remove(&client->dev); 1693 } 1694 1695 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1696 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1697 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1698 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1699 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1700 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1701 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1702 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1703 { } 1704 }; 1705 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1706 1707 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1708 .driver = { 1709 .name = SC16IS7XX_NAME, 1710 .of_match_table = sc16is7xx_dt_ids, 1711 }, 1712 .probe_new = sc16is7xx_i2c_probe, 1713 .remove = sc16is7xx_i2c_remove, 1714 .id_table = sc16is7xx_i2c_id_table, 1715 }; 1716 1717 #endif 1718 1719 static int __init sc16is7xx_init(void) 1720 { 1721 int ret; 1722 1723 ret = uart_register_driver(&sc16is7xx_uart); 1724 if (ret) { 1725 pr_err("Registering UART driver failed\n"); 1726 return ret; 1727 } 1728 1729 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1730 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1731 if (ret < 0) { 1732 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1733 goto err_i2c; 1734 } 1735 #endif 1736 1737 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1738 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1739 if (ret < 0) { 1740 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1741 goto err_spi; 1742 } 1743 #endif 1744 return ret; 1745 1746 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1747 err_spi: 1748 #endif 1749 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1750 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1751 err_i2c: 1752 #endif 1753 uart_unregister_driver(&sc16is7xx_uart); 1754 return ret; 1755 } 1756 module_init(sc16is7xx_init); 1757 1758 static void __exit sc16is7xx_exit(void) 1759 { 1760 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1761 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1762 #endif 1763 1764 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1765 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1766 #endif 1767 uart_unregister_driver(&sc16is7xx_uart); 1768 } 1769 module_exit(sc16is7xx_exit); 1770 1771 MODULE_LICENSE("GPL"); 1772 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1773 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1774