1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 #include <uapi/linux/sched/types.h> 28 29 #define SC16IS7XX_NAME "sc16is7xx" 30 #define SC16IS7XX_MAX_DEVS 8 31 32 /* SC16IS7XX register definitions */ 33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 46 * - only on 75x/76x 47 */ 48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 49 * - only on 75x/76x 50 */ 51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 58 59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 62 63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 66 67 /* Enhanced Register set: Only if (LCR == 0xBF) */ 68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 73 74 /* IER register bits */ 75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 77 * interrupt */ 78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 79 * interrupt */ 80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 81 * interrupt */ 82 83 /* IER register bits - write only if (EFR[4] == 1) */ 84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 88 89 /* FCR register bits */ 90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 95 96 /* FCR register bits - write only if (EFR[4] == 1) */ 97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 99 100 /* IIR register bits */ 101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 108 * - only on 75x/76x 109 */ 110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 111 * - only on 75x/76x 112 */ 113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 115 * from active (LOW) 116 * to inactive (HIGH) 117 */ 118 /* LCR register bits */ 119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 121 * 122 * Word length bits table: 123 * 00 -> 5 bit words 124 * 01 -> 6 bit words 125 * 10 -> 7 bit words 126 * 11 -> 8 bit words 127 */ 128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 129 * 130 * STOP length bit table: 131 * 0 -> 1 stop bit 132 * 1 -> 1-1.5 stop bits if 133 * word length is 5, 134 * 2 stop bits otherwise 135 */ 136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 146 * reg set */ 147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 148 * reg set */ 149 150 /* MCR register bits */ 151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 152 * - only on 75x/76x 153 */ 154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 158 * - write enabled 159 * if (EFR[4] == 1) 160 */ 161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 162 * - write enabled 163 * if (EFR[4] == 1) 164 */ 165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 166 * - write enabled 167 * if (EFR[4] == 1) 168 */ 169 170 /* LSR register bits */ 171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 180 181 /* MSR register bits */ 182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 184 * or (IO4) 185 * - only on 75x/76x 186 */ 187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 188 * or (IO7) 189 * - only on 75x/76x 190 */ 191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 192 * or (IO6) 193 * - only on 75x/76x 194 */ 195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 197 * - only on 75x/76x 198 */ 199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 200 * - only on 75x/76x 201 */ 202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 206 207 /* 208 * TCR register bits 209 * TCR trigger levels are available from 0 to 60 characters with a granularity 210 * of four. 211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 212 * no built-in hardware check to make sure this condition is met. Also, the TCR 213 * must be programmed with this condition before auto RTS or software flow 214 * control is enabled to avoid spurious operation of the device. 215 */ 216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 218 219 /* 220 * TLR register bits 221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 223 * trigger levels. Trigger levels from 4 characters to 60 characters are 224 * available with a granularity of four. 225 * 226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 228 * the trigger level defined in FCR is discarded. This applies to both transmit 229 * FIFO and receive FIFO trigger level setting. 230 * 231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 232 * default state, that is, '00'. 233 */ 234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 236 237 /* IOControl register bits (Only 750/760) */ 238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 239 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 240 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 242 243 /* EFCR register bits */ 244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 245 * mode (RS485) */ 246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 251 * 0 = rate upto 115.2 kbit/s 252 * - Only 750/760 253 * 1 = rate upto 1.152 Mbit/s 254 * - Only 760 255 */ 256 257 /* EFR register bits */ 258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 262 * and writing to IER[7:4], 263 * FCR[5:4], MCR[7:5] 264 */ 265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 267 * 268 * SWFLOW bits 3 & 2 table: 269 * 00 -> no transmitter flow 270 * control 271 * 01 -> transmitter generates 272 * XON2 and XOFF2 273 * 10 -> transmitter generates 274 * XON1 and XOFF1 275 * 11 -> transmitter generates 276 * XON1, XON2, XOFF1 and 277 * XOFF2 278 */ 279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 281 * 282 * SWFLOW bits 3 & 2 table: 283 * 00 -> no received flow 284 * control 285 * 01 -> receiver compares 286 * XON2 and XOFF2 287 * 10 -> receiver compares 288 * XON1 and XOFF1 289 * 11 -> receiver compares 290 * XON1, XON2, XOFF1 and 291 * XOFF2 292 */ 293 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 294 SC16IS7XX_EFR_AUTOCTS_BIT | \ 295 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 296 SC16IS7XX_EFR_SWFLOW3_BIT | \ 297 SC16IS7XX_EFR_SWFLOW2_BIT | \ 298 SC16IS7XX_EFR_SWFLOW1_BIT | \ 299 SC16IS7XX_EFR_SWFLOW0_BIT) 300 301 302 /* Misc definitions */ 303 #define SC16IS7XX_FIFO_SIZE (64) 304 #define SC16IS7XX_REG_SHIFT 2 305 #define SC16IS7XX_GPIOS_PER_BANK 4 306 307 struct sc16is7xx_devtype { 308 char name[10]; 309 int nr_gpio; 310 int nr_uart; 311 }; 312 313 #define SC16IS7XX_RECONF_MD (1 << 0) 314 #define SC16IS7XX_RECONF_IER (1 << 1) 315 #define SC16IS7XX_RECONF_RS485 (1 << 2) 316 317 struct sc16is7xx_one_config { 318 unsigned int flags; 319 u8 ier_mask; 320 u8 ier_val; 321 }; 322 323 struct sc16is7xx_one { 324 struct uart_port port; 325 u8 line; 326 struct kthread_work tx_work; 327 struct kthread_work reg_work; 328 struct kthread_delayed_work ms_work; 329 struct sc16is7xx_one_config config; 330 bool irda_mode; 331 unsigned int old_mctrl; 332 }; 333 334 struct sc16is7xx_port { 335 const struct sc16is7xx_devtype *devtype; 336 struct regmap *regmap; 337 struct clk *clk; 338 #ifdef CONFIG_GPIOLIB 339 struct gpio_chip gpio; 340 unsigned long gpio_valid_mask; 341 #endif 342 u8 mctrl_mask; 343 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 344 struct kthread_worker kworker; 345 struct task_struct *kworker_task; 346 struct mutex efr_lock; 347 struct sc16is7xx_one p[]; 348 }; 349 350 static unsigned long sc16is7xx_lines; 351 352 static struct uart_driver sc16is7xx_uart = { 353 .owner = THIS_MODULE, 354 .dev_name = "ttySC", 355 .nr = SC16IS7XX_MAX_DEVS, 356 }; 357 358 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 359 static void sc16is7xx_stop_tx(struct uart_port *port); 360 361 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 362 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 363 364 static int sc16is7xx_line(struct uart_port *port) 365 { 366 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 367 368 return one->line; 369 } 370 371 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 372 { 373 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 374 unsigned int val = 0; 375 const u8 line = sc16is7xx_line(port); 376 377 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 378 379 return val; 380 } 381 382 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 383 { 384 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 385 const u8 line = sc16is7xx_line(port); 386 387 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 388 } 389 390 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 391 { 392 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 393 const u8 line = sc16is7xx_line(port); 394 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 395 396 regcache_cache_bypass(s->regmap, true); 397 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 398 regcache_cache_bypass(s->regmap, false); 399 } 400 401 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 402 { 403 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 404 const u8 line = sc16is7xx_line(port); 405 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 406 407 /* 408 * Don't send zero-length data, at least on SPI it confuses the chip 409 * delivering wrong TXLVL data. 410 */ 411 if (unlikely(!to_send)) 412 return; 413 414 regcache_cache_bypass(s->regmap, true); 415 regmap_raw_write(s->regmap, addr, s->buf, to_send); 416 regcache_cache_bypass(s->regmap, false); 417 } 418 419 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 420 u8 mask, u8 val) 421 { 422 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 423 const u8 line = sc16is7xx_line(port); 424 425 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 426 mask, val); 427 } 428 429 static int sc16is7xx_alloc_line(void) 430 { 431 int i; 432 433 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 434 435 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 436 if (!test_and_set_bit(i, &sc16is7xx_lines)) 437 break; 438 439 return i; 440 } 441 442 static void sc16is7xx_power(struct uart_port *port, int on) 443 { 444 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 445 SC16IS7XX_IER_SLEEP_BIT, 446 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 447 } 448 449 static const struct sc16is7xx_devtype sc16is74x_devtype = { 450 .name = "SC16IS74X", 451 .nr_gpio = 0, 452 .nr_uart = 1, 453 }; 454 455 static const struct sc16is7xx_devtype sc16is750_devtype = { 456 .name = "SC16IS750", 457 .nr_gpio = 8, 458 .nr_uart = 1, 459 }; 460 461 static const struct sc16is7xx_devtype sc16is752_devtype = { 462 .name = "SC16IS752", 463 .nr_gpio = 8, 464 .nr_uart = 2, 465 }; 466 467 static const struct sc16is7xx_devtype sc16is760_devtype = { 468 .name = "SC16IS760", 469 .nr_gpio = 8, 470 .nr_uart = 1, 471 }; 472 473 static const struct sc16is7xx_devtype sc16is762_devtype = { 474 .name = "SC16IS762", 475 .nr_gpio = 8, 476 .nr_uart = 2, 477 }; 478 479 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 480 { 481 switch (reg >> SC16IS7XX_REG_SHIFT) { 482 case SC16IS7XX_RHR_REG: 483 case SC16IS7XX_IIR_REG: 484 case SC16IS7XX_LSR_REG: 485 case SC16IS7XX_MSR_REG: 486 case SC16IS7XX_TXLVL_REG: 487 case SC16IS7XX_RXLVL_REG: 488 case SC16IS7XX_IOSTATE_REG: 489 case SC16IS7XX_IOCONTROL_REG: 490 return true; 491 default: 492 break; 493 } 494 495 return false; 496 } 497 498 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 499 { 500 switch (reg >> SC16IS7XX_REG_SHIFT) { 501 case SC16IS7XX_RHR_REG: 502 return true; 503 default: 504 break; 505 } 506 507 return false; 508 } 509 510 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 511 { 512 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 513 u8 lcr; 514 u8 prescaler = 0; 515 unsigned long clk = port->uartclk, div = clk / 16 / baud; 516 517 if (div > 0xffff) { 518 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 519 div /= 4; 520 } 521 522 /* In an amazing feat of design, the Enhanced Features Register shares 523 * the address of the Interrupt Identification Register, and is 524 * switched in by writing a magic value (0xbf) to the Line Control 525 * Register. Any interrupt firing during this time will see the EFR 526 * where it expects the IIR to be, leading to "Unexpected interrupt" 527 * messages. 528 * 529 * Prevent this possibility by claiming a mutex while accessing the 530 * EFR, and claiming the same mutex from within the interrupt handler. 531 * This is similar to disabling the interrupt, but that doesn't work 532 * because the bulk of the interrupt processing is run as a workqueue 533 * job in thread context. 534 */ 535 mutex_lock(&s->efr_lock); 536 537 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 538 539 /* Open the LCR divisors for configuration */ 540 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 541 SC16IS7XX_LCR_CONF_MODE_B); 542 543 /* Enable enhanced features */ 544 regcache_cache_bypass(s->regmap, true); 545 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 546 SC16IS7XX_EFR_ENABLE_BIT, 547 SC16IS7XX_EFR_ENABLE_BIT); 548 549 regcache_cache_bypass(s->regmap, false); 550 551 /* Put LCR back to the normal mode */ 552 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 553 554 mutex_unlock(&s->efr_lock); 555 556 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 557 SC16IS7XX_MCR_CLKSEL_BIT, 558 prescaler); 559 560 /* Open the LCR divisors for configuration */ 561 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 562 SC16IS7XX_LCR_CONF_MODE_A); 563 564 /* Write the new divisor */ 565 regcache_cache_bypass(s->regmap, true); 566 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 567 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 568 regcache_cache_bypass(s->regmap, false); 569 570 /* Put LCR back to the normal mode */ 571 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 572 573 return DIV_ROUND_CLOSEST(clk / 16, div); 574 } 575 576 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 577 unsigned int iir) 578 { 579 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 580 unsigned int lsr = 0, bytes_read, i; 581 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 582 u8 ch, flag; 583 584 if (unlikely(rxlen >= sizeof(s->buf))) { 585 dev_warn_ratelimited(port->dev, 586 "ttySC%i: Possible RX FIFO overrun: %d\n", 587 port->line, rxlen); 588 port->icount.buf_overrun++; 589 /* Ensure sanity of RX level */ 590 rxlen = sizeof(s->buf); 591 } 592 593 while (rxlen) { 594 /* Only read lsr if there are possible errors in FIFO */ 595 if (read_lsr) { 596 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 597 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 598 read_lsr = false; /* No errors left in FIFO */ 599 } else 600 lsr = 0; 601 602 if (read_lsr) { 603 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 604 bytes_read = 1; 605 } else { 606 sc16is7xx_fifo_read(port, rxlen); 607 bytes_read = rxlen; 608 } 609 610 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 611 612 port->icount.rx++; 613 flag = TTY_NORMAL; 614 615 if (unlikely(lsr)) { 616 if (lsr & SC16IS7XX_LSR_BI_BIT) { 617 port->icount.brk++; 618 if (uart_handle_break(port)) 619 continue; 620 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 621 port->icount.parity++; 622 else if (lsr & SC16IS7XX_LSR_FE_BIT) 623 port->icount.frame++; 624 else if (lsr & SC16IS7XX_LSR_OE_BIT) 625 port->icount.overrun++; 626 627 lsr &= port->read_status_mask; 628 if (lsr & SC16IS7XX_LSR_BI_BIT) 629 flag = TTY_BREAK; 630 else if (lsr & SC16IS7XX_LSR_PE_BIT) 631 flag = TTY_PARITY; 632 else if (lsr & SC16IS7XX_LSR_FE_BIT) 633 flag = TTY_FRAME; 634 else if (lsr & SC16IS7XX_LSR_OE_BIT) 635 flag = TTY_OVERRUN; 636 } 637 638 for (i = 0; i < bytes_read; ++i) { 639 ch = s->buf[i]; 640 if (uart_handle_sysrq_char(port, ch)) 641 continue; 642 643 if (lsr & port->ignore_status_mask) 644 continue; 645 646 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 647 flag); 648 } 649 rxlen -= bytes_read; 650 } 651 652 tty_flip_buffer_push(&port->state->port); 653 } 654 655 static void sc16is7xx_handle_tx(struct uart_port *port) 656 { 657 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 658 struct circ_buf *xmit = &port->state->xmit; 659 unsigned int txlen, to_send, i; 660 unsigned long flags; 661 662 if (unlikely(port->x_char)) { 663 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 664 port->icount.tx++; 665 port->x_char = 0; 666 return; 667 } 668 669 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 670 spin_lock_irqsave(&port->lock, flags); 671 sc16is7xx_stop_tx(port); 672 spin_unlock_irqrestore(&port->lock, flags); 673 return; 674 } 675 676 /* Get length of data pending in circular buffer */ 677 to_send = uart_circ_chars_pending(xmit); 678 if (likely(to_send)) { 679 /* Limit to size of TX FIFO */ 680 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 681 if (txlen > SC16IS7XX_FIFO_SIZE) { 682 dev_err_ratelimited(port->dev, 683 "chip reports %d free bytes in TX fifo, but it only has %d", 684 txlen, SC16IS7XX_FIFO_SIZE); 685 txlen = 0; 686 } 687 to_send = (to_send > txlen) ? txlen : to_send; 688 689 /* Convert to linear buffer */ 690 for (i = 0; i < to_send; ++i) { 691 s->buf[i] = xmit->buf[xmit->tail]; 692 uart_xmit_advance(port, 1); 693 } 694 695 sc16is7xx_fifo_write(port, to_send); 696 } 697 698 spin_lock_irqsave(&port->lock, flags); 699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 700 uart_write_wakeup(port); 701 702 if (uart_circ_empty(xmit)) 703 sc16is7xx_stop_tx(port); 704 spin_unlock_irqrestore(&port->lock, flags); 705 } 706 707 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 708 { 709 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 710 unsigned int mctrl = 0; 711 712 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 713 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 714 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 715 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 716 return mctrl; 717 } 718 719 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 720 { 721 struct uart_port *port = &one->port; 722 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 723 unsigned long flags; 724 unsigned int status, changed; 725 726 lockdep_assert_held_once(&s->efr_lock); 727 728 status = sc16is7xx_get_hwmctrl(port); 729 changed = status ^ one->old_mctrl; 730 731 if (changed == 0) 732 return; 733 734 one->old_mctrl = status; 735 736 spin_lock_irqsave(&port->lock, flags); 737 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 738 port->icount.rng++; 739 if (changed & TIOCM_DSR) 740 port->icount.dsr++; 741 if (changed & TIOCM_CAR) 742 uart_handle_dcd_change(port, status & TIOCM_CAR); 743 if (changed & TIOCM_CTS) 744 uart_handle_cts_change(port, status & TIOCM_CTS); 745 746 wake_up_interruptible(&port->state->port.delta_msr_wait); 747 spin_unlock_irqrestore(&port->lock, flags); 748 } 749 750 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 751 { 752 struct uart_port *port = &s->p[portno].port; 753 754 do { 755 unsigned int iir, rxlen; 756 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 757 758 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 759 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 760 return false; 761 762 iir &= SC16IS7XX_IIR_ID_MASK; 763 764 switch (iir) { 765 case SC16IS7XX_IIR_RDI_SRC: 766 case SC16IS7XX_IIR_RLSE_SRC: 767 case SC16IS7XX_IIR_RTOI_SRC: 768 case SC16IS7XX_IIR_XOFFI_SRC: 769 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 770 771 /* 772 * There is a silicon bug that makes the chip report a 773 * time-out interrupt but no data in the FIFO. This is 774 * described in errata section 18.1.4. 775 * 776 * When this happens, read one byte from the FIFO to 777 * clear the interrupt. 778 */ 779 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 780 rxlen = 1; 781 782 if (rxlen) 783 sc16is7xx_handle_rx(port, rxlen, iir); 784 break; 785 /* CTSRTS interrupt comes only when CTS goes inactive */ 786 case SC16IS7XX_IIR_CTSRTS_SRC: 787 case SC16IS7XX_IIR_MSI_SRC: 788 sc16is7xx_update_mlines(one); 789 break; 790 case SC16IS7XX_IIR_THRI_SRC: 791 sc16is7xx_handle_tx(port); 792 break; 793 default: 794 dev_err_ratelimited(port->dev, 795 "ttySC%i: Unexpected interrupt: %x", 796 port->line, iir); 797 break; 798 } 799 } while (0); 800 return true; 801 } 802 803 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 804 { 805 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 806 807 mutex_lock(&s->efr_lock); 808 809 while (1) { 810 bool keep_polling = false; 811 int i; 812 813 for (i = 0; i < s->devtype->nr_uart; ++i) 814 keep_polling |= sc16is7xx_port_irq(s, i); 815 if (!keep_polling) 816 break; 817 } 818 819 mutex_unlock(&s->efr_lock); 820 821 return IRQ_HANDLED; 822 } 823 824 static void sc16is7xx_tx_proc(struct kthread_work *ws) 825 { 826 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 827 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 828 unsigned long flags; 829 830 if ((port->rs485.flags & SER_RS485_ENABLED) && 831 (port->rs485.delay_rts_before_send > 0)) 832 msleep(port->rs485.delay_rts_before_send); 833 834 mutex_lock(&s->efr_lock); 835 sc16is7xx_handle_tx(port); 836 mutex_unlock(&s->efr_lock); 837 838 spin_lock_irqsave(&port->lock, flags); 839 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 840 spin_unlock_irqrestore(&port->lock, flags); 841 } 842 843 static void sc16is7xx_reconf_rs485(struct uart_port *port) 844 { 845 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 846 SC16IS7XX_EFCR_RTS_INVERT_BIT; 847 u32 efcr = 0; 848 struct serial_rs485 *rs485 = &port->rs485; 849 unsigned long irqflags; 850 851 spin_lock_irqsave(&port->lock, irqflags); 852 if (rs485->flags & SER_RS485_ENABLED) { 853 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 854 855 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 856 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 857 } 858 spin_unlock_irqrestore(&port->lock, irqflags); 859 860 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 861 } 862 863 static void sc16is7xx_reg_proc(struct kthread_work *ws) 864 { 865 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 866 struct sc16is7xx_one_config config; 867 unsigned long irqflags; 868 869 spin_lock_irqsave(&one->port.lock, irqflags); 870 config = one->config; 871 memset(&one->config, 0, sizeof(one->config)); 872 spin_unlock_irqrestore(&one->port.lock, irqflags); 873 874 if (config.flags & SC16IS7XX_RECONF_MD) { 875 u8 mcr = 0; 876 877 /* Device ignores RTS setting when hardware flow is enabled */ 878 if (one->port.mctrl & TIOCM_RTS) 879 mcr |= SC16IS7XX_MCR_RTS_BIT; 880 881 if (one->port.mctrl & TIOCM_DTR) 882 mcr |= SC16IS7XX_MCR_DTR_BIT; 883 884 if (one->port.mctrl & TIOCM_LOOP) 885 mcr |= SC16IS7XX_MCR_LOOP_BIT; 886 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 887 SC16IS7XX_MCR_RTS_BIT | 888 SC16IS7XX_MCR_DTR_BIT | 889 SC16IS7XX_MCR_LOOP_BIT, 890 mcr); 891 } 892 893 if (config.flags & SC16IS7XX_RECONF_IER) 894 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 895 config.ier_mask, config.ier_val); 896 897 if (config.flags & SC16IS7XX_RECONF_RS485) 898 sc16is7xx_reconf_rs485(&one->port); 899 } 900 901 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 902 { 903 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 904 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 905 906 lockdep_assert_held_once(&port->lock); 907 908 one->config.flags |= SC16IS7XX_RECONF_IER; 909 one->config.ier_mask |= bit; 910 one->config.ier_val &= ~bit; 911 kthread_queue_work(&s->kworker, &one->reg_work); 912 } 913 914 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 915 { 916 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 917 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 918 919 lockdep_assert_held_once(&port->lock); 920 921 one->config.flags |= SC16IS7XX_RECONF_IER; 922 one->config.ier_mask |= bit; 923 one->config.ier_val |= bit; 924 kthread_queue_work(&s->kworker, &one->reg_work); 925 } 926 927 static void sc16is7xx_stop_tx(struct uart_port *port) 928 { 929 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 930 } 931 932 static void sc16is7xx_stop_rx(struct uart_port *port) 933 { 934 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 935 } 936 937 static void sc16is7xx_ms_proc(struct kthread_work *ws) 938 { 939 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 940 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 941 942 if (one->port.state) { 943 mutex_lock(&s->efr_lock); 944 sc16is7xx_update_mlines(one); 945 mutex_unlock(&s->efr_lock); 946 947 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 948 } 949 } 950 951 static void sc16is7xx_enable_ms(struct uart_port *port) 952 { 953 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 954 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 955 956 lockdep_assert_held_once(&port->lock); 957 958 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 959 } 960 961 static void sc16is7xx_start_tx(struct uart_port *port) 962 { 963 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 964 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 965 966 kthread_queue_work(&s->kworker, &one->tx_work); 967 } 968 969 static void sc16is7xx_throttle(struct uart_port *port) 970 { 971 unsigned long flags; 972 973 /* 974 * Hardware flow control is enabled and thus the device ignores RTS 975 * value set in MCR register. Stop reading data from RX FIFO so the 976 * AutoRTS feature will de-activate RTS output. 977 */ 978 spin_lock_irqsave(&port->lock, flags); 979 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 980 spin_unlock_irqrestore(&port->lock, flags); 981 } 982 983 static void sc16is7xx_unthrottle(struct uart_port *port) 984 { 985 unsigned long flags; 986 987 spin_lock_irqsave(&port->lock, flags); 988 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 989 spin_unlock_irqrestore(&port->lock, flags); 990 } 991 992 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 993 { 994 unsigned int lsr; 995 996 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 997 998 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 999 } 1000 1001 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 1002 { 1003 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1004 1005 /* Called with port lock taken so we can only return cached value */ 1006 return one->old_mctrl; 1007 } 1008 1009 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 1010 { 1011 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1012 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1013 1014 one->config.flags |= SC16IS7XX_RECONF_MD; 1015 kthread_queue_work(&s->kworker, &one->reg_work); 1016 } 1017 1018 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1019 { 1020 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1021 SC16IS7XX_LCR_TXBREAK_BIT, 1022 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1023 } 1024 1025 static void sc16is7xx_set_termios(struct uart_port *port, 1026 struct ktermios *termios, 1027 const struct ktermios *old) 1028 { 1029 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1030 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1031 unsigned int lcr, flow = 0; 1032 int baud; 1033 unsigned long flags; 1034 1035 kthread_cancel_delayed_work_sync(&one->ms_work); 1036 1037 /* Mask termios capabilities we don't support */ 1038 termios->c_cflag &= ~CMSPAR; 1039 1040 /* Word size */ 1041 switch (termios->c_cflag & CSIZE) { 1042 case CS5: 1043 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1044 break; 1045 case CS6: 1046 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1047 break; 1048 case CS7: 1049 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1050 break; 1051 case CS8: 1052 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1053 break; 1054 default: 1055 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1056 termios->c_cflag &= ~CSIZE; 1057 termios->c_cflag |= CS8; 1058 break; 1059 } 1060 1061 /* Parity */ 1062 if (termios->c_cflag & PARENB) { 1063 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1064 if (!(termios->c_cflag & PARODD)) 1065 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1066 } 1067 1068 /* Stop bits */ 1069 if (termios->c_cflag & CSTOPB) 1070 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1071 1072 /* Set read status mask */ 1073 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1074 if (termios->c_iflag & INPCK) 1075 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1076 SC16IS7XX_LSR_FE_BIT; 1077 if (termios->c_iflag & (BRKINT | PARMRK)) 1078 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1079 1080 /* Set status ignore mask */ 1081 port->ignore_status_mask = 0; 1082 if (termios->c_iflag & IGNBRK) 1083 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1084 if (!(termios->c_cflag & CREAD)) 1085 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1086 1087 /* As above, claim the mutex while accessing the EFR. */ 1088 mutex_lock(&s->efr_lock); 1089 1090 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1091 SC16IS7XX_LCR_CONF_MODE_B); 1092 1093 /* Configure flow control */ 1094 regcache_cache_bypass(s->regmap, true); 1095 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1096 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1097 1098 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1099 if (termios->c_cflag & CRTSCTS) { 1100 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1101 SC16IS7XX_EFR_AUTORTS_BIT; 1102 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1103 } 1104 if (termios->c_iflag & IXON) 1105 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1106 if (termios->c_iflag & IXOFF) 1107 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1108 1109 sc16is7xx_port_update(port, 1110 SC16IS7XX_EFR_REG, 1111 SC16IS7XX_EFR_FLOWCTRL_BITS, 1112 flow); 1113 regcache_cache_bypass(s->regmap, false); 1114 1115 /* Update LCR register */ 1116 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1117 1118 mutex_unlock(&s->efr_lock); 1119 1120 /* Get baud rate generator configuration */ 1121 baud = uart_get_baud_rate(port, termios, old, 1122 port->uartclk / 16 / 4 / 0xffff, 1123 port->uartclk / 16); 1124 1125 /* Setup baudrate generator */ 1126 baud = sc16is7xx_set_baud(port, baud); 1127 1128 spin_lock_irqsave(&port->lock, flags); 1129 1130 /* Update timeout according to new baud rate */ 1131 uart_update_timeout(port, termios->c_cflag, baud); 1132 1133 if (UART_ENABLE_MS(port, termios->c_cflag)) 1134 sc16is7xx_enable_ms(port); 1135 1136 spin_unlock_irqrestore(&port->lock, flags); 1137 } 1138 1139 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1140 struct serial_rs485 *rs485) 1141 { 1142 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1143 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1144 1145 if (rs485->flags & SER_RS485_ENABLED) { 1146 /* 1147 * RTS signal is handled by HW, it's timing can't be influenced. 1148 * However, it's sometimes useful to delay TX even without RTS 1149 * control therefore we try to handle .delay_rts_before_send. 1150 */ 1151 if (rs485->delay_rts_after_send) 1152 return -EINVAL; 1153 } 1154 1155 one->config.flags |= SC16IS7XX_RECONF_RS485; 1156 kthread_queue_work(&s->kworker, &one->reg_work); 1157 1158 return 0; 1159 } 1160 1161 static int sc16is7xx_startup(struct uart_port *port) 1162 { 1163 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1164 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1165 unsigned int val; 1166 unsigned long flags; 1167 1168 sc16is7xx_power(port, 1); 1169 1170 /* Reset FIFOs*/ 1171 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1172 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1173 udelay(5); 1174 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1175 SC16IS7XX_FCR_FIFO_BIT); 1176 1177 /* Enable EFR */ 1178 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1179 SC16IS7XX_LCR_CONF_MODE_B); 1180 1181 regcache_cache_bypass(s->regmap, true); 1182 1183 /* Enable write access to enhanced features and internal clock div */ 1184 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1185 SC16IS7XX_EFR_ENABLE_BIT, 1186 SC16IS7XX_EFR_ENABLE_BIT); 1187 1188 /* Enable TCR/TLR */ 1189 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1190 SC16IS7XX_MCR_TCRTLR_BIT, 1191 SC16IS7XX_MCR_TCRTLR_BIT); 1192 1193 /* Configure flow control levels */ 1194 /* Flow control halt level 48, resume level 24 */ 1195 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1196 SC16IS7XX_TCR_RX_RESUME(24) | 1197 SC16IS7XX_TCR_RX_HALT(48)); 1198 1199 regcache_cache_bypass(s->regmap, false); 1200 1201 /* Now, initialize the UART */ 1202 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1203 1204 /* Enable IrDA mode if requested in DT */ 1205 /* This bit must be written with LCR[7] = 0 */ 1206 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1207 SC16IS7XX_MCR_IRDA_BIT, 1208 one->irda_mode ? 1209 SC16IS7XX_MCR_IRDA_BIT : 0); 1210 1211 /* Enable the Rx and Tx FIFO */ 1212 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1213 SC16IS7XX_EFCR_RXDISABLE_BIT | 1214 SC16IS7XX_EFCR_TXDISABLE_BIT, 1215 0); 1216 1217 /* Enable RX, CTS change and modem lines interrupts */ 1218 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1219 SC16IS7XX_IER_MSI_BIT; 1220 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1221 1222 /* Enable modem status polling */ 1223 spin_lock_irqsave(&port->lock, flags); 1224 sc16is7xx_enable_ms(port); 1225 spin_unlock_irqrestore(&port->lock, flags); 1226 1227 return 0; 1228 } 1229 1230 static void sc16is7xx_shutdown(struct uart_port *port) 1231 { 1232 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1233 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1234 1235 kthread_cancel_delayed_work_sync(&one->ms_work); 1236 1237 /* Disable all interrupts */ 1238 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1239 /* Disable TX/RX */ 1240 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1241 SC16IS7XX_EFCR_RXDISABLE_BIT | 1242 SC16IS7XX_EFCR_TXDISABLE_BIT, 1243 SC16IS7XX_EFCR_RXDISABLE_BIT | 1244 SC16IS7XX_EFCR_TXDISABLE_BIT); 1245 1246 sc16is7xx_power(port, 0); 1247 1248 kthread_flush_worker(&s->kworker); 1249 } 1250 1251 static const char *sc16is7xx_type(struct uart_port *port) 1252 { 1253 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1254 1255 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1256 } 1257 1258 static int sc16is7xx_request_port(struct uart_port *port) 1259 { 1260 /* Do nothing */ 1261 return 0; 1262 } 1263 1264 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1265 { 1266 if (flags & UART_CONFIG_TYPE) 1267 port->type = PORT_SC16IS7XX; 1268 } 1269 1270 static int sc16is7xx_verify_port(struct uart_port *port, 1271 struct serial_struct *s) 1272 { 1273 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1274 return -EINVAL; 1275 if (s->irq != port->irq) 1276 return -EINVAL; 1277 1278 return 0; 1279 } 1280 1281 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1282 unsigned int oldstate) 1283 { 1284 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1285 } 1286 1287 static void sc16is7xx_null_void(struct uart_port *port) 1288 { 1289 /* Do nothing */ 1290 } 1291 1292 static const struct uart_ops sc16is7xx_ops = { 1293 .tx_empty = sc16is7xx_tx_empty, 1294 .set_mctrl = sc16is7xx_set_mctrl, 1295 .get_mctrl = sc16is7xx_get_mctrl, 1296 .stop_tx = sc16is7xx_stop_tx, 1297 .start_tx = sc16is7xx_start_tx, 1298 .throttle = sc16is7xx_throttle, 1299 .unthrottle = sc16is7xx_unthrottle, 1300 .stop_rx = sc16is7xx_stop_rx, 1301 .enable_ms = sc16is7xx_enable_ms, 1302 .break_ctl = sc16is7xx_break_ctl, 1303 .startup = sc16is7xx_startup, 1304 .shutdown = sc16is7xx_shutdown, 1305 .set_termios = sc16is7xx_set_termios, 1306 .type = sc16is7xx_type, 1307 .request_port = sc16is7xx_request_port, 1308 .release_port = sc16is7xx_null_void, 1309 .config_port = sc16is7xx_config_port, 1310 .verify_port = sc16is7xx_verify_port, 1311 .pm = sc16is7xx_pm, 1312 }; 1313 1314 #ifdef CONFIG_GPIOLIB 1315 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1316 { 1317 unsigned int val; 1318 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1319 struct uart_port *port = &s->p[0].port; 1320 1321 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1322 1323 return !!(val & BIT(offset)); 1324 } 1325 1326 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1327 { 1328 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1329 struct uart_port *port = &s->p[0].port; 1330 1331 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1332 val ? BIT(offset) : 0); 1333 } 1334 1335 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1336 unsigned offset) 1337 { 1338 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1339 struct uart_port *port = &s->p[0].port; 1340 1341 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1342 1343 return 0; 1344 } 1345 1346 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1347 unsigned offset, int val) 1348 { 1349 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1350 struct uart_port *port = &s->p[0].port; 1351 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1352 1353 if (val) 1354 state |= BIT(offset); 1355 else 1356 state &= ~BIT(offset); 1357 1358 /* 1359 * If we write IOSTATE first, and then IODIR, the output value is not 1360 * transferred to the corresponding I/O pin. 1361 * The datasheet states that each register bit will be transferred to 1362 * the corresponding I/O pin programmed as output when writing to 1363 * IOSTATE. Therefore, configure direction first with IODIR, and then 1364 * set value after with IOSTATE. 1365 */ 1366 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1367 BIT(offset)); 1368 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1369 1370 return 0; 1371 } 1372 1373 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1374 unsigned long *valid_mask, 1375 unsigned int ngpios) 1376 { 1377 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1378 1379 *valid_mask = s->gpio_valid_mask; 1380 1381 return 0; 1382 } 1383 1384 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1385 { 1386 struct device *dev = s->p[0].port.dev; 1387 1388 if (!s->devtype->nr_gpio) 1389 return 0; 1390 1391 switch (s->mctrl_mask) { 1392 case 0: 1393 s->gpio_valid_mask = GENMASK(7, 0); 1394 break; 1395 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1396 s->gpio_valid_mask = GENMASK(3, 0); 1397 break; 1398 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1399 s->gpio_valid_mask = GENMASK(7, 4); 1400 break; 1401 default: 1402 break; 1403 } 1404 1405 if (s->gpio_valid_mask == 0) 1406 return 0; 1407 1408 s->gpio.owner = THIS_MODULE; 1409 s->gpio.parent = dev; 1410 s->gpio.label = dev_name(dev); 1411 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1412 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1413 s->gpio.get = sc16is7xx_gpio_get; 1414 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1415 s->gpio.set = sc16is7xx_gpio_set; 1416 s->gpio.base = -1; 1417 s->gpio.ngpio = s->devtype->nr_gpio; 1418 s->gpio.can_sleep = 1; 1419 1420 return gpiochip_add_data(&s->gpio, s); 1421 } 1422 #endif 1423 1424 /* 1425 * Configure ports designated to operate as modem control lines. 1426 */ 1427 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s) 1428 { 1429 int i; 1430 int ret; 1431 int count; 1432 u32 mctrl_port[2]; 1433 struct device *dev = s->p[0].port.dev; 1434 1435 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1436 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1437 return 0; 1438 1439 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1440 mctrl_port, count); 1441 if (ret) 1442 return ret; 1443 1444 s->mctrl_mask = 0; 1445 1446 for (i = 0; i < count; i++) { 1447 /* Use GPIO lines as modem control lines */ 1448 if (mctrl_port[i] == 0) 1449 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1450 else if (mctrl_port[i] == 1) 1451 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1452 } 1453 1454 if (s->mctrl_mask) 1455 regmap_update_bits( 1456 s->regmap, 1457 SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1458 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1459 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1460 1461 return 0; 1462 } 1463 1464 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1465 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1466 .delay_rts_before_send = 1, 1467 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1468 }; 1469 1470 static int sc16is7xx_probe(struct device *dev, 1471 const struct sc16is7xx_devtype *devtype, 1472 struct regmap *regmap, int irq) 1473 { 1474 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1475 unsigned int val; 1476 u32 uartclk = 0; 1477 int i, ret; 1478 struct sc16is7xx_port *s; 1479 1480 if (IS_ERR(regmap)) 1481 return PTR_ERR(regmap); 1482 1483 /* 1484 * This device does not have an identification register that would 1485 * tell us if we are really connected to the correct device. 1486 * The best we can do is to check if communication is at all possible. 1487 */ 1488 ret = regmap_read(regmap, 1489 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val); 1490 if (ret < 0) 1491 return -EPROBE_DEFER; 1492 1493 /* Alloc port structure */ 1494 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1495 if (!s) { 1496 dev_err(dev, "Error allocating port structure\n"); 1497 return -ENOMEM; 1498 } 1499 1500 /* Always ask for fixed clock rate from a property. */ 1501 device_property_read_u32(dev, "clock-frequency", &uartclk); 1502 1503 s->clk = devm_clk_get_optional(dev, NULL); 1504 if (IS_ERR(s->clk)) 1505 return PTR_ERR(s->clk); 1506 1507 ret = clk_prepare_enable(s->clk); 1508 if (ret) 1509 return ret; 1510 1511 freq = clk_get_rate(s->clk); 1512 if (freq == 0) { 1513 if (uartclk) 1514 freq = uartclk; 1515 if (pfreq) 1516 freq = *pfreq; 1517 if (freq) 1518 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1519 else 1520 return -EINVAL; 1521 } 1522 1523 s->regmap = regmap; 1524 s->devtype = devtype; 1525 dev_set_drvdata(dev, s); 1526 mutex_init(&s->efr_lock); 1527 1528 kthread_init_worker(&s->kworker); 1529 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1530 "sc16is7xx"); 1531 if (IS_ERR(s->kworker_task)) { 1532 ret = PTR_ERR(s->kworker_task); 1533 goto out_clk; 1534 } 1535 sched_set_fifo(s->kworker_task); 1536 1537 /* reset device, purging any pending irq / data */ 1538 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1539 SC16IS7XX_IOCONTROL_SRESET_BIT); 1540 1541 for (i = 0; i < devtype->nr_uart; ++i) { 1542 s->p[i].line = i; 1543 /* Initialize port data */ 1544 s->p[i].port.dev = dev; 1545 s->p[i].port.irq = irq; 1546 s->p[i].port.type = PORT_SC16IS7XX; 1547 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1548 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1549 s->p[i].port.iobase = i; 1550 /* 1551 * Use all ones as membase to make sure uart_configure_port() in 1552 * serial_core.c does not abort for SPI/I2C devices where the 1553 * membase address is not applicable. 1554 */ 1555 s->p[i].port.membase = (void __iomem *)~0; 1556 s->p[i].port.iotype = UPIO_PORT; 1557 s->p[i].port.uartclk = freq; 1558 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1559 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1560 s->p[i].port.ops = &sc16is7xx_ops; 1561 s->p[i].old_mctrl = 0; 1562 s->p[i].port.line = sc16is7xx_alloc_line(); 1563 1564 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1565 ret = -ENOMEM; 1566 goto out_ports; 1567 } 1568 1569 ret = uart_get_rs485_mode(&s->p[i].port); 1570 if (ret) 1571 goto out_ports; 1572 1573 /* Disable all interrupts */ 1574 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1575 /* Disable TX/RX */ 1576 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1577 SC16IS7XX_EFCR_RXDISABLE_BIT | 1578 SC16IS7XX_EFCR_TXDISABLE_BIT); 1579 1580 /* Initialize kthread work structs */ 1581 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1582 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1583 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1584 /* Register port */ 1585 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1586 1587 /* Enable EFR */ 1588 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1589 SC16IS7XX_LCR_CONF_MODE_B); 1590 1591 regcache_cache_bypass(s->regmap, true); 1592 1593 /* Enable write access to enhanced features */ 1594 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1595 SC16IS7XX_EFR_ENABLE_BIT); 1596 1597 regcache_cache_bypass(s->regmap, false); 1598 1599 /* Restore access to general registers */ 1600 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1601 1602 /* Go to suspend mode */ 1603 sc16is7xx_power(&s->p[i].port, 0); 1604 } 1605 1606 if (dev->of_node) { 1607 struct property *prop; 1608 const __be32 *p; 1609 u32 u; 1610 1611 of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1612 prop, p, u) 1613 if (u < devtype->nr_uart) 1614 s->p[u].irda_mode = true; 1615 } 1616 1617 ret = sc16is7xx_setup_mctrl_ports(s); 1618 if (ret) 1619 goto out_ports; 1620 1621 #ifdef CONFIG_GPIOLIB 1622 ret = sc16is7xx_setup_gpio_chip(s); 1623 if (ret) 1624 goto out_ports; 1625 #endif 1626 1627 /* 1628 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1629 * If that succeeds, we can allow sharing the interrupt as well. 1630 * In case the interrupt controller doesn't support that, we fall 1631 * back to a non-shared falling-edge trigger. 1632 */ 1633 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1634 IRQF_TRIGGER_LOW | IRQF_SHARED | 1635 IRQF_ONESHOT, 1636 dev_name(dev), s); 1637 if (!ret) 1638 return 0; 1639 1640 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1641 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1642 dev_name(dev), s); 1643 if (!ret) 1644 return 0; 1645 1646 #ifdef CONFIG_GPIOLIB 1647 if (s->gpio_valid_mask) 1648 gpiochip_remove(&s->gpio); 1649 #endif 1650 1651 out_ports: 1652 for (i--; i >= 0; i--) { 1653 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1654 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1655 } 1656 1657 kthread_stop(s->kworker_task); 1658 1659 out_clk: 1660 clk_disable_unprepare(s->clk); 1661 1662 return ret; 1663 } 1664 1665 static void sc16is7xx_remove(struct device *dev) 1666 { 1667 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1668 int i; 1669 1670 #ifdef CONFIG_GPIOLIB 1671 if (s->gpio_valid_mask) 1672 gpiochip_remove(&s->gpio); 1673 #endif 1674 1675 for (i = 0; i < s->devtype->nr_uart; i++) { 1676 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1677 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1678 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1679 sc16is7xx_power(&s->p[i].port, 0); 1680 } 1681 1682 kthread_flush_worker(&s->kworker); 1683 kthread_stop(s->kworker_task); 1684 1685 clk_disable_unprepare(s->clk); 1686 } 1687 1688 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1689 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1690 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1691 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1692 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1693 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1694 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1695 { } 1696 }; 1697 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1698 1699 static struct regmap_config regcfg = { 1700 .reg_bits = 7, 1701 .pad_bits = 1, 1702 .val_bits = 8, 1703 .cache_type = REGCACHE_RBTREE, 1704 .volatile_reg = sc16is7xx_regmap_volatile, 1705 .precious_reg = sc16is7xx_regmap_precious, 1706 }; 1707 1708 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1709 static int sc16is7xx_spi_probe(struct spi_device *spi) 1710 { 1711 const struct sc16is7xx_devtype *devtype; 1712 struct regmap *regmap; 1713 int ret; 1714 1715 /* Setup SPI bus */ 1716 spi->bits_per_word = 8; 1717 /* only supports mode 0 on SC16IS762 */ 1718 spi->mode = spi->mode ? : SPI_MODE_0; 1719 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1720 ret = spi_setup(spi); 1721 if (ret) 1722 return ret; 1723 1724 if (spi->dev.of_node) { 1725 devtype = device_get_match_data(&spi->dev); 1726 if (!devtype) 1727 return -ENODEV; 1728 } else { 1729 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1730 1731 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1732 } 1733 1734 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1735 (devtype->nr_uart - 1); 1736 regmap = devm_regmap_init_spi(spi, ®cfg); 1737 1738 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); 1739 } 1740 1741 static void sc16is7xx_spi_remove(struct spi_device *spi) 1742 { 1743 sc16is7xx_remove(&spi->dev); 1744 } 1745 1746 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1747 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1748 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1749 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1750 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1751 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1752 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1753 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1754 { } 1755 }; 1756 1757 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1758 1759 static struct spi_driver sc16is7xx_spi_uart_driver = { 1760 .driver = { 1761 .name = SC16IS7XX_NAME, 1762 .of_match_table = sc16is7xx_dt_ids, 1763 }, 1764 .probe = sc16is7xx_spi_probe, 1765 .remove = sc16is7xx_spi_remove, 1766 .id_table = sc16is7xx_spi_id_table, 1767 }; 1768 1769 MODULE_ALIAS("spi:sc16is7xx"); 1770 #endif 1771 1772 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1773 static int sc16is7xx_i2c_probe(struct i2c_client *i2c) 1774 { 1775 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1776 const struct sc16is7xx_devtype *devtype; 1777 struct regmap *regmap; 1778 1779 if (i2c->dev.of_node) { 1780 devtype = device_get_match_data(&i2c->dev); 1781 if (!devtype) 1782 return -ENODEV; 1783 } else { 1784 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1785 } 1786 1787 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1788 (devtype->nr_uart - 1); 1789 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1790 1791 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); 1792 } 1793 1794 static void sc16is7xx_i2c_remove(struct i2c_client *client) 1795 { 1796 sc16is7xx_remove(&client->dev); 1797 } 1798 1799 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1800 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1801 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1802 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1803 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1804 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1805 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1806 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1807 { } 1808 }; 1809 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1810 1811 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1812 .driver = { 1813 .name = SC16IS7XX_NAME, 1814 .of_match_table = sc16is7xx_dt_ids, 1815 }, 1816 .probe = sc16is7xx_i2c_probe, 1817 .remove = sc16is7xx_i2c_remove, 1818 .id_table = sc16is7xx_i2c_id_table, 1819 }; 1820 1821 #endif 1822 1823 static int __init sc16is7xx_init(void) 1824 { 1825 int ret; 1826 1827 ret = uart_register_driver(&sc16is7xx_uart); 1828 if (ret) { 1829 pr_err("Registering UART driver failed\n"); 1830 return ret; 1831 } 1832 1833 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1834 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1835 if (ret < 0) { 1836 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1837 goto err_i2c; 1838 } 1839 #endif 1840 1841 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1842 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1843 if (ret < 0) { 1844 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1845 goto err_spi; 1846 } 1847 #endif 1848 return ret; 1849 1850 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1851 err_spi: 1852 #endif 1853 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1854 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1855 err_i2c: 1856 #endif 1857 uart_unregister_driver(&sc16is7xx_uart); 1858 return ret; 1859 } 1860 module_init(sc16is7xx_init); 1861 1862 static void __exit sc16is7xx_exit(void) 1863 { 1864 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1865 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1866 #endif 1867 1868 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1869 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1870 #endif 1871 uart_unregister_driver(&sc16is7xx_uart); 1872 } 1873 module_exit(sc16is7xx_exit); 1874 1875 MODULE_LICENSE("GPL"); 1876 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1877 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1878