1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/i2c.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 #include <uapi/linux/sched/types.h> 28 29 #define SC16IS7XX_NAME "sc16is7xx" 30 #define SC16IS7XX_MAX_DEVS 8 31 32 /* SC16IS7XX register definitions */ 33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 46 * - only on 75x/76x 47 */ 48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 49 * - only on 75x/76x 50 */ 51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 58 59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 62 63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 66 67 /* Enhanced Register set: Only if (LCR == 0xBF) */ 68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 73 74 /* IER register bits */ 75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 77 * interrupt */ 78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 79 * interrupt */ 80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 81 * interrupt */ 82 83 /* IER register bits - write only if (EFR[4] == 1) */ 84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 88 89 /* FCR register bits */ 90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 95 96 /* FCR register bits - write only if (EFR[4] == 1) */ 97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 99 100 /* IIR register bits */ 101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 108 * - only on 75x/76x 109 */ 110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 111 * - only on 75x/76x 112 */ 113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 115 * from active (LOW) 116 * to inactive (HIGH) 117 */ 118 /* LCR register bits */ 119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 121 * 122 * Word length bits table: 123 * 00 -> 5 bit words 124 * 01 -> 6 bit words 125 * 10 -> 7 bit words 126 * 11 -> 8 bit words 127 */ 128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 129 * 130 * STOP length bit table: 131 * 0 -> 1 stop bit 132 * 1 -> 1-1.5 stop bits if 133 * word length is 5, 134 * 2 stop bits otherwise 135 */ 136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 146 * reg set */ 147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 148 * reg set */ 149 150 /* MCR register bits */ 151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 152 * - only on 75x/76x 153 */ 154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 158 * - write enabled 159 * if (EFR[4] == 1) 160 */ 161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 162 * - write enabled 163 * if (EFR[4] == 1) 164 */ 165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 166 * - write enabled 167 * if (EFR[4] == 1) 168 */ 169 170 /* LSR register bits */ 171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 180 181 /* MSR register bits */ 182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 184 * or (IO4) 185 * - only on 75x/76x 186 */ 187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 188 * or (IO7) 189 * - only on 75x/76x 190 */ 191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 192 * or (IO6) 193 * - only on 75x/76x 194 */ 195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 197 * - only on 75x/76x 198 */ 199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 200 * - only on 75x/76x 201 */ 202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 206 207 /* 208 * TCR register bits 209 * TCR trigger levels are available from 0 to 60 characters with a granularity 210 * of four. 211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 212 * no built-in hardware check to make sure this condition is met. Also, the TCR 213 * must be programmed with this condition before auto RTS or software flow 214 * control is enabled to avoid spurious operation of the device. 215 */ 216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 218 219 /* 220 * TLR register bits 221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 223 * trigger levels. Trigger levels from 4 characters to 60 characters are 224 * available with a granularity of four. 225 * 226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 228 * the trigger level defined in FCR is discarded. This applies to both transmit 229 * FIFO and receive FIFO trigger level setting. 230 * 231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 232 * default state, that is, '00'. 233 */ 234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 236 237 /* IOControl register bits (Only 750/760) */ 238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 239 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */ 240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 241 242 /* EFCR register bits */ 243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 244 * mode (RS485) */ 245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 250 * 0 = rate upto 115.2 kbit/s 251 * - Only 750/760 252 * 1 = rate upto 1.152 Mbit/s 253 * - Only 760 254 */ 255 256 /* EFR register bits */ 257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 261 * and writing to IER[7:4], 262 * FCR[5:4], MCR[7:5] 263 */ 264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 266 * 267 * SWFLOW bits 3 & 2 table: 268 * 00 -> no transmitter flow 269 * control 270 * 01 -> transmitter generates 271 * XON2 and XOFF2 272 * 10 -> transmitter generates 273 * XON1 and XOFF1 274 * 11 -> transmitter generates 275 * XON1, XON2, XOFF1 and 276 * XOFF2 277 */ 278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 280 * 281 * SWFLOW bits 3 & 2 table: 282 * 00 -> no received flow 283 * control 284 * 01 -> receiver compares 285 * XON2 and XOFF2 286 * 10 -> receiver compares 287 * XON1 and XOFF1 288 * 11 -> receiver compares 289 * XON1, XON2, XOFF1 and 290 * XOFF2 291 */ 292 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 293 SC16IS7XX_EFR_AUTOCTS_BIT | \ 294 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 295 SC16IS7XX_EFR_SWFLOW3_BIT | \ 296 SC16IS7XX_EFR_SWFLOW2_BIT | \ 297 SC16IS7XX_EFR_SWFLOW1_BIT | \ 298 SC16IS7XX_EFR_SWFLOW0_BIT) 299 300 301 /* Misc definitions */ 302 #define SC16IS7XX_FIFO_SIZE (64) 303 #define SC16IS7XX_REG_SHIFT 2 304 305 struct sc16is7xx_devtype { 306 char name[10]; 307 int nr_gpio; 308 int nr_uart; 309 int has_mctrl; 310 }; 311 312 #define SC16IS7XX_RECONF_MD (1 << 0) 313 #define SC16IS7XX_RECONF_IER (1 << 1) 314 #define SC16IS7XX_RECONF_RS485 (1 << 2) 315 316 struct sc16is7xx_one_config { 317 unsigned int flags; 318 u8 ier_mask; 319 u8 ier_val; 320 }; 321 322 struct sc16is7xx_one { 323 struct uart_port port; 324 u8 line; 325 struct kthread_work tx_work; 326 struct kthread_work reg_work; 327 struct kthread_delayed_work ms_work; 328 struct sc16is7xx_one_config config; 329 bool irda_mode; 330 unsigned int old_mctrl; 331 }; 332 333 struct sc16is7xx_port { 334 const struct sc16is7xx_devtype *devtype; 335 struct regmap *regmap; 336 struct clk *clk; 337 #ifdef CONFIG_GPIOLIB 338 struct gpio_chip gpio; 339 #endif 340 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 341 struct kthread_worker kworker; 342 struct task_struct *kworker_task; 343 struct mutex efr_lock; 344 struct sc16is7xx_one p[]; 345 }; 346 347 static unsigned long sc16is7xx_lines; 348 349 static struct uart_driver sc16is7xx_uart = { 350 .owner = THIS_MODULE, 351 .dev_name = "ttySC", 352 .nr = SC16IS7XX_MAX_DEVS, 353 }; 354 355 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 356 static void sc16is7xx_stop_tx(struct uart_port *port); 357 358 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 359 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 360 361 static int sc16is7xx_line(struct uart_port *port) 362 { 363 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 364 365 return one->line; 366 } 367 368 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 369 { 370 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 371 unsigned int val = 0; 372 const u8 line = sc16is7xx_line(port); 373 374 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); 375 376 return val; 377 } 378 379 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 380 { 381 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 382 const u8 line = sc16is7xx_line(port); 383 384 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); 385 } 386 387 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 388 { 389 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 390 const u8 line = sc16is7xx_line(port); 391 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; 392 393 regcache_cache_bypass(s->regmap, true); 394 regmap_raw_read(s->regmap, addr, s->buf, rxlen); 395 regcache_cache_bypass(s->regmap, false); 396 } 397 398 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 399 { 400 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 401 const u8 line = sc16is7xx_line(port); 402 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line; 403 404 /* 405 * Don't send zero-length data, at least on SPI it confuses the chip 406 * delivering wrong TXLVL data. 407 */ 408 if (unlikely(!to_send)) 409 return; 410 411 regcache_cache_bypass(s->regmap, true); 412 regmap_raw_write(s->regmap, addr, s->buf, to_send); 413 regcache_cache_bypass(s->regmap, false); 414 } 415 416 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 417 u8 mask, u8 val) 418 { 419 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 420 const u8 line = sc16is7xx_line(port); 421 422 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, 423 mask, val); 424 } 425 426 static int sc16is7xx_alloc_line(void) 427 { 428 int i; 429 430 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG); 431 432 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++) 433 if (!test_and_set_bit(i, &sc16is7xx_lines)) 434 break; 435 436 return i; 437 } 438 439 static void sc16is7xx_power(struct uart_port *port, int on) 440 { 441 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 442 SC16IS7XX_IER_SLEEP_BIT, 443 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 444 } 445 446 static const struct sc16is7xx_devtype sc16is74x_devtype = { 447 .name = "SC16IS74X", 448 .nr_gpio = 0, 449 .nr_uart = 1, 450 .has_mctrl = 0, 451 }; 452 453 static const struct sc16is7xx_devtype sc16is750_devtype = { 454 .name = "SC16IS750", 455 .nr_gpio = 4, 456 .nr_uart = 1, 457 .has_mctrl = 1, 458 }; 459 460 static const struct sc16is7xx_devtype sc16is752_devtype = { 461 .name = "SC16IS752", 462 .nr_gpio = 0, 463 .nr_uart = 2, 464 .has_mctrl = 1, 465 }; 466 467 static const struct sc16is7xx_devtype sc16is760_devtype = { 468 .name = "SC16IS760", 469 .nr_gpio = 4, 470 .nr_uart = 1, 471 .has_mctrl = 1, 472 }; 473 474 static const struct sc16is7xx_devtype sc16is762_devtype = { 475 .name = "SC16IS762", 476 .nr_gpio = 0, 477 .nr_uart = 2, 478 .has_mctrl = 1, 479 }; 480 481 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 482 { 483 switch (reg >> SC16IS7XX_REG_SHIFT) { 484 case SC16IS7XX_RHR_REG: 485 case SC16IS7XX_IIR_REG: 486 case SC16IS7XX_LSR_REG: 487 case SC16IS7XX_MSR_REG: 488 case SC16IS7XX_TXLVL_REG: 489 case SC16IS7XX_RXLVL_REG: 490 case SC16IS7XX_IOSTATE_REG: 491 return true; 492 default: 493 break; 494 } 495 496 return false; 497 } 498 499 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 500 { 501 switch (reg >> SC16IS7XX_REG_SHIFT) { 502 case SC16IS7XX_RHR_REG: 503 return true; 504 default: 505 break; 506 } 507 508 return false; 509 } 510 511 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 512 { 513 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 514 u8 lcr; 515 u8 prescaler = 0; 516 unsigned long clk = port->uartclk, div = clk / 16 / baud; 517 518 if (div > 0xffff) { 519 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 520 div /= 4; 521 } 522 523 /* In an amazing feat of design, the Enhanced Features Register shares 524 * the address of the Interrupt Identification Register, and is 525 * switched in by writing a magic value (0xbf) to the Line Control 526 * Register. Any interrupt firing during this time will see the EFR 527 * where it expects the IIR to be, leading to "Unexpected interrupt" 528 * messages. 529 * 530 * Prevent this possibility by claiming a mutex while accessing the 531 * EFR, and claiming the same mutex from within the interrupt handler. 532 * This is similar to disabling the interrupt, but that doesn't work 533 * because the bulk of the interrupt processing is run as a workqueue 534 * job in thread context. 535 */ 536 mutex_lock(&s->efr_lock); 537 538 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 539 540 /* Open the LCR divisors for configuration */ 541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 542 SC16IS7XX_LCR_CONF_MODE_B); 543 544 /* Enable enhanced features */ 545 regcache_cache_bypass(s->regmap, true); 546 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 547 SC16IS7XX_EFR_ENABLE_BIT, 548 SC16IS7XX_EFR_ENABLE_BIT); 549 550 regcache_cache_bypass(s->regmap, false); 551 552 /* Put LCR back to the normal mode */ 553 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 554 555 mutex_unlock(&s->efr_lock); 556 557 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 558 SC16IS7XX_MCR_CLKSEL_BIT, 559 prescaler); 560 561 /* Open the LCR divisors for configuration */ 562 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 563 SC16IS7XX_LCR_CONF_MODE_A); 564 565 /* Write the new divisor */ 566 regcache_cache_bypass(s->regmap, true); 567 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 568 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 569 regcache_cache_bypass(s->regmap, false); 570 571 /* Put LCR back to the normal mode */ 572 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 573 574 return DIV_ROUND_CLOSEST(clk / 16, div); 575 } 576 577 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 578 unsigned int iir) 579 { 580 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 581 unsigned int lsr = 0, ch, flag, bytes_read, i; 582 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 583 584 if (unlikely(rxlen >= sizeof(s->buf))) { 585 dev_warn_ratelimited(port->dev, 586 "ttySC%i: Possible RX FIFO overrun: %d\n", 587 port->line, rxlen); 588 port->icount.buf_overrun++; 589 /* Ensure sanity of RX level */ 590 rxlen = sizeof(s->buf); 591 } 592 593 while (rxlen) { 594 /* Only read lsr if there are possible errors in FIFO */ 595 if (read_lsr) { 596 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 597 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 598 read_lsr = false; /* No errors left in FIFO */ 599 } else 600 lsr = 0; 601 602 if (read_lsr) { 603 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 604 bytes_read = 1; 605 } else { 606 sc16is7xx_fifo_read(port, rxlen); 607 bytes_read = rxlen; 608 } 609 610 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 611 612 port->icount.rx++; 613 flag = TTY_NORMAL; 614 615 if (unlikely(lsr)) { 616 if (lsr & SC16IS7XX_LSR_BI_BIT) { 617 port->icount.brk++; 618 if (uart_handle_break(port)) 619 continue; 620 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 621 port->icount.parity++; 622 else if (lsr & SC16IS7XX_LSR_FE_BIT) 623 port->icount.frame++; 624 else if (lsr & SC16IS7XX_LSR_OE_BIT) 625 port->icount.overrun++; 626 627 lsr &= port->read_status_mask; 628 if (lsr & SC16IS7XX_LSR_BI_BIT) 629 flag = TTY_BREAK; 630 else if (lsr & SC16IS7XX_LSR_PE_BIT) 631 flag = TTY_PARITY; 632 else if (lsr & SC16IS7XX_LSR_FE_BIT) 633 flag = TTY_FRAME; 634 else if (lsr & SC16IS7XX_LSR_OE_BIT) 635 flag = TTY_OVERRUN; 636 } 637 638 for (i = 0; i < bytes_read; ++i) { 639 ch = s->buf[i]; 640 if (uart_handle_sysrq_char(port, ch)) 641 continue; 642 643 if (lsr & port->ignore_status_mask) 644 continue; 645 646 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 647 flag); 648 } 649 rxlen -= bytes_read; 650 } 651 652 tty_flip_buffer_push(&port->state->port); 653 } 654 655 static void sc16is7xx_handle_tx(struct uart_port *port) 656 { 657 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 658 struct circ_buf *xmit = &port->state->xmit; 659 unsigned int txlen, to_send, i; 660 unsigned long flags; 661 662 if (unlikely(port->x_char)) { 663 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 664 port->icount.tx++; 665 port->x_char = 0; 666 return; 667 } 668 669 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 670 spin_lock_irqsave(&port->lock, flags); 671 sc16is7xx_stop_tx(port); 672 spin_unlock_irqrestore(&port->lock, flags); 673 return; 674 } 675 676 /* Get length of data pending in circular buffer */ 677 to_send = uart_circ_chars_pending(xmit); 678 if (likely(to_send)) { 679 /* Limit to size of TX FIFO */ 680 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 681 if (txlen > SC16IS7XX_FIFO_SIZE) { 682 dev_err_ratelimited(port->dev, 683 "chip reports %d free bytes in TX fifo, but it only has %d", 684 txlen, SC16IS7XX_FIFO_SIZE); 685 txlen = 0; 686 } 687 to_send = (to_send > txlen) ? txlen : to_send; 688 689 /* Add data to send */ 690 port->icount.tx += to_send; 691 692 /* Convert to linear buffer */ 693 for (i = 0; i < to_send; ++i) { 694 s->buf[i] = xmit->buf[xmit->tail]; 695 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 696 } 697 698 sc16is7xx_fifo_write(port, to_send); 699 } 700 701 spin_lock_irqsave(&port->lock, flags); 702 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 703 uart_write_wakeup(port); 704 705 if (uart_circ_empty(xmit)) 706 sc16is7xx_stop_tx(port); 707 spin_unlock_irqrestore(&port->lock, flags); 708 } 709 710 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 711 { 712 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 713 unsigned int mctrl = 0; 714 715 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 716 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 717 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 718 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 719 return mctrl; 720 } 721 722 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 723 { 724 struct uart_port *port = &one->port; 725 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 726 unsigned long flags; 727 unsigned int status, changed; 728 729 lockdep_assert_held_once(&s->efr_lock); 730 731 status = sc16is7xx_get_hwmctrl(port); 732 changed = status ^ one->old_mctrl; 733 734 if (changed == 0) 735 return; 736 737 one->old_mctrl = status; 738 739 spin_lock_irqsave(&port->lock, flags); 740 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 741 port->icount.rng++; 742 if (changed & TIOCM_DSR) 743 port->icount.dsr++; 744 if (changed & TIOCM_CAR) 745 uart_handle_dcd_change(port, status & TIOCM_CAR); 746 if (changed & TIOCM_CTS) 747 uart_handle_cts_change(port, status & TIOCM_CTS); 748 749 wake_up_interruptible(&port->state->port.delta_msr_wait); 750 spin_unlock_irqrestore(&port->lock, flags); 751 } 752 753 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 754 { 755 struct uart_port *port = &s->p[portno].port; 756 757 do { 758 unsigned int iir, rxlen; 759 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 760 761 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 762 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 763 return false; 764 765 iir &= SC16IS7XX_IIR_ID_MASK; 766 767 switch (iir) { 768 case SC16IS7XX_IIR_RDI_SRC: 769 case SC16IS7XX_IIR_RLSE_SRC: 770 case SC16IS7XX_IIR_RTOI_SRC: 771 case SC16IS7XX_IIR_XOFFI_SRC: 772 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 773 if (rxlen) 774 sc16is7xx_handle_rx(port, rxlen, iir); 775 break; 776 /* CTSRTS interrupt comes only when CTS goes inactive */ 777 case SC16IS7XX_IIR_CTSRTS_SRC: 778 case SC16IS7XX_IIR_MSI_SRC: 779 sc16is7xx_update_mlines(one); 780 break; 781 case SC16IS7XX_IIR_THRI_SRC: 782 sc16is7xx_handle_tx(port); 783 break; 784 default: 785 dev_err_ratelimited(port->dev, 786 "ttySC%i: Unexpected interrupt: %x", 787 port->line, iir); 788 break; 789 } 790 } while (0); 791 return true; 792 } 793 794 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 795 { 796 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 797 798 mutex_lock(&s->efr_lock); 799 800 while (1) { 801 bool keep_polling = false; 802 int i; 803 804 for (i = 0; i < s->devtype->nr_uart; ++i) 805 keep_polling |= sc16is7xx_port_irq(s, i); 806 if (!keep_polling) 807 break; 808 } 809 810 mutex_unlock(&s->efr_lock); 811 812 return IRQ_HANDLED; 813 } 814 815 static void sc16is7xx_tx_proc(struct kthread_work *ws) 816 { 817 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 818 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 819 unsigned long flags; 820 821 if ((port->rs485.flags & SER_RS485_ENABLED) && 822 (port->rs485.delay_rts_before_send > 0)) 823 msleep(port->rs485.delay_rts_before_send); 824 825 mutex_lock(&s->efr_lock); 826 sc16is7xx_handle_tx(port); 827 mutex_unlock(&s->efr_lock); 828 829 spin_lock_irqsave(&port->lock, flags); 830 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 831 spin_unlock_irqrestore(&port->lock, flags); 832 } 833 834 static void sc16is7xx_reconf_rs485(struct uart_port *port) 835 { 836 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 837 SC16IS7XX_EFCR_RTS_INVERT_BIT; 838 u32 efcr = 0; 839 struct serial_rs485 *rs485 = &port->rs485; 840 unsigned long irqflags; 841 842 spin_lock_irqsave(&port->lock, irqflags); 843 if (rs485->flags & SER_RS485_ENABLED) { 844 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 845 846 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 847 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 848 } 849 spin_unlock_irqrestore(&port->lock, irqflags); 850 851 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 852 } 853 854 static void sc16is7xx_reg_proc(struct kthread_work *ws) 855 { 856 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 857 struct sc16is7xx_one_config config; 858 unsigned long irqflags; 859 860 spin_lock_irqsave(&one->port.lock, irqflags); 861 config = one->config; 862 memset(&one->config, 0, sizeof(one->config)); 863 spin_unlock_irqrestore(&one->port.lock, irqflags); 864 865 if (config.flags & SC16IS7XX_RECONF_MD) { 866 u8 mcr = 0; 867 868 /* Device ignores RTS setting when hardware flow is enabled */ 869 if (one->port.mctrl & TIOCM_RTS) 870 mcr |= SC16IS7XX_MCR_RTS_BIT; 871 872 if (one->port.mctrl & TIOCM_DTR) 873 mcr |= SC16IS7XX_MCR_DTR_BIT; 874 875 if (one->port.mctrl & TIOCM_LOOP) 876 mcr |= SC16IS7XX_MCR_LOOP_BIT; 877 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 878 SC16IS7XX_MCR_RTS_BIT | 879 SC16IS7XX_MCR_DTR_BIT | 880 SC16IS7XX_MCR_LOOP_BIT, 881 mcr); 882 } 883 884 if (config.flags & SC16IS7XX_RECONF_IER) 885 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 886 config.ier_mask, config.ier_val); 887 888 if (config.flags & SC16IS7XX_RECONF_RS485) 889 sc16is7xx_reconf_rs485(&one->port); 890 } 891 892 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 893 { 894 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 895 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 896 897 lockdep_assert_held_once(&port->lock); 898 899 one->config.flags |= SC16IS7XX_RECONF_IER; 900 one->config.ier_mask |= bit; 901 one->config.ier_val &= ~bit; 902 kthread_queue_work(&s->kworker, &one->reg_work); 903 } 904 905 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 906 { 907 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 908 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 909 910 lockdep_assert_held_once(&port->lock); 911 912 one->config.flags |= SC16IS7XX_RECONF_IER; 913 one->config.ier_mask |= bit; 914 one->config.ier_val |= bit; 915 kthread_queue_work(&s->kworker, &one->reg_work); 916 } 917 918 static void sc16is7xx_stop_tx(struct uart_port *port) 919 { 920 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 921 } 922 923 static void sc16is7xx_stop_rx(struct uart_port *port) 924 { 925 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 926 } 927 928 static void sc16is7xx_ms_proc(struct kthread_work *ws) 929 { 930 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 931 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 932 933 if (one->port.state) { 934 mutex_lock(&s->efr_lock); 935 sc16is7xx_update_mlines(one); 936 mutex_unlock(&s->efr_lock); 937 938 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 939 } 940 } 941 942 static void sc16is7xx_enable_ms(struct uart_port *port) 943 { 944 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 945 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 946 947 lockdep_assert_held_once(&port->lock); 948 949 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 950 } 951 952 static void sc16is7xx_start_tx(struct uart_port *port) 953 { 954 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 955 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 956 957 kthread_queue_work(&s->kworker, &one->tx_work); 958 } 959 960 static void sc16is7xx_throttle(struct uart_port *port) 961 { 962 unsigned long flags; 963 964 /* 965 * Hardware flow control is enabled and thus the device ignores RTS 966 * value set in MCR register. Stop reading data from RX FIFO so the 967 * AutoRTS feature will de-activate RTS output. 968 */ 969 spin_lock_irqsave(&port->lock, flags); 970 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 971 spin_unlock_irqrestore(&port->lock, flags); 972 } 973 974 static void sc16is7xx_unthrottle(struct uart_port *port) 975 { 976 unsigned long flags; 977 978 spin_lock_irqsave(&port->lock, flags); 979 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 980 spin_unlock_irqrestore(&port->lock, flags); 981 } 982 983 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 984 { 985 unsigned int lsr; 986 987 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 988 989 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 990 } 991 992 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 993 { 994 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 995 996 /* Called with port lock taken so we can only return cached value */ 997 return one->old_mctrl; 998 } 999 1000 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 1001 { 1002 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1003 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1004 1005 one->config.flags |= SC16IS7XX_RECONF_MD; 1006 kthread_queue_work(&s->kworker, &one->reg_work); 1007 } 1008 1009 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1010 { 1011 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1012 SC16IS7XX_LCR_TXBREAK_BIT, 1013 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1014 } 1015 1016 static void sc16is7xx_set_termios(struct uart_port *port, 1017 struct ktermios *termios, 1018 struct ktermios *old) 1019 { 1020 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1021 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1022 unsigned int lcr, flow = 0; 1023 int baud; 1024 unsigned long flags; 1025 1026 kthread_cancel_delayed_work_sync(&one->ms_work); 1027 1028 /* Mask termios capabilities we don't support */ 1029 termios->c_cflag &= ~CMSPAR; 1030 1031 /* Word size */ 1032 switch (termios->c_cflag & CSIZE) { 1033 case CS5: 1034 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1035 break; 1036 case CS6: 1037 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1038 break; 1039 case CS7: 1040 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1041 break; 1042 case CS8: 1043 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1044 break; 1045 default: 1046 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1047 termios->c_cflag &= ~CSIZE; 1048 termios->c_cflag |= CS8; 1049 break; 1050 } 1051 1052 /* Parity */ 1053 if (termios->c_cflag & PARENB) { 1054 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1055 if (!(termios->c_cflag & PARODD)) 1056 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1057 } 1058 1059 /* Stop bits */ 1060 if (termios->c_cflag & CSTOPB) 1061 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1062 1063 /* Set read status mask */ 1064 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1065 if (termios->c_iflag & INPCK) 1066 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1067 SC16IS7XX_LSR_FE_BIT; 1068 if (termios->c_iflag & (BRKINT | PARMRK)) 1069 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1070 1071 /* Set status ignore mask */ 1072 port->ignore_status_mask = 0; 1073 if (termios->c_iflag & IGNBRK) 1074 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1075 if (!(termios->c_cflag & CREAD)) 1076 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1077 1078 /* As above, claim the mutex while accessing the EFR. */ 1079 mutex_lock(&s->efr_lock); 1080 1081 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1082 SC16IS7XX_LCR_CONF_MODE_B); 1083 1084 /* Configure flow control */ 1085 regcache_cache_bypass(s->regmap, true); 1086 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1087 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1088 1089 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1090 if (termios->c_cflag & CRTSCTS) { 1091 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1092 SC16IS7XX_EFR_AUTORTS_BIT; 1093 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1094 } 1095 if (termios->c_iflag & IXON) 1096 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1097 if (termios->c_iflag & IXOFF) 1098 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1099 1100 sc16is7xx_port_update(port, 1101 SC16IS7XX_EFR_REG, 1102 SC16IS7XX_EFR_FLOWCTRL_BITS, 1103 flow); 1104 regcache_cache_bypass(s->regmap, false); 1105 1106 /* Update LCR register */ 1107 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1108 1109 mutex_unlock(&s->efr_lock); 1110 1111 /* Get baud rate generator configuration */ 1112 baud = uart_get_baud_rate(port, termios, old, 1113 port->uartclk / 16 / 4 / 0xffff, 1114 port->uartclk / 16); 1115 1116 /* Setup baudrate generator */ 1117 baud = sc16is7xx_set_baud(port, baud); 1118 1119 spin_lock_irqsave(&port->lock, flags); 1120 1121 /* Update timeout according to new baud rate */ 1122 uart_update_timeout(port, termios->c_cflag, baud); 1123 1124 if (UART_ENABLE_MS(port, termios->c_cflag)) 1125 sc16is7xx_enable_ms(port); 1126 1127 spin_unlock_irqrestore(&port->lock, flags); 1128 } 1129 1130 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1131 struct serial_rs485 *rs485) 1132 { 1133 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1134 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1135 1136 if (rs485->flags & SER_RS485_ENABLED) { 1137 /* 1138 * RTS signal is handled by HW, it's timing can't be influenced. 1139 * However, it's sometimes useful to delay TX even without RTS 1140 * control therefore we try to handle .delay_rts_before_send. 1141 */ 1142 if (rs485->delay_rts_after_send) 1143 return -EINVAL; 1144 } 1145 1146 one->config.flags |= SC16IS7XX_RECONF_RS485; 1147 kthread_queue_work(&s->kworker, &one->reg_work); 1148 1149 return 0; 1150 } 1151 1152 static int sc16is7xx_startup(struct uart_port *port) 1153 { 1154 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1155 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1156 unsigned int val; 1157 unsigned long flags; 1158 1159 sc16is7xx_power(port, 1); 1160 1161 /* Reset FIFOs*/ 1162 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1163 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1164 udelay(5); 1165 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1166 SC16IS7XX_FCR_FIFO_BIT); 1167 1168 /* Enable EFR */ 1169 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1170 SC16IS7XX_LCR_CONF_MODE_B); 1171 1172 regcache_cache_bypass(s->regmap, true); 1173 1174 /* Enable write access to enhanced features and internal clock div */ 1175 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1176 SC16IS7XX_EFR_ENABLE_BIT, 1177 SC16IS7XX_EFR_ENABLE_BIT); 1178 1179 /* Enable TCR/TLR */ 1180 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1181 SC16IS7XX_MCR_TCRTLR_BIT, 1182 SC16IS7XX_MCR_TCRTLR_BIT); 1183 1184 /* Configure flow control levels */ 1185 /* Flow control halt level 48, resume level 24 */ 1186 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1187 SC16IS7XX_TCR_RX_RESUME(24) | 1188 SC16IS7XX_TCR_RX_HALT(48)); 1189 1190 regcache_cache_bypass(s->regmap, false); 1191 1192 /* Now, initialize the UART */ 1193 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1194 1195 /* Enable IrDA mode if requested in DT */ 1196 /* This bit must be written with LCR[7] = 0 */ 1197 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1198 SC16IS7XX_MCR_IRDA_BIT, 1199 one->irda_mode ? 1200 SC16IS7XX_MCR_IRDA_BIT : 0); 1201 1202 /* Enable the Rx and Tx FIFO */ 1203 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1204 SC16IS7XX_EFCR_RXDISABLE_BIT | 1205 SC16IS7XX_EFCR_TXDISABLE_BIT, 1206 0); 1207 1208 /* Enable RX, CTS change and modem lines interrupts */ 1209 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1210 SC16IS7XX_IER_MSI_BIT; 1211 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1212 1213 /* Enable modem status polling */ 1214 spin_lock_irqsave(&port->lock, flags); 1215 sc16is7xx_enable_ms(port); 1216 spin_unlock_irqrestore(&port->lock, flags); 1217 1218 return 0; 1219 } 1220 1221 static void sc16is7xx_shutdown(struct uart_port *port) 1222 { 1223 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1224 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1225 1226 kthread_cancel_delayed_work_sync(&one->ms_work); 1227 1228 /* Disable all interrupts */ 1229 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1230 /* Disable TX/RX */ 1231 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1232 SC16IS7XX_EFCR_RXDISABLE_BIT | 1233 SC16IS7XX_EFCR_TXDISABLE_BIT, 1234 SC16IS7XX_EFCR_RXDISABLE_BIT | 1235 SC16IS7XX_EFCR_TXDISABLE_BIT); 1236 1237 sc16is7xx_power(port, 0); 1238 1239 kthread_flush_worker(&s->kworker); 1240 } 1241 1242 static const char *sc16is7xx_type(struct uart_port *port) 1243 { 1244 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1245 1246 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1247 } 1248 1249 static int sc16is7xx_request_port(struct uart_port *port) 1250 { 1251 /* Do nothing */ 1252 return 0; 1253 } 1254 1255 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1256 { 1257 if (flags & UART_CONFIG_TYPE) 1258 port->type = PORT_SC16IS7XX; 1259 } 1260 1261 static int sc16is7xx_verify_port(struct uart_port *port, 1262 struct serial_struct *s) 1263 { 1264 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1265 return -EINVAL; 1266 if (s->irq != port->irq) 1267 return -EINVAL; 1268 1269 return 0; 1270 } 1271 1272 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1273 unsigned int oldstate) 1274 { 1275 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1276 } 1277 1278 static void sc16is7xx_null_void(struct uart_port *port) 1279 { 1280 /* Do nothing */ 1281 } 1282 1283 static const struct uart_ops sc16is7xx_ops = { 1284 .tx_empty = sc16is7xx_tx_empty, 1285 .set_mctrl = sc16is7xx_set_mctrl, 1286 .get_mctrl = sc16is7xx_get_mctrl, 1287 .stop_tx = sc16is7xx_stop_tx, 1288 .start_tx = sc16is7xx_start_tx, 1289 .throttle = sc16is7xx_throttle, 1290 .unthrottle = sc16is7xx_unthrottle, 1291 .stop_rx = sc16is7xx_stop_rx, 1292 .enable_ms = sc16is7xx_enable_ms, 1293 .break_ctl = sc16is7xx_break_ctl, 1294 .startup = sc16is7xx_startup, 1295 .shutdown = sc16is7xx_shutdown, 1296 .set_termios = sc16is7xx_set_termios, 1297 .type = sc16is7xx_type, 1298 .request_port = sc16is7xx_request_port, 1299 .release_port = sc16is7xx_null_void, 1300 .config_port = sc16is7xx_config_port, 1301 .verify_port = sc16is7xx_verify_port, 1302 .pm = sc16is7xx_pm, 1303 }; 1304 1305 #ifdef CONFIG_GPIOLIB 1306 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1307 { 1308 unsigned int val; 1309 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1310 struct uart_port *port = &s->p[0].port; 1311 1312 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1313 1314 return !!(val & BIT(offset)); 1315 } 1316 1317 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1318 { 1319 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1320 struct uart_port *port = &s->p[0].port; 1321 1322 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1323 val ? BIT(offset) : 0); 1324 } 1325 1326 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1327 unsigned offset) 1328 { 1329 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1330 struct uart_port *port = &s->p[0].port; 1331 1332 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1333 1334 return 0; 1335 } 1336 1337 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1338 unsigned offset, int val) 1339 { 1340 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1341 struct uart_port *port = &s->p[0].port; 1342 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1343 1344 if (val) 1345 state |= BIT(offset); 1346 else 1347 state &= ~BIT(offset); 1348 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1349 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1350 BIT(offset)); 1351 1352 return 0; 1353 } 1354 #endif 1355 1356 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1357 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1358 .delay_rts_before_send = 1, 1359 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1360 }; 1361 1362 static int sc16is7xx_probe(struct device *dev, 1363 const struct sc16is7xx_devtype *devtype, 1364 struct regmap *regmap, int irq) 1365 { 1366 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1367 unsigned int val; 1368 u32 uartclk = 0; 1369 int i, ret; 1370 struct sc16is7xx_port *s; 1371 1372 if (IS_ERR(regmap)) 1373 return PTR_ERR(regmap); 1374 1375 /* 1376 * This device does not have an identification register that would 1377 * tell us if we are really connected to the correct device. 1378 * The best we can do is to check if communication is at all possible. 1379 */ 1380 ret = regmap_read(regmap, 1381 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val); 1382 if (ret < 0) 1383 return -EPROBE_DEFER; 1384 1385 /* Alloc port structure */ 1386 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1387 if (!s) { 1388 dev_err(dev, "Error allocating port structure\n"); 1389 return -ENOMEM; 1390 } 1391 1392 /* Always ask for fixed clock rate from a property. */ 1393 device_property_read_u32(dev, "clock-frequency", &uartclk); 1394 1395 s->clk = devm_clk_get_optional(dev, NULL); 1396 if (IS_ERR(s->clk)) 1397 return PTR_ERR(s->clk); 1398 1399 ret = clk_prepare_enable(s->clk); 1400 if (ret) 1401 return ret; 1402 1403 freq = clk_get_rate(s->clk); 1404 if (freq == 0) { 1405 if (uartclk) 1406 freq = uartclk; 1407 if (pfreq) 1408 freq = *pfreq; 1409 if (freq) 1410 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1411 else 1412 return -EINVAL; 1413 } 1414 1415 s->regmap = regmap; 1416 s->devtype = devtype; 1417 dev_set_drvdata(dev, s); 1418 mutex_init(&s->efr_lock); 1419 1420 kthread_init_worker(&s->kworker); 1421 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1422 "sc16is7xx"); 1423 if (IS_ERR(s->kworker_task)) { 1424 ret = PTR_ERR(s->kworker_task); 1425 goto out_clk; 1426 } 1427 sched_set_fifo(s->kworker_task); 1428 1429 #ifdef CONFIG_GPIOLIB 1430 if (devtype->nr_gpio) { 1431 /* Setup GPIO cotroller */ 1432 s->gpio.owner = THIS_MODULE; 1433 s->gpio.parent = dev; 1434 s->gpio.label = dev_name(dev); 1435 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1436 s->gpio.get = sc16is7xx_gpio_get; 1437 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1438 s->gpio.set = sc16is7xx_gpio_set; 1439 s->gpio.base = -1; 1440 s->gpio.ngpio = devtype->nr_gpio; 1441 s->gpio.can_sleep = 1; 1442 ret = gpiochip_add_data(&s->gpio, s); 1443 if (ret) 1444 goto out_thread; 1445 } 1446 #endif 1447 1448 /* reset device, purging any pending irq / data */ 1449 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, 1450 SC16IS7XX_IOCONTROL_SRESET_BIT); 1451 1452 for (i = 0; i < devtype->nr_uart; ++i) { 1453 s->p[i].line = i; 1454 /* Initialize port data */ 1455 s->p[i].port.dev = dev; 1456 s->p[i].port.irq = irq; 1457 s->p[i].port.type = PORT_SC16IS7XX; 1458 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1459 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1460 s->p[i].port.iobase = i; 1461 s->p[i].port.iotype = UPIO_PORT; 1462 s->p[i].port.uartclk = freq; 1463 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1464 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1465 s->p[i].port.ops = &sc16is7xx_ops; 1466 s->p[i].old_mctrl = 0; 1467 s->p[i].port.line = sc16is7xx_alloc_line(); 1468 1469 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1470 ret = -ENOMEM; 1471 goto out_ports; 1472 } 1473 1474 /* Disable all interrupts */ 1475 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1476 /* Disable TX/RX */ 1477 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1478 SC16IS7XX_EFCR_RXDISABLE_BIT | 1479 SC16IS7XX_EFCR_TXDISABLE_BIT); 1480 1481 /* Use GPIO lines as modem status registers */ 1482 if (devtype->has_mctrl) 1483 sc16is7xx_port_write(&s->p[i].port, 1484 SC16IS7XX_IOCONTROL_REG, 1485 SC16IS7XX_IOCONTROL_MODEM_BIT); 1486 1487 /* Initialize kthread work structs */ 1488 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1489 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1490 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1491 /* Register port */ 1492 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1493 1494 /* Enable EFR */ 1495 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1496 SC16IS7XX_LCR_CONF_MODE_B); 1497 1498 regcache_cache_bypass(s->regmap, true); 1499 1500 /* Enable write access to enhanced features */ 1501 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1502 SC16IS7XX_EFR_ENABLE_BIT); 1503 1504 regcache_cache_bypass(s->regmap, false); 1505 1506 /* Restore access to general registers */ 1507 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1508 1509 /* Go to suspend mode */ 1510 sc16is7xx_power(&s->p[i].port, 0); 1511 } 1512 1513 if (dev->of_node) { 1514 struct property *prop; 1515 const __be32 *p; 1516 u32 u; 1517 1518 of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1519 prop, p, u) 1520 if (u < devtype->nr_uart) 1521 s->p[u].irda_mode = true; 1522 } 1523 1524 /* 1525 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1526 * If that succeeds, we can allow sharing the interrupt as well. 1527 * In case the interrupt controller doesn't support that, we fall 1528 * back to a non-shared falling-edge trigger. 1529 */ 1530 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1531 IRQF_TRIGGER_LOW | IRQF_SHARED | 1532 IRQF_ONESHOT, 1533 dev_name(dev), s); 1534 if (!ret) 1535 return 0; 1536 1537 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1538 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1539 dev_name(dev), s); 1540 if (!ret) 1541 return 0; 1542 1543 out_ports: 1544 for (i--; i >= 0; i--) { 1545 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1546 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1547 } 1548 1549 #ifdef CONFIG_GPIOLIB 1550 if (devtype->nr_gpio) 1551 gpiochip_remove(&s->gpio); 1552 1553 out_thread: 1554 #endif 1555 kthread_stop(s->kworker_task); 1556 1557 out_clk: 1558 clk_disable_unprepare(s->clk); 1559 1560 return ret; 1561 } 1562 1563 static void sc16is7xx_remove(struct device *dev) 1564 { 1565 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1566 int i; 1567 1568 #ifdef CONFIG_GPIOLIB 1569 if (s->devtype->nr_gpio) 1570 gpiochip_remove(&s->gpio); 1571 #endif 1572 1573 for (i = 0; i < s->devtype->nr_uart; i++) { 1574 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1575 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1576 clear_bit(s->p[i].port.line, &sc16is7xx_lines); 1577 sc16is7xx_power(&s->p[i].port, 0); 1578 } 1579 1580 kthread_flush_worker(&s->kworker); 1581 kthread_stop(s->kworker_task); 1582 1583 clk_disable_unprepare(s->clk); 1584 } 1585 1586 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1587 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1588 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1589 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1590 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1591 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1592 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1593 { } 1594 }; 1595 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1596 1597 static struct regmap_config regcfg = { 1598 .reg_bits = 7, 1599 .pad_bits = 1, 1600 .val_bits = 8, 1601 .cache_type = REGCACHE_RBTREE, 1602 .volatile_reg = sc16is7xx_regmap_volatile, 1603 .precious_reg = sc16is7xx_regmap_precious, 1604 }; 1605 1606 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1607 static int sc16is7xx_spi_probe(struct spi_device *spi) 1608 { 1609 const struct sc16is7xx_devtype *devtype; 1610 struct regmap *regmap; 1611 int ret; 1612 1613 /* Setup SPI bus */ 1614 spi->bits_per_word = 8; 1615 /* only supports mode 0 on SC16IS762 */ 1616 spi->mode = spi->mode ? : SPI_MODE_0; 1617 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1618 ret = spi_setup(spi); 1619 if (ret) 1620 return ret; 1621 1622 if (spi->dev.of_node) { 1623 devtype = device_get_match_data(&spi->dev); 1624 if (!devtype) 1625 return -ENODEV; 1626 } else { 1627 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1628 1629 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1630 } 1631 1632 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1633 (devtype->nr_uart - 1); 1634 regmap = devm_regmap_init_spi(spi, ®cfg); 1635 1636 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); 1637 } 1638 1639 static void sc16is7xx_spi_remove(struct spi_device *spi) 1640 { 1641 sc16is7xx_remove(&spi->dev); 1642 } 1643 1644 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1645 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1646 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1647 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1648 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1649 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1650 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1651 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1652 { } 1653 }; 1654 1655 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1656 1657 static struct spi_driver sc16is7xx_spi_uart_driver = { 1658 .driver = { 1659 .name = SC16IS7XX_NAME, 1660 .of_match_table = sc16is7xx_dt_ids, 1661 }, 1662 .probe = sc16is7xx_spi_probe, 1663 .remove = sc16is7xx_spi_remove, 1664 .id_table = sc16is7xx_spi_id_table, 1665 }; 1666 1667 MODULE_ALIAS("spi:sc16is7xx"); 1668 #endif 1669 1670 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1671 static int sc16is7xx_i2c_probe(struct i2c_client *i2c, 1672 const struct i2c_device_id *id) 1673 { 1674 const struct sc16is7xx_devtype *devtype; 1675 struct regmap *regmap; 1676 1677 if (i2c->dev.of_node) { 1678 devtype = device_get_match_data(&i2c->dev); 1679 if (!devtype) 1680 return -ENODEV; 1681 } else { 1682 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1683 } 1684 1685 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1686 (devtype->nr_uart - 1); 1687 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1688 1689 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); 1690 } 1691 1692 static int sc16is7xx_i2c_remove(struct i2c_client *client) 1693 { 1694 sc16is7xx_remove(&client->dev); 1695 1696 return 0; 1697 } 1698 1699 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1700 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1701 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1702 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1703 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1704 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1705 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1706 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1707 { } 1708 }; 1709 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1710 1711 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1712 .driver = { 1713 .name = SC16IS7XX_NAME, 1714 .of_match_table = sc16is7xx_dt_ids, 1715 }, 1716 .probe = sc16is7xx_i2c_probe, 1717 .remove = sc16is7xx_i2c_remove, 1718 .id_table = sc16is7xx_i2c_id_table, 1719 }; 1720 1721 #endif 1722 1723 static int __init sc16is7xx_init(void) 1724 { 1725 int ret; 1726 1727 ret = uart_register_driver(&sc16is7xx_uart); 1728 if (ret) { 1729 pr_err("Registering UART driver failed\n"); 1730 return ret; 1731 } 1732 1733 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1734 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1735 if (ret < 0) { 1736 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1737 goto err_i2c; 1738 } 1739 #endif 1740 1741 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1742 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1743 if (ret < 0) { 1744 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1745 goto err_spi; 1746 } 1747 #endif 1748 return ret; 1749 1750 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1751 err_spi: 1752 #endif 1753 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1754 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1755 err_i2c: 1756 #endif 1757 uart_unregister_driver(&sc16is7xx_uart); 1758 return ret; 1759 } 1760 module_init(sc16is7xx_init); 1761 1762 static void __exit sc16is7xx_exit(void) 1763 { 1764 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1765 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1766 #endif 1767 1768 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1769 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1770 #endif 1771 uart_unregister_driver(&sc16is7xx_uart); 1772 } 1773 module_exit(sc16is7xx_exit); 1774 1775 MODULE_LICENSE("GPL"); 1776 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1777 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1778