1 /* 2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 3 * Author: Jon Ringle <jringle@gridpoint.com> 4 * 5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/gpio.h> 19 #include <linux/i2c.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/regmap.h> 24 #include <linux/serial_core.h> 25 #include <linux/serial.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/uaccess.h> 29 30 #define SC16IS7XX_NAME "sc16is7xx" 31 32 /* SC16IS7XX register definitions */ 33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 46 * - only on 75x/76x 47 */ 48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 49 * - only on 75x/76x 50 */ 51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 52 * - only on 75x/76x 53 */ 54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 55 * - only on 75x/76x 56 */ 57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 58 59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 62 63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 66 67 /* Enhanced Register set: Only if (LCR == 0xBF) */ 68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 73 74 /* IER register bits */ 75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 77 * interrupt */ 78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 79 * interrupt */ 80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 81 * interrupt */ 82 83 /* IER register bits - write only if (EFR[4] == 1) */ 84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 88 89 /* FCR register bits */ 90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 95 96 /* FCR register bits - write only if (EFR[4] == 1) */ 97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 99 100 /* IIR register bits */ 101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 108 * - only on 75x/76x 109 */ 110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 111 * - only on 75x/76x 112 */ 113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 115 * from active (LOW) 116 * to inactive (HIGH) 117 */ 118 /* LCR register bits */ 119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 121 * 122 * Word length bits table: 123 * 00 -> 5 bit words 124 * 01 -> 6 bit words 125 * 10 -> 7 bit words 126 * 11 -> 8 bit words 127 */ 128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 129 * 130 * STOP length bit table: 131 * 0 -> 1 stop bit 132 * 1 -> 1-1.5 stop bits if 133 * word length is 5, 134 * 2 stop bits otherwise 135 */ 136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 146 * reg set */ 147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 148 * reg set */ 149 150 /* MCR register bits */ 151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 152 * - only on 75x/76x 153 */ 154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 158 * - write enabled 159 * if (EFR[4] == 1) 160 */ 161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 162 * - write enabled 163 * if (EFR[4] == 1) 164 */ 165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 166 * - write enabled 167 * if (EFR[4] == 1) 168 */ 169 170 /* LSR register bits */ 171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 180 181 /* MSR register bits */ 182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 184 * or (IO4) 185 * - only on 75x/76x 186 */ 187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 188 * or (IO7) 189 * - only on 75x/76x 190 */ 191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 192 * or (IO6) 193 * - only on 75x/76x 194 */ 195 #define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */ 196 #define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4) 197 * - only on 75x/76x 198 */ 199 #define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7) 200 * - only on 75x/76x 201 */ 202 #define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6) 203 * - only on 75x/76x 204 */ 205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 206 207 /* 208 * TCR register bits 209 * TCR trigger levels are available from 0 to 60 characters with a granularity 210 * of four. 211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 212 * no built-in hardware check to make sure this condition is met. Also, the TCR 213 * must be programmed with this condition before auto RTS or software flow 214 * control is enabled to avoid spurious operation of the device. 215 */ 216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 218 219 /* 220 * TLR register bits 221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 223 * trigger levels. Trigger levels from 4 characters to 60 characters are 224 * available with a granularity of four. 225 * 226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 228 * the trigger level defined in FCR is discarded. This applies to both transmit 229 * FIFO and receive FIFO trigger level setting. 230 * 231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 232 * default state, that is, '00'. 233 */ 234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 236 237 /* IOControl register bits (Only 750/760) */ 238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 239 #define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */ 240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 241 242 /* EFCR register bits */ 243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 244 * mode (RS485) */ 245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 250 * 0 = rate upto 115.2 kbit/s 251 * - Only 750/760 252 * 1 = rate upto 1.152 Mbit/s 253 * - Only 760 254 */ 255 256 /* EFR register bits */ 257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 261 * and writing to IER[7:4], 262 * FCR[5:4], MCR[7:5] 263 */ 264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 266 * 267 * SWFLOW bits 3 & 2 table: 268 * 00 -> no transmitter flow 269 * control 270 * 01 -> transmitter generates 271 * XON2 and XOFF2 272 * 10 -> transmitter generates 273 * XON1 and XOFF1 274 * 11 -> transmitter generates 275 * XON1, XON2, XOFF1 and 276 * XOFF2 277 */ 278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 280 * 281 * SWFLOW bits 3 & 2 table: 282 * 00 -> no received flow 283 * control 284 * 01 -> receiver compares 285 * XON2 and XOFF2 286 * 10 -> receiver compares 287 * XON1 and XOFF1 288 * 11 -> receiver compares 289 * XON1, XON2, XOFF1 and 290 * XOFF2 291 */ 292 293 /* Misc definitions */ 294 #define SC16IS7XX_FIFO_SIZE (64) 295 #define SC16IS7XX_REG_SHIFT 2 296 297 struct sc16is7xx_devtype { 298 char name[10]; 299 int nr_gpio; 300 int nr_uart; 301 }; 302 303 struct sc16is7xx_one { 304 struct uart_port port; 305 struct work_struct tx_work; 306 struct work_struct md_work; 307 308 struct serial_rs485 rs485; 309 }; 310 311 struct sc16is7xx_port { 312 struct uart_driver uart; 313 struct sc16is7xx_devtype *devtype; 314 struct regmap *regmap; 315 struct mutex mutex; 316 struct clk *clk; 317 #ifdef CONFIG_GPIOLIB 318 struct gpio_chip gpio; 319 #endif 320 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 321 struct sc16is7xx_one p[0]; 322 }; 323 324 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 325 326 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 327 { 328 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 329 unsigned int val = 0; 330 331 regmap_read(s->regmap, 332 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val); 333 334 return val; 335 } 336 337 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 338 { 339 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 340 341 regmap_write(s->regmap, 342 (reg << SC16IS7XX_REG_SHIFT) | port->line, val); 343 } 344 345 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 346 u8 mask, u8 val) 347 { 348 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 349 350 regmap_update_bits(s->regmap, 351 (reg << SC16IS7XX_REG_SHIFT) | port->line, 352 mask, val); 353 } 354 355 356 static void sc16is7xx_power(struct uart_port *port, int on) 357 { 358 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 359 SC16IS7XX_IER_SLEEP_BIT, 360 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 361 } 362 363 static const struct sc16is7xx_devtype sc16is74x_devtype = { 364 .name = "SC16IS74X", 365 .nr_gpio = 0, 366 .nr_uart = 1, 367 }; 368 369 static const struct sc16is7xx_devtype sc16is750_devtype = { 370 .name = "SC16IS750", 371 .nr_gpio = 8, 372 .nr_uart = 1, 373 }; 374 375 static const struct sc16is7xx_devtype sc16is752_devtype = { 376 .name = "SC16IS752", 377 .nr_gpio = 8, 378 .nr_uart = 2, 379 }; 380 381 static const struct sc16is7xx_devtype sc16is760_devtype = { 382 .name = "SC16IS760", 383 .nr_gpio = 8, 384 .nr_uart = 1, 385 }; 386 387 static const struct sc16is7xx_devtype sc16is762_devtype = { 388 .name = "SC16IS762", 389 .nr_gpio = 8, 390 .nr_uart = 2, 391 }; 392 393 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 394 { 395 switch (reg >> SC16IS7XX_REG_SHIFT) { 396 case SC16IS7XX_RHR_REG: 397 case SC16IS7XX_IIR_REG: 398 case SC16IS7XX_LSR_REG: 399 case SC16IS7XX_MSR_REG: 400 case SC16IS7XX_TXLVL_REG: 401 case SC16IS7XX_RXLVL_REG: 402 case SC16IS7XX_IOSTATE_REG: 403 return true; 404 default: 405 break; 406 } 407 408 return false; 409 } 410 411 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 412 { 413 switch (reg >> SC16IS7XX_REG_SHIFT) { 414 case SC16IS7XX_RHR_REG: 415 return true; 416 default: 417 break; 418 } 419 420 return false; 421 } 422 423 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 424 { 425 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 426 u8 lcr; 427 u8 prescaler = 0; 428 unsigned long clk = port->uartclk, div = clk / 16 / baud; 429 430 if (div > 0xffff) { 431 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 432 div /= 4; 433 } 434 435 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 436 437 /* Open the LCR divisors for configuration */ 438 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 439 SC16IS7XX_LCR_CONF_MODE_B); 440 441 /* Enable enhanced features */ 442 regcache_cache_bypass(s->regmap, true); 443 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 444 SC16IS7XX_EFR_ENABLE_BIT); 445 regcache_cache_bypass(s->regmap, false); 446 447 /* Put LCR back to the normal mode */ 448 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 449 450 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 451 SC16IS7XX_MCR_CLKSEL_BIT, 452 prescaler); 453 454 /* Open the LCR divisors for configuration */ 455 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 456 SC16IS7XX_LCR_CONF_MODE_A); 457 458 /* Write the new divisor */ 459 regcache_cache_bypass(s->regmap, true); 460 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 461 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 462 regcache_cache_bypass(s->regmap, false); 463 464 /* Put LCR back to the normal mode */ 465 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 466 467 return DIV_ROUND_CLOSEST(clk / 16, div); 468 } 469 470 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 471 unsigned int iir) 472 { 473 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 474 unsigned int lsr = 0, ch, flag, bytes_read, i; 475 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 476 477 if (unlikely(rxlen >= sizeof(s->buf))) { 478 dev_warn_ratelimited(port->dev, 479 "Port %i: Possible RX FIFO overrun: %d\n", 480 port->line, rxlen); 481 port->icount.buf_overrun++; 482 /* Ensure sanity of RX level */ 483 rxlen = sizeof(s->buf); 484 } 485 486 while (rxlen) { 487 /* Only read lsr if there are possible errors in FIFO */ 488 if (read_lsr) { 489 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 490 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 491 read_lsr = false; /* No errors left in FIFO */ 492 } else 493 lsr = 0; 494 495 if (read_lsr) { 496 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 497 bytes_read = 1; 498 } else { 499 regcache_cache_bypass(s->regmap, true); 500 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG, 501 s->buf, rxlen); 502 regcache_cache_bypass(s->regmap, false); 503 bytes_read = rxlen; 504 } 505 506 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 507 508 port->icount.rx++; 509 flag = TTY_NORMAL; 510 511 if (unlikely(lsr)) { 512 if (lsr & SC16IS7XX_LSR_BI_BIT) { 513 port->icount.brk++; 514 if (uart_handle_break(port)) 515 continue; 516 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 517 port->icount.parity++; 518 else if (lsr & SC16IS7XX_LSR_FE_BIT) 519 port->icount.frame++; 520 else if (lsr & SC16IS7XX_LSR_OE_BIT) 521 port->icount.overrun++; 522 523 lsr &= port->read_status_mask; 524 if (lsr & SC16IS7XX_LSR_BI_BIT) 525 flag = TTY_BREAK; 526 else if (lsr & SC16IS7XX_LSR_PE_BIT) 527 flag = TTY_PARITY; 528 else if (lsr & SC16IS7XX_LSR_FE_BIT) 529 flag = TTY_FRAME; 530 else if (lsr & SC16IS7XX_LSR_OE_BIT) 531 flag = TTY_OVERRUN; 532 } 533 534 for (i = 0; i < bytes_read; ++i) { 535 ch = s->buf[i]; 536 if (uart_handle_sysrq_char(port, ch)) 537 continue; 538 539 if (lsr & port->ignore_status_mask) 540 continue; 541 542 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 543 flag); 544 } 545 rxlen -= bytes_read; 546 } 547 548 tty_flip_buffer_push(&port->state->port); 549 } 550 551 static void sc16is7xx_handle_tx(struct uart_port *port) 552 { 553 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 554 struct circ_buf *xmit = &port->state->xmit; 555 unsigned int txlen, to_send, i; 556 557 if (unlikely(port->x_char)) { 558 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 559 port->icount.tx++; 560 port->x_char = 0; 561 return; 562 } 563 564 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 565 return; 566 567 /* Get length of data pending in circular buffer */ 568 to_send = uart_circ_chars_pending(xmit); 569 if (likely(to_send)) { 570 /* Limit to size of TX FIFO */ 571 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 572 to_send = (to_send > txlen) ? txlen : to_send; 573 574 /* Add data to send */ 575 port->icount.tx += to_send; 576 577 /* Convert to linear buffer */ 578 for (i = 0; i < to_send; ++i) { 579 s->buf[i] = xmit->buf[xmit->tail]; 580 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 581 } 582 regcache_cache_bypass(s->regmap, true); 583 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send); 584 regcache_cache_bypass(s->regmap, false); 585 } 586 587 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 588 uart_write_wakeup(port); 589 } 590 591 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 592 { 593 struct uart_port *port = &s->p[portno].port; 594 595 do { 596 unsigned int iir, msr, rxlen; 597 598 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 599 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 600 break; 601 602 iir &= SC16IS7XX_IIR_ID_MASK; 603 604 switch (iir) { 605 case SC16IS7XX_IIR_RDI_SRC: 606 case SC16IS7XX_IIR_RLSE_SRC: 607 case SC16IS7XX_IIR_RTOI_SRC: 608 case SC16IS7XX_IIR_XOFFI_SRC: 609 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 610 if (rxlen) 611 sc16is7xx_handle_rx(port, rxlen, iir); 612 break; 613 614 case SC16IS7XX_IIR_CTSRTS_SRC: 615 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 616 uart_handle_cts_change(port, 617 !!(msr & SC16IS7XX_MSR_CTS_BIT)); 618 break; 619 case SC16IS7XX_IIR_THRI_SRC: 620 mutex_lock(&s->mutex); 621 sc16is7xx_handle_tx(port); 622 mutex_unlock(&s->mutex); 623 break; 624 default: 625 dev_err_ratelimited(port->dev, 626 "Port %i: Unexpected interrupt: %x", 627 port->line, iir); 628 break; 629 } 630 } while (1); 631 } 632 633 static irqreturn_t sc16is7xx_ist(int irq, void *dev_id) 634 { 635 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 636 int i; 637 638 for (i = 0; i < s->uart.nr; ++i) 639 sc16is7xx_port_irq(s, i); 640 641 return IRQ_HANDLED; 642 } 643 644 static void sc16is7xx_wq_proc(struct work_struct *ws) 645 { 646 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work); 647 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 648 649 mutex_lock(&s->mutex); 650 sc16is7xx_handle_tx(&one->port); 651 mutex_unlock(&s->mutex); 652 } 653 654 static void sc16is7xx_stop_tx(struct uart_port* port) 655 { 656 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 657 struct circ_buf *xmit = &one->port.state->xmit; 658 659 /* handle rs485 */ 660 if (one->rs485.flags & SER_RS485_ENABLED) { 661 /* do nothing if current tx not yet completed */ 662 int lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 663 if (!(lsr & SC16IS7XX_LSR_TEMT_BIT)) 664 return; 665 666 if (uart_circ_empty(xmit) && 667 (one->rs485.delay_rts_after_send > 0)) 668 mdelay(one->rs485.delay_rts_after_send); 669 } 670 671 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 672 SC16IS7XX_IER_THRI_BIT, 673 0); 674 } 675 676 static void sc16is7xx_stop_rx(struct uart_port* port) 677 { 678 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 679 680 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT; 681 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 682 SC16IS7XX_LSR_DR_BIT, 683 0); 684 } 685 686 static void sc16is7xx_start_tx(struct uart_port *port) 687 { 688 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 689 690 /* handle rs485 */ 691 if ((one->rs485.flags & SER_RS485_ENABLED) && 692 (one->rs485.delay_rts_before_send > 0)) { 693 mdelay(one->rs485.delay_rts_before_send); 694 } 695 696 if (!work_pending(&one->tx_work)) 697 schedule_work(&one->tx_work); 698 } 699 700 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 701 { 702 unsigned int lvl, lsr; 703 704 lvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 705 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 706 707 return ((lsr & SC16IS7XX_LSR_THRE_BIT) && !lvl) ? TIOCSER_TEMT : 0; 708 } 709 710 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 711 { 712 /* DCD and DSR are not wired and CTS/RTS is handled automatically 713 * so just indicate DSR and CAR asserted 714 */ 715 return TIOCM_DSR | TIOCM_CAR; 716 } 717 718 static void sc16is7xx_md_proc(struct work_struct *ws) 719 { 720 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work); 721 722 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 723 SC16IS7XX_MCR_LOOP_BIT, 724 (one->port.mctrl & TIOCM_LOOP) ? 725 SC16IS7XX_MCR_LOOP_BIT : 0); 726 } 727 728 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 729 { 730 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 731 732 schedule_work(&one->md_work); 733 } 734 735 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 736 { 737 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 738 SC16IS7XX_LCR_TXBREAK_BIT, 739 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 740 } 741 742 static void sc16is7xx_set_termios(struct uart_port *port, 743 struct ktermios *termios, 744 struct ktermios *old) 745 { 746 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 747 unsigned int lcr, flow = 0; 748 int baud; 749 750 /* Mask termios capabilities we don't support */ 751 termios->c_cflag &= ~CMSPAR; 752 753 /* Word size */ 754 switch (termios->c_cflag & CSIZE) { 755 case CS5: 756 lcr = SC16IS7XX_LCR_WORD_LEN_5; 757 break; 758 case CS6: 759 lcr = SC16IS7XX_LCR_WORD_LEN_6; 760 break; 761 case CS7: 762 lcr = SC16IS7XX_LCR_WORD_LEN_7; 763 break; 764 case CS8: 765 lcr = SC16IS7XX_LCR_WORD_LEN_8; 766 break; 767 default: 768 lcr = SC16IS7XX_LCR_WORD_LEN_8; 769 termios->c_cflag &= ~CSIZE; 770 termios->c_cflag |= CS8; 771 break; 772 } 773 774 /* Parity */ 775 if (termios->c_cflag & PARENB) { 776 lcr |= SC16IS7XX_LCR_PARITY_BIT; 777 if (!(termios->c_cflag & PARODD)) 778 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 779 } 780 781 /* Stop bits */ 782 if (termios->c_cflag & CSTOPB) 783 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 784 785 /* Set read status mask */ 786 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 787 if (termios->c_iflag & INPCK) 788 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 789 SC16IS7XX_LSR_FE_BIT; 790 if (termios->c_iflag & (BRKINT | PARMRK)) 791 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 792 793 /* Set status ignore mask */ 794 port->ignore_status_mask = 0; 795 if (termios->c_iflag & IGNBRK) 796 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 797 if (!(termios->c_cflag & CREAD)) 798 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 799 800 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 801 SC16IS7XX_LCR_CONF_MODE_B); 802 803 /* Configure flow control */ 804 regcache_cache_bypass(s->regmap, true); 805 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 806 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 807 if (termios->c_cflag & CRTSCTS) 808 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 809 SC16IS7XX_EFR_AUTORTS_BIT; 810 if (termios->c_iflag & IXON) 811 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 812 if (termios->c_iflag & IXOFF) 813 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 814 815 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow); 816 regcache_cache_bypass(s->regmap, false); 817 818 /* Update LCR register */ 819 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 820 821 /* Get baud rate generator configuration */ 822 baud = uart_get_baud_rate(port, termios, old, 823 port->uartclk / 16 / 4 / 0xffff, 824 port->uartclk / 16); 825 826 /* Setup baudrate generator */ 827 baud = sc16is7xx_set_baud(port, baud); 828 829 /* Update timeout according to new baud rate */ 830 uart_update_timeout(port, termios->c_cflag, baud); 831 } 832 833 #if defined(TIOCSRS485) && defined(TIOCGRS485) 834 static void sc16is7xx_config_rs485(struct uart_port *port, 835 struct serial_rs485 *rs485) 836 { 837 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 838 839 one->rs485 = *rs485; 840 841 if (one->rs485.flags & SER_RS485_ENABLED) { 842 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 843 SC16IS7XX_EFCR_AUTO_RS485_BIT, 844 SC16IS7XX_EFCR_AUTO_RS485_BIT); 845 } else { 846 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 847 SC16IS7XX_EFCR_AUTO_RS485_BIT, 848 0); 849 } 850 } 851 #endif 852 853 static int sc16is7xx_ioctl(struct uart_port *port, unsigned int cmd, 854 unsigned long arg) 855 { 856 #if defined(TIOCSRS485) && defined(TIOCGRS485) 857 struct serial_rs485 rs485; 858 859 switch (cmd) { 860 case TIOCSRS485: 861 if (copy_from_user(&rs485, (void __user *)arg, sizeof(rs485))) 862 return -EFAULT; 863 864 sc16is7xx_config_rs485(port, &rs485); 865 return 0; 866 case TIOCGRS485: 867 if (copy_to_user((void __user *)arg, 868 &(to_sc16is7xx_one(port, port)->rs485), 869 sizeof(rs485))) 870 return -EFAULT; 871 return 0; 872 default: 873 break; 874 } 875 #endif 876 877 return -ENOIOCTLCMD; 878 } 879 880 static int sc16is7xx_startup(struct uart_port *port) 881 { 882 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 883 unsigned int val; 884 885 sc16is7xx_power(port, 1); 886 887 /* Reset FIFOs*/ 888 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 889 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 890 udelay(5); 891 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 892 SC16IS7XX_FCR_FIFO_BIT); 893 894 /* Enable EFR */ 895 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 896 SC16IS7XX_LCR_CONF_MODE_B); 897 898 regcache_cache_bypass(s->regmap, true); 899 900 /* Enable write access to enhanced features and internal clock div */ 901 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 902 SC16IS7XX_EFR_ENABLE_BIT); 903 904 /* Enable TCR/TLR */ 905 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 906 SC16IS7XX_MCR_TCRTLR_BIT, 907 SC16IS7XX_MCR_TCRTLR_BIT); 908 909 /* Configure flow control levels */ 910 /* Flow control halt level 48, resume level 24 */ 911 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 912 SC16IS7XX_TCR_RX_RESUME(24) | 913 SC16IS7XX_TCR_RX_HALT(48)); 914 915 regcache_cache_bypass(s->regmap, false); 916 917 /* Now, initialize the UART */ 918 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 919 920 /* Enable the Rx and Tx FIFO */ 921 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 922 SC16IS7XX_EFCR_RXDISABLE_BIT | 923 SC16IS7XX_EFCR_TXDISABLE_BIT, 924 0); 925 926 /* Enable RX, TX, CTS change interrupts */ 927 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT | 928 SC16IS7XX_IER_CTSI_BIT; 929 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 930 931 return 0; 932 } 933 934 static void sc16is7xx_shutdown(struct uart_port *port) 935 { 936 /* Disable all interrupts */ 937 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 938 /* Disable TX/RX */ 939 sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG, 940 SC16IS7XX_EFCR_RXDISABLE_BIT | 941 SC16IS7XX_EFCR_TXDISABLE_BIT); 942 943 sc16is7xx_power(port, 0); 944 } 945 946 static const char *sc16is7xx_type(struct uart_port *port) 947 { 948 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 949 950 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 951 } 952 953 static int sc16is7xx_request_port(struct uart_port *port) 954 { 955 /* Do nothing */ 956 return 0; 957 } 958 959 static void sc16is7xx_config_port(struct uart_port *port, int flags) 960 { 961 if (flags & UART_CONFIG_TYPE) 962 port->type = PORT_SC16IS7XX; 963 } 964 965 static int sc16is7xx_verify_port(struct uart_port *port, 966 struct serial_struct *s) 967 { 968 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 969 return -EINVAL; 970 if (s->irq != port->irq) 971 return -EINVAL; 972 973 return 0; 974 } 975 976 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 977 unsigned int oldstate) 978 { 979 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 980 } 981 982 static void sc16is7xx_null_void(struct uart_port *port) 983 { 984 /* Do nothing */ 985 } 986 987 static const struct uart_ops sc16is7xx_ops = { 988 .tx_empty = sc16is7xx_tx_empty, 989 .set_mctrl = sc16is7xx_set_mctrl, 990 .get_mctrl = sc16is7xx_get_mctrl, 991 .stop_tx = sc16is7xx_stop_tx, 992 .start_tx = sc16is7xx_start_tx, 993 .stop_rx = sc16is7xx_stop_rx, 994 .break_ctl = sc16is7xx_break_ctl, 995 .startup = sc16is7xx_startup, 996 .shutdown = sc16is7xx_shutdown, 997 .set_termios = sc16is7xx_set_termios, 998 .type = sc16is7xx_type, 999 .request_port = sc16is7xx_request_port, 1000 .release_port = sc16is7xx_null_void, 1001 .config_port = sc16is7xx_config_port, 1002 .verify_port = sc16is7xx_verify_port, 1003 .ioctl = sc16is7xx_ioctl, 1004 .pm = sc16is7xx_pm, 1005 }; 1006 1007 #ifdef CONFIG_GPIOLIB 1008 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1009 { 1010 unsigned int val; 1011 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1012 gpio); 1013 struct uart_port *port = &s->p[0].port; 1014 1015 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1016 1017 return !!(val & BIT(offset)); 1018 } 1019 1020 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1021 { 1022 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1023 gpio); 1024 struct uart_port *port = &s->p[0].port; 1025 1026 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1027 val ? BIT(offset) : 0); 1028 } 1029 1030 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1031 unsigned offset) 1032 { 1033 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1034 gpio); 1035 struct uart_port *port = &s->p[0].port; 1036 1037 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1038 1039 return 0; 1040 } 1041 1042 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1043 unsigned offset, int val) 1044 { 1045 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1046 gpio); 1047 struct uart_port *port = &s->p[0].port; 1048 1049 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1050 val ? BIT(offset) : 0); 1051 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1052 BIT(offset)); 1053 1054 return 0; 1055 } 1056 #endif 1057 1058 static int sc16is7xx_probe(struct device *dev, 1059 struct sc16is7xx_devtype *devtype, 1060 struct regmap *regmap, int irq, unsigned long flags) 1061 { 1062 unsigned long freq, *pfreq = dev_get_platdata(dev); 1063 int i, ret; 1064 struct sc16is7xx_port *s; 1065 1066 if (IS_ERR(regmap)) 1067 return PTR_ERR(regmap); 1068 1069 /* Alloc port structure */ 1070 s = devm_kzalloc(dev, sizeof(*s) + 1071 sizeof(struct sc16is7xx_one) * devtype->nr_uart, 1072 GFP_KERNEL); 1073 if (!s) { 1074 dev_err(dev, "Error allocating port structure\n"); 1075 return -ENOMEM; 1076 } 1077 1078 s->clk = devm_clk_get(dev, NULL); 1079 if (IS_ERR(s->clk)) { 1080 if (pfreq) 1081 freq = *pfreq; 1082 else 1083 return PTR_ERR(s->clk); 1084 } else { 1085 freq = clk_get_rate(s->clk); 1086 } 1087 1088 s->regmap = regmap; 1089 s->devtype = devtype; 1090 dev_set_drvdata(dev, s); 1091 1092 /* Register UART driver */ 1093 s->uart.owner = THIS_MODULE; 1094 s->uart.dev_name = "ttySC"; 1095 s->uart.nr = devtype->nr_uart; 1096 ret = uart_register_driver(&s->uart); 1097 if (ret) { 1098 dev_err(dev, "Registering UART driver failed\n"); 1099 goto out_clk; 1100 } 1101 1102 #ifdef CONFIG_GPIOLIB 1103 if (devtype->nr_gpio) { 1104 /* Setup GPIO cotroller */ 1105 s->gpio.owner = THIS_MODULE; 1106 s->gpio.dev = dev; 1107 s->gpio.label = dev_name(dev); 1108 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1109 s->gpio.get = sc16is7xx_gpio_get; 1110 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1111 s->gpio.set = sc16is7xx_gpio_set; 1112 s->gpio.base = -1; 1113 s->gpio.ngpio = devtype->nr_gpio; 1114 s->gpio.can_sleep = 1; 1115 ret = gpiochip_add(&s->gpio); 1116 if (ret) 1117 goto out_uart; 1118 } 1119 #endif 1120 1121 mutex_init(&s->mutex); 1122 1123 for (i = 0; i < devtype->nr_uart; ++i) { 1124 /* Initialize port data */ 1125 s->p[i].port.line = i; 1126 s->p[i].port.dev = dev; 1127 s->p[i].port.irq = irq; 1128 s->p[i].port.type = PORT_SC16IS7XX; 1129 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1130 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1131 s->p[i].port.iotype = UPIO_PORT; 1132 s->p[i].port.uartclk = freq; 1133 s->p[i].port.ops = &sc16is7xx_ops; 1134 /* Disable all interrupts */ 1135 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1136 /* Disable TX/RX */ 1137 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1138 SC16IS7XX_EFCR_RXDISABLE_BIT | 1139 SC16IS7XX_EFCR_TXDISABLE_BIT); 1140 /* Initialize queue for start TX */ 1141 INIT_WORK(&s->p[i].tx_work, sc16is7xx_wq_proc); 1142 /* Initialize queue for changing mode */ 1143 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc); 1144 /* Register port */ 1145 uart_add_one_port(&s->uart, &s->p[i].port); 1146 /* Go to suspend mode */ 1147 sc16is7xx_power(&s->p[i].port, 0); 1148 } 1149 1150 /* Setup interrupt */ 1151 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_ist, 1152 IRQF_ONESHOT | flags, dev_name(dev), s); 1153 if (!ret) 1154 return 0; 1155 1156 mutex_destroy(&s->mutex); 1157 1158 #ifdef CONFIG_GPIOLIB 1159 if (devtype->nr_gpio) 1160 WARN_ON(gpiochip_remove(&s->gpio)); 1161 1162 out_uart: 1163 #endif 1164 uart_unregister_driver(&s->uart); 1165 1166 out_clk: 1167 if (!IS_ERR(s->clk)) 1168 clk_disable_unprepare(s->clk); 1169 1170 return ret; 1171 } 1172 1173 static int sc16is7xx_remove(struct device *dev) 1174 { 1175 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1176 int i, ret = 0; 1177 1178 #ifdef CONFIG_GPIOLIB 1179 if (s->devtype->nr_gpio) { 1180 ret = gpiochip_remove(&s->gpio); 1181 if (ret) 1182 return ret; 1183 } 1184 #endif 1185 1186 for (i = 0; i < s->uart.nr; i++) { 1187 cancel_work_sync(&s->p[i].tx_work); 1188 cancel_work_sync(&s->p[i].md_work); 1189 uart_remove_one_port(&s->uart, &s->p[i].port); 1190 sc16is7xx_power(&s->p[i].port, 0); 1191 } 1192 1193 mutex_destroy(&s->mutex); 1194 uart_unregister_driver(&s->uart); 1195 if (!IS_ERR(s->clk)) 1196 clk_disable_unprepare(s->clk); 1197 1198 return ret; 1199 } 1200 1201 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1202 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1203 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1204 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1205 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1206 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1207 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1208 { } 1209 }; 1210 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1211 1212 static struct regmap_config regcfg = { 1213 .reg_bits = 7, 1214 .pad_bits = 1, 1215 .val_bits = 8, 1216 .cache_type = REGCACHE_RBTREE, 1217 .volatile_reg = sc16is7xx_regmap_volatile, 1218 .precious_reg = sc16is7xx_regmap_precious, 1219 }; 1220 1221 static int sc16is7xx_i2c_probe(struct i2c_client *i2c, 1222 const struct i2c_device_id *id) 1223 { 1224 struct sc16is7xx_devtype *devtype; 1225 unsigned long flags = 0; 1226 struct regmap *regmap; 1227 1228 if (i2c->dev.of_node) { 1229 const struct of_device_id *of_id = 1230 of_match_device(sc16is7xx_dt_ids, &i2c->dev); 1231 1232 devtype = (struct sc16is7xx_devtype *)of_id->data; 1233 } else { 1234 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1235 flags = IRQF_TRIGGER_FALLING; 1236 } 1237 1238 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1239 (devtype->nr_uart - 1); 1240 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1241 1242 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags); 1243 } 1244 1245 static int sc16is7xx_i2c_remove(struct i2c_client *client) 1246 { 1247 return sc16is7xx_remove(&client->dev); 1248 } 1249 1250 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1251 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1252 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1253 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1254 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1255 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1256 { } 1257 }; 1258 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1259 1260 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1261 .driver = { 1262 .name = SC16IS7XX_NAME, 1263 .owner = THIS_MODULE, 1264 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1265 }, 1266 .probe = sc16is7xx_i2c_probe, 1267 .remove = sc16is7xx_i2c_remove, 1268 .id_table = sc16is7xx_i2c_id_table, 1269 }; 1270 module_i2c_driver(sc16is7xx_i2c_uart_driver); 1271 MODULE_ALIAS("i2c:sc16is7xx"); 1272 1273 MODULE_LICENSE("GPL"); 1274 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1275 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1276