1 /* 2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 3 * Author: Jon Ringle <jringle@gridpoint.com> 4 * 5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/gpio.h> 19 #include <linux/i2c.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/regmap.h> 24 #include <linux/serial_core.h> 25 #include <linux/serial.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/spi/spi.h> 29 #include <linux/uaccess.h> 30 31 #define SC16IS7XX_NAME "sc16is7xx" 32 33 /* SC16IS7XX register definitions */ 34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 47 * - only on 75x/76x 48 */ 49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 50 * - only on 75x/76x 51 */ 52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 53 * - only on 75x/76x 54 */ 55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 56 * - only on 75x/76x 57 */ 58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 59 60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 63 64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 67 68 /* Enhanced Register set: Only if (LCR == 0xBF) */ 69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 74 75 /* IER register bits */ 76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 78 * interrupt */ 79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 80 * interrupt */ 81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 82 * interrupt */ 83 84 /* IER register bits - write only if (EFR[4] == 1) */ 85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 89 90 /* FCR register bits */ 91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 96 97 /* FCR register bits - write only if (EFR[4] == 1) */ 98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 100 101 /* IIR register bits */ 102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 109 * - only on 75x/76x 110 */ 111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 112 * - only on 75x/76x 113 */ 114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 116 * from active (LOW) 117 * to inactive (HIGH) 118 */ 119 /* LCR register bits */ 120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 122 * 123 * Word length bits table: 124 * 00 -> 5 bit words 125 * 01 -> 6 bit words 126 * 10 -> 7 bit words 127 * 11 -> 8 bit words 128 */ 129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 130 * 131 * STOP length bit table: 132 * 0 -> 1 stop bit 133 * 1 -> 1-1.5 stop bits if 134 * word length is 5, 135 * 2 stop bits otherwise 136 */ 137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 147 * reg set */ 148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 149 * reg set */ 150 151 /* MCR register bits */ 152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 153 * - only on 75x/76x 154 */ 155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 159 * - write enabled 160 * if (EFR[4] == 1) 161 */ 162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 171 /* LSR register bits */ 172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 181 182 /* MSR register bits */ 183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 185 * or (IO4) 186 * - only on 75x/76x 187 */ 188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 189 * or (IO7) 190 * - only on 75x/76x 191 */ 192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 193 * or (IO6) 194 * - only on 75x/76x 195 */ 196 #define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */ 197 #define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4) 198 * - only on 75x/76x 199 */ 200 #define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7) 201 * - only on 75x/76x 202 */ 203 #define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6) 204 * - only on 75x/76x 205 */ 206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 207 208 /* 209 * TCR register bits 210 * TCR trigger levels are available from 0 to 60 characters with a granularity 211 * of four. 212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 213 * no built-in hardware check to make sure this condition is met. Also, the TCR 214 * must be programmed with this condition before auto RTS or software flow 215 * control is enabled to avoid spurious operation of the device. 216 */ 217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 219 220 /* 221 * TLR register bits 222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 224 * trigger levels. Trigger levels from 4 characters to 60 characters are 225 * available with a granularity of four. 226 * 227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 229 * the trigger level defined in FCR is discarded. This applies to both transmit 230 * FIFO and receive FIFO trigger level setting. 231 * 232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 233 * default state, that is, '00'. 234 */ 235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 237 238 /* IOControl register bits (Only 750/760) */ 239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 240 #define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */ 241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 242 243 /* EFCR register bits */ 244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 245 * mode (RS485) */ 246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 251 * 0 = rate upto 115.2 kbit/s 252 * - Only 750/760 253 * 1 = rate upto 1.152 Mbit/s 254 * - Only 760 255 */ 256 257 /* EFR register bits */ 258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 262 * and writing to IER[7:4], 263 * FCR[5:4], MCR[7:5] 264 */ 265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 267 * 268 * SWFLOW bits 3 & 2 table: 269 * 00 -> no transmitter flow 270 * control 271 * 01 -> transmitter generates 272 * XON2 and XOFF2 273 * 10 -> transmitter generates 274 * XON1 and XOFF1 275 * 11 -> transmitter generates 276 * XON1, XON2, XOFF1 and 277 * XOFF2 278 */ 279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 281 * 282 * SWFLOW bits 3 & 2 table: 283 * 00 -> no received flow 284 * control 285 * 01 -> receiver compares 286 * XON2 and XOFF2 287 * 10 -> receiver compares 288 * XON1 and XOFF1 289 * 11 -> receiver compares 290 * XON1, XON2, XOFF1 and 291 * XOFF2 292 */ 293 294 /* Misc definitions */ 295 #define SC16IS7XX_FIFO_SIZE (64) 296 #define SC16IS7XX_REG_SHIFT 2 297 298 struct sc16is7xx_devtype { 299 char name[10]; 300 int nr_gpio; 301 int nr_uart; 302 }; 303 304 #define SC16IS7XX_RECONF_MD (1 << 0) 305 #define SC16IS7XX_RECONF_IER (1 << 1) 306 #define SC16IS7XX_RECONF_RS485 (1 << 2) 307 308 struct sc16is7xx_one_config { 309 unsigned int flags; 310 u8 ier_clear; 311 }; 312 313 struct sc16is7xx_one { 314 struct uart_port port; 315 struct kthread_work tx_work; 316 struct kthread_work reg_work; 317 struct sc16is7xx_one_config config; 318 }; 319 320 struct sc16is7xx_port { 321 struct uart_driver uart; 322 struct sc16is7xx_devtype *devtype; 323 struct regmap *regmap; 324 struct clk *clk; 325 #ifdef CONFIG_GPIOLIB 326 struct gpio_chip gpio; 327 #endif 328 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 329 struct kthread_worker kworker; 330 struct task_struct *kworker_task; 331 struct kthread_work irq_work; 332 struct sc16is7xx_one p[0]; 333 }; 334 335 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 336 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 337 338 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 339 { 340 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 341 unsigned int val = 0; 342 343 regmap_read(s->regmap, 344 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val); 345 346 return val; 347 } 348 349 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 350 { 351 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 352 353 regmap_write(s->regmap, 354 (reg << SC16IS7XX_REG_SHIFT) | port->line, val); 355 } 356 357 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 358 u8 mask, u8 val) 359 { 360 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 361 362 regmap_update_bits(s->regmap, 363 (reg << SC16IS7XX_REG_SHIFT) | port->line, 364 mask, val); 365 } 366 367 368 static void sc16is7xx_power(struct uart_port *port, int on) 369 { 370 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 371 SC16IS7XX_IER_SLEEP_BIT, 372 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 373 } 374 375 static const struct sc16is7xx_devtype sc16is74x_devtype = { 376 .name = "SC16IS74X", 377 .nr_gpio = 0, 378 .nr_uart = 1, 379 }; 380 381 static const struct sc16is7xx_devtype sc16is750_devtype = { 382 .name = "SC16IS750", 383 .nr_gpio = 8, 384 .nr_uart = 1, 385 }; 386 387 static const struct sc16is7xx_devtype sc16is752_devtype = { 388 .name = "SC16IS752", 389 .nr_gpio = 8, 390 .nr_uart = 2, 391 }; 392 393 static const struct sc16is7xx_devtype sc16is760_devtype = { 394 .name = "SC16IS760", 395 .nr_gpio = 8, 396 .nr_uart = 1, 397 }; 398 399 static const struct sc16is7xx_devtype sc16is762_devtype = { 400 .name = "SC16IS762", 401 .nr_gpio = 8, 402 .nr_uart = 2, 403 }; 404 405 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 406 { 407 switch (reg >> SC16IS7XX_REG_SHIFT) { 408 case SC16IS7XX_RHR_REG: 409 case SC16IS7XX_IIR_REG: 410 case SC16IS7XX_LSR_REG: 411 case SC16IS7XX_MSR_REG: 412 case SC16IS7XX_TXLVL_REG: 413 case SC16IS7XX_RXLVL_REG: 414 case SC16IS7XX_IOSTATE_REG: 415 return true; 416 default: 417 break; 418 } 419 420 return false; 421 } 422 423 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 424 { 425 switch (reg >> SC16IS7XX_REG_SHIFT) { 426 case SC16IS7XX_RHR_REG: 427 return true; 428 default: 429 break; 430 } 431 432 return false; 433 } 434 435 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 436 { 437 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 438 u8 lcr; 439 u8 prescaler = 0; 440 unsigned long clk = port->uartclk, div = clk / 16 / baud; 441 442 if (div > 0xffff) { 443 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 444 div /= 4; 445 } 446 447 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 448 449 /* Open the LCR divisors for configuration */ 450 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 451 SC16IS7XX_LCR_CONF_MODE_B); 452 453 /* Enable enhanced features */ 454 regcache_cache_bypass(s->regmap, true); 455 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 456 SC16IS7XX_EFR_ENABLE_BIT); 457 regcache_cache_bypass(s->regmap, false); 458 459 /* Put LCR back to the normal mode */ 460 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 461 462 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 463 SC16IS7XX_MCR_CLKSEL_BIT, 464 prescaler); 465 466 /* Open the LCR divisors for configuration */ 467 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 468 SC16IS7XX_LCR_CONF_MODE_A); 469 470 /* Write the new divisor */ 471 regcache_cache_bypass(s->regmap, true); 472 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 473 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 474 regcache_cache_bypass(s->regmap, false); 475 476 /* Put LCR back to the normal mode */ 477 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 478 479 return DIV_ROUND_CLOSEST(clk / 16, div); 480 } 481 482 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 483 unsigned int iir) 484 { 485 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 486 unsigned int lsr = 0, ch, flag, bytes_read, i; 487 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 488 489 if (unlikely(rxlen >= sizeof(s->buf))) { 490 dev_warn_ratelimited(port->dev, 491 "Port %i: Possible RX FIFO overrun: %d\n", 492 port->line, rxlen); 493 port->icount.buf_overrun++; 494 /* Ensure sanity of RX level */ 495 rxlen = sizeof(s->buf); 496 } 497 498 while (rxlen) { 499 /* Only read lsr if there are possible errors in FIFO */ 500 if (read_lsr) { 501 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 502 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 503 read_lsr = false; /* No errors left in FIFO */ 504 } else 505 lsr = 0; 506 507 if (read_lsr) { 508 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 509 bytes_read = 1; 510 } else { 511 regcache_cache_bypass(s->regmap, true); 512 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG, 513 s->buf, rxlen); 514 regcache_cache_bypass(s->regmap, false); 515 bytes_read = rxlen; 516 } 517 518 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 519 520 port->icount.rx++; 521 flag = TTY_NORMAL; 522 523 if (unlikely(lsr)) { 524 if (lsr & SC16IS7XX_LSR_BI_BIT) { 525 port->icount.brk++; 526 if (uart_handle_break(port)) 527 continue; 528 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 529 port->icount.parity++; 530 else if (lsr & SC16IS7XX_LSR_FE_BIT) 531 port->icount.frame++; 532 else if (lsr & SC16IS7XX_LSR_OE_BIT) 533 port->icount.overrun++; 534 535 lsr &= port->read_status_mask; 536 if (lsr & SC16IS7XX_LSR_BI_BIT) 537 flag = TTY_BREAK; 538 else if (lsr & SC16IS7XX_LSR_PE_BIT) 539 flag = TTY_PARITY; 540 else if (lsr & SC16IS7XX_LSR_FE_BIT) 541 flag = TTY_FRAME; 542 else if (lsr & SC16IS7XX_LSR_OE_BIT) 543 flag = TTY_OVERRUN; 544 } 545 546 for (i = 0; i < bytes_read; ++i) { 547 ch = s->buf[i]; 548 if (uart_handle_sysrq_char(port, ch)) 549 continue; 550 551 if (lsr & port->ignore_status_mask) 552 continue; 553 554 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 555 flag); 556 } 557 rxlen -= bytes_read; 558 } 559 560 tty_flip_buffer_push(&port->state->port); 561 } 562 563 static void sc16is7xx_handle_tx(struct uart_port *port) 564 { 565 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 566 struct circ_buf *xmit = &port->state->xmit; 567 unsigned int txlen, to_send, i; 568 569 if (unlikely(port->x_char)) { 570 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 571 port->icount.tx++; 572 port->x_char = 0; 573 return; 574 } 575 576 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 577 return; 578 579 /* Get length of data pending in circular buffer */ 580 to_send = uart_circ_chars_pending(xmit); 581 if (likely(to_send)) { 582 /* Limit to size of TX FIFO */ 583 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 584 to_send = (to_send > txlen) ? txlen : to_send; 585 586 /* Add data to send */ 587 port->icount.tx += to_send; 588 589 /* Convert to linear buffer */ 590 for (i = 0; i < to_send; ++i) { 591 s->buf[i] = xmit->buf[xmit->tail]; 592 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 593 } 594 regcache_cache_bypass(s->regmap, true); 595 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send); 596 regcache_cache_bypass(s->regmap, false); 597 } 598 599 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 600 uart_write_wakeup(port); 601 } 602 603 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 604 { 605 struct uart_port *port = &s->p[portno].port; 606 607 do { 608 unsigned int iir, msr, rxlen; 609 610 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 611 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 612 break; 613 614 iir &= SC16IS7XX_IIR_ID_MASK; 615 616 switch (iir) { 617 case SC16IS7XX_IIR_RDI_SRC: 618 case SC16IS7XX_IIR_RLSE_SRC: 619 case SC16IS7XX_IIR_RTOI_SRC: 620 case SC16IS7XX_IIR_XOFFI_SRC: 621 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 622 if (rxlen) 623 sc16is7xx_handle_rx(port, rxlen, iir); 624 break; 625 626 case SC16IS7XX_IIR_CTSRTS_SRC: 627 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 628 uart_handle_cts_change(port, 629 !!(msr & SC16IS7XX_MSR_CTS_BIT)); 630 break; 631 case SC16IS7XX_IIR_THRI_SRC: 632 sc16is7xx_handle_tx(port); 633 break; 634 default: 635 dev_err_ratelimited(port->dev, 636 "Port %i: Unexpected interrupt: %x", 637 port->line, iir); 638 break; 639 } 640 } while (1); 641 } 642 643 static void sc16is7xx_ist(struct kthread_work *ws) 644 { 645 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work); 646 int i; 647 648 for (i = 0; i < s->uart.nr; ++i) 649 sc16is7xx_port_irq(s, i); 650 } 651 652 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 653 { 654 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 655 656 queue_kthread_work(&s->kworker, &s->irq_work); 657 658 return IRQ_HANDLED; 659 } 660 661 static void sc16is7xx_tx_proc(struct kthread_work *ws) 662 { 663 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 664 665 if ((port->rs485.flags & SER_RS485_ENABLED) && 666 (port->rs485.delay_rts_before_send > 0)) 667 msleep(port->rs485.delay_rts_before_send); 668 669 sc16is7xx_handle_tx(port); 670 } 671 672 static void sc16is7xx_reconf_rs485(struct uart_port *port) 673 { 674 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 675 SC16IS7XX_EFCR_RTS_INVERT_BIT; 676 u32 efcr = 0; 677 struct serial_rs485 *rs485 = &port->rs485; 678 unsigned long irqflags; 679 680 spin_lock_irqsave(&port->lock, irqflags); 681 if (rs485->flags & SER_RS485_ENABLED) { 682 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 683 684 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 685 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 686 } 687 spin_unlock_irqrestore(&port->lock, irqflags); 688 689 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 690 } 691 692 static void sc16is7xx_reg_proc(struct kthread_work *ws) 693 { 694 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 695 struct sc16is7xx_one_config config; 696 unsigned long irqflags; 697 698 spin_lock_irqsave(&one->port.lock, irqflags); 699 config = one->config; 700 memset(&one->config, 0, sizeof(one->config)); 701 spin_unlock_irqrestore(&one->port.lock, irqflags); 702 703 if (config.flags & SC16IS7XX_RECONF_MD) 704 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 705 SC16IS7XX_MCR_LOOP_BIT, 706 (one->port.mctrl & TIOCM_LOOP) ? 707 SC16IS7XX_MCR_LOOP_BIT : 0); 708 709 if (config.flags & SC16IS7XX_RECONF_IER) 710 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 711 config.ier_clear, 0); 712 713 if (config.flags & SC16IS7XX_RECONF_RS485) 714 sc16is7xx_reconf_rs485(&one->port); 715 } 716 717 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 718 { 719 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 720 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 721 722 one->config.flags |= SC16IS7XX_RECONF_IER; 723 one->config.ier_clear |= bit; 724 queue_kthread_work(&s->kworker, &one->reg_work); 725 } 726 727 static void sc16is7xx_stop_tx(struct uart_port *port) 728 { 729 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 730 } 731 732 static void sc16is7xx_stop_rx(struct uart_port *port) 733 { 734 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 735 } 736 737 static void sc16is7xx_start_tx(struct uart_port *port) 738 { 739 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 740 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 741 742 queue_kthread_work(&s->kworker, &one->tx_work); 743 } 744 745 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 746 { 747 unsigned int lsr; 748 749 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 750 751 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 752 } 753 754 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 755 { 756 /* DCD and DSR are not wired and CTS/RTS is handled automatically 757 * so just indicate DSR and CAR asserted 758 */ 759 return TIOCM_DSR | TIOCM_CAR; 760 } 761 762 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 763 { 764 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 765 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 766 767 one->config.flags |= SC16IS7XX_RECONF_MD; 768 queue_kthread_work(&s->kworker, &one->reg_work); 769 } 770 771 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 772 { 773 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 774 SC16IS7XX_LCR_TXBREAK_BIT, 775 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 776 } 777 778 static void sc16is7xx_set_termios(struct uart_port *port, 779 struct ktermios *termios, 780 struct ktermios *old) 781 { 782 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 783 unsigned int lcr, flow = 0; 784 int baud; 785 786 /* Mask termios capabilities we don't support */ 787 termios->c_cflag &= ~CMSPAR; 788 789 /* Word size */ 790 switch (termios->c_cflag & CSIZE) { 791 case CS5: 792 lcr = SC16IS7XX_LCR_WORD_LEN_5; 793 break; 794 case CS6: 795 lcr = SC16IS7XX_LCR_WORD_LEN_6; 796 break; 797 case CS7: 798 lcr = SC16IS7XX_LCR_WORD_LEN_7; 799 break; 800 case CS8: 801 lcr = SC16IS7XX_LCR_WORD_LEN_8; 802 break; 803 default: 804 lcr = SC16IS7XX_LCR_WORD_LEN_8; 805 termios->c_cflag &= ~CSIZE; 806 termios->c_cflag |= CS8; 807 break; 808 } 809 810 /* Parity */ 811 if (termios->c_cflag & PARENB) { 812 lcr |= SC16IS7XX_LCR_PARITY_BIT; 813 if (!(termios->c_cflag & PARODD)) 814 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 815 } 816 817 /* Stop bits */ 818 if (termios->c_cflag & CSTOPB) 819 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 820 821 /* Set read status mask */ 822 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 823 if (termios->c_iflag & INPCK) 824 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 825 SC16IS7XX_LSR_FE_BIT; 826 if (termios->c_iflag & (BRKINT | PARMRK)) 827 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 828 829 /* Set status ignore mask */ 830 port->ignore_status_mask = 0; 831 if (termios->c_iflag & IGNBRK) 832 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 833 if (!(termios->c_cflag & CREAD)) 834 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 835 836 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 837 SC16IS7XX_LCR_CONF_MODE_B); 838 839 /* Configure flow control */ 840 regcache_cache_bypass(s->regmap, true); 841 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 842 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 843 if (termios->c_cflag & CRTSCTS) 844 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 845 SC16IS7XX_EFR_AUTORTS_BIT; 846 if (termios->c_iflag & IXON) 847 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 848 if (termios->c_iflag & IXOFF) 849 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 850 851 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow); 852 regcache_cache_bypass(s->regmap, false); 853 854 /* Update LCR register */ 855 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 856 857 /* Get baud rate generator configuration */ 858 baud = uart_get_baud_rate(port, termios, old, 859 port->uartclk / 16 / 4 / 0xffff, 860 port->uartclk / 16); 861 862 /* Setup baudrate generator */ 863 baud = sc16is7xx_set_baud(port, baud); 864 865 /* Update timeout according to new baud rate */ 866 uart_update_timeout(port, termios->c_cflag, baud); 867 } 868 869 static int sc16is7xx_config_rs485(struct uart_port *port, 870 struct serial_rs485 *rs485) 871 { 872 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 873 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 874 875 if (rs485->flags & SER_RS485_ENABLED) { 876 bool rts_during_rx, rts_during_tx; 877 878 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND; 879 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND; 880 881 if (rts_during_rx == rts_during_tx) 882 dev_err(port->dev, 883 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n", 884 rts_during_tx, rts_during_rx); 885 886 /* 887 * RTS signal is handled by HW, it's timing can't be influenced. 888 * However, it's sometimes useful to delay TX even without RTS 889 * control therefore we try to handle .delay_rts_before_send. 890 */ 891 if (rs485->delay_rts_after_send) 892 return -EINVAL; 893 } 894 895 port->rs485 = *rs485; 896 one->config.flags |= SC16IS7XX_RECONF_RS485; 897 queue_kthread_work(&s->kworker, &one->reg_work); 898 899 return 0; 900 } 901 902 static int sc16is7xx_startup(struct uart_port *port) 903 { 904 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 905 unsigned int val; 906 907 sc16is7xx_power(port, 1); 908 909 /* Reset FIFOs*/ 910 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 911 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 912 udelay(5); 913 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 914 SC16IS7XX_FCR_FIFO_BIT); 915 916 /* Enable EFR */ 917 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 918 SC16IS7XX_LCR_CONF_MODE_B); 919 920 regcache_cache_bypass(s->regmap, true); 921 922 /* Enable write access to enhanced features and internal clock div */ 923 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 924 SC16IS7XX_EFR_ENABLE_BIT); 925 926 /* Enable TCR/TLR */ 927 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 928 SC16IS7XX_MCR_TCRTLR_BIT, 929 SC16IS7XX_MCR_TCRTLR_BIT); 930 931 /* Configure flow control levels */ 932 /* Flow control halt level 48, resume level 24 */ 933 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 934 SC16IS7XX_TCR_RX_RESUME(24) | 935 SC16IS7XX_TCR_RX_HALT(48)); 936 937 regcache_cache_bypass(s->regmap, false); 938 939 /* Now, initialize the UART */ 940 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 941 942 /* Enable the Rx and Tx FIFO */ 943 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 944 SC16IS7XX_EFCR_RXDISABLE_BIT | 945 SC16IS7XX_EFCR_TXDISABLE_BIT, 946 0); 947 948 /* Enable RX, TX, CTS change interrupts */ 949 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT | 950 SC16IS7XX_IER_CTSI_BIT; 951 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 952 953 return 0; 954 } 955 956 static void sc16is7xx_shutdown(struct uart_port *port) 957 { 958 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 959 960 /* Disable all interrupts */ 961 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 962 /* Disable TX/RX */ 963 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 964 SC16IS7XX_EFCR_RXDISABLE_BIT | 965 SC16IS7XX_EFCR_TXDISABLE_BIT, 966 SC16IS7XX_EFCR_RXDISABLE_BIT | 967 SC16IS7XX_EFCR_TXDISABLE_BIT); 968 969 sc16is7xx_power(port, 0); 970 971 flush_kthread_worker(&s->kworker); 972 } 973 974 static const char *sc16is7xx_type(struct uart_port *port) 975 { 976 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 977 978 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 979 } 980 981 static int sc16is7xx_request_port(struct uart_port *port) 982 { 983 /* Do nothing */ 984 return 0; 985 } 986 987 static void sc16is7xx_config_port(struct uart_port *port, int flags) 988 { 989 if (flags & UART_CONFIG_TYPE) 990 port->type = PORT_SC16IS7XX; 991 } 992 993 static int sc16is7xx_verify_port(struct uart_port *port, 994 struct serial_struct *s) 995 { 996 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 997 return -EINVAL; 998 if (s->irq != port->irq) 999 return -EINVAL; 1000 1001 return 0; 1002 } 1003 1004 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1005 unsigned int oldstate) 1006 { 1007 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1008 } 1009 1010 static void sc16is7xx_null_void(struct uart_port *port) 1011 { 1012 /* Do nothing */ 1013 } 1014 1015 static const struct uart_ops sc16is7xx_ops = { 1016 .tx_empty = sc16is7xx_tx_empty, 1017 .set_mctrl = sc16is7xx_set_mctrl, 1018 .get_mctrl = sc16is7xx_get_mctrl, 1019 .stop_tx = sc16is7xx_stop_tx, 1020 .start_tx = sc16is7xx_start_tx, 1021 .stop_rx = sc16is7xx_stop_rx, 1022 .break_ctl = sc16is7xx_break_ctl, 1023 .startup = sc16is7xx_startup, 1024 .shutdown = sc16is7xx_shutdown, 1025 .set_termios = sc16is7xx_set_termios, 1026 .type = sc16is7xx_type, 1027 .request_port = sc16is7xx_request_port, 1028 .release_port = sc16is7xx_null_void, 1029 .config_port = sc16is7xx_config_port, 1030 .verify_port = sc16is7xx_verify_port, 1031 .pm = sc16is7xx_pm, 1032 }; 1033 1034 #ifdef CONFIG_GPIOLIB 1035 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1036 { 1037 unsigned int val; 1038 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1039 gpio); 1040 struct uart_port *port = &s->p[0].port; 1041 1042 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1043 1044 return !!(val & BIT(offset)); 1045 } 1046 1047 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1048 { 1049 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1050 gpio); 1051 struct uart_port *port = &s->p[0].port; 1052 1053 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1054 val ? BIT(offset) : 0); 1055 } 1056 1057 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1058 unsigned offset) 1059 { 1060 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1061 gpio); 1062 struct uart_port *port = &s->p[0].port; 1063 1064 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1065 1066 return 0; 1067 } 1068 1069 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1070 unsigned offset, int val) 1071 { 1072 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port, 1073 gpio); 1074 struct uart_port *port = &s->p[0].port; 1075 1076 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1077 val ? BIT(offset) : 0); 1078 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1079 BIT(offset)); 1080 1081 return 0; 1082 } 1083 #endif 1084 1085 static int sc16is7xx_probe(struct device *dev, 1086 struct sc16is7xx_devtype *devtype, 1087 struct regmap *regmap, int irq, unsigned long flags) 1088 { 1089 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 }; 1090 unsigned long freq, *pfreq = dev_get_platdata(dev); 1091 int i, ret; 1092 struct sc16is7xx_port *s; 1093 1094 if (IS_ERR(regmap)) 1095 return PTR_ERR(regmap); 1096 1097 /* Alloc port structure */ 1098 s = devm_kzalloc(dev, sizeof(*s) + 1099 sizeof(struct sc16is7xx_one) * devtype->nr_uart, 1100 GFP_KERNEL); 1101 if (!s) { 1102 dev_err(dev, "Error allocating port structure\n"); 1103 return -ENOMEM; 1104 } 1105 1106 s->clk = devm_clk_get(dev, NULL); 1107 if (IS_ERR(s->clk)) { 1108 if (pfreq) 1109 freq = *pfreq; 1110 else 1111 return PTR_ERR(s->clk); 1112 } else { 1113 clk_prepare_enable(s->clk); 1114 freq = clk_get_rate(s->clk); 1115 } 1116 1117 s->regmap = regmap; 1118 s->devtype = devtype; 1119 dev_set_drvdata(dev, s); 1120 1121 /* Register UART driver */ 1122 s->uart.owner = THIS_MODULE; 1123 s->uart.dev_name = "ttySC"; 1124 s->uart.nr = devtype->nr_uart; 1125 ret = uart_register_driver(&s->uart); 1126 if (ret) { 1127 dev_err(dev, "Registering UART driver failed\n"); 1128 goto out_clk; 1129 } 1130 1131 init_kthread_worker(&s->kworker); 1132 init_kthread_work(&s->irq_work, sc16is7xx_ist); 1133 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1134 "sc16is7xx"); 1135 if (IS_ERR(s->kworker_task)) { 1136 ret = PTR_ERR(s->kworker_task); 1137 goto out_uart; 1138 } 1139 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param); 1140 1141 #ifdef CONFIG_GPIOLIB 1142 if (devtype->nr_gpio) { 1143 /* Setup GPIO cotroller */ 1144 s->gpio.owner = THIS_MODULE; 1145 s->gpio.dev = dev; 1146 s->gpio.label = dev_name(dev); 1147 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1148 s->gpio.get = sc16is7xx_gpio_get; 1149 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1150 s->gpio.set = sc16is7xx_gpio_set; 1151 s->gpio.base = -1; 1152 s->gpio.ngpio = devtype->nr_gpio; 1153 s->gpio.can_sleep = 1; 1154 ret = gpiochip_add(&s->gpio); 1155 if (ret) 1156 goto out_thread; 1157 } 1158 #endif 1159 1160 for (i = 0; i < devtype->nr_uart; ++i) { 1161 /* Initialize port data */ 1162 s->p[i].port.line = i; 1163 s->p[i].port.dev = dev; 1164 s->p[i].port.irq = irq; 1165 s->p[i].port.type = PORT_SC16IS7XX; 1166 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1167 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1168 s->p[i].port.iotype = UPIO_PORT; 1169 s->p[i].port.uartclk = freq; 1170 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1171 s->p[i].port.ops = &sc16is7xx_ops; 1172 /* Disable all interrupts */ 1173 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1174 /* Disable TX/RX */ 1175 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1176 SC16IS7XX_EFCR_RXDISABLE_BIT | 1177 SC16IS7XX_EFCR_TXDISABLE_BIT); 1178 /* Initialize kthread work structs */ 1179 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1180 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1181 /* Register port */ 1182 uart_add_one_port(&s->uart, &s->p[i].port); 1183 /* Go to suspend mode */ 1184 sc16is7xx_power(&s->p[i].port, 0); 1185 } 1186 1187 /* Setup interrupt */ 1188 ret = devm_request_irq(dev, irq, sc16is7xx_irq, 1189 IRQF_ONESHOT | flags, dev_name(dev), s); 1190 if (!ret) 1191 return 0; 1192 1193 for (i = 0; i < s->uart.nr; i++) 1194 uart_remove_one_port(&s->uart, &s->p[i].port); 1195 1196 #ifdef CONFIG_GPIOLIB 1197 if (devtype->nr_gpio) 1198 gpiochip_remove(&s->gpio); 1199 1200 out_thread: 1201 #endif 1202 kthread_stop(s->kworker_task); 1203 1204 out_uart: 1205 uart_unregister_driver(&s->uart); 1206 1207 out_clk: 1208 if (!IS_ERR(s->clk)) 1209 clk_disable_unprepare(s->clk); 1210 1211 return ret; 1212 } 1213 1214 static int sc16is7xx_remove(struct device *dev) 1215 { 1216 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1217 int i; 1218 1219 #ifdef CONFIG_GPIOLIB 1220 if (s->devtype->nr_gpio) 1221 gpiochip_remove(&s->gpio); 1222 #endif 1223 1224 for (i = 0; i < s->uart.nr; i++) { 1225 uart_remove_one_port(&s->uart, &s->p[i].port); 1226 sc16is7xx_power(&s->p[i].port, 0); 1227 } 1228 1229 flush_kthread_worker(&s->kworker); 1230 kthread_stop(s->kworker_task); 1231 1232 uart_unregister_driver(&s->uart); 1233 if (!IS_ERR(s->clk)) 1234 clk_disable_unprepare(s->clk); 1235 1236 return 0; 1237 } 1238 1239 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1240 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1241 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1242 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1243 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1244 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1245 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1246 { } 1247 }; 1248 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1249 1250 static struct regmap_config regcfg = { 1251 .reg_bits = 7, 1252 .pad_bits = 1, 1253 .val_bits = 8, 1254 .cache_type = REGCACHE_RBTREE, 1255 .volatile_reg = sc16is7xx_regmap_volatile, 1256 .precious_reg = sc16is7xx_regmap_precious, 1257 }; 1258 1259 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1260 static int sc16is7xx_spi_probe(struct spi_device *spi) 1261 { 1262 struct sc16is7xx_devtype *devtype; 1263 unsigned long flags = 0; 1264 struct regmap *regmap; 1265 int ret; 1266 1267 /* Setup SPI bus */ 1268 spi->bits_per_word = 8; 1269 /* only supports mode 0 on SC16IS762 */ 1270 spi->mode = spi->mode ? : SPI_MODE_0; 1271 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; 1272 ret = spi_setup(spi); 1273 if (ret) 1274 return ret; 1275 1276 if (spi->dev.of_node) { 1277 const struct of_device_id *of_id = 1278 of_match_device(sc16is7xx_dt_ids, &spi->dev); 1279 1280 devtype = (struct sc16is7xx_devtype *)of_id->data; 1281 } else { 1282 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1283 1284 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1285 flags = IRQF_TRIGGER_FALLING; 1286 } 1287 1288 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1289 (devtype->nr_uart - 1); 1290 regmap = devm_regmap_init_spi(spi, ®cfg); 1291 1292 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags); 1293 } 1294 1295 static int sc16is7xx_spi_remove(struct spi_device *spi) 1296 { 1297 return sc16is7xx_remove(&spi->dev); 1298 } 1299 1300 static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1301 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1302 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1303 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1304 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1305 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1306 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1307 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1308 { } 1309 }; 1310 1311 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1312 1313 static struct spi_driver sc16is7xx_spi_uart_driver = { 1314 .driver = { 1315 .name = SC16IS7XX_NAME, 1316 .owner = THIS_MODULE, 1317 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1318 }, 1319 .probe = sc16is7xx_spi_probe, 1320 .remove = sc16is7xx_spi_remove, 1321 .id_table = sc16is7xx_spi_id_table, 1322 }; 1323 1324 MODULE_ALIAS("spi:sc16is7xx"); 1325 #endif 1326 1327 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1328 static int sc16is7xx_i2c_probe(struct i2c_client *i2c, 1329 const struct i2c_device_id *id) 1330 { 1331 struct sc16is7xx_devtype *devtype; 1332 unsigned long flags = 0; 1333 struct regmap *regmap; 1334 1335 if (i2c->dev.of_node) { 1336 const struct of_device_id *of_id = 1337 of_match_device(sc16is7xx_dt_ids, &i2c->dev); 1338 1339 devtype = (struct sc16is7xx_devtype *)of_id->data; 1340 } else { 1341 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1342 flags = IRQF_TRIGGER_FALLING; 1343 } 1344 1345 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) | 1346 (devtype->nr_uart - 1); 1347 regmap = devm_regmap_init_i2c(i2c, ®cfg); 1348 1349 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags); 1350 } 1351 1352 static int sc16is7xx_i2c_remove(struct i2c_client *client) 1353 { 1354 return sc16is7xx_remove(&client->dev); 1355 } 1356 1357 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1358 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1359 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1360 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1361 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1362 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1363 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1364 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1365 { } 1366 }; 1367 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1368 1369 static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1370 .driver = { 1371 .name = SC16IS7XX_NAME, 1372 .owner = THIS_MODULE, 1373 .of_match_table = of_match_ptr(sc16is7xx_dt_ids), 1374 }, 1375 .probe = sc16is7xx_i2c_probe, 1376 .remove = sc16is7xx_i2c_remove, 1377 .id_table = sc16is7xx_i2c_id_table, 1378 }; 1379 1380 MODULE_ALIAS("i2c:sc16is7xx"); 1381 #endif 1382 1383 static int __init sc16is7xx_init(void) 1384 { 1385 int ret = 0; 1386 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1387 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1388 if (ret < 0) { 1389 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1390 return ret; 1391 } 1392 #endif 1393 1394 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1395 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1396 if (ret < 0) { 1397 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1398 return ret; 1399 } 1400 #endif 1401 return ret; 1402 } 1403 module_init(sc16is7xx_init); 1404 1405 static void __exit sc16is7xx_exit(void) 1406 { 1407 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1408 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1409 #endif 1410 1411 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1412 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1413 #endif 1414 } 1415 module_exit(sc16is7xx_exit); 1416 1417 MODULE_LICENSE("GPL"); 1418 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1419 MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1420