1 /* 2 * Support for the asynchronous serial interface (DUART) included 3 * in the BCM1250 and derived System-On-a-Chip (SOC) devices. 4 * 5 * Copyright (c) 2007 Maciej W. Rozycki 6 * 7 * Derived from drivers/char/sb1250_duart.c for which the following 8 * copyright applies: 9 * 10 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 * 17 * References: 18 * 19 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation 20 */ 21 22 #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 23 #define SUPPORT_SYSRQ 24 #endif 25 26 #include <linux/compiler.h> 27 #include <linux/console.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/ioport.h> 33 #include <linux/kernel.h> 34 #include <linux/major.h> 35 #include <linux/serial.h> 36 #include <linux/serial_core.h> 37 #include <linux/spinlock.h> 38 #include <linux/sysrq.h> 39 #include <linux/tty.h> 40 #include <linux/types.h> 41 42 #include <linux/atomic.h> 43 #include <asm/io.h> 44 #include <asm/war.h> 45 46 #include <asm/sibyte/sb1250.h> 47 #include <asm/sibyte/sb1250_uart.h> 48 #include <asm/sibyte/swarm.h> 49 50 51 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 52 #include <asm/sibyte/bcm1480_regs.h> 53 #include <asm/sibyte/bcm1480_int.h> 54 55 #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0) 56 #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0) 57 #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line)) 58 59 #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING 60 61 #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line) 62 #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line) 63 #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line) 64 65 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 66 #include <asm/sibyte/sb1250_regs.h> 67 #include <asm/sibyte/sb1250_int.h> 68 69 #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0) 70 #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0) 71 #define SBD_INT(line) (K_INT_UART_0 + (line)) 72 73 #else 74 #error invalid SB1250 UART configuration 75 76 #endif 77 78 79 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); 80 MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver"); 81 MODULE_LICENSE("GPL"); 82 83 84 #define DUART_MAX_CHIP 2 85 #define DUART_MAX_SIDE 2 86 87 /* 88 * Per-port state. 89 */ 90 struct sbd_port { 91 struct sbd_duart *duart; 92 struct uart_port port; 93 unsigned char __iomem *memctrl; 94 int tx_stopped; 95 int initialised; 96 }; 97 98 /* 99 * Per-DUART state for the shared register space. 100 */ 101 struct sbd_duart { 102 struct sbd_port sport[2]; 103 unsigned long mapctrl; 104 atomic_t map_guard; 105 }; 106 107 #define to_sport(uport) container_of(uport, struct sbd_port, port) 108 109 static struct sbd_duart sbd_duarts[DUART_MAX_CHIP]; 110 111 112 /* 113 * Reading and writing SB1250 DUART registers. 114 * 115 * There are three register spaces: two per-channel ones and 116 * a shared one. We have to define accessors appropriately. 117 * All registers are 64-bit and all but the Baud Rate Clock 118 * registers only define 8 least significant bits. There is 119 * also a workaround to take into account. Raw accessors use 120 * the full register width, but cooked ones truncate it 121 * intentionally so that the rest of the driver does not care. 122 */ 123 static u64 __read_sbdchn(struct sbd_port *sport, int reg) 124 { 125 void __iomem *csr = sport->port.membase + reg; 126 127 return __raw_readq(csr); 128 } 129 130 static u64 __read_sbdshr(struct sbd_port *sport, int reg) 131 { 132 void __iomem *csr = sport->memctrl + reg; 133 134 return __raw_readq(csr); 135 } 136 137 static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value) 138 { 139 void __iomem *csr = sport->port.membase + reg; 140 141 __raw_writeq(value, csr); 142 } 143 144 static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value) 145 { 146 void __iomem *csr = sport->memctrl + reg; 147 148 __raw_writeq(value, csr); 149 } 150 151 /* 152 * In bug 1956, we get glitches that can mess up uart registers. This 153 * "read-mode-reg after any register access" is an accepted workaround. 154 */ 155 static void __war_sbd1956(struct sbd_port *sport) 156 { 157 __read_sbdchn(sport, R_DUART_MODE_REG_1); 158 __read_sbdchn(sport, R_DUART_MODE_REG_2); 159 } 160 161 static unsigned char read_sbdchn(struct sbd_port *sport, int reg) 162 { 163 unsigned char retval; 164 165 retval = __read_sbdchn(sport, reg); 166 if (SIBYTE_1956_WAR) 167 __war_sbd1956(sport); 168 return retval; 169 } 170 171 static unsigned char read_sbdshr(struct sbd_port *sport, int reg) 172 { 173 unsigned char retval; 174 175 retval = __read_sbdshr(sport, reg); 176 if (SIBYTE_1956_WAR) 177 __war_sbd1956(sport); 178 return retval; 179 } 180 181 static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value) 182 { 183 __write_sbdchn(sport, reg, value); 184 if (SIBYTE_1956_WAR) 185 __war_sbd1956(sport); 186 } 187 188 static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value) 189 { 190 __write_sbdshr(sport, reg, value); 191 if (SIBYTE_1956_WAR) 192 __war_sbd1956(sport); 193 } 194 195 196 static int sbd_receive_ready(struct sbd_port *sport) 197 { 198 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY; 199 } 200 201 static int sbd_receive_drain(struct sbd_port *sport) 202 { 203 int loops = 10000; 204 205 while (sbd_receive_ready(sport) && --loops) 206 read_sbdchn(sport, R_DUART_RX_HOLD); 207 return loops; 208 } 209 210 static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport) 211 { 212 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY; 213 } 214 215 static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport) 216 { 217 int loops = 10000; 218 219 while (!sbd_transmit_ready(sport) && --loops) 220 udelay(2); 221 return loops; 222 } 223 224 static int sbd_transmit_empty(struct sbd_port *sport) 225 { 226 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT; 227 } 228 229 static int sbd_line_drain(struct sbd_port *sport) 230 { 231 int loops = 10000; 232 233 while (!sbd_transmit_empty(sport) && --loops) 234 udelay(2); 235 return loops; 236 } 237 238 239 static unsigned int sbd_tx_empty(struct uart_port *uport) 240 { 241 struct sbd_port *sport = to_sport(uport); 242 243 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0; 244 } 245 246 static unsigned int sbd_get_mctrl(struct uart_port *uport) 247 { 248 struct sbd_port *sport = to_sport(uport); 249 unsigned int mctrl, status; 250 251 status = read_sbdshr(sport, R_DUART_IN_PORT); 252 status >>= (uport->line) % 2; 253 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) | 254 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) | 255 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) | 256 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0); 257 return mctrl; 258 } 259 260 static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl) 261 { 262 struct sbd_port *sport = to_sport(uport); 263 unsigned int clr = 0, set = 0, mode2; 264 265 if (mctrl & TIOCM_DTR) 266 set |= M_DUART_SET_OPR2; 267 else 268 clr |= M_DUART_CLR_OPR2; 269 if (mctrl & TIOCM_RTS) 270 set |= M_DUART_SET_OPR0; 271 else 272 clr |= M_DUART_CLR_OPR0; 273 clr <<= (uport->line) % 2; 274 set <<= (uport->line) % 2; 275 276 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2); 277 mode2 &= ~M_DUART_CHAN_MODE; 278 if (mctrl & TIOCM_LOOP) 279 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP; 280 else 281 mode2 |= V_DUART_CHAN_MODE_NORMAL; 282 283 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); 284 write_sbdshr(sport, R_DUART_SET_OPR, set); 285 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2); 286 } 287 288 static void sbd_stop_tx(struct uart_port *uport) 289 { 290 struct sbd_port *sport = to_sport(uport); 291 292 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 293 sport->tx_stopped = 1; 294 }; 295 296 static void sbd_start_tx(struct uart_port *uport) 297 { 298 struct sbd_port *sport = to_sport(uport); 299 unsigned int mask; 300 301 /* Enable tx interrupts. */ 302 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 303 mask |= M_DUART_IMR_TX; 304 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 305 306 /* Go!, go!, go!... */ 307 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 308 sport->tx_stopped = 0; 309 }; 310 311 static void sbd_stop_rx(struct uart_port *uport) 312 { 313 struct sbd_port *sport = to_sport(uport); 314 315 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); 316 }; 317 318 static void sbd_enable_ms(struct uart_port *uport) 319 { 320 struct sbd_port *sport = to_sport(uport); 321 322 write_sbdchn(sport, R_DUART_AUXCTL_X, 323 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA); 324 } 325 326 static void sbd_break_ctl(struct uart_port *uport, int break_state) 327 { 328 struct sbd_port *sport = to_sport(uport); 329 330 if (break_state == -1) 331 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK); 332 else 333 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK); 334 } 335 336 337 static void sbd_receive_chars(struct sbd_port *sport) 338 { 339 struct uart_port *uport = &sport->port; 340 struct uart_icount *icount; 341 unsigned int status, ch, flag; 342 int count; 343 344 for (count = 16; count; count--) { 345 status = read_sbdchn(sport, R_DUART_STATUS); 346 if (!(status & M_DUART_RX_RDY)) 347 break; 348 349 ch = read_sbdchn(sport, R_DUART_RX_HOLD); 350 351 flag = TTY_NORMAL; 352 353 icount = &uport->icount; 354 icount->rx++; 355 356 if (unlikely(status & 357 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR | 358 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) { 359 if (status & M_DUART_RCVD_BRK) { 360 icount->brk++; 361 if (uart_handle_break(uport)) 362 continue; 363 } else if (status & M_DUART_FRM_ERR) 364 icount->frame++; 365 else if (status & M_DUART_PARITY_ERR) 366 icount->parity++; 367 if (status & M_DUART_OVRUN_ERR) 368 icount->overrun++; 369 370 status &= uport->read_status_mask; 371 if (status & M_DUART_RCVD_BRK) 372 flag = TTY_BREAK; 373 else if (status & M_DUART_FRM_ERR) 374 flag = TTY_FRAME; 375 else if (status & M_DUART_PARITY_ERR) 376 flag = TTY_PARITY; 377 } 378 379 if (uart_handle_sysrq_char(uport, ch)) 380 continue; 381 382 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag); 383 } 384 385 tty_flip_buffer_push(uport->state->port.tty); 386 } 387 388 static void sbd_transmit_chars(struct sbd_port *sport) 389 { 390 struct uart_port *uport = &sport->port; 391 struct circ_buf *xmit = &sport->port.state->xmit; 392 unsigned int mask; 393 int stop_tx; 394 395 /* XON/XOFF chars. */ 396 if (sport->port.x_char) { 397 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char); 398 sport->port.icount.tx++; 399 sport->port.x_char = 0; 400 return; 401 } 402 403 /* If nothing to do or stopped or hardware stopped. */ 404 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)); 405 406 /* Send char. */ 407 if (!stop_tx) { 408 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]); 409 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 410 sport->port.icount.tx++; 411 412 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 413 uart_write_wakeup(&sport->port); 414 } 415 416 /* Are we are done? */ 417 if (stop_tx || uart_circ_empty(xmit)) { 418 /* Disable tx interrupts. */ 419 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 420 mask &= ~M_DUART_IMR_TX; 421 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 422 } 423 } 424 425 static void sbd_status_handle(struct sbd_port *sport) 426 { 427 struct uart_port *uport = &sport->port; 428 unsigned int delta; 429 430 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); 431 delta >>= (uport->line) % 2; 432 433 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG)) 434 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL)); 435 436 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG)) 437 uport->icount.dsr++; 438 439 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) << 440 S_DUART_IN_PIN_CHNG)) 441 wake_up_interruptible(&uport->state->port.delta_msr_wait); 442 } 443 444 static irqreturn_t sbd_interrupt(int irq, void *dev_id) 445 { 446 struct sbd_port *sport = dev_id; 447 struct uart_port *uport = &sport->port; 448 irqreturn_t status = IRQ_NONE; 449 unsigned int intstat; 450 int count; 451 452 for (count = 16; count; count--) { 453 intstat = read_sbdshr(sport, 454 R_DUART_ISRREG((uport->line) % 2)); 455 intstat &= read_sbdshr(sport, 456 R_DUART_IMRREG((uport->line) % 2)); 457 intstat &= M_DUART_ISR_ALL; 458 if (!intstat) 459 break; 460 461 if (intstat & M_DUART_ISR_RX) 462 sbd_receive_chars(sport); 463 if (intstat & M_DUART_ISR_IN) 464 sbd_status_handle(sport); 465 if (intstat & M_DUART_ISR_TX) 466 sbd_transmit_chars(sport); 467 468 status = IRQ_HANDLED; 469 } 470 471 return status; 472 } 473 474 475 static int sbd_startup(struct uart_port *uport) 476 { 477 struct sbd_port *sport = to_sport(uport); 478 unsigned int mode1; 479 int ret; 480 481 ret = request_irq(sport->port.irq, sbd_interrupt, 482 IRQF_SHARED, "sb1250-duart", sport); 483 if (ret) 484 return ret; 485 486 /* Clear the receive FIFO. */ 487 sbd_receive_drain(sport); 488 489 /* Clear the interrupt registers. */ 490 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT); 491 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); 492 493 /* Set rx/tx interrupt to FIFO available. */ 494 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1); 495 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT); 496 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1); 497 498 /* Disable tx, enable rx. */ 499 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN); 500 sport->tx_stopped = 1; 501 502 /* Enable interrupts. */ 503 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 504 M_DUART_IMR_IN | M_DUART_IMR_RX); 505 506 return 0; 507 } 508 509 static void sbd_shutdown(struct uart_port *uport) 510 { 511 struct sbd_port *sport = to_sport(uport); 512 513 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); 514 sport->tx_stopped = 1; 515 free_irq(sport->port.irq, sport); 516 } 517 518 519 static void sbd_init_port(struct sbd_port *sport) 520 { 521 struct uart_port *uport = &sport->port; 522 523 if (sport->initialised) 524 return; 525 526 /* There is no DUART reset feature, so just set some sane defaults. */ 527 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX); 528 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX); 529 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8); 530 write_sbdchn(sport, R_DUART_MODE_REG_2, 0); 531 write_sbdchn(sport, R_DUART_FULL_CTL, 532 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15)); 533 write_sbdchn(sport, R_DUART_OPCR_X, 0); 534 write_sbdchn(sport, R_DUART_AUXCTL_X, 0); 535 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); 536 537 sport->initialised = 1; 538 } 539 540 static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios, 541 struct ktermios *old_termios) 542 { 543 struct sbd_port *sport = to_sport(uport); 544 unsigned int mode1 = 0, mode2 = 0, aux = 0; 545 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0; 546 unsigned int oldmode1, oldmode2, oldaux; 547 unsigned int baud, brg; 548 unsigned int command; 549 550 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD | 551 M_DUART_BITS_PER_CHAR); 552 mode2mask |= ~M_DUART_STOP_BIT_LEN_2; 553 auxmask |= ~M_DUART_CTS_CHNG_ENA; 554 555 /* Byte size. */ 556 switch (termios->c_cflag & CSIZE) { 557 case CS5: 558 case CS6: 559 /* Unsupported, leave unchanged. */ 560 mode1mask |= M_DUART_PARITY_MODE; 561 break; 562 case CS7: 563 mode1 |= V_DUART_BITS_PER_CHAR_7; 564 break; 565 case CS8: 566 default: 567 mode1 |= V_DUART_BITS_PER_CHAR_8; 568 break; 569 } 570 571 /* Parity and stop bits. */ 572 if (termios->c_cflag & CSTOPB) 573 mode2 |= M_DUART_STOP_BIT_LEN_2; 574 else 575 mode2 |= M_DUART_STOP_BIT_LEN_1; 576 if (termios->c_cflag & PARENB) 577 mode1 |= V_DUART_PARITY_MODE_ADD; 578 else 579 mode1 |= V_DUART_PARITY_MODE_NONE; 580 if (termios->c_cflag & PARODD) 581 mode1 |= M_DUART_PARITY_TYPE_ODD; 582 else 583 mode1 |= M_DUART_PARITY_TYPE_EVEN; 584 585 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000); 586 brg = V_DUART_BAUD_RATE(baud); 587 /* The actual lower bound is 1221bps, so compensate. */ 588 if (brg > M_DUART_CLK_COUNTER) 589 brg = M_DUART_CLK_COUNTER; 590 591 uart_update_timeout(uport, termios->c_cflag, baud); 592 593 uport->read_status_mask = M_DUART_OVRUN_ERR; 594 if (termios->c_iflag & INPCK) 595 uport->read_status_mask |= M_DUART_FRM_ERR | 596 M_DUART_PARITY_ERR; 597 if (termios->c_iflag & (BRKINT | PARMRK)) 598 uport->read_status_mask |= M_DUART_RCVD_BRK; 599 600 uport->ignore_status_mask = 0; 601 if (termios->c_iflag & IGNPAR) 602 uport->ignore_status_mask |= M_DUART_FRM_ERR | 603 M_DUART_PARITY_ERR; 604 if (termios->c_iflag & IGNBRK) { 605 uport->ignore_status_mask |= M_DUART_RCVD_BRK; 606 if (termios->c_iflag & IGNPAR) 607 uport->ignore_status_mask |= M_DUART_OVRUN_ERR; 608 } 609 610 if (termios->c_cflag & CREAD) 611 command = M_DUART_RX_EN; 612 else 613 command = M_DUART_RX_DIS; 614 615 if (termios->c_cflag & CRTSCTS) 616 aux |= M_DUART_CTS_CHNG_ENA; 617 else 618 aux &= ~M_DUART_CTS_CHNG_ENA; 619 620 spin_lock(&uport->lock); 621 622 if (sport->tx_stopped) 623 command |= M_DUART_TX_DIS; 624 else 625 command |= M_DUART_TX_EN; 626 627 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask; 628 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask; 629 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask; 630 631 if (!sport->tx_stopped) 632 sbd_line_drain(sport); 633 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); 634 635 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1); 636 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2); 637 write_sbdchn(sport, R_DUART_CLK_SEL, brg); 638 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux); 639 640 write_sbdchn(sport, R_DUART_CMD, command); 641 642 spin_unlock(&uport->lock); 643 } 644 645 646 static const char *sbd_type(struct uart_port *uport) 647 { 648 return "SB1250 DUART"; 649 } 650 651 static void sbd_release_port(struct uart_port *uport) 652 { 653 struct sbd_port *sport = to_sport(uport); 654 struct sbd_duart *duart = sport->duart; 655 int map_guard; 656 657 iounmap(sport->memctrl); 658 sport->memctrl = NULL; 659 iounmap(uport->membase); 660 uport->membase = NULL; 661 662 map_guard = atomic_add_return(-1, &duart->map_guard); 663 if (!map_guard) 664 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING); 665 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); 666 } 667 668 static int sbd_map_port(struct uart_port *uport) 669 { 670 const char *err = KERN_ERR "sbd: Cannot map MMIO\n"; 671 struct sbd_port *sport = to_sport(uport); 672 struct sbd_duart *duart = sport->duart; 673 674 if (!uport->membase) 675 uport->membase = ioremap_nocache(uport->mapbase, 676 DUART_CHANREG_SPACING); 677 if (!uport->membase) { 678 printk(err); 679 return -ENOMEM; 680 } 681 682 if (!sport->memctrl) 683 sport->memctrl = ioremap_nocache(duart->mapctrl, 684 DUART_CHANREG_SPACING); 685 if (!sport->memctrl) { 686 printk(err); 687 iounmap(uport->membase); 688 uport->membase = NULL; 689 return -ENOMEM; 690 } 691 692 return 0; 693 } 694 695 static int sbd_request_port(struct uart_port *uport) 696 { 697 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n"; 698 struct sbd_duart *duart = to_sport(uport)->duart; 699 int map_guard; 700 int ret = 0; 701 702 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING, 703 "sb1250-duart")) { 704 printk(err); 705 return -EBUSY; 706 } 707 map_guard = atomic_add_return(1, &duart->map_guard); 708 if (map_guard == 1) { 709 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING, 710 "sb1250-duart")) { 711 atomic_add(-1, &duart->map_guard); 712 printk(err); 713 ret = -EBUSY; 714 } 715 } 716 if (!ret) { 717 ret = sbd_map_port(uport); 718 if (ret) { 719 map_guard = atomic_add_return(-1, &duart->map_guard); 720 if (!map_guard) 721 release_mem_region(duart->mapctrl, 722 DUART_CHANREG_SPACING); 723 } 724 } 725 if (ret) { 726 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); 727 return ret; 728 } 729 return 0; 730 } 731 732 static void sbd_config_port(struct uart_port *uport, int flags) 733 { 734 struct sbd_port *sport = to_sport(uport); 735 736 if (flags & UART_CONFIG_TYPE) { 737 if (sbd_request_port(uport)) 738 return; 739 740 uport->type = PORT_SB1250_DUART; 741 742 sbd_init_port(sport); 743 } 744 } 745 746 static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser) 747 { 748 int ret = 0; 749 750 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART) 751 ret = -EINVAL; 752 if (ser->irq != uport->irq) 753 ret = -EINVAL; 754 if (ser->baud_base != uport->uartclk / 16) 755 ret = -EINVAL; 756 return ret; 757 } 758 759 760 static const struct uart_ops sbd_ops = { 761 .tx_empty = sbd_tx_empty, 762 .set_mctrl = sbd_set_mctrl, 763 .get_mctrl = sbd_get_mctrl, 764 .stop_tx = sbd_stop_tx, 765 .start_tx = sbd_start_tx, 766 .stop_rx = sbd_stop_rx, 767 .enable_ms = sbd_enable_ms, 768 .break_ctl = sbd_break_ctl, 769 .startup = sbd_startup, 770 .shutdown = sbd_shutdown, 771 .set_termios = sbd_set_termios, 772 .type = sbd_type, 773 .release_port = sbd_release_port, 774 .request_port = sbd_request_port, 775 .config_port = sbd_config_port, 776 .verify_port = sbd_verify_port, 777 }; 778 779 /* Initialize SB1250 DUART port structures. */ 780 static void __init sbd_probe_duarts(void) 781 { 782 static int probed; 783 int chip, side; 784 int max_lines, line; 785 786 if (probed) 787 return; 788 789 /* Set the number of available units based on the SOC type. */ 790 switch (soc_type) { 791 case K_SYS_SOC_TYPE_BCM1x55: 792 case K_SYS_SOC_TYPE_BCM1x80: 793 max_lines = 4; 794 break; 795 default: 796 /* Assume at least two serial ports at the normal address. */ 797 max_lines = 2; 798 break; 799 } 800 801 probed = 1; 802 803 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines; 804 chip++) { 805 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line); 806 807 for (side = 0; side < DUART_MAX_SIDE && line < max_lines; 808 side++, line++) { 809 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 810 struct uart_port *uport = &sport->port; 811 812 sport->duart = &sbd_duarts[chip]; 813 814 uport->irq = SBD_INT(line); 815 uport->uartclk = 100000000 / 20 * 16; 816 uport->fifosize = 16; 817 uport->iotype = UPIO_MEM; 818 uport->flags = UPF_BOOT_AUTOCONF; 819 uport->ops = &sbd_ops; 820 uport->line = line; 821 uport->mapbase = SBD_CHANREGS(line); 822 } 823 } 824 } 825 826 827 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE 828 /* 829 * Serial console stuff. Very basic, polling driver for doing serial 830 * console output. The console_lock is held by the caller, so we 831 * shouldn't be interrupted for more console activity. 832 */ 833 static void sbd_console_putchar(struct uart_port *uport, int ch) 834 { 835 struct sbd_port *sport = to_sport(uport); 836 837 sbd_transmit_drain(sport); 838 write_sbdchn(sport, R_DUART_TX_HOLD, ch); 839 } 840 841 static void sbd_console_write(struct console *co, const char *s, 842 unsigned int count) 843 { 844 int chip = co->index / DUART_MAX_SIDE; 845 int side = co->index % DUART_MAX_SIDE; 846 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 847 struct uart_port *uport = &sport->port; 848 unsigned long flags; 849 unsigned int mask; 850 851 /* Disable transmit interrupts and enable the transmitter. */ 852 spin_lock_irqsave(&uport->lock, flags); 853 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 854 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 855 mask & ~M_DUART_IMR_TX); 856 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 857 spin_unlock_irqrestore(&uport->lock, flags); 858 859 uart_console_write(&sport->port, s, count, sbd_console_putchar); 860 861 /* Restore transmit interrupts and the transmitter enable. */ 862 spin_lock_irqsave(&uport->lock, flags); 863 sbd_line_drain(sport); 864 if (sport->tx_stopped) 865 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 866 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 867 spin_unlock_irqrestore(&uport->lock, flags); 868 } 869 870 static int __init sbd_console_setup(struct console *co, char *options) 871 { 872 int chip = co->index / DUART_MAX_SIDE; 873 int side = co->index % DUART_MAX_SIDE; 874 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 875 struct uart_port *uport = &sport->port; 876 int baud = 115200; 877 int bits = 8; 878 int parity = 'n'; 879 int flow = 'n'; 880 int ret; 881 882 if (!sport->duart) 883 return -ENXIO; 884 885 ret = sbd_map_port(uport); 886 if (ret) 887 return ret; 888 889 sbd_init_port(sport); 890 891 if (options) 892 uart_parse_options(options, &baud, &parity, &bits, &flow); 893 return uart_set_options(uport, co, baud, parity, bits, flow); 894 } 895 896 static struct uart_driver sbd_reg; 897 static struct console sbd_console = { 898 .name = "duart", 899 .write = sbd_console_write, 900 .device = uart_console_device, 901 .setup = sbd_console_setup, 902 .flags = CON_PRINTBUFFER, 903 .index = -1, 904 .data = &sbd_reg 905 }; 906 907 static int __init sbd_serial_console_init(void) 908 { 909 sbd_probe_duarts(); 910 register_console(&sbd_console); 911 912 return 0; 913 } 914 915 console_initcall(sbd_serial_console_init); 916 917 #define SERIAL_SB1250_DUART_CONSOLE &sbd_console 918 #else 919 #define SERIAL_SB1250_DUART_CONSOLE NULL 920 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */ 921 922 923 static struct uart_driver sbd_reg = { 924 .owner = THIS_MODULE, 925 .driver_name = "sb1250_duart", 926 .dev_name = "duart", 927 .major = TTY_MAJOR, 928 .minor = SB1250_DUART_MINOR_BASE, 929 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE, 930 .cons = SERIAL_SB1250_DUART_CONSOLE, 931 }; 932 933 /* Set up the driver and register it. */ 934 static int __init sbd_init(void) 935 { 936 int i, ret; 937 938 sbd_probe_duarts(); 939 940 ret = uart_register_driver(&sbd_reg); 941 if (ret) 942 return ret; 943 944 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) { 945 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; 946 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; 947 struct uart_port *uport = &sport->port; 948 949 if (sport->duart) 950 uart_add_one_port(&sbd_reg, uport); 951 } 952 953 return 0; 954 } 955 956 /* Unload the driver. Unregister stuff, get ready to go away. */ 957 static void __exit sbd_exit(void) 958 { 959 int i; 960 961 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) { 962 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; 963 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; 964 struct uart_port *uport = &sport->port; 965 966 if (sport->duart) 967 uart_remove_one_port(&sbd_reg, uport); 968 } 969 970 uart_unregister_driver(&sbd_reg); 971 } 972 973 module_init(sbd_init); 974 module_exit(sbd_exit); 975