1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Support for the asynchronous serial interface (DUART) included 4 * in the BCM1250 and derived System-On-a-Chip (SOC) devices. 5 * 6 * Copyright (c) 2007 Maciej W. Rozycki 7 * 8 * Derived from drivers/char/sb1250_duart.c for which the following 9 * copyright applies: 10 * 11 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation 12 * 13 * References: 14 * 15 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation 16 */ 17 18 #include <linux/compiler.h> 19 #include <linux/console.h> 20 #include <linux/delay.h> 21 #include <linux/errno.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/major.h> 28 #include <linux/serial.h> 29 #include <linux/serial_core.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty.h> 33 #include <linux/tty_flip.h> 34 #include <linux/types.h> 35 36 #include <linux/refcount.h> 37 #include <linux/io.h> 38 39 #include <asm/sibyte/sb1250.h> 40 #include <asm/sibyte/sb1250_uart.h> 41 #include <asm/sibyte/swarm.h> 42 43 44 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 45 #include <asm/sibyte/bcm1480_regs.h> 46 #include <asm/sibyte/bcm1480_int.h> 47 48 #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0) 49 #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0) 50 #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line)) 51 52 #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING 53 54 #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line) 55 #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line) 56 #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line) 57 58 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 59 #include <asm/sibyte/sb1250_regs.h> 60 #include <asm/sibyte/sb1250_int.h> 61 62 #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0) 63 #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0) 64 #define SBD_INT(line) (K_INT_UART_0 + (line)) 65 66 #else 67 #error invalid SB1250 UART configuration 68 69 #endif 70 71 72 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); 73 MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver"); 74 MODULE_LICENSE("GPL"); 75 76 77 #define DUART_MAX_CHIP 2 78 #define DUART_MAX_SIDE 2 79 80 /* 81 * Per-port state. 82 */ 83 struct sbd_port { 84 struct sbd_duart *duart; 85 struct uart_port port; 86 unsigned char __iomem *memctrl; 87 int tx_stopped; 88 int initialised; 89 }; 90 91 /* 92 * Per-DUART state for the shared register space. 93 */ 94 struct sbd_duart { 95 struct sbd_port sport[2]; 96 unsigned long mapctrl; 97 refcount_t map_guard; 98 }; 99 100 #define to_sport(uport) container_of(uport, struct sbd_port, port) 101 102 static struct sbd_duart sbd_duarts[DUART_MAX_CHIP]; 103 104 105 /* 106 * Reading and writing SB1250 DUART registers. 107 * 108 * There are three register spaces: two per-channel ones and 109 * a shared one. We have to define accessors appropriately. 110 * All registers are 64-bit and all but the Baud Rate Clock 111 * registers only define 8 least significant bits. There is 112 * also a workaround to take into account. Raw accessors use 113 * the full register width, but cooked ones truncate it 114 * intentionally so that the rest of the driver does not care. 115 */ 116 static u64 __read_sbdchn(struct sbd_port *sport, int reg) 117 { 118 void __iomem *csr = sport->port.membase + reg; 119 120 return __raw_readq(csr); 121 } 122 123 static u64 __read_sbdshr(struct sbd_port *sport, int reg) 124 { 125 void __iomem *csr = sport->memctrl + reg; 126 127 return __raw_readq(csr); 128 } 129 130 static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value) 131 { 132 void __iomem *csr = sport->port.membase + reg; 133 134 __raw_writeq(value, csr); 135 } 136 137 static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value) 138 { 139 void __iomem *csr = sport->memctrl + reg; 140 141 __raw_writeq(value, csr); 142 } 143 144 /* 145 * In bug 1956, we get glitches that can mess up uart registers. This 146 * "read-mode-reg after any register access" is an accepted workaround. 147 */ 148 static void __war_sbd1956(struct sbd_port *sport) 149 { 150 __read_sbdchn(sport, R_DUART_MODE_REG_1); 151 __read_sbdchn(sport, R_DUART_MODE_REG_2); 152 } 153 154 static unsigned char read_sbdchn(struct sbd_port *sport, int reg) 155 { 156 unsigned char retval; 157 158 retval = __read_sbdchn(sport, reg); 159 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) 160 __war_sbd1956(sport); 161 return retval; 162 } 163 164 static unsigned char read_sbdshr(struct sbd_port *sport, int reg) 165 { 166 unsigned char retval; 167 168 retval = __read_sbdshr(sport, reg); 169 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) 170 __war_sbd1956(sport); 171 return retval; 172 } 173 174 static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value) 175 { 176 __write_sbdchn(sport, reg, value); 177 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) 178 __war_sbd1956(sport); 179 } 180 181 static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value) 182 { 183 __write_sbdshr(sport, reg, value); 184 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) 185 __war_sbd1956(sport); 186 } 187 188 189 static int sbd_receive_ready(struct sbd_port *sport) 190 { 191 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY; 192 } 193 194 static int sbd_receive_drain(struct sbd_port *sport) 195 { 196 int loops = 10000; 197 198 while (sbd_receive_ready(sport) && --loops) 199 read_sbdchn(sport, R_DUART_RX_HOLD); 200 return loops; 201 } 202 203 static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport) 204 { 205 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY; 206 } 207 208 static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport) 209 { 210 int loops = 10000; 211 212 while (!sbd_transmit_ready(sport) && --loops) 213 udelay(2); 214 return loops; 215 } 216 217 static int sbd_transmit_empty(struct sbd_port *sport) 218 { 219 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT; 220 } 221 222 static int sbd_line_drain(struct sbd_port *sport) 223 { 224 int loops = 10000; 225 226 while (!sbd_transmit_empty(sport) && --loops) 227 udelay(2); 228 return loops; 229 } 230 231 232 static unsigned int sbd_tx_empty(struct uart_port *uport) 233 { 234 struct sbd_port *sport = to_sport(uport); 235 236 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0; 237 } 238 239 static unsigned int sbd_get_mctrl(struct uart_port *uport) 240 { 241 struct sbd_port *sport = to_sport(uport); 242 unsigned int mctrl, status; 243 244 status = read_sbdshr(sport, R_DUART_IN_PORT); 245 status >>= (uport->line) % 2; 246 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) | 247 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) | 248 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) | 249 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0); 250 return mctrl; 251 } 252 253 static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl) 254 { 255 struct sbd_port *sport = to_sport(uport); 256 unsigned int clr = 0, set = 0, mode2; 257 258 if (mctrl & TIOCM_DTR) 259 set |= M_DUART_SET_OPR2; 260 else 261 clr |= M_DUART_CLR_OPR2; 262 if (mctrl & TIOCM_RTS) 263 set |= M_DUART_SET_OPR0; 264 else 265 clr |= M_DUART_CLR_OPR0; 266 clr <<= (uport->line) % 2; 267 set <<= (uport->line) % 2; 268 269 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2); 270 mode2 &= ~M_DUART_CHAN_MODE; 271 if (mctrl & TIOCM_LOOP) 272 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP; 273 else 274 mode2 |= V_DUART_CHAN_MODE_NORMAL; 275 276 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); 277 write_sbdshr(sport, R_DUART_SET_OPR, set); 278 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2); 279 } 280 281 static void sbd_stop_tx(struct uart_port *uport) 282 { 283 struct sbd_port *sport = to_sport(uport); 284 285 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 286 sport->tx_stopped = 1; 287 }; 288 289 static void sbd_start_tx(struct uart_port *uport) 290 { 291 struct sbd_port *sport = to_sport(uport); 292 unsigned int mask; 293 294 /* Enable tx interrupts. */ 295 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 296 mask |= M_DUART_IMR_TX; 297 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 298 299 /* Go!, go!, go!... */ 300 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 301 sport->tx_stopped = 0; 302 }; 303 304 static void sbd_stop_rx(struct uart_port *uport) 305 { 306 struct sbd_port *sport = to_sport(uport); 307 308 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); 309 }; 310 311 static void sbd_enable_ms(struct uart_port *uport) 312 { 313 struct sbd_port *sport = to_sport(uport); 314 315 write_sbdchn(sport, R_DUART_AUXCTL_X, 316 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA); 317 } 318 319 static void sbd_break_ctl(struct uart_port *uport, int break_state) 320 { 321 struct sbd_port *sport = to_sport(uport); 322 323 if (break_state == -1) 324 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK); 325 else 326 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK); 327 } 328 329 330 static void sbd_receive_chars(struct sbd_port *sport) 331 { 332 struct uart_port *uport = &sport->port; 333 struct uart_icount *icount; 334 unsigned int status, ch, flag; 335 int count; 336 337 for (count = 16; count; count--) { 338 status = read_sbdchn(sport, R_DUART_STATUS); 339 if (!(status & M_DUART_RX_RDY)) 340 break; 341 342 ch = read_sbdchn(sport, R_DUART_RX_HOLD); 343 344 flag = TTY_NORMAL; 345 346 icount = &uport->icount; 347 icount->rx++; 348 349 if (unlikely(status & 350 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR | 351 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) { 352 if (status & M_DUART_RCVD_BRK) { 353 icount->brk++; 354 if (uart_handle_break(uport)) 355 continue; 356 } else if (status & M_DUART_FRM_ERR) 357 icount->frame++; 358 else if (status & M_DUART_PARITY_ERR) 359 icount->parity++; 360 if (status & M_DUART_OVRUN_ERR) 361 icount->overrun++; 362 363 status &= uport->read_status_mask; 364 if (status & M_DUART_RCVD_BRK) 365 flag = TTY_BREAK; 366 else if (status & M_DUART_FRM_ERR) 367 flag = TTY_FRAME; 368 else if (status & M_DUART_PARITY_ERR) 369 flag = TTY_PARITY; 370 } 371 372 if (uart_handle_sysrq_char(uport, ch)) 373 continue; 374 375 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag); 376 } 377 378 tty_flip_buffer_push(&uport->state->port); 379 } 380 381 static void sbd_transmit_chars(struct sbd_port *sport) 382 { 383 struct uart_port *uport = &sport->port; 384 struct circ_buf *xmit = &sport->port.state->xmit; 385 unsigned int mask; 386 int stop_tx; 387 388 /* XON/XOFF chars. */ 389 if (sport->port.x_char) { 390 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char); 391 sport->port.icount.tx++; 392 sport->port.x_char = 0; 393 return; 394 } 395 396 /* If nothing to do or stopped or hardware stopped. */ 397 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)); 398 399 /* Send char. */ 400 if (!stop_tx) { 401 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]); 402 uart_xmit_advance(&sport->port, 1); 403 404 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 405 uart_write_wakeup(&sport->port); 406 } 407 408 /* Are we are done? */ 409 if (stop_tx || uart_circ_empty(xmit)) { 410 /* Disable tx interrupts. */ 411 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 412 mask &= ~M_DUART_IMR_TX; 413 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 414 } 415 } 416 417 static void sbd_status_handle(struct sbd_port *sport) 418 { 419 struct uart_port *uport = &sport->port; 420 unsigned int delta; 421 422 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); 423 delta >>= (uport->line) % 2; 424 425 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG)) 426 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL)); 427 428 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG)) 429 uport->icount.dsr++; 430 431 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) << 432 S_DUART_IN_PIN_CHNG)) 433 wake_up_interruptible(&uport->state->port.delta_msr_wait); 434 } 435 436 static irqreturn_t sbd_interrupt(int irq, void *dev_id) 437 { 438 struct sbd_port *sport = dev_id; 439 struct uart_port *uport = &sport->port; 440 irqreturn_t status = IRQ_NONE; 441 unsigned int intstat; 442 int count; 443 444 for (count = 16; count; count--) { 445 intstat = read_sbdshr(sport, 446 R_DUART_ISRREG((uport->line) % 2)); 447 intstat &= read_sbdshr(sport, 448 R_DUART_IMRREG((uport->line) % 2)); 449 intstat &= M_DUART_ISR_ALL; 450 if (!intstat) 451 break; 452 453 if (intstat & M_DUART_ISR_RX) 454 sbd_receive_chars(sport); 455 if (intstat & M_DUART_ISR_IN) 456 sbd_status_handle(sport); 457 if (intstat & M_DUART_ISR_TX) 458 sbd_transmit_chars(sport); 459 460 status = IRQ_HANDLED; 461 } 462 463 return status; 464 } 465 466 467 static int sbd_startup(struct uart_port *uport) 468 { 469 struct sbd_port *sport = to_sport(uport); 470 unsigned int mode1; 471 int ret; 472 473 ret = request_irq(sport->port.irq, sbd_interrupt, 474 IRQF_SHARED, "sb1250-duart", sport); 475 if (ret) 476 return ret; 477 478 /* Clear the receive FIFO. */ 479 sbd_receive_drain(sport); 480 481 /* Clear the interrupt registers. */ 482 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT); 483 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2)); 484 485 /* Set rx/tx interrupt to FIFO available. */ 486 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1); 487 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT); 488 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1); 489 490 /* Disable tx, enable rx. */ 491 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN); 492 sport->tx_stopped = 1; 493 494 /* Enable interrupts. */ 495 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 496 M_DUART_IMR_IN | M_DUART_IMR_RX); 497 498 return 0; 499 } 500 501 static void sbd_shutdown(struct uart_port *uport) 502 { 503 struct sbd_port *sport = to_sport(uport); 504 505 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); 506 sport->tx_stopped = 1; 507 free_irq(sport->port.irq, sport); 508 } 509 510 511 static void sbd_init_port(struct sbd_port *sport) 512 { 513 struct uart_port *uport = &sport->port; 514 515 if (sport->initialised) 516 return; 517 518 /* There is no DUART reset feature, so just set some sane defaults. */ 519 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX); 520 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX); 521 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8); 522 write_sbdchn(sport, R_DUART_MODE_REG_2, 0); 523 write_sbdchn(sport, R_DUART_FULL_CTL, 524 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15)); 525 write_sbdchn(sport, R_DUART_OPCR_X, 0); 526 write_sbdchn(sport, R_DUART_AUXCTL_X, 0); 527 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0); 528 529 sport->initialised = 1; 530 } 531 532 static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios, 533 const struct ktermios *old_termios) 534 { 535 struct sbd_port *sport = to_sport(uport); 536 unsigned int mode1 = 0, mode2 = 0, aux = 0; 537 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0; 538 unsigned int oldmode1, oldmode2, oldaux; 539 unsigned int baud, brg; 540 unsigned int command; 541 542 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD | 543 M_DUART_BITS_PER_CHAR); 544 mode2mask |= ~M_DUART_STOP_BIT_LEN_2; 545 auxmask |= ~M_DUART_CTS_CHNG_ENA; 546 547 /* Byte size. */ 548 switch (termios->c_cflag & CSIZE) { 549 case CS5: 550 case CS6: 551 /* Unsupported, leave unchanged. */ 552 mode1mask |= M_DUART_PARITY_MODE; 553 break; 554 case CS7: 555 mode1 |= V_DUART_BITS_PER_CHAR_7; 556 break; 557 case CS8: 558 default: 559 mode1 |= V_DUART_BITS_PER_CHAR_8; 560 break; 561 } 562 563 /* Parity and stop bits. */ 564 if (termios->c_cflag & CSTOPB) 565 mode2 |= M_DUART_STOP_BIT_LEN_2; 566 else 567 mode2 |= M_DUART_STOP_BIT_LEN_1; 568 if (termios->c_cflag & PARENB) 569 mode1 |= V_DUART_PARITY_MODE_ADD; 570 else 571 mode1 |= V_DUART_PARITY_MODE_NONE; 572 if (termios->c_cflag & PARODD) 573 mode1 |= M_DUART_PARITY_TYPE_ODD; 574 else 575 mode1 |= M_DUART_PARITY_TYPE_EVEN; 576 577 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000); 578 brg = V_DUART_BAUD_RATE(baud); 579 /* The actual lower bound is 1221bps, so compensate. */ 580 if (brg > M_DUART_CLK_COUNTER) 581 brg = M_DUART_CLK_COUNTER; 582 583 uart_update_timeout(uport, termios->c_cflag, baud); 584 585 uport->read_status_mask = M_DUART_OVRUN_ERR; 586 if (termios->c_iflag & INPCK) 587 uport->read_status_mask |= M_DUART_FRM_ERR | 588 M_DUART_PARITY_ERR; 589 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 590 uport->read_status_mask |= M_DUART_RCVD_BRK; 591 592 uport->ignore_status_mask = 0; 593 if (termios->c_iflag & IGNPAR) 594 uport->ignore_status_mask |= M_DUART_FRM_ERR | 595 M_DUART_PARITY_ERR; 596 if (termios->c_iflag & IGNBRK) { 597 uport->ignore_status_mask |= M_DUART_RCVD_BRK; 598 if (termios->c_iflag & IGNPAR) 599 uport->ignore_status_mask |= M_DUART_OVRUN_ERR; 600 } 601 602 if (termios->c_cflag & CREAD) 603 command = M_DUART_RX_EN; 604 else 605 command = M_DUART_RX_DIS; 606 607 if (termios->c_cflag & CRTSCTS) 608 aux |= M_DUART_CTS_CHNG_ENA; 609 else 610 aux &= ~M_DUART_CTS_CHNG_ENA; 611 612 spin_lock(&uport->lock); 613 614 if (sport->tx_stopped) 615 command |= M_DUART_TX_DIS; 616 else 617 command |= M_DUART_TX_EN; 618 619 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask; 620 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask; 621 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask; 622 623 if (!sport->tx_stopped) 624 sbd_line_drain(sport); 625 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS); 626 627 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1); 628 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2); 629 write_sbdchn(sport, R_DUART_CLK_SEL, brg); 630 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux); 631 632 write_sbdchn(sport, R_DUART_CMD, command); 633 634 spin_unlock(&uport->lock); 635 } 636 637 638 static const char *sbd_type(struct uart_port *uport) 639 { 640 return "SB1250 DUART"; 641 } 642 643 static void sbd_release_port(struct uart_port *uport) 644 { 645 struct sbd_port *sport = to_sport(uport); 646 struct sbd_duart *duart = sport->duart; 647 648 iounmap(sport->memctrl); 649 sport->memctrl = NULL; 650 iounmap(uport->membase); 651 uport->membase = NULL; 652 653 if(refcount_dec_and_test(&duart->map_guard)) 654 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING); 655 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); 656 } 657 658 static int sbd_map_port(struct uart_port *uport) 659 { 660 const char *err = KERN_ERR "sbd: Cannot map MMIO\n"; 661 struct sbd_port *sport = to_sport(uport); 662 struct sbd_duart *duart = sport->duart; 663 664 if (!uport->membase) 665 uport->membase = ioremap(uport->mapbase, 666 DUART_CHANREG_SPACING); 667 if (!uport->membase) { 668 printk(err); 669 return -ENOMEM; 670 } 671 672 if (!sport->memctrl) 673 sport->memctrl = ioremap(duart->mapctrl, 674 DUART_CHANREG_SPACING); 675 if (!sport->memctrl) { 676 printk(err); 677 iounmap(uport->membase); 678 uport->membase = NULL; 679 return -ENOMEM; 680 } 681 682 return 0; 683 } 684 685 static int sbd_request_port(struct uart_port *uport) 686 { 687 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n"; 688 struct sbd_duart *duart = to_sport(uport)->duart; 689 int ret = 0; 690 691 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING, 692 "sb1250-duart")) { 693 printk(err); 694 return -EBUSY; 695 } 696 refcount_inc(&duart->map_guard); 697 if (refcount_read(&duart->map_guard) == 1) { 698 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING, 699 "sb1250-duart")) { 700 refcount_dec(&duart->map_guard); 701 printk(err); 702 ret = -EBUSY; 703 } 704 } 705 if (!ret) { 706 ret = sbd_map_port(uport); 707 if (ret) { 708 if (refcount_dec_and_test(&duart->map_guard)) 709 release_mem_region(duart->mapctrl, 710 DUART_CHANREG_SPACING); 711 } 712 } 713 if (ret) { 714 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING); 715 return ret; 716 } 717 return 0; 718 } 719 720 static void sbd_config_port(struct uart_port *uport, int flags) 721 { 722 struct sbd_port *sport = to_sport(uport); 723 724 if (flags & UART_CONFIG_TYPE) { 725 if (sbd_request_port(uport)) 726 return; 727 728 uport->type = PORT_SB1250_DUART; 729 730 sbd_init_port(sport); 731 } 732 } 733 734 static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser) 735 { 736 int ret = 0; 737 738 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART) 739 ret = -EINVAL; 740 if (ser->irq != uport->irq) 741 ret = -EINVAL; 742 if (ser->baud_base != uport->uartclk / 16) 743 ret = -EINVAL; 744 return ret; 745 } 746 747 748 static const struct uart_ops sbd_ops = { 749 .tx_empty = sbd_tx_empty, 750 .set_mctrl = sbd_set_mctrl, 751 .get_mctrl = sbd_get_mctrl, 752 .stop_tx = sbd_stop_tx, 753 .start_tx = sbd_start_tx, 754 .stop_rx = sbd_stop_rx, 755 .enable_ms = sbd_enable_ms, 756 .break_ctl = sbd_break_ctl, 757 .startup = sbd_startup, 758 .shutdown = sbd_shutdown, 759 .set_termios = sbd_set_termios, 760 .type = sbd_type, 761 .release_port = sbd_release_port, 762 .request_port = sbd_request_port, 763 .config_port = sbd_config_port, 764 .verify_port = sbd_verify_port, 765 }; 766 767 /* Initialize SB1250 DUART port structures. */ 768 static void __init sbd_probe_duarts(void) 769 { 770 static int probed; 771 int chip, side; 772 int max_lines, line; 773 774 if (probed) 775 return; 776 777 /* Set the number of available units based on the SOC type. */ 778 switch (soc_type) { 779 case K_SYS_SOC_TYPE_BCM1x55: 780 case K_SYS_SOC_TYPE_BCM1x80: 781 max_lines = 4; 782 break; 783 default: 784 /* Assume at least two serial ports at the normal address. */ 785 max_lines = 2; 786 break; 787 } 788 789 probed = 1; 790 791 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines; 792 chip++) { 793 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line); 794 795 for (side = 0; side < DUART_MAX_SIDE && line < max_lines; 796 side++, line++) { 797 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 798 struct uart_port *uport = &sport->port; 799 800 sport->duart = &sbd_duarts[chip]; 801 802 uport->irq = SBD_INT(line); 803 uport->uartclk = 100000000 / 20 * 16; 804 uport->fifosize = 16; 805 uport->iotype = UPIO_MEM; 806 uport->flags = UPF_BOOT_AUTOCONF; 807 uport->ops = &sbd_ops; 808 uport->line = line; 809 uport->mapbase = SBD_CHANREGS(line); 810 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SB1250_DUART_CONSOLE); 811 } 812 } 813 } 814 815 816 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE 817 /* 818 * Serial console stuff. Very basic, polling driver for doing serial 819 * console output. The console_lock is held by the caller, so we 820 * shouldn't be interrupted for more console activity. 821 */ 822 static void sbd_console_putchar(struct uart_port *uport, unsigned char ch) 823 { 824 struct sbd_port *sport = to_sport(uport); 825 826 sbd_transmit_drain(sport); 827 write_sbdchn(sport, R_DUART_TX_HOLD, ch); 828 } 829 830 static void sbd_console_write(struct console *co, const char *s, 831 unsigned int count) 832 { 833 int chip = co->index / DUART_MAX_SIDE; 834 int side = co->index % DUART_MAX_SIDE; 835 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 836 struct uart_port *uport = &sport->port; 837 unsigned long flags; 838 unsigned int mask; 839 840 /* Disable transmit interrupts and enable the transmitter. */ 841 spin_lock_irqsave(&uport->lock, flags); 842 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 843 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 844 mask & ~M_DUART_IMR_TX); 845 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 846 spin_unlock_irqrestore(&uport->lock, flags); 847 848 uart_console_write(&sport->port, s, count, sbd_console_putchar); 849 850 /* Restore transmit interrupts and the transmitter enable. */ 851 spin_lock_irqsave(&uport->lock, flags); 852 sbd_line_drain(sport); 853 if (sport->tx_stopped) 854 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 855 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 856 spin_unlock_irqrestore(&uport->lock, flags); 857 } 858 859 static int __init sbd_console_setup(struct console *co, char *options) 860 { 861 int chip = co->index / DUART_MAX_SIDE; 862 int side = co->index % DUART_MAX_SIDE; 863 struct sbd_port *sport = &sbd_duarts[chip].sport[side]; 864 struct uart_port *uport = &sport->port; 865 int baud = 115200; 866 int bits = 8; 867 int parity = 'n'; 868 int flow = 'n'; 869 int ret; 870 871 if (!sport->duart) 872 return -ENXIO; 873 874 ret = sbd_map_port(uport); 875 if (ret) 876 return ret; 877 878 sbd_init_port(sport); 879 880 if (options) 881 uart_parse_options(options, &baud, &parity, &bits, &flow); 882 return uart_set_options(uport, co, baud, parity, bits, flow); 883 } 884 885 static struct uart_driver sbd_reg; 886 static struct console sbd_console = { 887 .name = "duart", 888 .write = sbd_console_write, 889 .device = uart_console_device, 890 .setup = sbd_console_setup, 891 .flags = CON_PRINTBUFFER, 892 .index = -1, 893 .data = &sbd_reg 894 }; 895 896 static int __init sbd_serial_console_init(void) 897 { 898 sbd_probe_duarts(); 899 register_console(&sbd_console); 900 901 return 0; 902 } 903 904 console_initcall(sbd_serial_console_init); 905 906 #define SERIAL_SB1250_DUART_CONSOLE &sbd_console 907 #else 908 #define SERIAL_SB1250_DUART_CONSOLE NULL 909 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */ 910 911 912 static struct uart_driver sbd_reg = { 913 .owner = THIS_MODULE, 914 .driver_name = "sb1250_duart", 915 .dev_name = "duart", 916 .major = TTY_MAJOR, 917 .minor = SB1250_DUART_MINOR_BASE, 918 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE, 919 .cons = SERIAL_SB1250_DUART_CONSOLE, 920 }; 921 922 /* Set up the driver and register it. */ 923 static int __init sbd_init(void) 924 { 925 int i, ret; 926 927 sbd_probe_duarts(); 928 929 ret = uart_register_driver(&sbd_reg); 930 if (ret) 931 return ret; 932 933 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) { 934 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; 935 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; 936 struct uart_port *uport = &sport->port; 937 938 if (sport->duart) 939 uart_add_one_port(&sbd_reg, uport); 940 } 941 942 return 0; 943 } 944 945 /* Unload the driver. Unregister stuff, get ready to go away. */ 946 static void __exit sbd_exit(void) 947 { 948 int i; 949 950 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) { 951 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE]; 952 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE]; 953 struct uart_port *uport = &sport->port; 954 955 if (sport->duart) 956 uart_remove_one_port(&sbd_reg, uport); 957 } 958 959 uart_unregister_driver(&sbd_reg); 960 } 961 962 module_init(sbd_init); 963 module_exit(sbd_exit); 964