1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Hote on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/ioport.h> 29 #include <linux/io.h> 30 #include <linux/platform_device.h> 31 #include <linux/init.h> 32 #include <linux/sysrq.h> 33 #include <linux/console.h> 34 #include <linux/tty.h> 35 #include <linux/tty_flip.h> 36 #include <linux/serial_core.h> 37 #include <linux/serial.h> 38 #include <linux/serial_s3c.h> 39 #include <linux/delay.h> 40 #include <linux/clk.h> 41 #include <linux/cpufreq.h> 42 #include <linux/of.h> 43 #include <asm/irq.h> 44 45 /* UART name and device definitions */ 46 47 #define S3C24XX_SERIAL_NAME "ttySAC" 48 #define S3C24XX_SERIAL_MAJOR 204 49 #define S3C24XX_SERIAL_MINOR 64 50 51 #define S3C24XX_TX_PIO 1 52 #define S3C24XX_TX_DMA 2 53 #define S3C24XX_RX_PIO 1 54 #define S3C24XX_RX_DMA 2 55 56 /* flag to ignore all characters coming in */ 57 #define RXSTAT_DUMMY_READ (0x10000000) 58 59 struct s3c24xx_uart_info { 60 char *name; 61 unsigned int type; 62 unsigned int fifosize; 63 unsigned long rx_fifomask; 64 unsigned long rx_fifoshift; 65 unsigned long rx_fifofull; 66 unsigned long tx_fifomask; 67 unsigned long tx_fifoshift; 68 unsigned long tx_fifofull; 69 unsigned int def_clk_sel; 70 unsigned long num_clks; 71 unsigned long clksel_mask; 72 unsigned long clksel_shift; 73 74 /* uart port features */ 75 76 unsigned int has_divslot:1; 77 }; 78 79 struct s3c24xx_serial_drv_data { 80 struct s3c24xx_uart_info *info; 81 struct s3c2410_uartcfg *def_cfg; 82 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; 83 }; 84 85 struct s3c24xx_uart_dma { 86 unsigned int rx_chan_id; 87 unsigned int tx_chan_id; 88 89 struct dma_slave_config rx_conf; 90 struct dma_slave_config tx_conf; 91 92 struct dma_chan *rx_chan; 93 struct dma_chan *tx_chan; 94 95 dma_addr_t rx_addr; 96 dma_addr_t tx_addr; 97 98 dma_cookie_t rx_cookie; 99 dma_cookie_t tx_cookie; 100 101 char *rx_buf; 102 103 dma_addr_t tx_transfer_addr; 104 105 size_t rx_size; 106 size_t tx_size; 107 108 struct dma_async_tx_descriptor *tx_desc; 109 struct dma_async_tx_descriptor *rx_desc; 110 111 int tx_bytes_requested; 112 int rx_bytes_requested; 113 }; 114 115 struct s3c24xx_uart_port { 116 unsigned char rx_claimed; 117 unsigned char tx_claimed; 118 unsigned char rx_enabled; 119 unsigned char tx_enabled; 120 unsigned int pm_level; 121 unsigned long baudclk_rate; 122 unsigned int min_dma_size; 123 124 unsigned int rx_irq; 125 unsigned int tx_irq; 126 127 unsigned int tx_in_progress; 128 unsigned int tx_mode; 129 unsigned int rx_mode; 130 131 struct s3c24xx_uart_info *info; 132 struct clk *clk; 133 struct clk *baudclk; 134 struct uart_port port; 135 struct s3c24xx_serial_drv_data *drv_data; 136 137 /* reference to platform data */ 138 struct s3c2410_uartcfg *cfg; 139 140 struct s3c24xx_uart_dma *dma; 141 142 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 143 struct notifier_block freq_transition; 144 #endif 145 }; 146 147 /* conversion functions */ 148 149 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 150 151 /* register access controls */ 152 153 #define portaddr(port, reg) ((port)->membase + (reg)) 154 #define portaddrl(port, reg) \ 155 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 156 157 static u32 rd_reg(struct uart_port *port, u32 reg) 158 { 159 switch (port->iotype) { 160 case UPIO_MEM: 161 return readb_relaxed(portaddr(port, reg)); 162 case UPIO_MEM32: 163 return readl_relaxed(portaddr(port, reg)); 164 default: 165 return 0; 166 } 167 return 0; 168 } 169 170 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 171 172 static void wr_reg(struct uart_port *port, u32 reg, u32 val) 173 { 174 switch (port->iotype) { 175 case UPIO_MEM: 176 writeb_relaxed(val, portaddr(port, reg)); 177 break; 178 case UPIO_MEM32: 179 writel_relaxed(val, portaddr(port, reg)); 180 break; 181 } 182 } 183 184 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 185 186 /* Byte-order aware bit setting/clearing functions. */ 187 188 static inline void s3c24xx_set_bit(struct uart_port *port, int idx, 189 unsigned int reg) 190 { 191 unsigned long flags; 192 u32 val; 193 194 local_irq_save(flags); 195 val = rd_regl(port, reg); 196 val |= (1 << idx); 197 wr_regl(port, reg, val); 198 local_irq_restore(flags); 199 } 200 201 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx, 202 unsigned int reg) 203 { 204 unsigned long flags; 205 u32 val; 206 207 local_irq_save(flags); 208 val = rd_regl(port, reg); 209 val &= ~(1 << idx); 210 wr_regl(port, reg, val); 211 local_irq_restore(flags); 212 } 213 214 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 215 { 216 return container_of(port, struct s3c24xx_uart_port, port); 217 } 218 219 /* translate a port to the device name */ 220 221 static inline const char *s3c24xx_serial_portname(struct uart_port *port) 222 { 223 return to_platform_device(port->dev)->name; 224 } 225 226 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) 227 { 228 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 229 } 230 231 /* 232 * s3c64xx and later SoC's include the interrupt mask and status registers in 233 * the controller itself, unlike the s3c24xx SoC's which have these registers 234 * in the interrupt controller. Check if the port type is s3c64xx or higher. 235 */ 236 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port) 237 { 238 return to_ourport(port)->info->type == PORT_S3C6400; 239 } 240 241 static void s3c24xx_serial_rx_enable(struct uart_port *port) 242 { 243 struct s3c24xx_uart_port *ourport = to_ourport(port); 244 unsigned long flags; 245 unsigned int ucon, ufcon; 246 int count = 10000; 247 248 spin_lock_irqsave(&port->lock, flags); 249 250 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 251 udelay(100); 252 253 ufcon = rd_regl(port, S3C2410_UFCON); 254 ufcon |= S3C2410_UFCON_RESETRX; 255 wr_regl(port, S3C2410_UFCON, ufcon); 256 257 ucon = rd_regl(port, S3C2410_UCON); 258 ucon |= S3C2410_UCON_RXIRQMODE; 259 wr_regl(port, S3C2410_UCON, ucon); 260 261 ourport->rx_enabled = 1; 262 spin_unlock_irqrestore(&port->lock, flags); 263 } 264 265 static void s3c24xx_serial_rx_disable(struct uart_port *port) 266 { 267 struct s3c24xx_uart_port *ourport = to_ourport(port); 268 unsigned long flags; 269 unsigned int ucon; 270 271 spin_lock_irqsave(&port->lock, flags); 272 273 ucon = rd_regl(port, S3C2410_UCON); 274 ucon &= ~S3C2410_UCON_RXIRQMODE; 275 wr_regl(port, S3C2410_UCON, ucon); 276 277 ourport->rx_enabled = 0; 278 spin_unlock_irqrestore(&port->lock, flags); 279 } 280 281 static void s3c24xx_serial_stop_tx(struct uart_port *port) 282 { 283 struct s3c24xx_uart_port *ourport = to_ourport(port); 284 struct s3c24xx_uart_dma *dma = ourport->dma; 285 struct circ_buf *xmit = &port->state->xmit; 286 struct dma_tx_state state; 287 int count; 288 289 if (!ourport->tx_enabled) 290 return; 291 292 if (s3c24xx_serial_has_interrupt_mask(port)) 293 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 294 else 295 disable_irq_nosync(ourport->tx_irq); 296 297 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 298 dmaengine_pause(dma->tx_chan); 299 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 300 dmaengine_terminate_all(dma->tx_chan); 301 dma_sync_single_for_cpu(ourport->port.dev, 302 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE); 303 async_tx_ack(dma->tx_desc); 304 count = dma->tx_bytes_requested - state.residue; 305 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 306 port->icount.tx += count; 307 } 308 309 ourport->tx_enabled = 0; 310 ourport->tx_in_progress = 0; 311 312 if (port->flags & UPF_CONS_FLOW) 313 s3c24xx_serial_rx_enable(port); 314 315 ourport->tx_mode = 0; 316 } 317 318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 319 320 static void s3c24xx_serial_tx_dma_complete(void *args) 321 { 322 struct s3c24xx_uart_port *ourport = args; 323 struct uart_port *port = &ourport->port; 324 struct circ_buf *xmit = &port->state->xmit; 325 struct s3c24xx_uart_dma *dma = ourport->dma; 326 struct dma_tx_state state; 327 unsigned long flags; 328 int count; 329 330 331 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 332 count = dma->tx_bytes_requested - state.residue; 333 async_tx_ack(dma->tx_desc); 334 335 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr, 336 dma->tx_size, DMA_TO_DEVICE); 337 338 spin_lock_irqsave(&port->lock, flags); 339 340 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 341 port->icount.tx += count; 342 ourport->tx_in_progress = 0; 343 344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 345 uart_write_wakeup(port); 346 347 s3c24xx_serial_start_next_tx(ourport); 348 spin_unlock_irqrestore(&port->lock, flags); 349 } 350 351 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 352 { 353 struct uart_port *port = &ourport->port; 354 u32 ucon; 355 356 /* Mask Tx interrupt */ 357 if (s3c24xx_serial_has_interrupt_mask(port)) 358 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 359 else 360 disable_irq_nosync(ourport->tx_irq); 361 362 /* Enable tx dma mode */ 363 ucon = rd_regl(port, S3C2410_UCON); 364 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 365 ucon |= (dma_get_cache_alignment() >= 16) ? 366 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1; 367 ucon |= S3C64XX_UCON_TXMODE_DMA; 368 wr_regl(port, S3C2410_UCON, ucon); 369 370 ourport->tx_mode = S3C24XX_TX_DMA; 371 } 372 373 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 374 { 375 struct uart_port *port = &ourport->port; 376 u32 ucon, ufcon; 377 378 /* Set ufcon txtrig */ 379 ourport->tx_in_progress = S3C24XX_TX_PIO; 380 ufcon = rd_regl(port, S3C2410_UFCON); 381 wr_regl(port, S3C2410_UFCON, ufcon); 382 383 /* Enable tx pio mode */ 384 ucon = rd_regl(port, S3C2410_UCON); 385 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 386 ucon |= S3C64XX_UCON_TXMODE_CPU; 387 wr_regl(port, S3C2410_UCON, ucon); 388 389 /* Unmask Tx interrupt */ 390 if (s3c24xx_serial_has_interrupt_mask(port)) 391 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 392 S3C64XX_UINTM); 393 else 394 enable_irq(ourport->tx_irq); 395 396 ourport->tx_mode = S3C24XX_TX_PIO; 397 } 398 399 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 400 { 401 if (ourport->tx_mode != S3C24XX_TX_PIO) 402 enable_tx_pio(ourport); 403 } 404 405 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 406 unsigned int count) 407 { 408 struct uart_port *port = &ourport->port; 409 struct circ_buf *xmit = &port->state->xmit; 410 struct s3c24xx_uart_dma *dma = ourport->dma; 411 412 413 if (ourport->tx_mode != S3C24XX_TX_DMA) 414 enable_tx_dma(ourport); 415 416 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 417 dma->tx_transfer_addr = dma->tx_addr + xmit->tail; 418 419 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr, 420 dma->tx_size, DMA_TO_DEVICE); 421 422 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 423 dma->tx_transfer_addr, dma->tx_size, 424 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 425 if (!dma->tx_desc) { 426 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 427 return -EIO; 428 } 429 430 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 431 dma->tx_desc->callback_param = ourport; 432 dma->tx_bytes_requested = dma->tx_size; 433 434 ourport->tx_in_progress = S3C24XX_TX_DMA; 435 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 436 dma_async_issue_pending(dma->tx_chan); 437 return 0; 438 } 439 440 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 441 { 442 struct uart_port *port = &ourport->port; 443 struct circ_buf *xmit = &port->state->xmit; 444 unsigned long count; 445 446 /* Get data size up to the end of buffer */ 447 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 448 449 if (!count) { 450 s3c24xx_serial_stop_tx(port); 451 return; 452 } 453 454 if (!ourport->dma || !ourport->dma->tx_chan || 455 count < ourport->min_dma_size || 456 xmit->tail & (dma_get_cache_alignment() - 1)) 457 s3c24xx_serial_start_tx_pio(ourport); 458 else 459 s3c24xx_serial_start_tx_dma(ourport, count); 460 } 461 462 static void s3c24xx_serial_start_tx(struct uart_port *port) 463 { 464 struct s3c24xx_uart_port *ourport = to_ourport(port); 465 struct circ_buf *xmit = &port->state->xmit; 466 467 if (!ourport->tx_enabled) { 468 if (port->flags & UPF_CONS_FLOW) 469 s3c24xx_serial_rx_disable(port); 470 471 ourport->tx_enabled = 1; 472 if (!ourport->dma || !ourport->dma->tx_chan) 473 s3c24xx_serial_start_tx_pio(ourport); 474 } 475 476 if (ourport->dma && ourport->dma->tx_chan) { 477 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) 478 s3c24xx_serial_start_next_tx(ourport); 479 } 480 } 481 482 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 483 struct tty_port *tty, int count) 484 { 485 struct s3c24xx_uart_dma *dma = ourport->dma; 486 int copied; 487 488 if (!count) 489 return; 490 491 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr, 492 dma->rx_size, DMA_FROM_DEVICE); 493 494 ourport->port.icount.rx += count; 495 if (!tty) { 496 dev_err(ourport->port.dev, "No tty port\n"); 497 return; 498 } 499 copied = tty_insert_flip_string(tty, 500 ((unsigned char *)(ourport->dma->rx_buf)), count); 501 if (copied != count) { 502 WARN_ON(1); 503 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 504 } 505 } 506 507 static void s3c24xx_serial_stop_rx(struct uart_port *port) 508 { 509 struct s3c24xx_uart_port *ourport = to_ourport(port); 510 struct s3c24xx_uart_dma *dma = ourport->dma; 511 struct tty_port *t = &port->state->port; 512 struct dma_tx_state state; 513 enum dma_status dma_status; 514 unsigned int received; 515 516 if (ourport->rx_enabled) { 517 dev_dbg(port->dev, "stopping rx\n"); 518 if (s3c24xx_serial_has_interrupt_mask(port)) 519 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 520 S3C64XX_UINTM); 521 else 522 disable_irq_nosync(ourport->rx_irq); 523 ourport->rx_enabled = 0; 524 } 525 if (dma && dma->rx_chan) { 526 dmaengine_pause(dma->tx_chan); 527 dma_status = dmaengine_tx_status(dma->rx_chan, 528 dma->rx_cookie, &state); 529 if (dma_status == DMA_IN_PROGRESS || 530 dma_status == DMA_PAUSED) { 531 received = dma->rx_bytes_requested - state.residue; 532 dmaengine_terminate_all(dma->rx_chan); 533 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 534 } 535 } 536 } 537 538 static inline struct s3c24xx_uart_info 539 *s3c24xx_port_to_info(struct uart_port *port) 540 { 541 return to_ourport(port)->info; 542 } 543 544 static inline struct s3c2410_uartcfg 545 *s3c24xx_port_to_cfg(struct uart_port *port) 546 { 547 struct s3c24xx_uart_port *ourport; 548 549 if (port->dev == NULL) 550 return NULL; 551 552 ourport = container_of(port, struct s3c24xx_uart_port, port); 553 return ourport->cfg; 554 } 555 556 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, 557 unsigned long ufstat) 558 { 559 struct s3c24xx_uart_info *info = ourport->info; 560 561 if (ufstat & info->rx_fifofull) 562 return ourport->port.fifosize; 563 564 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 565 } 566 567 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 568 static void s3c24xx_serial_rx_dma_complete(void *args) 569 { 570 struct s3c24xx_uart_port *ourport = args; 571 struct uart_port *port = &ourport->port; 572 573 struct s3c24xx_uart_dma *dma = ourport->dma; 574 struct tty_port *t = &port->state->port; 575 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 576 577 struct dma_tx_state state; 578 unsigned long flags; 579 int received; 580 581 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 582 received = dma->rx_bytes_requested - state.residue; 583 async_tx_ack(dma->rx_desc); 584 585 spin_lock_irqsave(&port->lock, flags); 586 587 if (received) 588 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 589 590 if (tty) { 591 tty_flip_buffer_push(t); 592 tty_kref_put(tty); 593 } 594 595 s3c64xx_start_rx_dma(ourport); 596 597 spin_unlock_irqrestore(&port->lock, flags); 598 } 599 600 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 601 { 602 struct s3c24xx_uart_dma *dma = ourport->dma; 603 604 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr, 605 dma->rx_size, DMA_FROM_DEVICE); 606 607 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 608 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 609 DMA_PREP_INTERRUPT); 610 if (!dma->rx_desc) { 611 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 612 return; 613 } 614 615 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 616 dma->rx_desc->callback_param = ourport; 617 dma->rx_bytes_requested = dma->rx_size; 618 619 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 620 dma_async_issue_pending(dma->rx_chan); 621 } 622 623 /* ? - where has parity gone?? */ 624 #define S3C2410_UERSTAT_PARITY (0x1000) 625 626 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 627 { 628 struct uart_port *port = &ourport->port; 629 unsigned int ucon; 630 631 /* set Rx mode to DMA mode */ 632 ucon = rd_regl(port, S3C2410_UCON); 633 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 634 S3C64XX_UCON_TIMEOUT_MASK | 635 S3C64XX_UCON_EMPTYINT_EN | 636 S3C64XX_UCON_DMASUS_EN | 637 S3C64XX_UCON_TIMEOUT_EN | 638 S3C64XX_UCON_RXMODE_MASK); 639 ucon |= S3C64XX_UCON_RXBURST_16 | 640 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 641 S3C64XX_UCON_EMPTYINT_EN | 642 S3C64XX_UCON_TIMEOUT_EN | 643 S3C64XX_UCON_RXMODE_DMA; 644 wr_regl(port, S3C2410_UCON, ucon); 645 646 ourport->rx_mode = S3C24XX_RX_DMA; 647 } 648 649 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 650 { 651 struct uart_port *port = &ourport->port; 652 unsigned int ucon; 653 654 /* set Rx mode to DMA mode */ 655 ucon = rd_regl(port, S3C2410_UCON); 656 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 657 S3C64XX_UCON_EMPTYINT_EN | 658 S3C64XX_UCON_DMASUS_EN | 659 S3C64XX_UCON_TIMEOUT_EN | 660 S3C64XX_UCON_RXMODE_MASK); 661 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 662 S3C64XX_UCON_TIMEOUT_EN | 663 S3C64XX_UCON_RXMODE_CPU; 664 wr_regl(port, S3C2410_UCON, ucon); 665 666 ourport->rx_mode = S3C24XX_RX_PIO; 667 } 668 669 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 670 671 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 672 { 673 unsigned int utrstat, received; 674 struct s3c24xx_uart_port *ourport = dev_id; 675 struct uart_port *port = &ourport->port; 676 struct s3c24xx_uart_dma *dma = ourport->dma; 677 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 678 struct tty_port *t = &port->state->port; 679 unsigned long flags; 680 struct dma_tx_state state; 681 682 utrstat = rd_regl(port, S3C2410_UTRSTAT); 683 rd_regl(port, S3C2410_UFSTAT); 684 685 spin_lock_irqsave(&port->lock, flags); 686 687 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 688 s3c64xx_start_rx_dma(ourport); 689 if (ourport->rx_mode == S3C24XX_RX_PIO) 690 enable_rx_dma(ourport); 691 goto finish; 692 } 693 694 if (ourport->rx_mode == S3C24XX_RX_DMA) { 695 dmaengine_pause(dma->rx_chan); 696 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 697 dmaengine_terminate_all(dma->rx_chan); 698 received = dma->rx_bytes_requested - state.residue; 699 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 700 701 enable_rx_pio(ourport); 702 } 703 704 s3c24xx_serial_rx_drain_fifo(ourport); 705 706 if (tty) { 707 tty_flip_buffer_push(t); 708 tty_kref_put(tty); 709 } 710 711 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 712 713 finish: 714 spin_unlock_irqrestore(&port->lock, flags); 715 716 return IRQ_HANDLED; 717 } 718 719 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 720 { 721 struct uart_port *port = &ourport->port; 722 unsigned int ufcon, ch, flag, ufstat, uerstat; 723 unsigned int fifocnt = 0; 724 int max_count = port->fifosize; 725 726 while (max_count-- > 0) { 727 /* 728 * Receive all characters known to be in FIFO 729 * before reading FIFO level again 730 */ 731 if (fifocnt == 0) { 732 ufstat = rd_regl(port, S3C2410_UFSTAT); 733 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 734 if (fifocnt == 0) 735 break; 736 } 737 fifocnt--; 738 739 uerstat = rd_regl(port, S3C2410_UERSTAT); 740 ch = rd_reg(port, S3C2410_URXH); 741 742 if (port->flags & UPF_CONS_FLOW) { 743 int txe = s3c24xx_serial_txempty_nofifo(port); 744 745 if (ourport->rx_enabled) { 746 if (!txe) { 747 ourport->rx_enabled = 0; 748 continue; 749 } 750 } else { 751 if (txe) { 752 ufcon = rd_regl(port, S3C2410_UFCON); 753 ufcon |= S3C2410_UFCON_RESETRX; 754 wr_regl(port, S3C2410_UFCON, ufcon); 755 ourport->rx_enabled = 1; 756 return; 757 } 758 continue; 759 } 760 } 761 762 /* insert the character into the buffer */ 763 764 flag = TTY_NORMAL; 765 port->icount.rx++; 766 767 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 768 dev_dbg(port->dev, 769 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 770 ch, uerstat); 771 772 /* check for break */ 773 if (uerstat & S3C2410_UERSTAT_BREAK) { 774 dev_dbg(port->dev, "break!\n"); 775 port->icount.brk++; 776 if (uart_handle_break(port)) 777 continue; /* Ignore character */ 778 } 779 780 if (uerstat & S3C2410_UERSTAT_FRAME) 781 port->icount.frame++; 782 if (uerstat & S3C2410_UERSTAT_OVERRUN) 783 port->icount.overrun++; 784 785 uerstat &= port->read_status_mask; 786 787 if (uerstat & S3C2410_UERSTAT_BREAK) 788 flag = TTY_BREAK; 789 else if (uerstat & S3C2410_UERSTAT_PARITY) 790 flag = TTY_PARITY; 791 else if (uerstat & (S3C2410_UERSTAT_FRAME | 792 S3C2410_UERSTAT_OVERRUN)) 793 flag = TTY_FRAME; 794 } 795 796 if (uart_handle_sysrq_char(port, ch)) 797 continue; /* Ignore character */ 798 799 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 800 ch, flag); 801 } 802 803 tty_flip_buffer_push(&port->state->port); 804 } 805 806 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 807 { 808 struct s3c24xx_uart_port *ourport = dev_id; 809 struct uart_port *port = &ourport->port; 810 unsigned long flags; 811 812 spin_lock_irqsave(&port->lock, flags); 813 s3c24xx_serial_rx_drain_fifo(ourport); 814 spin_unlock_irqrestore(&port->lock, flags); 815 816 return IRQ_HANDLED; 817 } 818 819 820 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id) 821 { 822 struct s3c24xx_uart_port *ourport = dev_id; 823 824 if (ourport->dma && ourport->dma->rx_chan) 825 return s3c24xx_serial_rx_chars_dma(dev_id); 826 return s3c24xx_serial_rx_chars_pio(dev_id); 827 } 828 829 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) 830 { 831 struct s3c24xx_uart_port *ourport = id; 832 struct uart_port *port = &ourport->port; 833 struct circ_buf *xmit = &port->state->xmit; 834 unsigned long flags; 835 int count, dma_count = 0; 836 837 spin_lock_irqsave(&port->lock, flags); 838 839 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 840 841 if (ourport->dma && ourport->dma->tx_chan && 842 count >= ourport->min_dma_size) { 843 int align = dma_get_cache_alignment() - 844 (xmit->tail & (dma_get_cache_alignment() - 1)); 845 if (count-align >= ourport->min_dma_size) { 846 dma_count = count-align; 847 count = align; 848 } 849 } 850 851 if (port->x_char) { 852 wr_reg(port, S3C2410_UTXH, port->x_char); 853 port->icount.tx++; 854 port->x_char = 0; 855 goto out; 856 } 857 858 /* if there isn't anything more to transmit, or the uart is now 859 * stopped, disable the uart and exit 860 */ 861 862 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 863 s3c24xx_serial_stop_tx(port); 864 goto out; 865 } 866 867 /* try and drain the buffer... */ 868 869 if (count > port->fifosize) { 870 count = port->fifosize; 871 dma_count = 0; 872 } 873 874 while (!uart_circ_empty(xmit) && count > 0) { 875 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) 876 break; 877 878 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); 879 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 880 port->icount.tx++; 881 count--; 882 } 883 884 if (!count && dma_count) { 885 s3c24xx_serial_start_tx_dma(ourport, dma_count); 886 goto out; 887 } 888 889 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 890 spin_unlock(&port->lock); 891 uart_write_wakeup(port); 892 spin_lock(&port->lock); 893 } 894 895 if (uart_circ_empty(xmit)) 896 s3c24xx_serial_stop_tx(port); 897 898 out: 899 spin_unlock_irqrestore(&port->lock, flags); 900 return IRQ_HANDLED; 901 } 902 903 /* interrupt handler for s3c64xx and later SoC's.*/ 904 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 905 { 906 struct s3c24xx_uart_port *ourport = id; 907 struct uart_port *port = &ourport->port; 908 unsigned int pend = rd_regl(port, S3C64XX_UINTP); 909 irqreturn_t ret = IRQ_HANDLED; 910 911 if (pend & S3C64XX_UINTM_RXD_MSK) { 912 ret = s3c24xx_serial_rx_chars(irq, id); 913 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 914 } 915 if (pend & S3C64XX_UINTM_TXD_MSK) { 916 ret = s3c24xx_serial_tx_chars(irq, id); 917 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 918 } 919 return ret; 920 } 921 922 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 923 { 924 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 925 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); 926 unsigned long ufcon = rd_regl(port, S3C2410_UFCON); 927 928 if (ufcon & S3C2410_UFCON_FIFOMODE) { 929 if ((ufstat & info->tx_fifomask) != 0 || 930 (ufstat & info->tx_fifofull)) 931 return 0; 932 933 return 1; 934 } 935 936 return s3c24xx_serial_txempty_nofifo(port); 937 } 938 939 /* no modem control lines */ 940 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 941 { 942 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); 943 944 if (umstat & S3C2410_UMSTAT_CTS) 945 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 946 else 947 return TIOCM_CAR | TIOCM_DSR; 948 } 949 950 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 951 { 952 unsigned int umcon = rd_regl(port, S3C2410_UMCON); 953 954 if (mctrl & TIOCM_RTS) 955 umcon |= S3C2410_UMCOM_RTS_LOW; 956 else 957 umcon &= ~S3C2410_UMCOM_RTS_LOW; 958 959 wr_regl(port, S3C2410_UMCON, umcon); 960 } 961 962 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 963 { 964 unsigned long flags; 965 unsigned int ucon; 966 967 spin_lock_irqsave(&port->lock, flags); 968 969 ucon = rd_regl(port, S3C2410_UCON); 970 971 if (break_state) 972 ucon |= S3C2410_UCON_SBREAK; 973 else 974 ucon &= ~S3C2410_UCON_SBREAK; 975 976 wr_regl(port, S3C2410_UCON, ucon); 977 978 spin_unlock_irqrestore(&port->lock, flags); 979 } 980 981 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 982 { 983 struct s3c24xx_uart_dma *dma = p->dma; 984 struct dma_slave_caps dma_caps; 985 const char *reason = NULL; 986 int ret; 987 988 /* Default slave configuration parameters */ 989 dma->rx_conf.direction = DMA_DEV_TO_MEM; 990 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 991 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 992 dma->rx_conf.src_maxburst = 1; 993 994 dma->tx_conf.direction = DMA_MEM_TO_DEV; 995 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 996 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 997 dma->tx_conf.dst_maxburst = 1; 998 999 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1000 1001 if (IS_ERR(dma->rx_chan)) { 1002 reason = "DMA RX channel request failed"; 1003 ret = PTR_ERR(dma->rx_chan); 1004 goto err_warn; 1005 } 1006 1007 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1008 if (ret < 0 || 1009 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1010 reason = "insufficient DMA RX engine capabilities"; 1011 ret = -EOPNOTSUPP; 1012 goto err_release_rx; 1013 } 1014 1015 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1016 1017 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1018 if (IS_ERR(dma->tx_chan)) { 1019 reason = "DMA TX channel request failed"; 1020 ret = PTR_ERR(dma->tx_chan); 1021 goto err_release_rx; 1022 } 1023 1024 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1025 if (ret < 0 || 1026 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1027 reason = "insufficient DMA TX engine capabilities"; 1028 ret = -EOPNOTSUPP; 1029 goto err_release_tx; 1030 } 1031 1032 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1033 1034 /* RX buffer */ 1035 dma->rx_size = PAGE_SIZE; 1036 1037 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1038 if (!dma->rx_buf) { 1039 ret = -ENOMEM; 1040 goto err_release_tx; 1041 } 1042 1043 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf, 1044 dma->rx_size, DMA_FROM_DEVICE); 1045 if (dma_mapping_error(p->port.dev, dma->rx_addr)) { 1046 reason = "DMA mapping error for RX buffer"; 1047 ret = -EIO; 1048 goto err_free_rx; 1049 } 1050 1051 /* TX buffer */ 1052 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf, 1053 UART_XMIT_SIZE, DMA_TO_DEVICE); 1054 if (dma_mapping_error(p->port.dev, dma->tx_addr)) { 1055 reason = "DMA mapping error for TX buffer"; 1056 ret = -EIO; 1057 goto err_unmap_rx; 1058 } 1059 1060 return 0; 1061 1062 err_unmap_rx: 1063 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size, 1064 DMA_FROM_DEVICE); 1065 err_free_rx: 1066 kfree(dma->rx_buf); 1067 err_release_tx: 1068 dma_release_channel(dma->tx_chan); 1069 err_release_rx: 1070 dma_release_channel(dma->rx_chan); 1071 err_warn: 1072 if (reason) 1073 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1074 return ret; 1075 } 1076 1077 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1078 { 1079 struct s3c24xx_uart_dma *dma = p->dma; 1080 1081 if (dma->rx_chan) { 1082 dmaengine_terminate_all(dma->rx_chan); 1083 dma_unmap_single(p->port.dev, dma->rx_addr, 1084 dma->rx_size, DMA_FROM_DEVICE); 1085 kfree(dma->rx_buf); 1086 dma_release_channel(dma->rx_chan); 1087 dma->rx_chan = NULL; 1088 } 1089 1090 if (dma->tx_chan) { 1091 dmaengine_terminate_all(dma->tx_chan); 1092 dma_unmap_single(p->port.dev, dma->tx_addr, 1093 UART_XMIT_SIZE, DMA_TO_DEVICE); 1094 dma_release_channel(dma->tx_chan); 1095 dma->tx_chan = NULL; 1096 } 1097 } 1098 1099 static void s3c24xx_serial_shutdown(struct uart_port *port) 1100 { 1101 struct s3c24xx_uart_port *ourport = to_ourport(port); 1102 1103 if (ourport->tx_claimed) { 1104 if (!s3c24xx_serial_has_interrupt_mask(port)) 1105 free_irq(ourport->tx_irq, ourport); 1106 ourport->tx_enabled = 0; 1107 ourport->tx_claimed = 0; 1108 ourport->tx_mode = 0; 1109 } 1110 1111 if (ourport->rx_claimed) { 1112 if (!s3c24xx_serial_has_interrupt_mask(port)) 1113 free_irq(ourport->rx_irq, ourport); 1114 ourport->rx_claimed = 0; 1115 ourport->rx_enabled = 0; 1116 } 1117 1118 /* Clear pending interrupts and mask all interrupts */ 1119 if (s3c24xx_serial_has_interrupt_mask(port)) { 1120 free_irq(port->irq, ourport); 1121 1122 wr_regl(port, S3C64XX_UINTP, 0xf); 1123 wr_regl(port, S3C64XX_UINTM, 0xf); 1124 } 1125 1126 if (ourport->dma) 1127 s3c24xx_serial_release_dma(ourport); 1128 1129 ourport->tx_in_progress = 0; 1130 } 1131 1132 static int s3c24xx_serial_startup(struct uart_port *port) 1133 { 1134 struct s3c24xx_uart_port *ourport = to_ourport(port); 1135 int ret; 1136 1137 ourport->rx_enabled = 1; 1138 1139 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, 1140 s3c24xx_serial_portname(port), ourport); 1141 1142 if (ret != 0) { 1143 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); 1144 return ret; 1145 } 1146 1147 ourport->rx_claimed = 1; 1148 1149 dev_dbg(port->dev, "requesting tx irq...\n"); 1150 1151 ourport->tx_enabled = 1; 1152 1153 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, 1154 s3c24xx_serial_portname(port), ourport); 1155 1156 if (ret) { 1157 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); 1158 goto err; 1159 } 1160 1161 ourport->tx_claimed = 1; 1162 1163 /* the port reset code should have done the correct 1164 * register setup for the port controls 1165 */ 1166 1167 return ret; 1168 1169 err: 1170 s3c24xx_serial_shutdown(port); 1171 return ret; 1172 } 1173 1174 static int s3c64xx_serial_startup(struct uart_port *port) 1175 { 1176 struct s3c24xx_uart_port *ourport = to_ourport(port); 1177 unsigned long flags; 1178 unsigned int ufcon; 1179 int ret; 1180 1181 wr_regl(port, S3C64XX_UINTM, 0xf); 1182 if (ourport->dma) { 1183 ret = s3c24xx_serial_request_dma(ourport); 1184 if (ret < 0) { 1185 devm_kfree(port->dev, ourport->dma); 1186 ourport->dma = NULL; 1187 } 1188 } 1189 1190 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1191 s3c24xx_serial_portname(port), ourport); 1192 if (ret) { 1193 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1194 return ret; 1195 } 1196 1197 /* For compatibility with s3c24xx Soc's */ 1198 ourport->rx_enabled = 1; 1199 ourport->rx_claimed = 1; 1200 ourport->tx_enabled = 0; 1201 ourport->tx_claimed = 1; 1202 1203 spin_lock_irqsave(&port->lock, flags); 1204 1205 ufcon = rd_regl(port, S3C2410_UFCON); 1206 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1207 if (!uart_console(port)) 1208 ufcon |= S3C2410_UFCON_RESETTX; 1209 wr_regl(port, S3C2410_UFCON, ufcon); 1210 1211 enable_rx_pio(ourport); 1212 1213 spin_unlock_irqrestore(&port->lock, flags); 1214 1215 /* Enable Rx Interrupt */ 1216 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1217 1218 return ret; 1219 } 1220 1221 /* power power management control */ 1222 1223 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1224 unsigned int old) 1225 { 1226 struct s3c24xx_uart_port *ourport = to_ourport(port); 1227 int timeout = 10000; 1228 1229 ourport->pm_level = level; 1230 1231 switch (level) { 1232 case 3: 1233 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1234 udelay(100); 1235 1236 if (!IS_ERR(ourport->baudclk)) 1237 clk_disable_unprepare(ourport->baudclk); 1238 1239 clk_disable_unprepare(ourport->clk); 1240 break; 1241 1242 case 0: 1243 clk_prepare_enable(ourport->clk); 1244 1245 if (!IS_ERR(ourport->baudclk)) 1246 clk_prepare_enable(ourport->baudclk); 1247 1248 break; 1249 default: 1250 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1251 } 1252 } 1253 1254 /* baud rate calculation 1255 * 1256 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1257 * of different sources, including the peripheral clock ("pclk") and an 1258 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1259 * with a programmable extra divisor. 1260 * 1261 * The following code goes through the clock sources, and calculates the 1262 * baud clocks (and the resultant actual baud rates) and then tries to 1263 * pick the closest one and select that. 1264 * 1265 */ 1266 1267 #define MAX_CLK_NAME_LENGTH 15 1268 1269 static inline int s3c24xx_serial_getsource(struct uart_port *port) 1270 { 1271 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1272 unsigned int ucon; 1273 1274 if (info->num_clks == 1) 1275 return 0; 1276 1277 ucon = rd_regl(port, S3C2410_UCON); 1278 ucon &= info->clksel_mask; 1279 return ucon >> info->clksel_shift; 1280 } 1281 1282 static void s3c24xx_serial_setsource(struct uart_port *port, 1283 unsigned int clk_sel) 1284 { 1285 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1286 unsigned int ucon; 1287 1288 if (info->num_clks == 1) 1289 return; 1290 1291 ucon = rd_regl(port, S3C2410_UCON); 1292 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1293 return; 1294 1295 ucon &= ~info->clksel_mask; 1296 ucon |= clk_sel << info->clksel_shift; 1297 wr_regl(port, S3C2410_UCON, ucon); 1298 } 1299 1300 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1301 unsigned int req_baud, struct clk **best_clk, 1302 unsigned int *clk_num) 1303 { 1304 struct s3c24xx_uart_info *info = ourport->info; 1305 struct clk *clk; 1306 unsigned long rate; 1307 unsigned int cnt, baud, quot, best_quot = 0; 1308 char clkname[MAX_CLK_NAME_LENGTH]; 1309 int calc_deviation, deviation = (1 << 30) - 1; 1310 1311 for (cnt = 0; cnt < info->num_clks; cnt++) { 1312 /* Keep selected clock if provided */ 1313 if (ourport->cfg->clk_sel && 1314 !(ourport->cfg->clk_sel & (1 << cnt))) 1315 continue; 1316 1317 sprintf(clkname, "clk_uart_baud%d", cnt); 1318 clk = clk_get(ourport->port.dev, clkname); 1319 if (IS_ERR(clk)) 1320 continue; 1321 1322 rate = clk_get_rate(clk); 1323 if (!rate) 1324 continue; 1325 1326 if (ourport->info->has_divslot) { 1327 unsigned long div = rate / req_baud; 1328 1329 /* The UDIVSLOT register on the newer UARTs allows us to 1330 * get a divisor adjustment of 1/16th on the baud clock. 1331 * 1332 * We don't keep the UDIVSLOT value (the 16ths we 1333 * calculated by not multiplying the baud by 16) as it 1334 * is easy enough to recalculate. 1335 */ 1336 1337 quot = div / 16; 1338 baud = rate / div; 1339 } else { 1340 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1341 baud = rate / (quot * 16); 1342 } 1343 quot--; 1344 1345 calc_deviation = req_baud - baud; 1346 if (calc_deviation < 0) 1347 calc_deviation = -calc_deviation; 1348 1349 if (calc_deviation < deviation) { 1350 *best_clk = clk; 1351 best_quot = quot; 1352 *clk_num = cnt; 1353 deviation = calc_deviation; 1354 } 1355 } 1356 1357 return best_quot; 1358 } 1359 1360 /* udivslot_table[] 1361 * 1362 * This table takes the fractional value of the baud divisor and gives 1363 * the recommended setting for the UDIVSLOT register. 1364 */ 1365 static u16 udivslot_table[16] = { 1366 [0] = 0x0000, 1367 [1] = 0x0080, 1368 [2] = 0x0808, 1369 [3] = 0x0888, 1370 [4] = 0x2222, 1371 [5] = 0x4924, 1372 [6] = 0x4A52, 1373 [7] = 0x54AA, 1374 [8] = 0x5555, 1375 [9] = 0xD555, 1376 [10] = 0xD5D5, 1377 [11] = 0xDDD5, 1378 [12] = 0xDDDD, 1379 [13] = 0xDFDD, 1380 [14] = 0xDFDF, 1381 [15] = 0xFFDF, 1382 }; 1383 1384 static void s3c24xx_serial_set_termios(struct uart_port *port, 1385 struct ktermios *termios, 1386 struct ktermios *old) 1387 { 1388 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1389 struct s3c24xx_uart_port *ourport = to_ourport(port); 1390 struct clk *clk = ERR_PTR(-EINVAL); 1391 unsigned long flags; 1392 unsigned int baud, quot, clk_sel = 0; 1393 unsigned int ulcon; 1394 unsigned int umcon; 1395 unsigned int udivslot = 0; 1396 1397 /* 1398 * We don't support modem control lines. 1399 */ 1400 termios->c_cflag &= ~(HUPCL | CMSPAR); 1401 termios->c_cflag |= CLOCAL; 1402 1403 /* 1404 * Ask the core to calculate the divisor for us. 1405 */ 1406 1407 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1408 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1409 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1410 quot = port->custom_divisor; 1411 if (IS_ERR(clk)) 1412 return; 1413 1414 /* check to see if we need to change clock source */ 1415 1416 if (ourport->baudclk != clk) { 1417 clk_prepare_enable(clk); 1418 1419 s3c24xx_serial_setsource(port, clk_sel); 1420 1421 if (!IS_ERR(ourport->baudclk)) { 1422 clk_disable_unprepare(ourport->baudclk); 1423 ourport->baudclk = ERR_PTR(-EINVAL); 1424 } 1425 1426 ourport->baudclk = clk; 1427 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1428 } 1429 1430 if (ourport->info->has_divslot) { 1431 unsigned int div = ourport->baudclk_rate / baud; 1432 1433 if (cfg->has_fracval) { 1434 udivslot = (div & 15); 1435 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1436 } else { 1437 udivslot = udivslot_table[div & 15]; 1438 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1439 udivslot, div & 15); 1440 } 1441 } 1442 1443 switch (termios->c_cflag & CSIZE) { 1444 case CS5: 1445 dev_dbg(port->dev, "config: 5bits/char\n"); 1446 ulcon = S3C2410_LCON_CS5; 1447 break; 1448 case CS6: 1449 dev_dbg(port->dev, "config: 6bits/char\n"); 1450 ulcon = S3C2410_LCON_CS6; 1451 break; 1452 case CS7: 1453 dev_dbg(port->dev, "config: 7bits/char\n"); 1454 ulcon = S3C2410_LCON_CS7; 1455 break; 1456 case CS8: 1457 default: 1458 dev_dbg(port->dev, "config: 8bits/char\n"); 1459 ulcon = S3C2410_LCON_CS8; 1460 break; 1461 } 1462 1463 /* preserve original lcon IR settings */ 1464 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1465 1466 if (termios->c_cflag & CSTOPB) 1467 ulcon |= S3C2410_LCON_STOPB; 1468 1469 if (termios->c_cflag & PARENB) { 1470 if (termios->c_cflag & PARODD) 1471 ulcon |= S3C2410_LCON_PODD; 1472 else 1473 ulcon |= S3C2410_LCON_PEVEN; 1474 } else { 1475 ulcon |= S3C2410_LCON_PNONE; 1476 } 1477 1478 spin_lock_irqsave(&port->lock, flags); 1479 1480 dev_dbg(port->dev, 1481 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1482 ulcon, quot, udivslot); 1483 1484 wr_regl(port, S3C2410_ULCON, ulcon); 1485 wr_regl(port, S3C2410_UBRDIV, quot); 1486 1487 port->status &= ~UPSTAT_AUTOCTS; 1488 1489 umcon = rd_regl(port, S3C2410_UMCON); 1490 if (termios->c_cflag & CRTSCTS) { 1491 umcon |= S3C2410_UMCOM_AFC; 1492 /* Disable RTS when RX FIFO contains 63 bytes */ 1493 umcon &= ~S3C2412_UMCON_AFC_8; 1494 port->status = UPSTAT_AUTOCTS; 1495 } else { 1496 umcon &= ~S3C2410_UMCOM_AFC; 1497 } 1498 wr_regl(port, S3C2410_UMCON, umcon); 1499 1500 if (ourport->info->has_divslot) 1501 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1502 1503 dev_dbg(port->dev, 1504 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1505 rd_regl(port, S3C2410_ULCON), 1506 rd_regl(port, S3C2410_UCON), 1507 rd_regl(port, S3C2410_UFCON)); 1508 1509 /* 1510 * Update the per-port timeout. 1511 */ 1512 uart_update_timeout(port, termios->c_cflag, baud); 1513 1514 /* 1515 * Which character status flags are we interested in? 1516 */ 1517 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1518 if (termios->c_iflag & INPCK) 1519 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1520 S3C2410_UERSTAT_PARITY; 1521 /* 1522 * Which character status flags should we ignore? 1523 */ 1524 port->ignore_status_mask = 0; 1525 if (termios->c_iflag & IGNPAR) 1526 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1527 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1528 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1529 1530 /* 1531 * Ignore all characters if CREAD is not set. 1532 */ 1533 if ((termios->c_cflag & CREAD) == 0) 1534 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1535 1536 spin_unlock_irqrestore(&port->lock, flags); 1537 } 1538 1539 static const char *s3c24xx_serial_type(struct uart_port *port) 1540 { 1541 switch (port->type) { 1542 case PORT_S3C2410: 1543 return "S3C2410"; 1544 case PORT_S3C2440: 1545 return "S3C2440"; 1546 case PORT_S3C2412: 1547 return "S3C2412"; 1548 case PORT_S3C6400: 1549 return "S3C6400/10"; 1550 default: 1551 return NULL; 1552 } 1553 } 1554 1555 #define MAP_SIZE (0x100) 1556 1557 static void s3c24xx_serial_release_port(struct uart_port *port) 1558 { 1559 release_mem_region(port->mapbase, MAP_SIZE); 1560 } 1561 1562 static int s3c24xx_serial_request_port(struct uart_port *port) 1563 { 1564 const char *name = s3c24xx_serial_portname(port); 1565 1566 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; 1567 } 1568 1569 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1570 { 1571 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1572 1573 if (flags & UART_CONFIG_TYPE && 1574 s3c24xx_serial_request_port(port) == 0) 1575 port->type = info->type; 1576 } 1577 1578 /* 1579 * verify the new serial_struct (for TIOCSSERIAL). 1580 */ 1581 static int 1582 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1583 { 1584 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1585 1586 if (ser->type != PORT_UNKNOWN && ser->type != info->type) 1587 return -EINVAL; 1588 1589 return 0; 1590 } 1591 1592 1593 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1594 1595 static struct console s3c24xx_serial_console; 1596 1597 static int __init s3c24xx_serial_console_init(void) 1598 { 1599 register_console(&s3c24xx_serial_console); 1600 return 0; 1601 } 1602 console_initcall(s3c24xx_serial_console_init); 1603 1604 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1605 #else 1606 #define S3C24XX_SERIAL_CONSOLE NULL 1607 #endif 1608 1609 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1610 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1611 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1612 unsigned char c); 1613 #endif 1614 1615 static struct uart_ops s3c24xx_serial_ops = { 1616 .pm = s3c24xx_serial_pm, 1617 .tx_empty = s3c24xx_serial_tx_empty, 1618 .get_mctrl = s3c24xx_serial_get_mctrl, 1619 .set_mctrl = s3c24xx_serial_set_mctrl, 1620 .stop_tx = s3c24xx_serial_stop_tx, 1621 .start_tx = s3c24xx_serial_start_tx, 1622 .stop_rx = s3c24xx_serial_stop_rx, 1623 .break_ctl = s3c24xx_serial_break_ctl, 1624 .startup = s3c24xx_serial_startup, 1625 .shutdown = s3c24xx_serial_shutdown, 1626 .set_termios = s3c24xx_serial_set_termios, 1627 .type = s3c24xx_serial_type, 1628 .release_port = s3c24xx_serial_release_port, 1629 .request_port = s3c24xx_serial_request_port, 1630 .config_port = s3c24xx_serial_config_port, 1631 .verify_port = s3c24xx_serial_verify_port, 1632 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1633 .poll_get_char = s3c24xx_serial_get_poll_char, 1634 .poll_put_char = s3c24xx_serial_put_poll_char, 1635 #endif 1636 }; 1637 1638 static struct uart_driver s3c24xx_uart_drv = { 1639 .owner = THIS_MODULE, 1640 .driver_name = "s3c2410_serial", 1641 .nr = CONFIG_SERIAL_SAMSUNG_UARTS, 1642 .cons = S3C24XX_SERIAL_CONSOLE, 1643 .dev_name = S3C24XX_SERIAL_NAME, 1644 .major = S3C24XX_SERIAL_MAJOR, 1645 .minor = S3C24XX_SERIAL_MINOR, 1646 }; 1647 1648 #define __PORT_LOCK_UNLOCKED(i) \ 1649 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock) 1650 static struct s3c24xx_uart_port 1651 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { 1652 [0] = { 1653 .port = { 1654 .lock = __PORT_LOCK_UNLOCKED(0), 1655 .iotype = UPIO_MEM, 1656 .uartclk = 0, 1657 .fifosize = 16, 1658 .ops = &s3c24xx_serial_ops, 1659 .flags = UPF_BOOT_AUTOCONF, 1660 .line = 0, 1661 } 1662 }, 1663 [1] = { 1664 .port = { 1665 .lock = __PORT_LOCK_UNLOCKED(1), 1666 .iotype = UPIO_MEM, 1667 .uartclk = 0, 1668 .fifosize = 16, 1669 .ops = &s3c24xx_serial_ops, 1670 .flags = UPF_BOOT_AUTOCONF, 1671 .line = 1, 1672 } 1673 }, 1674 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 1675 1676 [2] = { 1677 .port = { 1678 .lock = __PORT_LOCK_UNLOCKED(2), 1679 .iotype = UPIO_MEM, 1680 .uartclk = 0, 1681 .fifosize = 16, 1682 .ops = &s3c24xx_serial_ops, 1683 .flags = UPF_BOOT_AUTOCONF, 1684 .line = 2, 1685 } 1686 }, 1687 #endif 1688 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 1689 [3] = { 1690 .port = { 1691 .lock = __PORT_LOCK_UNLOCKED(3), 1692 .iotype = UPIO_MEM, 1693 .uartclk = 0, 1694 .fifosize = 16, 1695 .ops = &s3c24xx_serial_ops, 1696 .flags = UPF_BOOT_AUTOCONF, 1697 .line = 3, 1698 } 1699 } 1700 #endif 1701 }; 1702 #undef __PORT_LOCK_UNLOCKED 1703 1704 /* s3c24xx_serial_resetport 1705 * 1706 * reset the fifos and other the settings. 1707 */ 1708 1709 static void s3c24xx_serial_resetport(struct uart_port *port, 1710 struct s3c2410_uartcfg *cfg) 1711 { 1712 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1713 unsigned long ucon = rd_regl(port, S3C2410_UCON); 1714 unsigned int ucon_mask; 1715 1716 ucon_mask = info->clksel_mask; 1717 if (info->type == PORT_S3C2440) 1718 ucon_mask |= S3C2440_UCON0_DIVMASK; 1719 1720 ucon &= ucon_mask; 1721 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1722 1723 /* reset both fifos */ 1724 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1725 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1726 1727 /* some delay is required after fifo reset */ 1728 udelay(1); 1729 } 1730 1731 1732 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 1733 1734 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, 1735 unsigned long val, void *data) 1736 { 1737 struct s3c24xx_uart_port *port; 1738 struct uart_port *uport; 1739 1740 port = container_of(nb, struct s3c24xx_uart_port, freq_transition); 1741 uport = &port->port; 1742 1743 /* check to see if port is enabled */ 1744 1745 if (port->pm_level != 0) 1746 return 0; 1747 1748 /* try and work out if the baudrate is changing, we can detect 1749 * a change in rate, but we do not have support for detecting 1750 * a disturbance in the clock-rate over the change. 1751 */ 1752 1753 if (IS_ERR(port->baudclk)) 1754 goto exit; 1755 1756 if (port->baudclk_rate == clk_get_rate(port->baudclk)) 1757 goto exit; 1758 1759 if (val == CPUFREQ_PRECHANGE) { 1760 /* we should really shut the port down whilst the 1761 * frequency change is in progress. 1762 */ 1763 1764 } else if (val == CPUFREQ_POSTCHANGE) { 1765 struct ktermios *termios; 1766 struct tty_struct *tty; 1767 1768 if (uport->state == NULL) 1769 goto exit; 1770 1771 tty = uport->state->port.tty; 1772 1773 if (tty == NULL) 1774 goto exit; 1775 1776 termios = &tty->termios; 1777 1778 if (termios == NULL) { 1779 dev_warn(uport->dev, "%s: no termios?\n", __func__); 1780 goto exit; 1781 } 1782 1783 s3c24xx_serial_set_termios(uport, termios, NULL); 1784 } 1785 1786 exit: 1787 return 0; 1788 } 1789 1790 static inline int 1791 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1792 { 1793 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; 1794 1795 return cpufreq_register_notifier(&port->freq_transition, 1796 CPUFREQ_TRANSITION_NOTIFIER); 1797 } 1798 1799 static inline void 1800 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1801 { 1802 cpufreq_unregister_notifier(&port->freq_transition, 1803 CPUFREQ_TRANSITION_NOTIFIER); 1804 } 1805 1806 #else 1807 static inline int 1808 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1809 { 1810 return 0; 1811 } 1812 1813 static inline void 1814 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1815 { 1816 } 1817 #endif 1818 1819 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1820 { 1821 struct device *dev = ourport->port.dev; 1822 struct s3c24xx_uart_info *info = ourport->info; 1823 char clk_name[MAX_CLK_NAME_LENGTH]; 1824 unsigned int clk_sel; 1825 struct clk *clk; 1826 int clk_num; 1827 int ret; 1828 1829 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1830 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1831 if (!(clk_sel & (1 << clk_num))) 1832 continue; 1833 1834 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1835 clk = clk_get(dev, clk_name); 1836 if (IS_ERR(clk)) 1837 continue; 1838 1839 ret = clk_prepare_enable(clk); 1840 if (ret) { 1841 clk_put(clk); 1842 continue; 1843 } 1844 1845 ourport->baudclk = clk; 1846 ourport->baudclk_rate = clk_get_rate(clk); 1847 s3c24xx_serial_setsource(&ourport->port, clk_num); 1848 1849 return 0; 1850 } 1851 1852 return -EINVAL; 1853 } 1854 1855 /* s3c24xx_serial_init_port 1856 * 1857 * initialise a single serial port from the platform device given 1858 */ 1859 1860 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 1861 struct platform_device *platdev) 1862 { 1863 struct uart_port *port = &ourport->port; 1864 struct s3c2410_uartcfg *cfg = ourport->cfg; 1865 struct resource *res; 1866 int ret; 1867 1868 if (platdev == NULL) 1869 return -ENODEV; 1870 1871 if (port->mapbase != 0) 1872 return -EINVAL; 1873 1874 /* setup info for port */ 1875 port->dev = &platdev->dev; 1876 1877 /* Startup sequence is different for s3c64xx and higher SoC's */ 1878 if (s3c24xx_serial_has_interrupt_mask(port)) 1879 s3c24xx_serial_ops.startup = s3c64xx_serial_startup; 1880 1881 port->uartclk = 1; 1882 1883 if (cfg->uart_flags & UPF_CONS_FLOW) { 1884 dev_dbg(port->dev, "enabling flow control\n"); 1885 port->flags |= UPF_CONS_FLOW; 1886 } 1887 1888 /* sort our the physical and virtual addresses for each UART */ 1889 1890 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 1891 if (res == NULL) { 1892 dev_err(port->dev, "failed to find memory resource for uart\n"); 1893 return -EINVAL; 1894 } 1895 1896 dev_dbg(port->dev, "resource %pR)\n", res); 1897 1898 port->membase = devm_ioremap(port->dev, res->start, resource_size(res)); 1899 if (!port->membase) { 1900 dev_err(port->dev, "failed to remap controller address\n"); 1901 return -EBUSY; 1902 } 1903 1904 port->mapbase = res->start; 1905 ret = platform_get_irq(platdev, 0); 1906 if (ret < 0) 1907 port->irq = 0; 1908 else { 1909 port->irq = ret; 1910 ourport->rx_irq = ret; 1911 ourport->tx_irq = ret + 1; 1912 } 1913 1914 ret = platform_get_irq(platdev, 1); 1915 if (ret > 0) 1916 ourport->tx_irq = ret; 1917 /* 1918 * DMA is currently supported only on DT platforms, if DMA properties 1919 * are specified. 1920 */ 1921 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 1922 "dmas", NULL)) { 1923 ourport->dma = devm_kzalloc(port->dev, 1924 sizeof(*ourport->dma), 1925 GFP_KERNEL); 1926 if (!ourport->dma) { 1927 ret = -ENOMEM; 1928 goto err; 1929 } 1930 } 1931 1932 ourport->clk = clk_get(&platdev->dev, "uart"); 1933 if (IS_ERR(ourport->clk)) { 1934 pr_err("%s: Controller clock not found\n", 1935 dev_name(&platdev->dev)); 1936 ret = PTR_ERR(ourport->clk); 1937 goto err; 1938 } 1939 1940 ret = clk_prepare_enable(ourport->clk); 1941 if (ret) { 1942 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 1943 clk_put(ourport->clk); 1944 goto err; 1945 } 1946 1947 ret = s3c24xx_serial_enable_baudclk(ourport); 1948 if (ret) 1949 pr_warn("uart: failed to enable baudclk\n"); 1950 1951 /* Keep all interrupts masked and cleared */ 1952 if (s3c24xx_serial_has_interrupt_mask(port)) { 1953 wr_regl(port, S3C64XX_UINTM, 0xf); 1954 wr_regl(port, S3C64XX_UINTP, 0xf); 1955 wr_regl(port, S3C64XX_UINTSP, 0xf); 1956 } 1957 1958 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 1959 &port->mapbase, port->membase, port->irq, 1960 ourport->rx_irq, ourport->tx_irq, port->uartclk); 1961 1962 /* reset the fifos (and setup the uart) */ 1963 s3c24xx_serial_resetport(port, cfg); 1964 1965 return 0; 1966 1967 err: 1968 port->mapbase = 0; 1969 return ret; 1970 } 1971 1972 /* Device driver serial port probe */ 1973 1974 #ifdef CONFIG_OF 1975 static const struct of_device_id s3c24xx_uart_dt_match[]; 1976 #endif 1977 1978 static int probe_index; 1979 1980 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data( 1981 struct platform_device *pdev) 1982 { 1983 #ifdef CONFIG_OF 1984 if (pdev->dev.of_node) { 1985 const struct of_device_id *match; 1986 1987 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node); 1988 return (struct s3c24xx_serial_drv_data *)match->data; 1989 } 1990 #endif 1991 return (struct s3c24xx_serial_drv_data *) 1992 platform_get_device_id(pdev)->driver_data; 1993 } 1994 1995 static int s3c24xx_serial_probe(struct platform_device *pdev) 1996 { 1997 struct device_node *np = pdev->dev.of_node; 1998 struct s3c24xx_uart_port *ourport; 1999 int index = probe_index; 2000 int ret, prop = 0; 2001 2002 if (np) { 2003 ret = of_alias_get_id(np, "serial"); 2004 if (ret >= 0) 2005 index = ret; 2006 } 2007 2008 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 2009 dev_err(&pdev->dev, "serial%d out of range\n", index); 2010 return -EINVAL; 2011 } 2012 ourport = &s3c24xx_serial_ports[index]; 2013 2014 ourport->drv_data = s3c24xx_get_driver_data(pdev); 2015 if (!ourport->drv_data) { 2016 dev_err(&pdev->dev, "could not find driver data\n"); 2017 return -ENODEV; 2018 } 2019 2020 ourport->baudclk = ERR_PTR(-EINVAL); 2021 ourport->info = ourport->drv_data->info; 2022 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 2023 dev_get_platdata(&pdev->dev) : 2024 ourport->drv_data->def_cfg; 2025 2026 if (np) { 2027 of_property_read_u32(np, 2028 "samsung,uart-fifosize", &ourport->port.fifosize); 2029 2030 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 2031 switch (prop) { 2032 case 1: 2033 ourport->port.iotype = UPIO_MEM; 2034 break; 2035 case 4: 2036 ourport->port.iotype = UPIO_MEM32; 2037 break; 2038 default: 2039 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2040 prop); 2041 ret = -EINVAL; 2042 break; 2043 } 2044 } 2045 } 2046 2047 if (ourport->drv_data->fifosize[index]) 2048 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2049 else if (ourport->info->fifosize) 2050 ourport->port.fifosize = ourport->info->fifosize; 2051 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2052 2053 /* 2054 * DMA transfers must be aligned at least to cache line size, 2055 * so find minimal transfer size suitable for DMA mode 2056 */ 2057 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2058 dma_get_cache_alignment()); 2059 2060 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2061 2062 ret = s3c24xx_serial_init_port(ourport, pdev); 2063 if (ret < 0) 2064 return ret; 2065 2066 if (!s3c24xx_uart_drv.state) { 2067 ret = uart_register_driver(&s3c24xx_uart_drv); 2068 if (ret < 0) { 2069 pr_err("Failed to register Samsung UART driver\n"); 2070 return ret; 2071 } 2072 } 2073 2074 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2075 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2076 platform_set_drvdata(pdev, &ourport->port); 2077 2078 /* 2079 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2080 * so that a potential re-enablement through the pm-callback overlaps 2081 * and keeps the clock enabled in this case. 2082 */ 2083 clk_disable_unprepare(ourport->clk); 2084 if (!IS_ERR(ourport->baudclk)) 2085 clk_disable_unprepare(ourport->baudclk); 2086 2087 ret = s3c24xx_serial_cpufreq_register(ourport); 2088 if (ret < 0) 2089 dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); 2090 2091 probe_index++; 2092 2093 return 0; 2094 } 2095 2096 static int s3c24xx_serial_remove(struct platform_device *dev) 2097 { 2098 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2099 2100 if (port) { 2101 s3c24xx_serial_cpufreq_deregister(to_ourport(port)); 2102 uart_remove_one_port(&s3c24xx_uart_drv, port); 2103 } 2104 2105 uart_unregister_driver(&s3c24xx_uart_drv); 2106 2107 return 0; 2108 } 2109 2110 /* UART power management code */ 2111 #ifdef CONFIG_PM_SLEEP 2112 static int s3c24xx_serial_suspend(struct device *dev) 2113 { 2114 struct uart_port *port = s3c24xx_dev_to_port(dev); 2115 2116 if (port) 2117 uart_suspend_port(&s3c24xx_uart_drv, port); 2118 2119 return 0; 2120 } 2121 2122 static int s3c24xx_serial_resume(struct device *dev) 2123 { 2124 struct uart_port *port = s3c24xx_dev_to_port(dev); 2125 struct s3c24xx_uart_port *ourport = to_ourport(port); 2126 2127 if (port) { 2128 clk_prepare_enable(ourport->clk); 2129 if (!IS_ERR(ourport->baudclk)) 2130 clk_prepare_enable(ourport->baudclk); 2131 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2132 if (!IS_ERR(ourport->baudclk)) 2133 clk_disable_unprepare(ourport->baudclk); 2134 clk_disable_unprepare(ourport->clk); 2135 2136 uart_resume_port(&s3c24xx_uart_drv, port); 2137 } 2138 2139 return 0; 2140 } 2141 2142 static int s3c24xx_serial_resume_noirq(struct device *dev) 2143 { 2144 struct uart_port *port = s3c24xx_dev_to_port(dev); 2145 struct s3c24xx_uart_port *ourport = to_ourport(port); 2146 2147 if (port) { 2148 /* restore IRQ mask */ 2149 if (s3c24xx_serial_has_interrupt_mask(port)) { 2150 unsigned int uintm = 0xf; 2151 2152 if (ourport->tx_enabled) 2153 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2154 if (ourport->rx_enabled) 2155 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2156 clk_prepare_enable(ourport->clk); 2157 if (!IS_ERR(ourport->baudclk)) 2158 clk_prepare_enable(ourport->baudclk); 2159 wr_regl(port, S3C64XX_UINTM, uintm); 2160 if (!IS_ERR(ourport->baudclk)) 2161 clk_disable_unprepare(ourport->baudclk); 2162 clk_disable_unprepare(ourport->clk); 2163 } 2164 } 2165 2166 return 0; 2167 } 2168 2169 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2170 .suspend = s3c24xx_serial_suspend, 2171 .resume = s3c24xx_serial_resume, 2172 .resume_noirq = s3c24xx_serial_resume_noirq, 2173 }; 2174 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2175 2176 #else /* !CONFIG_PM_SLEEP */ 2177 2178 #define SERIAL_SAMSUNG_PM_OPS NULL 2179 #endif /* CONFIG_PM_SLEEP */ 2180 2181 /* Console code */ 2182 2183 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2184 2185 static struct uart_port *cons_uart; 2186 2187 static int 2188 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) 2189 { 2190 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2191 unsigned long ufstat, utrstat; 2192 2193 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2194 /* fifo mode - check amount of data in fifo registers... */ 2195 2196 ufstat = rd_regl(port, S3C2410_UFSTAT); 2197 return (ufstat & info->tx_fifofull) ? 0 : 1; 2198 } 2199 2200 /* in non-fifo mode, we go and use the tx buffer empty */ 2201 2202 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2203 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; 2204 } 2205 2206 static bool 2207 s3c24xx_port_configured(unsigned int ucon) 2208 { 2209 /* consider the serial port configured if the tx/rx mode set */ 2210 return (ucon & 0xf) != 0; 2211 } 2212 2213 #ifdef CONFIG_CONSOLE_POLL 2214 /* 2215 * Console polling routines for writing and reading from the uart while 2216 * in an interrupt or debug context. 2217 */ 2218 2219 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2220 { 2221 struct s3c24xx_uart_port *ourport = to_ourport(port); 2222 unsigned int ufstat; 2223 2224 ufstat = rd_regl(port, S3C2410_UFSTAT); 2225 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2226 return NO_POLL_CHAR; 2227 2228 return rd_reg(port, S3C2410_URXH); 2229 } 2230 2231 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2232 unsigned char c) 2233 { 2234 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2235 unsigned int ucon = rd_regl(port, S3C2410_UCON); 2236 2237 /* not possible to xmit on unconfigured port */ 2238 if (!s3c24xx_port_configured(ucon)) 2239 return; 2240 2241 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2242 cpu_relax(); 2243 wr_reg(port, S3C2410_UTXH, c); 2244 } 2245 2246 #endif /* CONFIG_CONSOLE_POLL */ 2247 2248 static void 2249 s3c24xx_serial_console_putchar(struct uart_port *port, int ch) 2250 { 2251 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2252 2253 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2254 cpu_relax(); 2255 wr_reg(port, S3C2410_UTXH, ch); 2256 } 2257 2258 static void 2259 s3c24xx_serial_console_write(struct console *co, const char *s, 2260 unsigned int count) 2261 { 2262 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); 2263 2264 /* not possible to xmit on unconfigured port */ 2265 if (!s3c24xx_port_configured(ucon)) 2266 return; 2267 2268 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2269 } 2270 2271 static void __init 2272 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2273 int *parity, int *bits) 2274 { 2275 struct clk *clk; 2276 unsigned int ulcon; 2277 unsigned int ucon; 2278 unsigned int ubrdiv; 2279 unsigned long rate; 2280 unsigned int clk_sel; 2281 char clk_name[MAX_CLK_NAME_LENGTH]; 2282 2283 ulcon = rd_regl(port, S3C2410_ULCON); 2284 ucon = rd_regl(port, S3C2410_UCON); 2285 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2286 2287 if (s3c24xx_port_configured(ucon)) { 2288 switch (ulcon & S3C2410_LCON_CSMASK) { 2289 case S3C2410_LCON_CS5: 2290 *bits = 5; 2291 break; 2292 case S3C2410_LCON_CS6: 2293 *bits = 6; 2294 break; 2295 case S3C2410_LCON_CS7: 2296 *bits = 7; 2297 break; 2298 case S3C2410_LCON_CS8: 2299 default: 2300 *bits = 8; 2301 break; 2302 } 2303 2304 switch (ulcon & S3C2410_LCON_PMASK) { 2305 case S3C2410_LCON_PEVEN: 2306 *parity = 'e'; 2307 break; 2308 2309 case S3C2410_LCON_PODD: 2310 *parity = 'o'; 2311 break; 2312 2313 case S3C2410_LCON_PNONE: 2314 default: 2315 *parity = 'n'; 2316 } 2317 2318 /* now calculate the baud rate */ 2319 2320 clk_sel = s3c24xx_serial_getsource(port); 2321 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2322 2323 clk = clk_get(port->dev, clk_name); 2324 if (!IS_ERR(clk)) 2325 rate = clk_get_rate(clk); 2326 else 2327 rate = 1; 2328 2329 *baud = rate / (16 * (ubrdiv + 1)); 2330 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2331 } 2332 2333 } 2334 2335 static int __init 2336 s3c24xx_serial_console_setup(struct console *co, char *options) 2337 { 2338 struct uart_port *port; 2339 int baud = 9600; 2340 int bits = 8; 2341 int parity = 'n'; 2342 int flow = 'n'; 2343 2344 /* is this a valid port */ 2345 2346 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) 2347 co->index = 0; 2348 2349 port = &s3c24xx_serial_ports[co->index].port; 2350 2351 /* is the port configured? */ 2352 2353 if (port->mapbase == 0x0) 2354 return -ENODEV; 2355 2356 cons_uart = port; 2357 2358 /* 2359 * Check whether an invalid uart number has been specified, and 2360 * if so, search for the first available port that does have 2361 * console support. 2362 */ 2363 if (options) 2364 uart_parse_options(options, &baud, &parity, &bits, &flow); 2365 else 2366 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2367 2368 dev_dbg(port->dev, "baud %d\n", baud); 2369 2370 return uart_set_options(port, co, baud, parity, bits, flow); 2371 } 2372 2373 static struct console s3c24xx_serial_console = { 2374 .name = S3C24XX_SERIAL_NAME, 2375 .device = uart_console_device, 2376 .flags = CON_PRINTBUFFER, 2377 .index = -1, 2378 .write = s3c24xx_serial_console_write, 2379 .setup = s3c24xx_serial_console_setup, 2380 .data = &s3c24xx_uart_drv, 2381 }; 2382 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2383 2384 #ifdef CONFIG_CPU_S3C2410 2385 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { 2386 .info = &(struct s3c24xx_uart_info) { 2387 .name = "Samsung S3C2410 UART", 2388 .type = PORT_S3C2410, 2389 .fifosize = 16, 2390 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2391 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2392 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2393 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2394 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2395 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2396 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2397 .num_clks = 2, 2398 .clksel_mask = S3C2410_UCON_CLKMASK, 2399 .clksel_shift = S3C2410_UCON_CLKSHIFT, 2400 }, 2401 .def_cfg = &(struct s3c2410_uartcfg) { 2402 .ucon = S3C2410_UCON_DEFAULT, 2403 .ufcon = S3C2410_UFCON_DEFAULT, 2404 }, 2405 }; 2406 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data) 2407 #else 2408 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2409 #endif 2410 2411 #ifdef CONFIG_CPU_S3C2412 2412 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { 2413 .info = &(struct s3c24xx_uart_info) { 2414 .name = "Samsung S3C2412 UART", 2415 .type = PORT_S3C2412, 2416 .fifosize = 64, 2417 .has_divslot = 1, 2418 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2419 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2420 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2421 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2422 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2423 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2424 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2425 .num_clks = 4, 2426 .clksel_mask = S3C2412_UCON_CLKMASK, 2427 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2428 }, 2429 .def_cfg = &(struct s3c2410_uartcfg) { 2430 .ucon = S3C2410_UCON_DEFAULT, 2431 .ufcon = S3C2410_UFCON_DEFAULT, 2432 }, 2433 }; 2434 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data) 2435 #else 2436 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2437 #endif 2438 2439 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ 2440 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) 2441 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { 2442 .info = &(struct s3c24xx_uart_info) { 2443 .name = "Samsung S3C2440 UART", 2444 .type = PORT_S3C2440, 2445 .fifosize = 64, 2446 .has_divslot = 1, 2447 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2448 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2449 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2450 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2451 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2452 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2453 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2454 .num_clks = 4, 2455 .clksel_mask = S3C2412_UCON_CLKMASK, 2456 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2457 }, 2458 .def_cfg = &(struct s3c2410_uartcfg) { 2459 .ucon = S3C2410_UCON_DEFAULT, 2460 .ufcon = S3C2410_UFCON_DEFAULT, 2461 }, 2462 }; 2463 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data) 2464 #else 2465 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2466 #endif 2467 2468 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2469 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2470 .info = &(struct s3c24xx_uart_info) { 2471 .name = "Samsung S3C6400 UART", 2472 .type = PORT_S3C6400, 2473 .fifosize = 64, 2474 .has_divslot = 1, 2475 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2476 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2477 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2478 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2479 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2480 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2481 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2482 .num_clks = 4, 2483 .clksel_mask = S3C6400_UCON_CLKMASK, 2484 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2485 }, 2486 .def_cfg = &(struct s3c2410_uartcfg) { 2487 .ucon = S3C2410_UCON_DEFAULT, 2488 .ufcon = S3C2410_UFCON_DEFAULT, 2489 }, 2490 }; 2491 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data) 2492 #else 2493 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2494 #endif 2495 2496 #ifdef CONFIG_CPU_S5PV210 2497 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2498 .info = &(struct s3c24xx_uart_info) { 2499 .name = "Samsung S5PV210 UART", 2500 .type = PORT_S3C6400, 2501 .has_divslot = 1, 2502 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2503 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2504 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2505 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2506 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2507 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2508 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2509 .num_clks = 2, 2510 .clksel_mask = S5PV210_UCON_CLKMASK, 2511 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2512 }, 2513 .def_cfg = &(struct s3c2410_uartcfg) { 2514 .ucon = S5PV210_UCON_DEFAULT, 2515 .ufcon = S5PV210_UFCON_DEFAULT, 2516 }, 2517 .fifosize = { 256, 64, 16, 16 }, 2518 }; 2519 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data) 2520 #else 2521 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2522 #endif 2523 2524 #if defined(CONFIG_ARCH_EXYNOS) 2525 #define EXYNOS_COMMON_SERIAL_DRV_DATA \ 2526 .info = &(struct s3c24xx_uart_info) { \ 2527 .name = "Samsung Exynos UART", \ 2528 .type = PORT_S3C6400, \ 2529 .has_divslot = 1, \ 2530 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2531 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2532 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2533 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2534 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2535 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2536 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2537 .num_clks = 1, \ 2538 .clksel_mask = 0, \ 2539 .clksel_shift = 0, \ 2540 }, \ 2541 .def_cfg = &(struct s3c2410_uartcfg) { \ 2542 .ucon = S5PV210_UCON_DEFAULT, \ 2543 .ufcon = S5PV210_UFCON_DEFAULT, \ 2544 .has_fracval = 1, \ 2545 } \ 2546 2547 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2548 EXYNOS_COMMON_SERIAL_DRV_DATA, 2549 .fifosize = { 256, 64, 16, 16 }, 2550 }; 2551 2552 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2553 EXYNOS_COMMON_SERIAL_DRV_DATA, 2554 .fifosize = { 64, 256, 16, 256 }, 2555 }; 2556 2557 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) 2558 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) 2559 #else 2560 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2561 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL 2562 #endif 2563 2564 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2565 { 2566 .name = "s3c2410-uart", 2567 .driver_data = S3C2410_SERIAL_DRV_DATA, 2568 }, { 2569 .name = "s3c2412-uart", 2570 .driver_data = S3C2412_SERIAL_DRV_DATA, 2571 }, { 2572 .name = "s3c2440-uart", 2573 .driver_data = S3C2440_SERIAL_DRV_DATA, 2574 }, { 2575 .name = "s3c6400-uart", 2576 .driver_data = S3C6400_SERIAL_DRV_DATA, 2577 }, { 2578 .name = "s5pv210-uart", 2579 .driver_data = S5PV210_SERIAL_DRV_DATA, 2580 }, { 2581 .name = "exynos4210-uart", 2582 .driver_data = EXYNOS4210_SERIAL_DRV_DATA, 2583 }, { 2584 .name = "exynos5433-uart", 2585 .driver_data = EXYNOS5433_SERIAL_DRV_DATA, 2586 }, 2587 { }, 2588 }; 2589 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2590 2591 #ifdef CONFIG_OF 2592 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2593 { .compatible = "samsung,s3c2410-uart", 2594 .data = (void *)S3C2410_SERIAL_DRV_DATA }, 2595 { .compatible = "samsung,s3c2412-uart", 2596 .data = (void *)S3C2412_SERIAL_DRV_DATA }, 2597 { .compatible = "samsung,s3c2440-uart", 2598 .data = (void *)S3C2440_SERIAL_DRV_DATA }, 2599 { .compatible = "samsung,s3c6400-uart", 2600 .data = (void *)S3C6400_SERIAL_DRV_DATA }, 2601 { .compatible = "samsung,s5pv210-uart", 2602 .data = (void *)S5PV210_SERIAL_DRV_DATA }, 2603 { .compatible = "samsung,exynos4210-uart", 2604 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, 2605 { .compatible = "samsung,exynos5433-uart", 2606 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, 2607 {}, 2608 }; 2609 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2610 #endif 2611 2612 static struct platform_driver samsung_serial_driver = { 2613 .probe = s3c24xx_serial_probe, 2614 .remove = s3c24xx_serial_remove, 2615 .id_table = s3c24xx_serial_driver_ids, 2616 .driver = { 2617 .name = "samsung-uart", 2618 .pm = SERIAL_SAMSUNG_PM_OPS, 2619 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2620 }, 2621 }; 2622 2623 module_platform_driver(samsung_serial_driver); 2624 2625 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2626 /* 2627 * Early console. 2628 */ 2629 2630 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) 2631 { 2632 switch (port->iotype) { 2633 case UPIO_MEM: 2634 writeb(val, portaddr(port, reg)); 2635 break; 2636 case UPIO_MEM32: 2637 writel(val, portaddr(port, reg)); 2638 break; 2639 } 2640 } 2641 2642 struct samsung_early_console_data { 2643 u32 txfull_mask; 2644 }; 2645 2646 static void samsung_early_busyuart(struct uart_port *port) 2647 { 2648 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2649 ; 2650 } 2651 2652 static void samsung_early_busyuart_fifo(struct uart_port *port) 2653 { 2654 struct samsung_early_console_data *data = port->private_data; 2655 2656 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 2657 ; 2658 } 2659 2660 static void samsung_early_putc(struct uart_port *port, int c) 2661 { 2662 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 2663 samsung_early_busyuart_fifo(port); 2664 else 2665 samsung_early_busyuart(port); 2666 2667 wr_reg_barrier(port, S3C2410_UTXH, c); 2668 } 2669 2670 static void samsung_early_write(struct console *con, const char *s, 2671 unsigned int n) 2672 { 2673 struct earlycon_device *dev = con->data; 2674 2675 uart_console_write(&dev->port, s, n, samsung_early_putc); 2676 } 2677 2678 static int __init samsung_early_console_setup(struct earlycon_device *device, 2679 const char *opt) 2680 { 2681 if (!device->port.membase) 2682 return -ENODEV; 2683 2684 device->con->write = samsung_early_write; 2685 return 0; 2686 } 2687 2688 /* S3C2410 */ 2689 static struct samsung_early_console_data s3c2410_early_console_data = { 2690 .txfull_mask = S3C2410_UFSTAT_TXFULL, 2691 }; 2692 2693 static int __init s3c2410_early_console_setup(struct earlycon_device *device, 2694 const char *opt) 2695 { 2696 device->port.private_data = &s3c2410_early_console_data; 2697 return samsung_early_console_setup(device, opt); 2698 } 2699 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", 2700 s3c2410_early_console_setup); 2701 2702 /* S3C2412, S3C2440, S3C64xx */ 2703 static struct samsung_early_console_data s3c2440_early_console_data = { 2704 .txfull_mask = S3C2440_UFSTAT_TXFULL, 2705 }; 2706 2707 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 2708 const char *opt) 2709 { 2710 device->port.private_data = &s3c2440_early_console_data; 2711 return samsung_early_console_setup(device, opt); 2712 } 2713 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart", 2714 s3c2440_early_console_setup); 2715 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", 2716 s3c2440_early_console_setup); 2717 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 2718 s3c2440_early_console_setup); 2719 2720 /* S5PV210, Exynos */ 2721 static struct samsung_early_console_data s5pv210_early_console_data = { 2722 .txfull_mask = S5PV210_UFSTAT_TXFULL, 2723 }; 2724 2725 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 2726 const char *opt) 2727 { 2728 device->port.private_data = &s5pv210_early_console_data; 2729 return samsung_early_console_setup(device, opt); 2730 } 2731 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 2732 s5pv210_early_console_setup); 2733 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 2734 s5pv210_early_console_setup); 2735 #endif 2736 2737 MODULE_ALIAS("platform:samsung-uart"); 2738 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 2739 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 2740 MODULE_LICENSE("GPL v2"); 2741