1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver core for Samsung SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 */ 8 9 /* Note on 2410 error handling 10 * 11 * The s3c2410 manual has a love/hate affair with the contents of the 12 * UERSTAT register in the UART blocks, and keeps marking some of the 13 * error bits as reserved. Having checked with the s3c2410x01, 14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED 15 * feature from the latter versions of the manual. 16 * 17 * If it becomes aparrent that latter versions of the 2410 remove these 18 * bits, then action will have to be taken to differentiate the versions 19 * and change the policy on BREAK 20 * 21 * BJD, 04-Nov-2004 22 */ 23 24 #include <linux/dmaengine.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/ioport.h> 29 #include <linux/io.h> 30 #include <linux/platform_device.h> 31 #include <linux/init.h> 32 #include <linux/sysrq.h> 33 #include <linux/console.h> 34 #include <linux/tty.h> 35 #include <linux/tty_flip.h> 36 #include <linux/serial_core.h> 37 #include <linux/serial.h> 38 #include <linux/serial_s3c.h> 39 #include <linux/delay.h> 40 #include <linux/clk.h> 41 #include <linux/cpufreq.h> 42 #include <linux/of.h> 43 #include <asm/irq.h> 44 45 /* UART name and device definitions */ 46 47 #define S3C24XX_SERIAL_NAME "ttySAC" 48 #define S3C24XX_SERIAL_MAJOR 204 49 #define S3C24XX_SERIAL_MINOR 64 50 51 #define S3C24XX_TX_PIO 1 52 #define S3C24XX_TX_DMA 2 53 #define S3C24XX_RX_PIO 1 54 #define S3C24XX_RX_DMA 2 55 56 /* flag to ignore all characters coming in */ 57 #define RXSTAT_DUMMY_READ (0x10000000) 58 59 enum s3c24xx_port_type { 60 TYPE_S3C24XX, 61 TYPE_S3C6400, 62 TYPE_APPLE_S5L, 63 }; 64 65 struct s3c24xx_uart_info { 66 const char *name; 67 enum s3c24xx_port_type type; 68 unsigned int port_type; 69 unsigned int fifosize; 70 unsigned long rx_fifomask; 71 unsigned long rx_fifoshift; 72 unsigned long rx_fifofull; 73 unsigned long tx_fifomask; 74 unsigned long tx_fifoshift; 75 unsigned long tx_fifofull; 76 unsigned int def_clk_sel; 77 unsigned long num_clks; 78 unsigned long clksel_mask; 79 unsigned long clksel_shift; 80 unsigned long ucon_mask; 81 82 /* uart port features */ 83 84 unsigned int has_divslot:1; 85 }; 86 87 struct s3c24xx_serial_drv_data { 88 const struct s3c24xx_uart_info info; 89 const struct s3c2410_uartcfg def_cfg; 90 const unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; 91 }; 92 93 struct s3c24xx_uart_dma { 94 unsigned int rx_chan_id; 95 unsigned int tx_chan_id; 96 97 struct dma_slave_config rx_conf; 98 struct dma_slave_config tx_conf; 99 100 struct dma_chan *rx_chan; 101 struct dma_chan *tx_chan; 102 103 dma_addr_t rx_addr; 104 dma_addr_t tx_addr; 105 106 dma_cookie_t rx_cookie; 107 dma_cookie_t tx_cookie; 108 109 char *rx_buf; 110 111 dma_addr_t tx_transfer_addr; 112 113 size_t rx_size; 114 size_t tx_size; 115 116 struct dma_async_tx_descriptor *tx_desc; 117 struct dma_async_tx_descriptor *rx_desc; 118 119 int tx_bytes_requested; 120 int rx_bytes_requested; 121 }; 122 123 struct s3c24xx_uart_port { 124 unsigned char rx_claimed; 125 unsigned char tx_claimed; 126 unsigned char rx_enabled; 127 unsigned char tx_enabled; 128 unsigned int pm_level; 129 unsigned long baudclk_rate; 130 unsigned int min_dma_size; 131 132 unsigned int rx_irq; 133 unsigned int tx_irq; 134 135 unsigned int tx_in_progress; 136 unsigned int tx_mode; 137 unsigned int rx_mode; 138 139 const struct s3c24xx_uart_info *info; 140 struct clk *clk; 141 struct clk *baudclk; 142 struct uart_port port; 143 const struct s3c24xx_serial_drv_data *drv_data; 144 145 /* reference to platform data */ 146 const struct s3c2410_uartcfg *cfg; 147 148 struct s3c24xx_uart_dma *dma; 149 150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 151 struct notifier_block freq_transition; 152 #endif 153 }; 154 155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport); 156 157 /* conversion functions */ 158 159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev) 160 161 /* register access controls */ 162 163 #define portaddr(port, reg) ((port)->membase + (reg)) 164 #define portaddrl(port, reg) \ 165 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 166 167 static u32 rd_reg(const struct uart_port *port, u32 reg) 168 { 169 switch (port->iotype) { 170 case UPIO_MEM: 171 return readb_relaxed(portaddr(port, reg)); 172 case UPIO_MEM32: 173 return readl_relaxed(portaddr(port, reg)); 174 default: 175 return 0; 176 } 177 return 0; 178 } 179 180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) 181 182 static void wr_reg(const struct uart_port *port, u32 reg, u32 val) 183 { 184 switch (port->iotype) { 185 case UPIO_MEM: 186 writeb_relaxed(val, portaddr(port, reg)); 187 break; 188 case UPIO_MEM32: 189 writel_relaxed(val, portaddr(port, reg)); 190 break; 191 } 192 } 193 194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) 195 196 /* Byte-order aware bit setting/clearing functions. */ 197 198 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx, 199 unsigned int reg) 200 { 201 unsigned long flags; 202 u32 val; 203 204 local_irq_save(flags); 205 val = rd_regl(port, reg); 206 val |= (1 << idx); 207 wr_regl(port, reg, val); 208 local_irq_restore(flags); 209 } 210 211 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx, 212 unsigned int reg) 213 { 214 unsigned long flags; 215 u32 val; 216 217 local_irq_save(flags); 218 val = rd_regl(port, reg); 219 val &= ~(1 << idx); 220 wr_regl(port, reg, val); 221 local_irq_restore(flags); 222 } 223 224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) 225 { 226 return container_of(port, struct s3c24xx_uart_port, port); 227 } 228 229 /* translate a port to the device name */ 230 231 static inline const char *s3c24xx_serial_portname(const struct uart_port *port) 232 { 233 return to_platform_device(port->dev)->name; 234 } 235 236 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port) 237 { 238 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; 239 } 240 241 static void s3c24xx_serial_rx_enable(struct uart_port *port) 242 { 243 struct s3c24xx_uart_port *ourport = to_ourport(port); 244 unsigned long flags; 245 unsigned int ucon, ufcon; 246 int count = 10000; 247 248 spin_lock_irqsave(&port->lock, flags); 249 250 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 251 udelay(100); 252 253 ufcon = rd_regl(port, S3C2410_UFCON); 254 ufcon |= S3C2410_UFCON_RESETRX; 255 wr_regl(port, S3C2410_UFCON, ufcon); 256 257 ucon = rd_regl(port, S3C2410_UCON); 258 ucon |= S3C2410_UCON_RXIRQMODE; 259 wr_regl(port, S3C2410_UCON, ucon); 260 261 ourport->rx_enabled = 1; 262 spin_unlock_irqrestore(&port->lock, flags); 263 } 264 265 static void s3c24xx_serial_rx_disable(struct uart_port *port) 266 { 267 struct s3c24xx_uart_port *ourport = to_ourport(port); 268 unsigned long flags; 269 unsigned int ucon; 270 271 spin_lock_irqsave(&port->lock, flags); 272 273 ucon = rd_regl(port, S3C2410_UCON); 274 ucon &= ~S3C2410_UCON_RXIRQMODE; 275 wr_regl(port, S3C2410_UCON, ucon); 276 277 ourport->rx_enabled = 0; 278 spin_unlock_irqrestore(&port->lock, flags); 279 } 280 281 static void s3c24xx_serial_stop_tx(struct uart_port *port) 282 { 283 struct s3c24xx_uart_port *ourport = to_ourport(port); 284 struct s3c24xx_uart_dma *dma = ourport->dma; 285 struct circ_buf *xmit = &port->state->xmit; 286 struct dma_tx_state state; 287 int count; 288 289 if (!ourport->tx_enabled) 290 return; 291 292 switch (ourport->info->type) { 293 case TYPE_S3C6400: 294 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 295 break; 296 case TYPE_APPLE_S5L: 297 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON); 298 break; 299 default: 300 disable_irq_nosync(ourport->tx_irq); 301 break; 302 } 303 304 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { 305 dmaengine_pause(dma->tx_chan); 306 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 307 dmaengine_terminate_all(dma->tx_chan); 308 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 309 dma->tx_transfer_addr, dma->tx_size, 310 DMA_TO_DEVICE); 311 async_tx_ack(dma->tx_desc); 312 count = dma->tx_bytes_requested - state.residue; 313 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 314 port->icount.tx += count; 315 } 316 317 ourport->tx_enabled = 0; 318 ourport->tx_in_progress = 0; 319 320 if (port->flags & UPF_CONS_FLOW) 321 s3c24xx_serial_rx_enable(port); 322 323 ourport->tx_mode = 0; 324 } 325 326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); 327 328 static void s3c24xx_serial_tx_dma_complete(void *args) 329 { 330 struct s3c24xx_uart_port *ourport = args; 331 struct uart_port *port = &ourport->port; 332 struct circ_buf *xmit = &port->state->xmit; 333 struct s3c24xx_uart_dma *dma = ourport->dma; 334 struct dma_tx_state state; 335 unsigned long flags; 336 int count; 337 338 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); 339 count = dma->tx_bytes_requested - state.residue; 340 async_tx_ack(dma->tx_desc); 341 342 dma_sync_single_for_cpu(dma->tx_chan->device->dev, 343 dma->tx_transfer_addr, dma->tx_size, 344 DMA_TO_DEVICE); 345 346 spin_lock_irqsave(&port->lock, flags); 347 348 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 349 port->icount.tx += count; 350 ourport->tx_in_progress = 0; 351 352 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 353 uart_write_wakeup(port); 354 355 s3c24xx_serial_start_next_tx(ourport); 356 spin_unlock_irqrestore(&port->lock, flags); 357 } 358 359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) 360 { 361 const struct uart_port *port = &ourport->port; 362 u32 ucon; 363 364 /* Mask Tx interrupt */ 365 switch (ourport->info->type) { 366 case TYPE_S3C6400: 367 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); 368 break; 369 case TYPE_APPLE_S5L: 370 WARN_ON(1); // No DMA 371 break; 372 default: 373 disable_irq_nosync(ourport->tx_irq); 374 break; 375 } 376 377 /* Enable tx dma mode */ 378 ucon = rd_regl(port, S3C2410_UCON); 379 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); 380 ucon |= S3C64XX_UCON_TXBURST_1; 381 ucon |= S3C64XX_UCON_TXMODE_DMA; 382 wr_regl(port, S3C2410_UCON, ucon); 383 384 ourport->tx_mode = S3C24XX_TX_DMA; 385 } 386 387 static void enable_tx_pio(struct s3c24xx_uart_port *ourport) 388 { 389 const struct uart_port *port = &ourport->port; 390 u32 ucon, ufcon; 391 392 /* Set ufcon txtrig */ 393 ourport->tx_in_progress = S3C24XX_TX_PIO; 394 ufcon = rd_regl(port, S3C2410_UFCON); 395 wr_regl(port, S3C2410_UFCON, ufcon); 396 397 /* Enable tx pio mode */ 398 ucon = rd_regl(port, S3C2410_UCON); 399 ucon &= ~(S3C64XX_UCON_TXMODE_MASK); 400 ucon |= S3C64XX_UCON_TXMODE_CPU; 401 wr_regl(port, S3C2410_UCON, ucon); 402 403 /* Unmask Tx interrupt */ 404 switch (ourport->info->type) { 405 case TYPE_S3C6400: 406 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, 407 S3C64XX_UINTM); 408 break; 409 case TYPE_APPLE_S5L: 410 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 411 wr_regl(port, S3C2410_UCON, ucon); 412 break; 413 default: 414 enable_irq(ourport->tx_irq); 415 break; 416 } 417 418 ourport->tx_mode = S3C24XX_TX_PIO; 419 420 /* 421 * The Apple version only has edge triggered TX IRQs, so we need 422 * to kick off the process by sending some characters here. 423 */ 424 if (ourport->info->type == TYPE_APPLE_S5L) 425 s3c24xx_serial_tx_chars(ourport); 426 } 427 428 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) 429 { 430 if (ourport->tx_mode != S3C24XX_TX_PIO) 431 enable_tx_pio(ourport); 432 } 433 434 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, 435 unsigned int count) 436 { 437 struct uart_port *port = &ourport->port; 438 struct circ_buf *xmit = &port->state->xmit; 439 struct s3c24xx_uart_dma *dma = ourport->dma; 440 441 if (ourport->tx_mode != S3C24XX_TX_DMA) 442 enable_tx_dma(ourport); 443 444 dma->tx_size = count & ~(dma_get_cache_alignment() - 1); 445 dma->tx_transfer_addr = dma->tx_addr + xmit->tail; 446 447 dma_sync_single_for_device(dma->tx_chan->device->dev, 448 dma->tx_transfer_addr, dma->tx_size, 449 DMA_TO_DEVICE); 450 451 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, 452 dma->tx_transfer_addr, dma->tx_size, 453 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 454 if (!dma->tx_desc) { 455 dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); 456 return -EIO; 457 } 458 459 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; 460 dma->tx_desc->callback_param = ourport; 461 dma->tx_bytes_requested = dma->tx_size; 462 463 ourport->tx_in_progress = S3C24XX_TX_DMA; 464 dma->tx_cookie = dmaengine_submit(dma->tx_desc); 465 dma_async_issue_pending(dma->tx_chan); 466 return 0; 467 } 468 469 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) 470 { 471 struct uart_port *port = &ourport->port; 472 struct circ_buf *xmit = &port->state->xmit; 473 unsigned long count; 474 475 /* Get data size up to the end of buffer */ 476 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 477 478 if (!count) { 479 s3c24xx_serial_stop_tx(port); 480 return; 481 } 482 483 if (!ourport->dma || !ourport->dma->tx_chan || 484 count < ourport->min_dma_size || 485 xmit->tail & (dma_get_cache_alignment() - 1)) 486 s3c24xx_serial_start_tx_pio(ourport); 487 else 488 s3c24xx_serial_start_tx_dma(ourport, count); 489 } 490 491 static void s3c24xx_serial_start_tx(struct uart_port *port) 492 { 493 struct s3c24xx_uart_port *ourport = to_ourport(port); 494 struct circ_buf *xmit = &port->state->xmit; 495 496 if (!ourport->tx_enabled) { 497 if (port->flags & UPF_CONS_FLOW) 498 s3c24xx_serial_rx_disable(port); 499 500 ourport->tx_enabled = 1; 501 if (!ourport->dma || !ourport->dma->tx_chan) 502 s3c24xx_serial_start_tx_pio(ourport); 503 } 504 505 if (ourport->dma && ourport->dma->tx_chan) { 506 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) 507 s3c24xx_serial_start_next_tx(ourport); 508 } 509 } 510 511 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, 512 struct tty_port *tty, int count) 513 { 514 struct s3c24xx_uart_dma *dma = ourport->dma; 515 int copied; 516 517 if (!count) 518 return; 519 520 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr, 521 dma->rx_size, DMA_FROM_DEVICE); 522 523 ourport->port.icount.rx += count; 524 if (!tty) { 525 dev_err(ourport->port.dev, "No tty port\n"); 526 return; 527 } 528 copied = tty_insert_flip_string(tty, 529 ((unsigned char *)(ourport->dma->rx_buf)), count); 530 if (copied != count) { 531 WARN_ON(1); 532 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); 533 } 534 } 535 536 static void s3c24xx_serial_stop_rx(struct uart_port *port) 537 { 538 struct s3c24xx_uart_port *ourport = to_ourport(port); 539 struct s3c24xx_uart_dma *dma = ourport->dma; 540 struct tty_port *t = &port->state->port; 541 struct dma_tx_state state; 542 enum dma_status dma_status; 543 unsigned int received; 544 545 if (ourport->rx_enabled) { 546 dev_dbg(port->dev, "stopping rx\n"); 547 switch (ourport->info->type) { 548 case TYPE_S3C6400: 549 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, 550 S3C64XX_UINTM); 551 break; 552 case TYPE_APPLE_S5L: 553 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 554 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 555 break; 556 default: 557 disable_irq_nosync(ourport->rx_irq); 558 break; 559 } 560 ourport->rx_enabled = 0; 561 } 562 if (dma && dma->rx_chan) { 563 dmaengine_pause(dma->tx_chan); 564 dma_status = dmaengine_tx_status(dma->rx_chan, 565 dma->rx_cookie, &state); 566 if (dma_status == DMA_IN_PROGRESS || 567 dma_status == DMA_PAUSED) { 568 received = dma->rx_bytes_requested - state.residue; 569 dmaengine_terminate_all(dma->rx_chan); 570 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 571 } 572 } 573 } 574 575 static inline const struct s3c24xx_uart_info 576 *s3c24xx_port_to_info(struct uart_port *port) 577 { 578 return to_ourport(port)->info; 579 } 580 581 static inline const struct s3c2410_uartcfg 582 *s3c24xx_port_to_cfg(const struct uart_port *port) 583 { 584 const struct s3c24xx_uart_port *ourport; 585 586 if (port->dev == NULL) 587 return NULL; 588 589 ourport = container_of(port, struct s3c24xx_uart_port, port); 590 return ourport->cfg; 591 } 592 593 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport, 594 unsigned long ufstat) 595 { 596 const struct s3c24xx_uart_info *info = ourport->info; 597 598 if (ufstat & info->rx_fifofull) 599 return ourport->port.fifosize; 600 601 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; 602 } 603 604 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); 605 static void s3c24xx_serial_rx_dma_complete(void *args) 606 { 607 struct s3c24xx_uart_port *ourport = args; 608 struct uart_port *port = &ourport->port; 609 610 struct s3c24xx_uart_dma *dma = ourport->dma; 611 struct tty_port *t = &port->state->port; 612 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 613 614 struct dma_tx_state state; 615 unsigned long flags; 616 int received; 617 618 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 619 received = dma->rx_bytes_requested - state.residue; 620 async_tx_ack(dma->rx_desc); 621 622 spin_lock_irqsave(&port->lock, flags); 623 624 if (received) 625 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 626 627 if (tty) { 628 tty_flip_buffer_push(t); 629 tty_kref_put(tty); 630 } 631 632 s3c64xx_start_rx_dma(ourport); 633 634 spin_unlock_irqrestore(&port->lock, flags); 635 } 636 637 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) 638 { 639 struct s3c24xx_uart_dma *dma = ourport->dma; 640 641 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr, 642 dma->rx_size, DMA_FROM_DEVICE); 643 644 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, 645 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, 646 DMA_PREP_INTERRUPT); 647 if (!dma->rx_desc) { 648 dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); 649 return; 650 } 651 652 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; 653 dma->rx_desc->callback_param = ourport; 654 dma->rx_bytes_requested = dma->rx_size; 655 656 dma->rx_cookie = dmaengine_submit(dma->rx_desc); 657 dma_async_issue_pending(dma->rx_chan); 658 } 659 660 /* ? - where has parity gone?? */ 661 #define S3C2410_UERSTAT_PARITY (0x1000) 662 663 static void enable_rx_dma(struct s3c24xx_uart_port *ourport) 664 { 665 struct uart_port *port = &ourport->port; 666 unsigned int ucon; 667 668 /* set Rx mode to DMA mode */ 669 ucon = rd_regl(port, S3C2410_UCON); 670 ucon &= ~(S3C64XX_UCON_RXBURST_MASK | 671 S3C64XX_UCON_TIMEOUT_MASK | 672 S3C64XX_UCON_EMPTYINT_EN | 673 S3C64XX_UCON_DMASUS_EN | 674 S3C64XX_UCON_TIMEOUT_EN | 675 S3C64XX_UCON_RXMODE_MASK); 676 ucon |= S3C64XX_UCON_RXBURST_1 | 677 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 678 S3C64XX_UCON_EMPTYINT_EN | 679 S3C64XX_UCON_TIMEOUT_EN | 680 S3C64XX_UCON_RXMODE_DMA; 681 wr_regl(port, S3C2410_UCON, ucon); 682 683 ourport->rx_mode = S3C24XX_RX_DMA; 684 } 685 686 static void enable_rx_pio(struct s3c24xx_uart_port *ourport) 687 { 688 struct uart_port *port = &ourport->port; 689 unsigned int ucon; 690 691 /* set Rx mode to DMA mode */ 692 ucon = rd_regl(port, S3C2410_UCON); 693 ucon &= ~S3C64XX_UCON_RXMODE_MASK; 694 ucon |= S3C64XX_UCON_RXMODE_CPU; 695 696 /* Apple types use these bits for IRQ masks */ 697 if (ourport->info->type != TYPE_APPLE_S5L) { 698 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | 699 S3C64XX_UCON_EMPTYINT_EN | 700 S3C64XX_UCON_DMASUS_EN | 701 S3C64XX_UCON_TIMEOUT_EN); 702 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | 703 S3C64XX_UCON_TIMEOUT_EN; 704 } 705 wr_regl(port, S3C2410_UCON, ucon); 706 707 ourport->rx_mode = S3C24XX_RX_PIO; 708 } 709 710 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); 711 712 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) 713 { 714 unsigned int utrstat, received; 715 struct s3c24xx_uart_port *ourport = dev_id; 716 struct uart_port *port = &ourport->port; 717 struct s3c24xx_uart_dma *dma = ourport->dma; 718 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); 719 struct tty_port *t = &port->state->port; 720 struct dma_tx_state state; 721 722 utrstat = rd_regl(port, S3C2410_UTRSTAT); 723 rd_regl(port, S3C2410_UFSTAT); 724 725 spin_lock(&port->lock); 726 727 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 728 s3c64xx_start_rx_dma(ourport); 729 if (ourport->rx_mode == S3C24XX_RX_PIO) 730 enable_rx_dma(ourport); 731 goto finish; 732 } 733 734 if (ourport->rx_mode == S3C24XX_RX_DMA) { 735 dmaengine_pause(dma->rx_chan); 736 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); 737 dmaengine_terminate_all(dma->rx_chan); 738 received = dma->rx_bytes_requested - state.residue; 739 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); 740 741 enable_rx_pio(ourport); 742 } 743 744 s3c24xx_serial_rx_drain_fifo(ourport); 745 746 if (tty) { 747 tty_flip_buffer_push(t); 748 tty_kref_put(tty); 749 } 750 751 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 752 753 finish: 754 spin_unlock(&port->lock); 755 756 return IRQ_HANDLED; 757 } 758 759 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) 760 { 761 struct uart_port *port = &ourport->port; 762 unsigned int ufcon, ch, flag, ufstat, uerstat; 763 unsigned int fifocnt = 0; 764 int max_count = port->fifosize; 765 766 while (max_count-- > 0) { 767 /* 768 * Receive all characters known to be in FIFO 769 * before reading FIFO level again 770 */ 771 if (fifocnt == 0) { 772 ufstat = rd_regl(port, S3C2410_UFSTAT); 773 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); 774 if (fifocnt == 0) 775 break; 776 } 777 fifocnt--; 778 779 uerstat = rd_regl(port, S3C2410_UERSTAT); 780 ch = rd_reg(port, S3C2410_URXH); 781 782 if (port->flags & UPF_CONS_FLOW) { 783 int txe = s3c24xx_serial_txempty_nofifo(port); 784 785 if (ourport->rx_enabled) { 786 if (!txe) { 787 ourport->rx_enabled = 0; 788 continue; 789 } 790 } else { 791 if (txe) { 792 ufcon = rd_regl(port, S3C2410_UFCON); 793 ufcon |= S3C2410_UFCON_RESETRX; 794 wr_regl(port, S3C2410_UFCON, ufcon); 795 ourport->rx_enabled = 1; 796 return; 797 } 798 continue; 799 } 800 } 801 802 /* insert the character into the buffer */ 803 804 flag = TTY_NORMAL; 805 port->icount.rx++; 806 807 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { 808 dev_dbg(port->dev, 809 "rxerr: port ch=0x%02x, rxs=0x%08x\n", 810 ch, uerstat); 811 812 /* check for break */ 813 if (uerstat & S3C2410_UERSTAT_BREAK) { 814 dev_dbg(port->dev, "break!\n"); 815 port->icount.brk++; 816 if (uart_handle_break(port)) 817 continue; /* Ignore character */ 818 } 819 820 if (uerstat & S3C2410_UERSTAT_FRAME) 821 port->icount.frame++; 822 if (uerstat & S3C2410_UERSTAT_OVERRUN) 823 port->icount.overrun++; 824 825 uerstat &= port->read_status_mask; 826 827 if (uerstat & S3C2410_UERSTAT_BREAK) 828 flag = TTY_BREAK; 829 else if (uerstat & S3C2410_UERSTAT_PARITY) 830 flag = TTY_PARITY; 831 else if (uerstat & (S3C2410_UERSTAT_FRAME | 832 S3C2410_UERSTAT_OVERRUN)) 833 flag = TTY_FRAME; 834 } 835 836 if (uart_handle_sysrq_char(port, ch)) 837 continue; /* Ignore character */ 838 839 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, 840 ch, flag); 841 } 842 843 tty_flip_buffer_push(&port->state->port); 844 } 845 846 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) 847 { 848 struct s3c24xx_uart_port *ourport = dev_id; 849 struct uart_port *port = &ourport->port; 850 851 spin_lock(&port->lock); 852 s3c24xx_serial_rx_drain_fifo(ourport); 853 spin_unlock(&port->lock); 854 855 return IRQ_HANDLED; 856 } 857 858 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id) 859 { 860 struct s3c24xx_uart_port *ourport = dev_id; 861 862 if (ourport->dma && ourport->dma->rx_chan) 863 return s3c24xx_serial_rx_chars_dma(dev_id); 864 return s3c24xx_serial_rx_chars_pio(dev_id); 865 } 866 867 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport) 868 { 869 struct uart_port *port = &ourport->port; 870 struct circ_buf *xmit = &port->state->xmit; 871 int count, dma_count = 0; 872 873 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 874 875 if (ourport->dma && ourport->dma->tx_chan && 876 count >= ourport->min_dma_size) { 877 int align = dma_get_cache_alignment() - 878 (xmit->tail & (dma_get_cache_alignment() - 1)); 879 if (count - align >= ourport->min_dma_size) { 880 dma_count = count - align; 881 count = align; 882 } 883 } 884 885 if (port->x_char) { 886 wr_reg(port, S3C2410_UTXH, port->x_char); 887 port->icount.tx++; 888 port->x_char = 0; 889 return; 890 } 891 892 /* if there isn't anything more to transmit, or the uart is now 893 * stopped, disable the uart and exit 894 */ 895 896 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 897 s3c24xx_serial_stop_tx(port); 898 return; 899 } 900 901 /* try and drain the buffer... */ 902 903 if (count > port->fifosize) { 904 count = port->fifosize; 905 dma_count = 0; 906 } 907 908 while (!uart_circ_empty(xmit) && count > 0) { 909 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) 910 break; 911 912 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); 913 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 914 port->icount.tx++; 915 count--; 916 } 917 918 if (!count && dma_count) { 919 s3c24xx_serial_start_tx_dma(ourport, dma_count); 920 return; 921 } 922 923 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 924 uart_write_wakeup(port); 925 926 if (uart_circ_empty(xmit)) 927 s3c24xx_serial_stop_tx(port); 928 } 929 930 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id) 931 { 932 struct s3c24xx_uart_port *ourport = id; 933 struct uart_port *port = &ourport->port; 934 935 spin_lock(&port->lock); 936 937 s3c24xx_serial_tx_chars(ourport); 938 939 spin_unlock(&port->lock); 940 return IRQ_HANDLED; 941 } 942 943 /* interrupt handler for s3c64xx and later SoC's.*/ 944 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) 945 { 946 const struct s3c24xx_uart_port *ourport = id; 947 const struct uart_port *port = &ourport->port; 948 unsigned int pend = rd_regl(port, S3C64XX_UINTP); 949 irqreturn_t ret = IRQ_HANDLED; 950 951 if (pend & S3C64XX_UINTM_RXD_MSK) { 952 ret = s3c24xx_serial_rx_irq(irq, id); 953 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); 954 } 955 if (pend & S3C64XX_UINTM_TXD_MSK) { 956 ret = s3c24xx_serial_tx_irq(irq, id); 957 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); 958 } 959 return ret; 960 } 961 962 /* interrupt handler for Apple SoC's.*/ 963 static irqreturn_t apple_serial_handle_irq(int irq, void *id) 964 { 965 const struct s3c24xx_uart_port *ourport = id; 966 const struct uart_port *port = &ourport->port; 967 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT); 968 irqreturn_t ret = IRQ_NONE; 969 970 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) { 971 wr_regl(port, S3C2410_UTRSTAT, 972 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO); 973 ret = s3c24xx_serial_rx_irq(irq, id); 974 } 975 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) { 976 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH); 977 ret = s3c24xx_serial_tx_irq(irq, id); 978 } 979 980 return ret; 981 } 982 983 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) 984 { 985 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 986 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); 987 unsigned long ufcon = rd_regl(port, S3C2410_UFCON); 988 989 if (ufcon & S3C2410_UFCON_FIFOMODE) { 990 if ((ufstat & info->tx_fifomask) != 0 || 991 (ufstat & info->tx_fifofull)) 992 return 0; 993 994 return 1; 995 } 996 997 return s3c24xx_serial_txempty_nofifo(port); 998 } 999 1000 /* no modem control lines */ 1001 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) 1002 { 1003 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); 1004 1005 if (umstat & S3C2410_UMSTAT_CTS) 1006 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1007 else 1008 return TIOCM_CAR | TIOCM_DSR; 1009 } 1010 1011 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 1012 { 1013 unsigned int umcon = rd_regl(port, S3C2410_UMCON); 1014 1015 if (mctrl & TIOCM_RTS) 1016 umcon |= S3C2410_UMCOM_RTS_LOW; 1017 else 1018 umcon &= ~S3C2410_UMCOM_RTS_LOW; 1019 1020 wr_regl(port, S3C2410_UMCON, umcon); 1021 } 1022 1023 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) 1024 { 1025 unsigned long flags; 1026 unsigned int ucon; 1027 1028 spin_lock_irqsave(&port->lock, flags); 1029 1030 ucon = rd_regl(port, S3C2410_UCON); 1031 1032 if (break_state) 1033 ucon |= S3C2410_UCON_SBREAK; 1034 else 1035 ucon &= ~S3C2410_UCON_SBREAK; 1036 1037 wr_regl(port, S3C2410_UCON, ucon); 1038 1039 spin_unlock_irqrestore(&port->lock, flags); 1040 } 1041 1042 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) 1043 { 1044 struct s3c24xx_uart_dma *dma = p->dma; 1045 struct dma_slave_caps dma_caps; 1046 const char *reason = NULL; 1047 int ret; 1048 1049 /* Default slave configuration parameters */ 1050 dma->rx_conf.direction = DMA_DEV_TO_MEM; 1051 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1052 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; 1053 dma->rx_conf.src_maxburst = 1; 1054 1055 dma->tx_conf.direction = DMA_MEM_TO_DEV; 1056 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1057 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; 1058 dma->tx_conf.dst_maxburst = 1; 1059 1060 dma->rx_chan = dma_request_chan(p->port.dev, "rx"); 1061 1062 if (IS_ERR(dma->rx_chan)) { 1063 reason = "DMA RX channel request failed"; 1064 ret = PTR_ERR(dma->rx_chan); 1065 goto err_warn; 1066 } 1067 1068 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); 1069 if (ret < 0 || 1070 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1071 reason = "insufficient DMA RX engine capabilities"; 1072 ret = -EOPNOTSUPP; 1073 goto err_release_rx; 1074 } 1075 1076 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); 1077 1078 dma->tx_chan = dma_request_chan(p->port.dev, "tx"); 1079 if (IS_ERR(dma->tx_chan)) { 1080 reason = "DMA TX channel request failed"; 1081 ret = PTR_ERR(dma->tx_chan); 1082 goto err_release_rx; 1083 } 1084 1085 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); 1086 if (ret < 0 || 1087 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { 1088 reason = "insufficient DMA TX engine capabilities"; 1089 ret = -EOPNOTSUPP; 1090 goto err_release_tx; 1091 } 1092 1093 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); 1094 1095 /* RX buffer */ 1096 dma->rx_size = PAGE_SIZE; 1097 1098 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); 1099 if (!dma->rx_buf) { 1100 ret = -ENOMEM; 1101 goto err_release_tx; 1102 } 1103 1104 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf, 1105 dma->rx_size, DMA_FROM_DEVICE); 1106 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) { 1107 reason = "DMA mapping error for RX buffer"; 1108 ret = -EIO; 1109 goto err_free_rx; 1110 } 1111 1112 /* TX buffer */ 1113 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev, 1114 p->port.state->xmit.buf, UART_XMIT_SIZE, 1115 DMA_TO_DEVICE); 1116 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) { 1117 reason = "DMA mapping error for TX buffer"; 1118 ret = -EIO; 1119 goto err_unmap_rx; 1120 } 1121 1122 return 0; 1123 1124 err_unmap_rx: 1125 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1126 dma->rx_size, DMA_FROM_DEVICE); 1127 err_free_rx: 1128 kfree(dma->rx_buf); 1129 err_release_tx: 1130 dma_release_channel(dma->tx_chan); 1131 err_release_rx: 1132 dma_release_channel(dma->rx_chan); 1133 err_warn: 1134 if (reason) 1135 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); 1136 return ret; 1137 } 1138 1139 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) 1140 { 1141 struct s3c24xx_uart_dma *dma = p->dma; 1142 1143 if (dma->rx_chan) { 1144 dmaengine_terminate_all(dma->rx_chan); 1145 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr, 1146 dma->rx_size, DMA_FROM_DEVICE); 1147 kfree(dma->rx_buf); 1148 dma_release_channel(dma->rx_chan); 1149 dma->rx_chan = NULL; 1150 } 1151 1152 if (dma->tx_chan) { 1153 dmaengine_terminate_all(dma->tx_chan); 1154 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr, 1155 UART_XMIT_SIZE, DMA_TO_DEVICE); 1156 dma_release_channel(dma->tx_chan); 1157 dma->tx_chan = NULL; 1158 } 1159 } 1160 1161 static void s3c24xx_serial_shutdown(struct uart_port *port) 1162 { 1163 struct s3c24xx_uart_port *ourport = to_ourport(port); 1164 1165 if (ourport->tx_claimed) { 1166 free_irq(ourport->tx_irq, ourport); 1167 ourport->tx_enabled = 0; 1168 ourport->tx_claimed = 0; 1169 ourport->tx_mode = 0; 1170 } 1171 1172 if (ourport->rx_claimed) { 1173 free_irq(ourport->rx_irq, ourport); 1174 ourport->rx_claimed = 0; 1175 ourport->rx_enabled = 0; 1176 } 1177 1178 if (ourport->dma) 1179 s3c24xx_serial_release_dma(ourport); 1180 1181 ourport->tx_in_progress = 0; 1182 } 1183 1184 static void s3c64xx_serial_shutdown(struct uart_port *port) 1185 { 1186 struct s3c24xx_uart_port *ourport = to_ourport(port); 1187 1188 ourport->tx_enabled = 0; 1189 ourport->tx_mode = 0; 1190 ourport->rx_enabled = 0; 1191 1192 free_irq(port->irq, ourport); 1193 1194 wr_regl(port, S3C64XX_UINTP, 0xf); 1195 wr_regl(port, S3C64XX_UINTM, 0xf); 1196 1197 if (ourport->dma) 1198 s3c24xx_serial_release_dma(ourport); 1199 1200 ourport->tx_in_progress = 0; 1201 } 1202 1203 static void apple_s5l_serial_shutdown(struct uart_port *port) 1204 { 1205 struct s3c24xx_uart_port *ourport = to_ourport(port); 1206 1207 unsigned int ucon; 1208 1209 ucon = rd_regl(port, S3C2410_UCON); 1210 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 1211 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 1212 APPLE_S5L_UCON_RXTO_ENA_MSK); 1213 wr_regl(port, S3C2410_UCON, ucon); 1214 1215 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1216 1217 free_irq(port->irq, ourport); 1218 1219 ourport->tx_enabled = 0; 1220 ourport->tx_mode = 0; 1221 ourport->rx_enabled = 0; 1222 1223 if (ourport->dma) 1224 s3c24xx_serial_release_dma(ourport); 1225 1226 ourport->tx_in_progress = 0; 1227 } 1228 1229 static int s3c24xx_serial_startup(struct uart_port *port) 1230 { 1231 struct s3c24xx_uart_port *ourport = to_ourport(port); 1232 int ret; 1233 1234 ourport->rx_enabled = 1; 1235 1236 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0, 1237 s3c24xx_serial_portname(port), ourport); 1238 1239 if (ret != 0) { 1240 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); 1241 return ret; 1242 } 1243 1244 ourport->rx_claimed = 1; 1245 1246 dev_dbg(port->dev, "requesting tx irq...\n"); 1247 1248 ourport->tx_enabled = 1; 1249 1250 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0, 1251 s3c24xx_serial_portname(port), ourport); 1252 1253 if (ret) { 1254 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); 1255 goto err; 1256 } 1257 1258 ourport->tx_claimed = 1; 1259 1260 /* the port reset code should have done the correct 1261 * register setup for the port controls 1262 */ 1263 1264 return ret; 1265 1266 err: 1267 s3c24xx_serial_shutdown(port); 1268 return ret; 1269 } 1270 1271 static int s3c64xx_serial_startup(struct uart_port *port) 1272 { 1273 struct s3c24xx_uart_port *ourport = to_ourport(port); 1274 unsigned long flags; 1275 unsigned int ufcon; 1276 int ret; 1277 1278 wr_regl(port, S3C64XX_UINTM, 0xf); 1279 if (ourport->dma) { 1280 ret = s3c24xx_serial_request_dma(ourport); 1281 if (ret < 0) { 1282 devm_kfree(port->dev, ourport->dma); 1283 ourport->dma = NULL; 1284 } 1285 } 1286 1287 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 1288 s3c24xx_serial_portname(port), ourport); 1289 if (ret) { 1290 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1291 return ret; 1292 } 1293 1294 /* For compatibility with s3c24xx Soc's */ 1295 ourport->rx_enabled = 1; 1296 ourport->tx_enabled = 0; 1297 1298 spin_lock_irqsave(&port->lock, flags); 1299 1300 ufcon = rd_regl(port, S3C2410_UFCON); 1301 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1302 if (!uart_console(port)) 1303 ufcon |= S3C2410_UFCON_RESETTX; 1304 wr_regl(port, S3C2410_UFCON, ufcon); 1305 1306 enable_rx_pio(ourport); 1307 1308 spin_unlock_irqrestore(&port->lock, flags); 1309 1310 /* Enable Rx Interrupt */ 1311 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); 1312 1313 return ret; 1314 } 1315 1316 static int apple_s5l_serial_startup(struct uart_port *port) 1317 { 1318 struct s3c24xx_uart_port *ourport = to_ourport(port); 1319 unsigned long flags; 1320 unsigned int ufcon; 1321 int ret; 1322 1323 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 1324 1325 ret = request_irq(port->irq, apple_serial_handle_irq, 0, 1326 s3c24xx_serial_portname(port), ourport); 1327 if (ret) { 1328 dev_err(port->dev, "cannot get irq %d\n", port->irq); 1329 return ret; 1330 } 1331 1332 /* For compatibility with s3c24xx Soc's */ 1333 ourport->rx_enabled = 1; 1334 ourport->tx_enabled = 0; 1335 1336 spin_lock_irqsave(&port->lock, flags); 1337 1338 ufcon = rd_regl(port, S3C2410_UFCON); 1339 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; 1340 if (!uart_console(port)) 1341 ufcon |= S3C2410_UFCON_RESETTX; 1342 wr_regl(port, S3C2410_UFCON, ufcon); 1343 1344 enable_rx_pio(ourport); 1345 1346 spin_unlock_irqrestore(&port->lock, flags); 1347 1348 /* Enable Rx Interrupt */ 1349 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); 1350 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON); 1351 1352 return ret; 1353 } 1354 1355 /* power power management control */ 1356 1357 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, 1358 unsigned int old) 1359 { 1360 struct s3c24xx_uart_port *ourport = to_ourport(port); 1361 int timeout = 10000; 1362 1363 ourport->pm_level = level; 1364 1365 switch (level) { 1366 case 3: 1367 while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) 1368 udelay(100); 1369 1370 if (!IS_ERR(ourport->baudclk)) 1371 clk_disable_unprepare(ourport->baudclk); 1372 1373 clk_disable_unprepare(ourport->clk); 1374 break; 1375 1376 case 0: 1377 clk_prepare_enable(ourport->clk); 1378 1379 if (!IS_ERR(ourport->baudclk)) 1380 clk_prepare_enable(ourport->baudclk); 1381 break; 1382 default: 1383 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); 1384 } 1385 } 1386 1387 /* baud rate calculation 1388 * 1389 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number 1390 * of different sources, including the peripheral clock ("pclk") and an 1391 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") 1392 * with a programmable extra divisor. 1393 * 1394 * The following code goes through the clock sources, and calculates the 1395 * baud clocks (and the resultant actual baud rates) and then tries to 1396 * pick the closest one and select that. 1397 * 1398 */ 1399 1400 #define MAX_CLK_NAME_LENGTH 15 1401 1402 static inline int s3c24xx_serial_getsource(struct uart_port *port) 1403 { 1404 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1405 unsigned int ucon; 1406 1407 if (info->num_clks == 1) 1408 return 0; 1409 1410 ucon = rd_regl(port, S3C2410_UCON); 1411 ucon &= info->clksel_mask; 1412 return ucon >> info->clksel_shift; 1413 } 1414 1415 static void s3c24xx_serial_setsource(struct uart_port *port, 1416 unsigned int clk_sel) 1417 { 1418 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1419 unsigned int ucon; 1420 1421 if (info->num_clks == 1) 1422 return; 1423 1424 ucon = rd_regl(port, S3C2410_UCON); 1425 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) 1426 return; 1427 1428 ucon &= ~info->clksel_mask; 1429 ucon |= clk_sel << info->clksel_shift; 1430 wr_regl(port, S3C2410_UCON, ucon); 1431 } 1432 1433 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, 1434 unsigned int req_baud, struct clk **best_clk, 1435 unsigned int *clk_num) 1436 { 1437 const struct s3c24xx_uart_info *info = ourport->info; 1438 struct clk *clk; 1439 unsigned long rate; 1440 unsigned int cnt, baud, quot, best_quot = 0; 1441 char clkname[MAX_CLK_NAME_LENGTH]; 1442 int calc_deviation, deviation = (1 << 30) - 1; 1443 1444 for (cnt = 0; cnt < info->num_clks; cnt++) { 1445 /* Keep selected clock if provided */ 1446 if (ourport->cfg->clk_sel && 1447 !(ourport->cfg->clk_sel & (1 << cnt))) 1448 continue; 1449 1450 sprintf(clkname, "clk_uart_baud%d", cnt); 1451 clk = clk_get(ourport->port.dev, clkname); 1452 if (IS_ERR(clk)) 1453 continue; 1454 1455 rate = clk_get_rate(clk); 1456 if (!rate) 1457 continue; 1458 1459 if (ourport->info->has_divslot) { 1460 unsigned long div = rate / req_baud; 1461 1462 /* The UDIVSLOT register on the newer UARTs allows us to 1463 * get a divisor adjustment of 1/16th on the baud clock. 1464 * 1465 * We don't keep the UDIVSLOT value (the 16ths we 1466 * calculated by not multiplying the baud by 16) as it 1467 * is easy enough to recalculate. 1468 */ 1469 1470 quot = div / 16; 1471 baud = rate / div; 1472 } else { 1473 quot = (rate + (8 * req_baud)) / (16 * req_baud); 1474 baud = rate / (quot * 16); 1475 } 1476 quot--; 1477 1478 calc_deviation = req_baud - baud; 1479 if (calc_deviation < 0) 1480 calc_deviation = -calc_deviation; 1481 1482 if (calc_deviation < deviation) { 1483 *best_clk = clk; 1484 best_quot = quot; 1485 *clk_num = cnt; 1486 deviation = calc_deviation; 1487 } 1488 } 1489 1490 return best_quot; 1491 } 1492 1493 /* udivslot_table[] 1494 * 1495 * This table takes the fractional value of the baud divisor and gives 1496 * the recommended setting for the UDIVSLOT register. 1497 */ 1498 static const u16 udivslot_table[16] = { 1499 [0] = 0x0000, 1500 [1] = 0x0080, 1501 [2] = 0x0808, 1502 [3] = 0x0888, 1503 [4] = 0x2222, 1504 [5] = 0x4924, 1505 [6] = 0x4A52, 1506 [7] = 0x54AA, 1507 [8] = 0x5555, 1508 [9] = 0xD555, 1509 [10] = 0xD5D5, 1510 [11] = 0xDDD5, 1511 [12] = 0xDDDD, 1512 [13] = 0xDFDD, 1513 [14] = 0xDFDF, 1514 [15] = 0xFFDF, 1515 }; 1516 1517 static void s3c24xx_serial_set_termios(struct uart_port *port, 1518 struct ktermios *termios, 1519 struct ktermios *old) 1520 { 1521 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 1522 struct s3c24xx_uart_port *ourport = to_ourport(port); 1523 struct clk *clk = ERR_PTR(-EINVAL); 1524 unsigned long flags; 1525 unsigned int baud, quot, clk_sel = 0; 1526 unsigned int ulcon; 1527 unsigned int umcon; 1528 unsigned int udivslot = 0; 1529 1530 /* 1531 * We don't support modem control lines. 1532 */ 1533 termios->c_cflag &= ~(HUPCL | CMSPAR); 1534 termios->c_cflag |= CLOCAL; 1535 1536 /* 1537 * Ask the core to calculate the divisor for us. 1538 */ 1539 1540 baud = uart_get_baud_rate(port, termios, old, 0, 3000000); 1541 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 1542 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 1543 quot = port->custom_divisor; 1544 if (IS_ERR(clk)) 1545 return; 1546 1547 /* check to see if we need to change clock source */ 1548 1549 if (ourport->baudclk != clk) { 1550 clk_prepare_enable(clk); 1551 1552 s3c24xx_serial_setsource(port, clk_sel); 1553 1554 if (!IS_ERR(ourport->baudclk)) { 1555 clk_disable_unprepare(ourport->baudclk); 1556 ourport->baudclk = ERR_PTR(-EINVAL); 1557 } 1558 1559 ourport->baudclk = clk; 1560 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; 1561 } 1562 1563 if (ourport->info->has_divslot) { 1564 unsigned int div = ourport->baudclk_rate / baud; 1565 1566 if (cfg->has_fracval) { 1567 udivslot = (div & 15); 1568 dev_dbg(port->dev, "fracval = %04x\n", udivslot); 1569 } else { 1570 udivslot = udivslot_table[div & 15]; 1571 dev_dbg(port->dev, "udivslot = %04x (div %d)\n", 1572 udivslot, div & 15); 1573 } 1574 } 1575 1576 switch (termios->c_cflag & CSIZE) { 1577 case CS5: 1578 dev_dbg(port->dev, "config: 5bits/char\n"); 1579 ulcon = S3C2410_LCON_CS5; 1580 break; 1581 case CS6: 1582 dev_dbg(port->dev, "config: 6bits/char\n"); 1583 ulcon = S3C2410_LCON_CS6; 1584 break; 1585 case CS7: 1586 dev_dbg(port->dev, "config: 7bits/char\n"); 1587 ulcon = S3C2410_LCON_CS7; 1588 break; 1589 case CS8: 1590 default: 1591 dev_dbg(port->dev, "config: 8bits/char\n"); 1592 ulcon = S3C2410_LCON_CS8; 1593 break; 1594 } 1595 1596 /* preserve original lcon IR settings */ 1597 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); 1598 1599 if (termios->c_cflag & CSTOPB) 1600 ulcon |= S3C2410_LCON_STOPB; 1601 1602 if (termios->c_cflag & PARENB) { 1603 if (termios->c_cflag & PARODD) 1604 ulcon |= S3C2410_LCON_PODD; 1605 else 1606 ulcon |= S3C2410_LCON_PEVEN; 1607 } else { 1608 ulcon |= S3C2410_LCON_PNONE; 1609 } 1610 1611 spin_lock_irqsave(&port->lock, flags); 1612 1613 dev_dbg(port->dev, 1614 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1615 ulcon, quot, udivslot); 1616 1617 wr_regl(port, S3C2410_ULCON, ulcon); 1618 wr_regl(port, S3C2410_UBRDIV, quot); 1619 1620 port->status &= ~UPSTAT_AUTOCTS; 1621 1622 umcon = rd_regl(port, S3C2410_UMCON); 1623 if (termios->c_cflag & CRTSCTS) { 1624 umcon |= S3C2410_UMCOM_AFC; 1625 /* Disable RTS when RX FIFO contains 63 bytes */ 1626 umcon &= ~S3C2412_UMCON_AFC_8; 1627 port->status = UPSTAT_AUTOCTS; 1628 } else { 1629 umcon &= ~S3C2410_UMCOM_AFC; 1630 } 1631 wr_regl(port, S3C2410_UMCON, umcon); 1632 1633 if (ourport->info->has_divslot) 1634 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1635 1636 dev_dbg(port->dev, 1637 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1638 rd_regl(port, S3C2410_ULCON), 1639 rd_regl(port, S3C2410_UCON), 1640 rd_regl(port, S3C2410_UFCON)); 1641 1642 /* 1643 * Update the per-port timeout. 1644 */ 1645 uart_update_timeout(port, termios->c_cflag, baud); 1646 1647 /* 1648 * Which character status flags are we interested in? 1649 */ 1650 port->read_status_mask = S3C2410_UERSTAT_OVERRUN; 1651 if (termios->c_iflag & INPCK) 1652 port->read_status_mask |= S3C2410_UERSTAT_FRAME | 1653 S3C2410_UERSTAT_PARITY; 1654 /* 1655 * Which character status flags should we ignore? 1656 */ 1657 port->ignore_status_mask = 0; 1658 if (termios->c_iflag & IGNPAR) 1659 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; 1660 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) 1661 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; 1662 1663 /* 1664 * Ignore all characters if CREAD is not set. 1665 */ 1666 if ((termios->c_cflag & CREAD) == 0) 1667 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1668 1669 spin_unlock_irqrestore(&port->lock, flags); 1670 } 1671 1672 static const char *s3c24xx_serial_type(struct uart_port *port) 1673 { 1674 const struct s3c24xx_uart_port *ourport = to_ourport(port); 1675 1676 switch (ourport->info->type) { 1677 case TYPE_S3C24XX: 1678 return "S3C24XX"; 1679 case TYPE_S3C6400: 1680 return "S3C6400/10"; 1681 case TYPE_APPLE_S5L: 1682 return "APPLE S5L"; 1683 default: 1684 return NULL; 1685 } 1686 } 1687 1688 static void s3c24xx_serial_config_port(struct uart_port *port, int flags) 1689 { 1690 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1691 1692 if (flags & UART_CONFIG_TYPE) 1693 port->type = info->port_type; 1694 } 1695 1696 /* 1697 * verify the new serial_struct (for TIOCSSERIAL). 1698 */ 1699 static int 1700 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 1701 { 1702 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1703 1704 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type) 1705 return -EINVAL; 1706 1707 return 0; 1708 } 1709 1710 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 1711 1712 static struct console s3c24xx_serial_console; 1713 1714 static void __init s3c24xx_serial_register_console(void) 1715 { 1716 register_console(&s3c24xx_serial_console); 1717 } 1718 1719 static void s3c24xx_serial_unregister_console(void) 1720 { 1721 if (s3c24xx_serial_console.flags & CON_ENABLED) 1722 unregister_console(&s3c24xx_serial_console); 1723 } 1724 1725 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console 1726 #else 1727 static inline void s3c24xx_serial_register_console(void) { } 1728 static inline void s3c24xx_serial_unregister_console(void) { } 1729 #define S3C24XX_SERIAL_CONSOLE NULL 1730 #endif 1731 1732 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1733 static int s3c24xx_serial_get_poll_char(struct uart_port *port); 1734 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1735 unsigned char c); 1736 #endif 1737 1738 static const struct uart_ops s3c24xx_serial_ops = { 1739 .pm = s3c24xx_serial_pm, 1740 .tx_empty = s3c24xx_serial_tx_empty, 1741 .get_mctrl = s3c24xx_serial_get_mctrl, 1742 .set_mctrl = s3c24xx_serial_set_mctrl, 1743 .stop_tx = s3c24xx_serial_stop_tx, 1744 .start_tx = s3c24xx_serial_start_tx, 1745 .stop_rx = s3c24xx_serial_stop_rx, 1746 .break_ctl = s3c24xx_serial_break_ctl, 1747 .startup = s3c24xx_serial_startup, 1748 .shutdown = s3c24xx_serial_shutdown, 1749 .set_termios = s3c24xx_serial_set_termios, 1750 .type = s3c24xx_serial_type, 1751 .config_port = s3c24xx_serial_config_port, 1752 .verify_port = s3c24xx_serial_verify_port, 1753 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1754 .poll_get_char = s3c24xx_serial_get_poll_char, 1755 .poll_put_char = s3c24xx_serial_put_poll_char, 1756 #endif 1757 }; 1758 1759 static const struct uart_ops s3c64xx_serial_ops = { 1760 .pm = s3c24xx_serial_pm, 1761 .tx_empty = s3c24xx_serial_tx_empty, 1762 .get_mctrl = s3c24xx_serial_get_mctrl, 1763 .set_mctrl = s3c24xx_serial_set_mctrl, 1764 .stop_tx = s3c24xx_serial_stop_tx, 1765 .start_tx = s3c24xx_serial_start_tx, 1766 .stop_rx = s3c24xx_serial_stop_rx, 1767 .break_ctl = s3c24xx_serial_break_ctl, 1768 .startup = s3c64xx_serial_startup, 1769 .shutdown = s3c64xx_serial_shutdown, 1770 .set_termios = s3c24xx_serial_set_termios, 1771 .type = s3c24xx_serial_type, 1772 .config_port = s3c24xx_serial_config_port, 1773 .verify_port = s3c24xx_serial_verify_port, 1774 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1775 .poll_get_char = s3c24xx_serial_get_poll_char, 1776 .poll_put_char = s3c24xx_serial_put_poll_char, 1777 #endif 1778 }; 1779 1780 static const struct uart_ops apple_s5l_serial_ops = { 1781 .pm = s3c24xx_serial_pm, 1782 .tx_empty = s3c24xx_serial_tx_empty, 1783 .get_mctrl = s3c24xx_serial_get_mctrl, 1784 .set_mctrl = s3c24xx_serial_set_mctrl, 1785 .stop_tx = s3c24xx_serial_stop_tx, 1786 .start_tx = s3c24xx_serial_start_tx, 1787 .stop_rx = s3c24xx_serial_stop_rx, 1788 .break_ctl = s3c24xx_serial_break_ctl, 1789 .startup = apple_s5l_serial_startup, 1790 .shutdown = apple_s5l_serial_shutdown, 1791 .set_termios = s3c24xx_serial_set_termios, 1792 .type = s3c24xx_serial_type, 1793 .config_port = s3c24xx_serial_config_port, 1794 .verify_port = s3c24xx_serial_verify_port, 1795 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1796 .poll_get_char = s3c24xx_serial_get_poll_char, 1797 .poll_put_char = s3c24xx_serial_put_poll_char, 1798 #endif 1799 }; 1800 1801 static struct uart_driver s3c24xx_uart_drv = { 1802 .owner = THIS_MODULE, 1803 .driver_name = "s3c2410_serial", 1804 .nr = CONFIG_SERIAL_SAMSUNG_UARTS, 1805 .cons = S3C24XX_SERIAL_CONSOLE, 1806 .dev_name = S3C24XX_SERIAL_NAME, 1807 .major = S3C24XX_SERIAL_MAJOR, 1808 .minor = S3C24XX_SERIAL_MINOR, 1809 }; 1810 1811 #define __PORT_LOCK_UNLOCKED(i) \ 1812 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock) 1813 static struct s3c24xx_uart_port 1814 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { 1815 [0] = { 1816 .port = { 1817 .lock = __PORT_LOCK_UNLOCKED(0), 1818 .iotype = UPIO_MEM, 1819 .uartclk = 0, 1820 .fifosize = 16, 1821 .ops = &s3c24xx_serial_ops, 1822 .flags = UPF_BOOT_AUTOCONF, 1823 .line = 0, 1824 } 1825 }, 1826 [1] = { 1827 .port = { 1828 .lock = __PORT_LOCK_UNLOCKED(1), 1829 .iotype = UPIO_MEM, 1830 .uartclk = 0, 1831 .fifosize = 16, 1832 .ops = &s3c24xx_serial_ops, 1833 .flags = UPF_BOOT_AUTOCONF, 1834 .line = 1, 1835 } 1836 }, 1837 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 1838 [2] = { 1839 .port = { 1840 .lock = __PORT_LOCK_UNLOCKED(2), 1841 .iotype = UPIO_MEM, 1842 .uartclk = 0, 1843 .fifosize = 16, 1844 .ops = &s3c24xx_serial_ops, 1845 .flags = UPF_BOOT_AUTOCONF, 1846 .line = 2, 1847 } 1848 }, 1849 #endif 1850 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 1851 [3] = { 1852 .port = { 1853 .lock = __PORT_LOCK_UNLOCKED(3), 1854 .iotype = UPIO_MEM, 1855 .uartclk = 0, 1856 .fifosize = 16, 1857 .ops = &s3c24xx_serial_ops, 1858 .flags = UPF_BOOT_AUTOCONF, 1859 .line = 3, 1860 } 1861 } 1862 #endif 1863 }; 1864 #undef __PORT_LOCK_UNLOCKED 1865 1866 /* s3c24xx_serial_resetport 1867 * 1868 * reset the fifos and other the settings. 1869 */ 1870 1871 static void s3c24xx_serial_resetport(struct uart_port *port, 1872 const struct s3c2410_uartcfg *cfg) 1873 { 1874 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 1875 unsigned long ucon = rd_regl(port, S3C2410_UCON); 1876 1877 ucon &= (info->clksel_mask | info->ucon_mask); 1878 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 1879 1880 /* reset both fifos */ 1881 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 1882 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 1883 1884 /* some delay is required after fifo reset */ 1885 udelay(1); 1886 } 1887 1888 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 1889 1890 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, 1891 unsigned long val, void *data) 1892 { 1893 struct s3c24xx_uart_port *port; 1894 struct uart_port *uport; 1895 1896 port = container_of(nb, struct s3c24xx_uart_port, freq_transition); 1897 uport = &port->port; 1898 1899 /* check to see if port is enabled */ 1900 1901 if (port->pm_level != 0) 1902 return 0; 1903 1904 /* try and work out if the baudrate is changing, we can detect 1905 * a change in rate, but we do not have support for detecting 1906 * a disturbance in the clock-rate over the change. 1907 */ 1908 1909 if (IS_ERR(port->baudclk)) 1910 goto exit; 1911 1912 if (port->baudclk_rate == clk_get_rate(port->baudclk)) 1913 goto exit; 1914 1915 if (val == CPUFREQ_PRECHANGE) { 1916 /* we should really shut the port down whilst the 1917 * frequency change is in progress. 1918 */ 1919 1920 } else if (val == CPUFREQ_POSTCHANGE) { 1921 struct ktermios *termios; 1922 struct tty_struct *tty; 1923 1924 if (uport->state == NULL) 1925 goto exit; 1926 1927 tty = uport->state->port.tty; 1928 1929 if (tty == NULL) 1930 goto exit; 1931 1932 termios = &tty->termios; 1933 1934 if (termios == NULL) { 1935 dev_warn(uport->dev, "%s: no termios?\n", __func__); 1936 goto exit; 1937 } 1938 1939 s3c24xx_serial_set_termios(uport, termios, NULL); 1940 } 1941 1942 exit: 1943 return 0; 1944 } 1945 1946 static inline int 1947 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1948 { 1949 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; 1950 1951 return cpufreq_register_notifier(&port->freq_transition, 1952 CPUFREQ_TRANSITION_NOTIFIER); 1953 } 1954 1955 static inline void 1956 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1957 { 1958 cpufreq_unregister_notifier(&port->freq_transition, 1959 CPUFREQ_TRANSITION_NOTIFIER); 1960 } 1961 1962 #else 1963 static inline int 1964 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) 1965 { 1966 return 0; 1967 } 1968 1969 static inline void 1970 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) 1971 { 1972 } 1973 #endif 1974 1975 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport) 1976 { 1977 struct device *dev = ourport->port.dev; 1978 const struct s3c24xx_uart_info *info = ourport->info; 1979 char clk_name[MAX_CLK_NAME_LENGTH]; 1980 unsigned int clk_sel; 1981 struct clk *clk; 1982 int clk_num; 1983 int ret; 1984 1985 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; 1986 for (clk_num = 0; clk_num < info->num_clks; clk_num++) { 1987 if (!(clk_sel & (1 << clk_num))) 1988 continue; 1989 1990 sprintf(clk_name, "clk_uart_baud%d", clk_num); 1991 clk = clk_get(dev, clk_name); 1992 if (IS_ERR(clk)) 1993 continue; 1994 1995 ret = clk_prepare_enable(clk); 1996 if (ret) { 1997 clk_put(clk); 1998 continue; 1999 } 2000 2001 ourport->baudclk = clk; 2002 ourport->baudclk_rate = clk_get_rate(clk); 2003 s3c24xx_serial_setsource(&ourport->port, clk_num); 2004 2005 return 0; 2006 } 2007 2008 return -EINVAL; 2009 } 2010 2011 /* s3c24xx_serial_init_port 2012 * 2013 * initialise a single serial port from the platform device given 2014 */ 2015 2016 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, 2017 struct platform_device *platdev) 2018 { 2019 struct uart_port *port = &ourport->port; 2020 const struct s3c2410_uartcfg *cfg = ourport->cfg; 2021 struct resource *res; 2022 int ret; 2023 2024 if (platdev == NULL) 2025 return -ENODEV; 2026 2027 if (port->mapbase != 0) 2028 return -EINVAL; 2029 2030 /* setup info for port */ 2031 port->dev = &platdev->dev; 2032 2033 port->uartclk = 1; 2034 2035 if (cfg->uart_flags & UPF_CONS_FLOW) { 2036 dev_dbg(port->dev, "enabling flow control\n"); 2037 port->flags |= UPF_CONS_FLOW; 2038 } 2039 2040 /* sort our the physical and virtual addresses for each UART */ 2041 2042 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 2043 if (res == NULL) { 2044 dev_err(port->dev, "failed to find memory resource for uart\n"); 2045 return -EINVAL; 2046 } 2047 2048 dev_dbg(port->dev, "resource %pR)\n", res); 2049 2050 port->membase = devm_ioremap_resource(port->dev, res); 2051 if (IS_ERR(port->membase)) { 2052 dev_err(port->dev, "failed to remap controller address\n"); 2053 return -EBUSY; 2054 } 2055 2056 port->mapbase = res->start; 2057 ret = platform_get_irq(platdev, 0); 2058 if (ret < 0) { 2059 port->irq = 0; 2060 } else { 2061 port->irq = ret; 2062 ourport->rx_irq = ret; 2063 ourport->tx_irq = ret + 1; 2064 } 2065 2066 switch (ourport->info->type) { 2067 case TYPE_S3C24XX: 2068 ret = platform_get_irq(platdev, 1); 2069 if (ret > 0) 2070 ourport->tx_irq = ret; 2071 break; 2072 default: 2073 break; 2074 } 2075 2076 /* 2077 * DMA is currently supported only on DT platforms, if DMA properties 2078 * are specified. 2079 */ 2080 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, 2081 "dmas", NULL)) { 2082 ourport->dma = devm_kzalloc(port->dev, 2083 sizeof(*ourport->dma), 2084 GFP_KERNEL); 2085 if (!ourport->dma) { 2086 ret = -ENOMEM; 2087 goto err; 2088 } 2089 } 2090 2091 ourport->clk = clk_get(&platdev->dev, "uart"); 2092 if (IS_ERR(ourport->clk)) { 2093 pr_err("%s: Controller clock not found\n", 2094 dev_name(&platdev->dev)); 2095 ret = PTR_ERR(ourport->clk); 2096 goto err; 2097 } 2098 2099 ret = clk_prepare_enable(ourport->clk); 2100 if (ret) { 2101 pr_err("uart: clock failed to prepare+enable: %d\n", ret); 2102 clk_put(ourport->clk); 2103 goto err; 2104 } 2105 2106 ret = s3c24xx_serial_enable_baudclk(ourport); 2107 if (ret) 2108 pr_warn("uart: failed to enable baudclk\n"); 2109 2110 /* Keep all interrupts masked and cleared */ 2111 switch (ourport->info->type) { 2112 case TYPE_S3C6400: 2113 wr_regl(port, S3C64XX_UINTM, 0xf); 2114 wr_regl(port, S3C64XX_UINTP, 0xf); 2115 wr_regl(port, S3C64XX_UINTSP, 0xf); 2116 break; 2117 case TYPE_APPLE_S5L: { 2118 unsigned int ucon; 2119 2120 ucon = rd_regl(port, S3C2410_UCON); 2121 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2122 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2123 APPLE_S5L_UCON_RXTO_ENA_MSK); 2124 wr_regl(port, S3C2410_UCON, ucon); 2125 2126 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS); 2127 break; 2128 } 2129 default: 2130 break; 2131 } 2132 2133 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", 2134 &port->mapbase, port->membase, port->irq, 2135 ourport->rx_irq, ourport->tx_irq, port->uartclk); 2136 2137 /* reset the fifos (and setup the uart) */ 2138 s3c24xx_serial_resetport(port, cfg); 2139 2140 return 0; 2141 2142 err: 2143 port->mapbase = 0; 2144 return ret; 2145 } 2146 2147 /* Device driver serial port probe */ 2148 2149 static int probe_index; 2150 2151 static inline const struct s3c24xx_serial_drv_data * 2152 s3c24xx_get_driver_data(struct platform_device *pdev) 2153 { 2154 if (dev_of_node(&pdev->dev)) 2155 return of_device_get_match_data(&pdev->dev); 2156 2157 return (struct s3c24xx_serial_drv_data *) 2158 platform_get_device_id(pdev)->driver_data; 2159 } 2160 2161 static int s3c24xx_serial_probe(struct platform_device *pdev) 2162 { 2163 struct device_node *np = pdev->dev.of_node; 2164 struct s3c24xx_uart_port *ourport; 2165 int index = probe_index; 2166 int ret, prop = 0; 2167 2168 if (np) { 2169 ret = of_alias_get_id(np, "serial"); 2170 if (ret >= 0) 2171 index = ret; 2172 } 2173 2174 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { 2175 dev_err(&pdev->dev, "serial%d out of range\n", index); 2176 return -EINVAL; 2177 } 2178 ourport = &s3c24xx_serial_ports[index]; 2179 2180 ourport->drv_data = s3c24xx_get_driver_data(pdev); 2181 if (!ourport->drv_data) { 2182 dev_err(&pdev->dev, "could not find driver data\n"); 2183 return -ENODEV; 2184 } 2185 2186 ourport->baudclk = ERR_PTR(-EINVAL); 2187 ourport->info = &ourport->drv_data->info; 2188 ourport->cfg = (dev_get_platdata(&pdev->dev)) ? 2189 dev_get_platdata(&pdev->dev) : 2190 &ourport->drv_data->def_cfg; 2191 2192 switch (ourport->info->type) { 2193 case TYPE_S3C24XX: 2194 ourport->port.ops = &s3c24xx_serial_ops; 2195 break; 2196 case TYPE_S3C6400: 2197 ourport->port.ops = &s3c64xx_serial_ops; 2198 break; 2199 case TYPE_APPLE_S5L: 2200 ourport->port.ops = &apple_s5l_serial_ops; 2201 break; 2202 } 2203 2204 if (np) { 2205 of_property_read_u32(np, 2206 "samsung,uart-fifosize", &ourport->port.fifosize); 2207 2208 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 2209 switch (prop) { 2210 case 1: 2211 ourport->port.iotype = UPIO_MEM; 2212 break; 2213 case 4: 2214 ourport->port.iotype = UPIO_MEM32; 2215 break; 2216 default: 2217 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", 2218 prop); 2219 return -EINVAL; 2220 } 2221 } 2222 } 2223 2224 if (ourport->drv_data->fifosize[index]) 2225 ourport->port.fifosize = ourport->drv_data->fifosize[index]; 2226 else if (ourport->info->fifosize) 2227 ourport->port.fifosize = ourport->info->fifosize; 2228 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE); 2229 2230 /* 2231 * DMA transfers must be aligned at least to cache line size, 2232 * so find minimal transfer size suitable for DMA mode 2233 */ 2234 ourport->min_dma_size = max_t(int, ourport->port.fifosize, 2235 dma_get_cache_alignment()); 2236 2237 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport); 2238 2239 ret = s3c24xx_serial_init_port(ourport, pdev); 2240 if (ret < 0) 2241 return ret; 2242 2243 if (!s3c24xx_uart_drv.state) { 2244 ret = uart_register_driver(&s3c24xx_uart_drv); 2245 if (ret < 0) { 2246 pr_err("Failed to register Samsung UART driver\n"); 2247 return ret; 2248 } 2249 } 2250 2251 dev_dbg(&pdev->dev, "%s: adding port\n", __func__); 2252 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); 2253 platform_set_drvdata(pdev, &ourport->port); 2254 2255 /* 2256 * Deactivate the clock enabled in s3c24xx_serial_init_port here, 2257 * so that a potential re-enablement through the pm-callback overlaps 2258 * and keeps the clock enabled in this case. 2259 */ 2260 clk_disable_unprepare(ourport->clk); 2261 if (!IS_ERR(ourport->baudclk)) 2262 clk_disable_unprepare(ourport->baudclk); 2263 2264 ret = s3c24xx_serial_cpufreq_register(ourport); 2265 if (ret < 0) 2266 dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); 2267 2268 probe_index++; 2269 2270 return 0; 2271 } 2272 2273 static int s3c24xx_serial_remove(struct platform_device *dev) 2274 { 2275 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); 2276 2277 if (port) { 2278 s3c24xx_serial_cpufreq_deregister(to_ourport(port)); 2279 uart_remove_one_port(&s3c24xx_uart_drv, port); 2280 } 2281 2282 uart_unregister_driver(&s3c24xx_uart_drv); 2283 2284 return 0; 2285 } 2286 2287 /* UART power management code */ 2288 #ifdef CONFIG_PM_SLEEP 2289 static int s3c24xx_serial_suspend(struct device *dev) 2290 { 2291 struct uart_port *port = s3c24xx_dev_to_port(dev); 2292 2293 if (port) 2294 uart_suspend_port(&s3c24xx_uart_drv, port); 2295 2296 return 0; 2297 } 2298 2299 static int s3c24xx_serial_resume(struct device *dev) 2300 { 2301 struct uart_port *port = s3c24xx_dev_to_port(dev); 2302 struct s3c24xx_uart_port *ourport = to_ourport(port); 2303 2304 if (port) { 2305 clk_prepare_enable(ourport->clk); 2306 if (!IS_ERR(ourport->baudclk)) 2307 clk_prepare_enable(ourport->baudclk); 2308 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); 2309 if (!IS_ERR(ourport->baudclk)) 2310 clk_disable_unprepare(ourport->baudclk); 2311 clk_disable_unprepare(ourport->clk); 2312 2313 uart_resume_port(&s3c24xx_uart_drv, port); 2314 } 2315 2316 return 0; 2317 } 2318 2319 static int s3c24xx_serial_resume_noirq(struct device *dev) 2320 { 2321 struct uart_port *port = s3c24xx_dev_to_port(dev); 2322 struct s3c24xx_uart_port *ourport = to_ourport(port); 2323 2324 if (port) { 2325 /* restore IRQ mask */ 2326 switch (ourport->info->type) { 2327 case TYPE_S3C6400: { 2328 unsigned int uintm = 0xf; 2329 2330 if (ourport->tx_enabled) 2331 uintm &= ~S3C64XX_UINTM_TXD_MSK; 2332 if (ourport->rx_enabled) 2333 uintm &= ~S3C64XX_UINTM_RXD_MSK; 2334 clk_prepare_enable(ourport->clk); 2335 if (!IS_ERR(ourport->baudclk)) 2336 clk_prepare_enable(ourport->baudclk); 2337 wr_regl(port, S3C64XX_UINTM, uintm); 2338 if (!IS_ERR(ourport->baudclk)) 2339 clk_disable_unprepare(ourport->baudclk); 2340 clk_disable_unprepare(ourport->clk); 2341 break; 2342 } 2343 case TYPE_APPLE_S5L: { 2344 unsigned int ucon; 2345 int ret; 2346 2347 ret = clk_prepare_enable(ourport->clk); 2348 if (ret) { 2349 dev_err(dev, "clk_enable clk failed: %d\n", ret); 2350 return ret; 2351 } 2352 if (!IS_ERR(ourport->baudclk)) { 2353 ret = clk_prepare_enable(ourport->baudclk); 2354 if (ret) { 2355 dev_err(dev, "clk_enable baudclk failed: %d\n", ret); 2356 clk_disable_unprepare(ourport->clk); 2357 return ret; 2358 } 2359 } 2360 2361 ucon = rd_regl(port, S3C2410_UCON); 2362 2363 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK | 2364 APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2365 APPLE_S5L_UCON_RXTO_ENA_MSK); 2366 2367 if (ourport->tx_enabled) 2368 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK; 2369 if (ourport->rx_enabled) 2370 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK | 2371 APPLE_S5L_UCON_RXTO_ENA_MSK; 2372 2373 wr_regl(port, S3C2410_UCON, ucon); 2374 2375 if (!IS_ERR(ourport->baudclk)) 2376 clk_disable_unprepare(ourport->baudclk); 2377 clk_disable_unprepare(ourport->clk); 2378 break; 2379 } 2380 default: 2381 break; 2382 } 2383 } 2384 2385 return 0; 2386 } 2387 2388 static const struct dev_pm_ops s3c24xx_serial_pm_ops = { 2389 .suspend = s3c24xx_serial_suspend, 2390 .resume = s3c24xx_serial_resume, 2391 .resume_noirq = s3c24xx_serial_resume_noirq, 2392 }; 2393 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) 2394 2395 #else /* !CONFIG_PM_SLEEP */ 2396 2397 #define SERIAL_SAMSUNG_PM_OPS NULL 2398 #endif /* CONFIG_PM_SLEEP */ 2399 2400 /* Console code */ 2401 2402 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2403 2404 static struct uart_port *cons_uart; 2405 2406 static int 2407 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) 2408 { 2409 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); 2410 unsigned long ufstat, utrstat; 2411 2412 if (ufcon & S3C2410_UFCON_FIFOMODE) { 2413 /* fifo mode - check amount of data in fifo registers... */ 2414 2415 ufstat = rd_regl(port, S3C2410_UFSTAT); 2416 return (ufstat & info->tx_fifofull) ? 0 : 1; 2417 } 2418 2419 /* in non-fifo mode, we go and use the tx buffer empty */ 2420 2421 utrstat = rd_regl(port, S3C2410_UTRSTAT); 2422 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; 2423 } 2424 2425 static bool 2426 s3c24xx_port_configured(unsigned int ucon) 2427 { 2428 /* consider the serial port configured if the tx/rx mode set */ 2429 return (ucon & 0xf) != 0; 2430 } 2431 2432 #ifdef CONFIG_CONSOLE_POLL 2433 /* 2434 * Console polling routines for writing and reading from the uart while 2435 * in an interrupt or debug context. 2436 */ 2437 2438 static int s3c24xx_serial_get_poll_char(struct uart_port *port) 2439 { 2440 const struct s3c24xx_uart_port *ourport = to_ourport(port); 2441 unsigned int ufstat; 2442 2443 ufstat = rd_regl(port, S3C2410_UFSTAT); 2444 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) 2445 return NO_POLL_CHAR; 2446 2447 return rd_reg(port, S3C2410_URXH); 2448 } 2449 2450 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 2451 unsigned char c) 2452 { 2453 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2454 unsigned int ucon = rd_regl(port, S3C2410_UCON); 2455 2456 /* not possible to xmit on unconfigured port */ 2457 if (!s3c24xx_port_configured(ucon)) 2458 return; 2459 2460 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2461 cpu_relax(); 2462 wr_reg(port, S3C2410_UTXH, c); 2463 } 2464 2465 #endif /* CONFIG_CONSOLE_POLL */ 2466 2467 static void 2468 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch) 2469 { 2470 unsigned int ufcon = rd_regl(port, S3C2410_UFCON); 2471 2472 while (!s3c24xx_serial_console_txrdy(port, ufcon)) 2473 cpu_relax(); 2474 wr_reg(port, S3C2410_UTXH, ch); 2475 } 2476 2477 static void 2478 s3c24xx_serial_console_write(struct console *co, const char *s, 2479 unsigned int count) 2480 { 2481 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); 2482 unsigned long flags; 2483 bool locked = true; 2484 2485 /* not possible to xmit on unconfigured port */ 2486 if (!s3c24xx_port_configured(ucon)) 2487 return; 2488 2489 if (cons_uart->sysrq) 2490 locked = false; 2491 else if (oops_in_progress) 2492 locked = spin_trylock_irqsave(&cons_uart->lock, flags); 2493 else 2494 spin_lock_irqsave(&cons_uart->lock, flags); 2495 2496 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2497 2498 if (locked) 2499 spin_unlock_irqrestore(&cons_uart->lock, flags); 2500 } 2501 2502 /* Shouldn't be __init, as it can be instantiated from other module */ 2503 static void 2504 s3c24xx_serial_get_options(struct uart_port *port, int *baud, 2505 int *parity, int *bits) 2506 { 2507 struct clk *clk; 2508 unsigned int ulcon; 2509 unsigned int ucon; 2510 unsigned int ubrdiv; 2511 unsigned long rate; 2512 unsigned int clk_sel; 2513 char clk_name[MAX_CLK_NAME_LENGTH]; 2514 2515 ulcon = rd_regl(port, S3C2410_ULCON); 2516 ucon = rd_regl(port, S3C2410_UCON); 2517 ubrdiv = rd_regl(port, S3C2410_UBRDIV); 2518 2519 if (s3c24xx_port_configured(ucon)) { 2520 switch (ulcon & S3C2410_LCON_CSMASK) { 2521 case S3C2410_LCON_CS5: 2522 *bits = 5; 2523 break; 2524 case S3C2410_LCON_CS6: 2525 *bits = 6; 2526 break; 2527 case S3C2410_LCON_CS7: 2528 *bits = 7; 2529 break; 2530 case S3C2410_LCON_CS8: 2531 default: 2532 *bits = 8; 2533 break; 2534 } 2535 2536 switch (ulcon & S3C2410_LCON_PMASK) { 2537 case S3C2410_LCON_PEVEN: 2538 *parity = 'e'; 2539 break; 2540 2541 case S3C2410_LCON_PODD: 2542 *parity = 'o'; 2543 break; 2544 2545 case S3C2410_LCON_PNONE: 2546 default: 2547 *parity = 'n'; 2548 } 2549 2550 /* now calculate the baud rate */ 2551 2552 clk_sel = s3c24xx_serial_getsource(port); 2553 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 2554 2555 clk = clk_get(port->dev, clk_name); 2556 if (!IS_ERR(clk)) 2557 rate = clk_get_rate(clk); 2558 else 2559 rate = 1; 2560 2561 *baud = rate / (16 * (ubrdiv + 1)); 2562 dev_dbg(port->dev, "calculated baud %d\n", *baud); 2563 } 2564 } 2565 2566 /* Shouldn't be __init, as it can be instantiated from other module */ 2567 static int 2568 s3c24xx_serial_console_setup(struct console *co, char *options) 2569 { 2570 struct uart_port *port; 2571 int baud = 9600; 2572 int bits = 8; 2573 int parity = 'n'; 2574 int flow = 'n'; 2575 2576 /* is this a valid port */ 2577 2578 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) 2579 co->index = 0; 2580 2581 port = &s3c24xx_serial_ports[co->index].port; 2582 2583 /* is the port configured? */ 2584 2585 if (port->mapbase == 0x0) 2586 return -ENODEV; 2587 2588 cons_uart = port; 2589 2590 /* 2591 * Check whether an invalid uart number has been specified, and 2592 * if so, search for the first available port that does have 2593 * console support. 2594 */ 2595 if (options) 2596 uart_parse_options(options, &baud, &parity, &bits, &flow); 2597 else 2598 s3c24xx_serial_get_options(port, &baud, &parity, &bits); 2599 2600 dev_dbg(port->dev, "baud %d\n", baud); 2601 2602 return uart_set_options(port, co, baud, parity, bits, flow); 2603 } 2604 2605 static struct console s3c24xx_serial_console = { 2606 .name = S3C24XX_SERIAL_NAME, 2607 .device = uart_console_device, 2608 .flags = CON_PRINTBUFFER, 2609 .index = -1, 2610 .write = s3c24xx_serial_console_write, 2611 .setup = s3c24xx_serial_console_setup, 2612 .data = &s3c24xx_uart_drv, 2613 }; 2614 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ 2615 2616 #ifdef CONFIG_CPU_S3C2410 2617 static const struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { 2618 .info = { 2619 .name = "Samsung S3C2410 UART", 2620 .type = TYPE_S3C24XX, 2621 .port_type = PORT_S3C2410, 2622 .fifosize = 16, 2623 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2624 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2625 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2626 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2627 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2628 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2629 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2630 .num_clks = 2, 2631 .clksel_mask = S3C2410_UCON_CLKMASK, 2632 .clksel_shift = S3C2410_UCON_CLKSHIFT, 2633 }, 2634 .def_cfg = { 2635 .ucon = S3C2410_UCON_DEFAULT, 2636 .ufcon = S3C2410_UFCON_DEFAULT, 2637 }, 2638 }; 2639 #define S3C2410_SERIAL_DRV_DATA (&s3c2410_serial_drv_data) 2640 #else 2641 #define S3C2410_SERIAL_DRV_DATA NULL 2642 #endif 2643 2644 #ifdef CONFIG_CPU_S3C2412 2645 static const struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { 2646 .info = { 2647 .name = "Samsung S3C2412 UART", 2648 .type = TYPE_S3C24XX, 2649 .port_type = PORT_S3C2412, 2650 .fifosize = 64, 2651 .has_divslot = 1, 2652 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2653 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2654 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2655 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2656 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2657 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2658 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2659 .num_clks = 4, 2660 .clksel_mask = S3C2412_UCON_CLKMASK, 2661 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2662 }, 2663 .def_cfg = { 2664 .ucon = S3C2410_UCON_DEFAULT, 2665 .ufcon = S3C2410_UFCON_DEFAULT, 2666 }, 2667 }; 2668 #define S3C2412_SERIAL_DRV_DATA (&s3c2412_serial_drv_data) 2669 #else 2670 #define S3C2412_SERIAL_DRV_DATA NULL 2671 #endif 2672 2673 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ 2674 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) 2675 static const struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { 2676 .info = { 2677 .name = "Samsung S3C2440 UART", 2678 .type = TYPE_S3C24XX, 2679 .port_type = PORT_S3C2440, 2680 .fifosize = 64, 2681 .has_divslot = 1, 2682 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2683 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2684 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2685 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2686 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2687 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2688 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2689 .num_clks = 4, 2690 .clksel_mask = S3C2412_UCON_CLKMASK, 2691 .clksel_shift = S3C2412_UCON_CLKSHIFT, 2692 .ucon_mask = S3C2440_UCON0_DIVMASK, 2693 }, 2694 .def_cfg = { 2695 .ucon = S3C2410_UCON_DEFAULT, 2696 .ufcon = S3C2410_UFCON_DEFAULT, 2697 }, 2698 }; 2699 #define S3C2440_SERIAL_DRV_DATA (&s3c2440_serial_drv_data) 2700 #else 2701 #define S3C2440_SERIAL_DRV_DATA NULL 2702 #endif 2703 2704 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 2705 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { 2706 .info = { 2707 .name = "Samsung S3C6400 UART", 2708 .type = TYPE_S3C6400, 2709 .port_type = PORT_S3C6400, 2710 .fifosize = 64, 2711 .has_divslot = 1, 2712 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 2713 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 2714 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 2715 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 2716 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 2717 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 2718 .def_clk_sel = S3C2410_UCON_CLKSEL2, 2719 .num_clks = 4, 2720 .clksel_mask = S3C6400_UCON_CLKMASK, 2721 .clksel_shift = S3C6400_UCON_CLKSHIFT, 2722 }, 2723 .def_cfg = { 2724 .ucon = S3C2410_UCON_DEFAULT, 2725 .ufcon = S3C2410_UFCON_DEFAULT, 2726 }, 2727 }; 2728 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data) 2729 #else 2730 #define S3C6400_SERIAL_DRV_DATA NULL 2731 #endif 2732 2733 #ifdef CONFIG_CPU_S5PV210 2734 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { 2735 .info = { 2736 .name = "Samsung S5PV210 UART", 2737 .type = TYPE_S3C6400, 2738 .port_type = PORT_S3C6400, 2739 .has_divslot = 1, 2740 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2741 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2742 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2743 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2744 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2745 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2746 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2747 .num_clks = 2, 2748 .clksel_mask = S5PV210_UCON_CLKMASK, 2749 .clksel_shift = S5PV210_UCON_CLKSHIFT, 2750 }, 2751 .def_cfg = { 2752 .ucon = S5PV210_UCON_DEFAULT, 2753 .ufcon = S5PV210_UFCON_DEFAULT, 2754 }, 2755 .fifosize = { 256, 64, 16, 16 }, 2756 }; 2757 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data) 2758 #else 2759 #define S5PV210_SERIAL_DRV_DATA NULL 2760 #endif 2761 2762 #if defined(CONFIG_ARCH_EXYNOS) 2763 #define EXYNOS_COMMON_SERIAL_DRV_DATA() \ 2764 .info = { \ 2765 .name = "Samsung Exynos UART", \ 2766 .type = TYPE_S3C6400, \ 2767 .port_type = PORT_S3C6400, \ 2768 .has_divslot = 1, \ 2769 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ 2770 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ 2771 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ 2772 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ 2773 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ 2774 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ 2775 .def_clk_sel = S3C2410_UCON_CLKSEL0, \ 2776 .num_clks = 1, \ 2777 .clksel_mask = 0, \ 2778 .clksel_shift = 0, \ 2779 }, \ 2780 .def_cfg = { \ 2781 .ucon = S5PV210_UCON_DEFAULT, \ 2782 .ufcon = S5PV210_UFCON_DEFAULT, \ 2783 .has_fracval = 1, \ 2784 } \ 2785 2786 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 2787 EXYNOS_COMMON_SERIAL_DRV_DATA(), 2788 .fifosize = { 256, 64, 16, 16 }, 2789 }; 2790 2791 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { 2792 EXYNOS_COMMON_SERIAL_DRV_DATA(), 2793 .fifosize = { 64, 256, 16, 256 }, 2794 }; 2795 2796 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { 2797 EXYNOS_COMMON_SERIAL_DRV_DATA(), 2798 .fifosize = { 256, 64, 64, 64 }, 2799 }; 2800 2801 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) 2802 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) 2803 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) 2804 2805 #else 2806 #define EXYNOS4210_SERIAL_DRV_DATA NULL 2807 #define EXYNOS5433_SERIAL_DRV_DATA NULL 2808 #define EXYNOS850_SERIAL_DRV_DATA NULL 2809 #endif 2810 2811 #ifdef CONFIG_ARCH_APPLE 2812 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { 2813 .info = { 2814 .name = "Apple S5L UART", 2815 .type = TYPE_APPLE_S5L, 2816 .port_type = PORT_8250, 2817 .fifosize = 16, 2818 .rx_fifomask = S3C2410_UFSTAT_RXMASK, 2819 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, 2820 .rx_fifofull = S3C2410_UFSTAT_RXFULL, 2821 .tx_fifofull = S3C2410_UFSTAT_TXFULL, 2822 .tx_fifomask = S3C2410_UFSTAT_TXMASK, 2823 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, 2824 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2825 .num_clks = 1, 2826 .clksel_mask = 0, 2827 .clksel_shift = 0, 2828 .ucon_mask = APPLE_S5L_UCON_MASK, 2829 }, 2830 .def_cfg = { 2831 .ucon = APPLE_S5L_UCON_DEFAULT, 2832 .ufcon = S3C2410_UFCON_DEFAULT, 2833 }, 2834 }; 2835 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data) 2836 #else 2837 #define S5L_SERIAL_DRV_DATA NULL 2838 #endif 2839 2840 #if defined(CONFIG_ARCH_ARTPEC) 2841 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { 2842 .info = { 2843 .name = "Axis ARTPEC-8 UART", 2844 .type = TYPE_S3C6400, 2845 .port_type = PORT_S3C6400, 2846 .fifosize = 64, 2847 .has_divslot = 1, 2848 .rx_fifomask = S5PV210_UFSTAT_RXMASK, 2849 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, 2850 .rx_fifofull = S5PV210_UFSTAT_RXFULL, 2851 .tx_fifofull = S5PV210_UFSTAT_TXFULL, 2852 .tx_fifomask = S5PV210_UFSTAT_TXMASK, 2853 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, 2854 .def_clk_sel = S3C2410_UCON_CLKSEL0, 2855 .num_clks = 1, 2856 .clksel_mask = 0, 2857 .clksel_shift = 0, 2858 }, 2859 .def_cfg = { 2860 .ucon = S5PV210_UCON_DEFAULT, 2861 .ufcon = S5PV210_UFCON_DEFAULT, 2862 .has_fracval = 1, 2863 } 2864 }; 2865 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) 2866 #else 2867 #define ARTPEC8_SERIAL_DRV_DATA (NULL) 2868 #endif 2869 2870 static const struct platform_device_id s3c24xx_serial_driver_ids[] = { 2871 { 2872 .name = "s3c2410-uart", 2873 .driver_data = (kernel_ulong_t)S3C2410_SERIAL_DRV_DATA, 2874 }, { 2875 .name = "s3c2412-uart", 2876 .driver_data = (kernel_ulong_t)S3C2412_SERIAL_DRV_DATA, 2877 }, { 2878 .name = "s3c2440-uart", 2879 .driver_data = (kernel_ulong_t)S3C2440_SERIAL_DRV_DATA, 2880 }, { 2881 .name = "s3c6400-uart", 2882 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA, 2883 }, { 2884 .name = "s5pv210-uart", 2885 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA, 2886 }, { 2887 .name = "exynos4210-uart", 2888 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA, 2889 }, { 2890 .name = "exynos5433-uart", 2891 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA, 2892 }, { 2893 .name = "s5l-uart", 2894 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA, 2895 }, { 2896 .name = "exynos850-uart", 2897 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, 2898 }, { 2899 .name = "artpec8-uart", 2900 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, 2901 }, 2902 { }, 2903 }; 2904 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); 2905 2906 #ifdef CONFIG_OF 2907 static const struct of_device_id s3c24xx_uart_dt_match[] = { 2908 { .compatible = "samsung,s3c2410-uart", 2909 .data = S3C2410_SERIAL_DRV_DATA }, 2910 { .compatible = "samsung,s3c2412-uart", 2911 .data = S3C2412_SERIAL_DRV_DATA }, 2912 { .compatible = "samsung,s3c2440-uart", 2913 .data = S3C2440_SERIAL_DRV_DATA }, 2914 { .compatible = "samsung,s3c6400-uart", 2915 .data = S3C6400_SERIAL_DRV_DATA }, 2916 { .compatible = "samsung,s5pv210-uart", 2917 .data = S5PV210_SERIAL_DRV_DATA }, 2918 { .compatible = "samsung,exynos4210-uart", 2919 .data = EXYNOS4210_SERIAL_DRV_DATA }, 2920 { .compatible = "samsung,exynos5433-uart", 2921 .data = EXYNOS5433_SERIAL_DRV_DATA }, 2922 { .compatible = "apple,s5l-uart", 2923 .data = S5L_SERIAL_DRV_DATA }, 2924 { .compatible = "samsung,exynos850-uart", 2925 .data = EXYNOS850_SERIAL_DRV_DATA }, 2926 { .compatible = "axis,artpec8-uart", 2927 .data = ARTPEC8_SERIAL_DRV_DATA }, 2928 {}, 2929 }; 2930 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); 2931 #endif 2932 2933 static struct platform_driver samsung_serial_driver = { 2934 .probe = s3c24xx_serial_probe, 2935 .remove = s3c24xx_serial_remove, 2936 .id_table = s3c24xx_serial_driver_ids, 2937 .driver = { 2938 .name = "samsung-uart", 2939 .pm = SERIAL_SAMSUNG_PM_OPS, 2940 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), 2941 }, 2942 }; 2943 2944 static int __init samsung_serial_init(void) 2945 { 2946 int ret; 2947 2948 s3c24xx_serial_register_console(); 2949 2950 ret = platform_driver_register(&samsung_serial_driver); 2951 if (ret) { 2952 s3c24xx_serial_unregister_console(); 2953 return ret; 2954 } 2955 2956 return 0; 2957 } 2958 2959 static void __exit samsung_serial_exit(void) 2960 { 2961 platform_driver_unregister(&samsung_serial_driver); 2962 s3c24xx_serial_unregister_console(); 2963 } 2964 2965 module_init(samsung_serial_init); 2966 module_exit(samsung_serial_exit); 2967 2968 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE 2969 /* 2970 * Early console. 2971 */ 2972 2973 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val) 2974 { 2975 switch (port->iotype) { 2976 case UPIO_MEM: 2977 writeb(val, portaddr(port, reg)); 2978 break; 2979 case UPIO_MEM32: 2980 writel(val, portaddr(port, reg)); 2981 break; 2982 } 2983 } 2984 2985 struct samsung_early_console_data { 2986 u32 txfull_mask; 2987 u32 rxfifo_mask; 2988 }; 2989 2990 static void samsung_early_busyuart(const struct uart_port *port) 2991 { 2992 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) 2993 ; 2994 } 2995 2996 static void samsung_early_busyuart_fifo(const struct uart_port *port) 2997 { 2998 const struct samsung_early_console_data *data = port->private_data; 2999 3000 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) 3001 ; 3002 } 3003 3004 static void samsung_early_putc(struct uart_port *port, unsigned char c) 3005 { 3006 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) 3007 samsung_early_busyuart_fifo(port); 3008 else 3009 samsung_early_busyuart(port); 3010 3011 wr_reg_barrier(port, S3C2410_UTXH, c); 3012 } 3013 3014 static void samsung_early_write(struct console *con, const char *s, 3015 unsigned int n) 3016 { 3017 struct earlycon_device *dev = con->data; 3018 3019 uart_console_write(&dev->port, s, n, samsung_early_putc); 3020 } 3021 3022 static int samsung_early_read(struct console *con, char *s, unsigned int n) 3023 { 3024 struct earlycon_device *dev = con->data; 3025 const struct samsung_early_console_data *data = dev->port.private_data; 3026 int ch, ufstat, num_read = 0; 3027 3028 while (num_read < n) { 3029 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT); 3030 if (!(ufstat & data->rxfifo_mask)) 3031 break; 3032 ch = rd_reg(&dev->port, S3C2410_URXH); 3033 if (ch == NO_POLL_CHAR) 3034 break; 3035 3036 s[num_read++] = ch; 3037 } 3038 3039 return num_read; 3040 } 3041 3042 static int __init samsung_early_console_setup(struct earlycon_device *device, 3043 const char *opt) 3044 { 3045 if (!device->port.membase) 3046 return -ENODEV; 3047 3048 device->con->write = samsung_early_write; 3049 device->con->read = samsung_early_read; 3050 return 0; 3051 } 3052 3053 /* S3C2410 */ 3054 static struct samsung_early_console_data s3c2410_early_console_data = { 3055 .txfull_mask = S3C2410_UFSTAT_TXFULL, 3056 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK, 3057 }; 3058 3059 static int __init s3c2410_early_console_setup(struct earlycon_device *device, 3060 const char *opt) 3061 { 3062 device->port.private_data = &s3c2410_early_console_data; 3063 return samsung_early_console_setup(device, opt); 3064 } 3065 3066 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", 3067 s3c2410_early_console_setup); 3068 3069 /* S3C2412, S3C2440, S3C64xx */ 3070 static struct samsung_early_console_data s3c2440_early_console_data = { 3071 .txfull_mask = S3C2440_UFSTAT_TXFULL, 3072 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK, 3073 }; 3074 3075 static int __init s3c2440_early_console_setup(struct earlycon_device *device, 3076 const char *opt) 3077 { 3078 device->port.private_data = &s3c2440_early_console_data; 3079 return samsung_early_console_setup(device, opt); 3080 } 3081 3082 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart", 3083 s3c2440_early_console_setup); 3084 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", 3085 s3c2440_early_console_setup); 3086 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 3087 s3c2440_early_console_setup); 3088 3089 /* S5PV210, Exynos */ 3090 static struct samsung_early_console_data s5pv210_early_console_data = { 3091 .txfull_mask = S5PV210_UFSTAT_TXFULL, 3092 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK, 3093 }; 3094 3095 static int __init s5pv210_early_console_setup(struct earlycon_device *device, 3096 const char *opt) 3097 { 3098 device->port.private_data = &s5pv210_early_console_data; 3099 return samsung_early_console_setup(device, opt); 3100 } 3101 3102 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", 3103 s5pv210_early_console_setup); 3104 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", 3105 s5pv210_early_console_setup); 3106 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", 3107 s5pv210_early_console_setup); 3108 3109 /* Apple S5L */ 3110 static int __init apple_s5l_early_console_setup(struct earlycon_device *device, 3111 const char *opt) 3112 { 3113 /* Close enough to S3C2410 for earlycon... */ 3114 device->port.private_data = &s3c2410_early_console_data; 3115 3116 #ifdef CONFIG_ARM64 3117 /* ... but we need to override the existing fixmap entry as nGnRnE */ 3118 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase, 3119 __pgprot(PROT_DEVICE_nGnRnE)); 3120 #endif 3121 return samsung_early_console_setup(device, opt); 3122 } 3123 3124 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup); 3125 #endif 3126 3127 MODULE_ALIAS("platform:samsung-uart"); 3128 MODULE_DESCRIPTION("Samsung SoC Serial port driver"); 3129 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 3130 MODULE_LICENSE("GPL v2"); 3131