1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for SA11x0 serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 */ 9 10 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 11 #define SUPPORT_SYSRQ 12 #endif 13 14 #include <linux/module.h> 15 #include <linux/ioport.h> 16 #include <linux/init.h> 17 #include <linux/console.h> 18 #include <linux/sysrq.h> 19 #include <linux/platform_data/sa11x0-serial.h> 20 #include <linux/platform_device.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/serial.h> 25 #include <linux/io.h> 26 27 #include <asm/irq.h> 28 #include <mach/hardware.h> 29 #include <mach/irqs.h> 30 31 /* We've been assigned a range on the "Low-density serial ports" major */ 32 #define SERIAL_SA1100_MAJOR 204 33 #define MINOR_START 5 34 35 #define NR_PORTS 3 36 37 #define SA1100_ISR_PASS_LIMIT 256 38 39 /* 40 * Convert from ignore_status_mask or read_status_mask to UTSR[01] 41 */ 42 #define SM_TO_UTSR0(x) ((x) & 0xff) 43 #define SM_TO_UTSR1(x) ((x) >> 8) 44 #define UTSR0_TO_SM(x) ((x)) 45 #define UTSR1_TO_SM(x) ((x) << 8) 46 47 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) 48 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) 49 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) 50 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) 51 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) 52 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) 53 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) 54 55 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0) 56 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1) 57 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2) 58 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3) 59 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0) 60 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1) 61 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR) 62 63 /* 64 * This is the size of our serial port register set. 65 */ 66 #define UART_PORT_SIZE 0x24 67 68 /* 69 * This determines how often we check the modem status signals 70 * for any change. They generally aren't connected to an IRQ 71 * so we have to poll them. We also check immediately before 72 * filling the TX fifo incase CTS has been dropped. 73 */ 74 #define MCTRL_TIMEOUT (250*HZ/1000) 75 76 struct sa1100_port { 77 struct uart_port port; 78 struct timer_list timer; 79 unsigned int old_status; 80 }; 81 82 /* 83 * Handle any change of modem status signal since we were last called. 84 */ 85 static void sa1100_mctrl_check(struct sa1100_port *sport) 86 { 87 unsigned int status, changed; 88 89 status = sport->port.ops->get_mctrl(&sport->port); 90 changed = status ^ sport->old_status; 91 92 if (changed == 0) 93 return; 94 95 sport->old_status = status; 96 97 if (changed & TIOCM_RI) 98 sport->port.icount.rng++; 99 if (changed & TIOCM_DSR) 100 sport->port.icount.dsr++; 101 if (changed & TIOCM_CAR) 102 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 103 if (changed & TIOCM_CTS) 104 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 105 106 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 107 } 108 109 /* 110 * This is our per-port timeout handler, for checking the 111 * modem status signals. 112 */ 113 static void sa1100_timeout(struct timer_list *t) 114 { 115 struct sa1100_port *sport = from_timer(sport, t, timer); 116 unsigned long flags; 117 118 if (sport->port.state) { 119 spin_lock_irqsave(&sport->port.lock, flags); 120 sa1100_mctrl_check(sport); 121 spin_unlock_irqrestore(&sport->port.lock, flags); 122 123 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 124 } 125 } 126 127 /* 128 * interrupts disabled on entry 129 */ 130 static void sa1100_stop_tx(struct uart_port *port) 131 { 132 struct sa1100_port *sport = 133 container_of(port, struct sa1100_port, port); 134 u32 utcr3; 135 136 utcr3 = UART_GET_UTCR3(sport); 137 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE); 138 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS); 139 } 140 141 /* 142 * port locked and interrupts disabled 143 */ 144 static void sa1100_start_tx(struct uart_port *port) 145 { 146 struct sa1100_port *sport = 147 container_of(port, struct sa1100_port, port); 148 u32 utcr3; 149 150 utcr3 = UART_GET_UTCR3(sport); 151 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS); 152 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE); 153 } 154 155 /* 156 * Interrupts enabled 157 */ 158 static void sa1100_stop_rx(struct uart_port *port) 159 { 160 struct sa1100_port *sport = 161 container_of(port, struct sa1100_port, port); 162 u32 utcr3; 163 164 utcr3 = UART_GET_UTCR3(sport); 165 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE); 166 } 167 168 /* 169 * Set the modem control timer to fire immediately. 170 */ 171 static void sa1100_enable_ms(struct uart_port *port) 172 { 173 struct sa1100_port *sport = 174 container_of(port, struct sa1100_port, port); 175 176 mod_timer(&sport->timer, jiffies); 177 } 178 179 static void 180 sa1100_rx_chars(struct sa1100_port *sport) 181 { 182 unsigned int status, ch, flg; 183 184 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | 185 UTSR0_TO_SM(UART_GET_UTSR0(sport)); 186 while (status & UTSR1_TO_SM(UTSR1_RNE)) { 187 ch = UART_GET_CHAR(sport); 188 189 sport->port.icount.rx++; 190 191 flg = TTY_NORMAL; 192 193 /* 194 * note that the error handling code is 195 * out of the main execution path 196 */ 197 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) { 198 if (status & UTSR1_TO_SM(UTSR1_PRE)) 199 sport->port.icount.parity++; 200 else if (status & UTSR1_TO_SM(UTSR1_FRE)) 201 sport->port.icount.frame++; 202 if (status & UTSR1_TO_SM(UTSR1_ROR)) 203 sport->port.icount.overrun++; 204 205 status &= sport->port.read_status_mask; 206 207 if (status & UTSR1_TO_SM(UTSR1_PRE)) 208 flg = TTY_PARITY; 209 else if (status & UTSR1_TO_SM(UTSR1_FRE)) 210 flg = TTY_FRAME; 211 212 #ifdef SUPPORT_SYSRQ 213 sport->port.sysrq = 0; 214 #endif 215 } 216 217 if (uart_handle_sysrq_char(&sport->port, ch)) 218 goto ignore_char; 219 220 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg); 221 222 ignore_char: 223 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | 224 UTSR0_TO_SM(UART_GET_UTSR0(sport)); 225 } 226 227 spin_unlock(&sport->port.lock); 228 tty_flip_buffer_push(&sport->port.state->port); 229 spin_lock(&sport->port.lock); 230 } 231 232 static void sa1100_tx_chars(struct sa1100_port *sport) 233 { 234 struct circ_buf *xmit = &sport->port.state->xmit; 235 236 if (sport->port.x_char) { 237 UART_PUT_CHAR(sport, sport->port.x_char); 238 sport->port.icount.tx++; 239 sport->port.x_char = 0; 240 return; 241 } 242 243 /* 244 * Check the modem control lines before 245 * transmitting anything. 246 */ 247 sa1100_mctrl_check(sport); 248 249 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 250 sa1100_stop_tx(&sport->port); 251 return; 252 } 253 254 /* 255 * Tried using FIFO (not checking TNF) for fifo fill: 256 * still had the '4 bytes repeated' problem. 257 */ 258 while (UART_GET_UTSR1(sport) & UTSR1_TNF) { 259 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]); 260 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 261 sport->port.icount.tx++; 262 if (uart_circ_empty(xmit)) 263 break; 264 } 265 266 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 267 uart_write_wakeup(&sport->port); 268 269 if (uart_circ_empty(xmit)) 270 sa1100_stop_tx(&sport->port); 271 } 272 273 static irqreturn_t sa1100_int(int irq, void *dev_id) 274 { 275 struct sa1100_port *sport = dev_id; 276 unsigned int status, pass_counter = 0; 277 278 spin_lock(&sport->port.lock); 279 status = UART_GET_UTSR0(sport); 280 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; 281 do { 282 if (status & (UTSR0_RFS | UTSR0_RID)) { 283 /* Clear the receiver idle bit, if set */ 284 if (status & UTSR0_RID) 285 UART_PUT_UTSR0(sport, UTSR0_RID); 286 sa1100_rx_chars(sport); 287 } 288 289 /* Clear the relevant break bits */ 290 if (status & (UTSR0_RBB | UTSR0_REB)) 291 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB)); 292 293 if (status & UTSR0_RBB) 294 sport->port.icount.brk++; 295 296 if (status & UTSR0_REB) 297 uart_handle_break(&sport->port); 298 299 if (status & UTSR0_TFS) 300 sa1100_tx_chars(sport); 301 if (pass_counter++ > SA1100_ISR_PASS_LIMIT) 302 break; 303 status = UART_GET_UTSR0(sport); 304 status &= SM_TO_UTSR0(sport->port.read_status_mask) | 305 ~UTSR0_TFS; 306 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); 307 spin_unlock(&sport->port.lock); 308 309 return IRQ_HANDLED; 310 } 311 312 /* 313 * Return TIOCSER_TEMT when transmitter is not busy. 314 */ 315 static unsigned int sa1100_tx_empty(struct uart_port *port) 316 { 317 struct sa1100_port *sport = 318 container_of(port, struct sa1100_port, port); 319 320 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT; 321 } 322 323 static unsigned int sa1100_get_mctrl(struct uart_port *port) 324 { 325 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 326 } 327 328 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl) 329 { 330 } 331 332 /* 333 * Interrupts always disabled. 334 */ 335 static void sa1100_break_ctl(struct uart_port *port, int break_state) 336 { 337 struct sa1100_port *sport = 338 container_of(port, struct sa1100_port, port); 339 unsigned long flags; 340 unsigned int utcr3; 341 342 spin_lock_irqsave(&sport->port.lock, flags); 343 utcr3 = UART_GET_UTCR3(sport); 344 if (break_state == -1) 345 utcr3 |= UTCR3_BRK; 346 else 347 utcr3 &= ~UTCR3_BRK; 348 UART_PUT_UTCR3(sport, utcr3); 349 spin_unlock_irqrestore(&sport->port.lock, flags); 350 } 351 352 static int sa1100_startup(struct uart_port *port) 353 { 354 struct sa1100_port *sport = 355 container_of(port, struct sa1100_port, port); 356 int retval; 357 358 /* 359 * Allocate the IRQ 360 */ 361 retval = request_irq(sport->port.irq, sa1100_int, 0, 362 "sa11x0-uart", sport); 363 if (retval) 364 return retval; 365 366 /* 367 * Finally, clear and enable interrupts 368 */ 369 UART_PUT_UTSR0(sport, -1); 370 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE); 371 372 /* 373 * Enable modem status interrupts 374 */ 375 spin_lock_irq(&sport->port.lock); 376 sa1100_enable_ms(&sport->port); 377 spin_unlock_irq(&sport->port.lock); 378 379 return 0; 380 } 381 382 static void sa1100_shutdown(struct uart_port *port) 383 { 384 struct sa1100_port *sport = 385 container_of(port, struct sa1100_port, port); 386 387 /* 388 * Stop our timer. 389 */ 390 del_timer_sync(&sport->timer); 391 392 /* 393 * Free the interrupt 394 */ 395 free_irq(sport->port.irq, sport); 396 397 /* 398 * Disable all interrupts, port and break condition. 399 */ 400 UART_PUT_UTCR3(sport, 0); 401 } 402 403 static void 404 sa1100_set_termios(struct uart_port *port, struct ktermios *termios, 405 struct ktermios *old) 406 { 407 struct sa1100_port *sport = 408 container_of(port, struct sa1100_port, port); 409 unsigned long flags; 410 unsigned int utcr0, old_utcr3, baud, quot; 411 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 412 413 /* 414 * We only support CS7 and CS8. 415 */ 416 while ((termios->c_cflag & CSIZE) != CS7 && 417 (termios->c_cflag & CSIZE) != CS8) { 418 termios->c_cflag &= ~CSIZE; 419 termios->c_cflag |= old_csize; 420 old_csize = CS8; 421 } 422 423 if ((termios->c_cflag & CSIZE) == CS8) 424 utcr0 = UTCR0_DSS; 425 else 426 utcr0 = 0; 427 428 if (termios->c_cflag & CSTOPB) 429 utcr0 |= UTCR0_SBS; 430 if (termios->c_cflag & PARENB) { 431 utcr0 |= UTCR0_PE; 432 if (!(termios->c_cflag & PARODD)) 433 utcr0 |= UTCR0_OES; 434 } 435 436 /* 437 * Ask the core to calculate the divisor for us. 438 */ 439 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 440 quot = uart_get_divisor(port, baud); 441 442 spin_lock_irqsave(&sport->port.lock, flags); 443 444 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); 445 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); 446 if (termios->c_iflag & INPCK) 447 sport->port.read_status_mask |= 448 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); 449 if (termios->c_iflag & (BRKINT | PARMRK)) 450 sport->port.read_status_mask |= 451 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); 452 453 /* 454 * Characters to ignore 455 */ 456 sport->port.ignore_status_mask = 0; 457 if (termios->c_iflag & IGNPAR) 458 sport->port.ignore_status_mask |= 459 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); 460 if (termios->c_iflag & IGNBRK) { 461 sport->port.ignore_status_mask |= 462 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); 463 /* 464 * If we're ignoring parity and break indicators, 465 * ignore overruns too (for real raw support). 466 */ 467 if (termios->c_iflag & IGNPAR) 468 sport->port.ignore_status_mask |= 469 UTSR1_TO_SM(UTSR1_ROR); 470 } 471 472 del_timer_sync(&sport->timer); 473 474 /* 475 * Update the per-port timeout. 476 */ 477 uart_update_timeout(port, termios->c_cflag, baud); 478 479 /* 480 * disable interrupts and drain transmitter 481 */ 482 old_utcr3 = UART_GET_UTCR3(sport); 483 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)); 484 485 while (UART_GET_UTSR1(sport) & UTSR1_TBY) 486 barrier(); 487 488 /* then, disable everything */ 489 UART_PUT_UTCR3(sport, 0); 490 491 /* set the parity, stop bits and data size */ 492 UART_PUT_UTCR0(sport, utcr0); 493 494 /* set the baud rate */ 495 quot -= 1; 496 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8)); 497 UART_PUT_UTCR2(sport, (quot & 0xff)); 498 499 UART_PUT_UTSR0(sport, -1); 500 501 UART_PUT_UTCR3(sport, old_utcr3); 502 503 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 504 sa1100_enable_ms(&sport->port); 505 506 spin_unlock_irqrestore(&sport->port.lock, flags); 507 } 508 509 static const char *sa1100_type(struct uart_port *port) 510 { 511 struct sa1100_port *sport = 512 container_of(port, struct sa1100_port, port); 513 514 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL; 515 } 516 517 /* 518 * Release the memory region(s) being used by 'port'. 519 */ 520 static void sa1100_release_port(struct uart_port *port) 521 { 522 struct sa1100_port *sport = 523 container_of(port, struct sa1100_port, port); 524 525 release_mem_region(sport->port.mapbase, UART_PORT_SIZE); 526 } 527 528 /* 529 * Request the memory region(s) being used by 'port'. 530 */ 531 static int sa1100_request_port(struct uart_port *port) 532 { 533 struct sa1100_port *sport = 534 container_of(port, struct sa1100_port, port); 535 536 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, 537 "sa11x0-uart") != NULL ? 0 : -EBUSY; 538 } 539 540 /* 541 * Configure/autoconfigure the port. 542 */ 543 static void sa1100_config_port(struct uart_port *port, int flags) 544 { 545 struct sa1100_port *sport = 546 container_of(port, struct sa1100_port, port); 547 548 if (flags & UART_CONFIG_TYPE && 549 sa1100_request_port(&sport->port) == 0) 550 sport->port.type = PORT_SA1100; 551 } 552 553 /* 554 * Verify the new serial_struct (for TIOCSSERIAL). 555 * The only change we allow are to the flags and type, and 556 * even then only between PORT_SA1100 and PORT_UNKNOWN 557 */ 558 static int 559 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser) 560 { 561 struct sa1100_port *sport = 562 container_of(port, struct sa1100_port, port); 563 int ret = 0; 564 565 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100) 566 ret = -EINVAL; 567 if (sport->port.irq != ser->irq) 568 ret = -EINVAL; 569 if (ser->io_type != SERIAL_IO_MEM) 570 ret = -EINVAL; 571 if (sport->port.uartclk / 16 != ser->baud_base) 572 ret = -EINVAL; 573 if ((void *)sport->port.mapbase != ser->iomem_base) 574 ret = -EINVAL; 575 if (sport->port.iobase != ser->port) 576 ret = -EINVAL; 577 if (ser->hub6 != 0) 578 ret = -EINVAL; 579 return ret; 580 } 581 582 static struct uart_ops sa1100_pops = { 583 .tx_empty = sa1100_tx_empty, 584 .set_mctrl = sa1100_set_mctrl, 585 .get_mctrl = sa1100_get_mctrl, 586 .stop_tx = sa1100_stop_tx, 587 .start_tx = sa1100_start_tx, 588 .stop_rx = sa1100_stop_rx, 589 .enable_ms = sa1100_enable_ms, 590 .break_ctl = sa1100_break_ctl, 591 .startup = sa1100_startup, 592 .shutdown = sa1100_shutdown, 593 .set_termios = sa1100_set_termios, 594 .type = sa1100_type, 595 .release_port = sa1100_release_port, 596 .request_port = sa1100_request_port, 597 .config_port = sa1100_config_port, 598 .verify_port = sa1100_verify_port, 599 }; 600 601 static struct sa1100_port sa1100_ports[NR_PORTS]; 602 603 /* 604 * Setup the SA1100 serial ports. Note that we don't include the IrDA 605 * port here since we have our own SIR/FIR driver (see drivers/net/irda) 606 * 607 * Note also that we support "console=ttySAx" where "x" is either 0 or 1. 608 * Which serial port this ends up being depends on the machine you're 609 * running this kernel on. I'm not convinced that this is a good idea, 610 * but that's the way it traditionally works. 611 * 612 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer 613 * used here. 614 */ 615 static void __init sa1100_init_ports(void) 616 { 617 static int first = 1; 618 int i; 619 620 if (!first) 621 return; 622 first = 0; 623 624 for (i = 0; i < NR_PORTS; i++) { 625 sa1100_ports[i].port.uartclk = 3686400; 626 sa1100_ports[i].port.ops = &sa1100_pops; 627 sa1100_ports[i].port.fifosize = 8; 628 sa1100_ports[i].port.line = i; 629 sa1100_ports[i].port.iotype = UPIO_MEM; 630 timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0); 631 } 632 633 /* 634 * make transmit lines outputs, so that when the port 635 * is closed, the output is in the MARK state. 636 */ 637 PPDR |= PPC_TXD1 | PPC_TXD3; 638 PPSR |= PPC_TXD1 | PPC_TXD3; 639 } 640 641 void sa1100_register_uart_fns(struct sa1100_port_fns *fns) 642 { 643 if (fns->get_mctrl) 644 sa1100_pops.get_mctrl = fns->get_mctrl; 645 if (fns->set_mctrl) 646 sa1100_pops.set_mctrl = fns->set_mctrl; 647 648 sa1100_pops.pm = fns->pm; 649 /* 650 * FIXME: fns->set_wake is unused - this should be called from 651 * the suspend() callback if device_may_wakeup(dev)) is set. 652 */ 653 } 654 655 void __init sa1100_register_uart(int idx, int port) 656 { 657 if (idx >= NR_PORTS) { 658 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx); 659 return; 660 } 661 662 switch (port) { 663 case 1: 664 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; 665 sa1100_ports[idx].port.mapbase = _Ser1UTCR0; 666 sa1100_ports[idx].port.irq = IRQ_Ser1UART; 667 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; 668 break; 669 670 case 2: 671 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; 672 sa1100_ports[idx].port.mapbase = _Ser2UTCR0; 673 sa1100_ports[idx].port.irq = IRQ_Ser2ICP; 674 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; 675 break; 676 677 case 3: 678 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; 679 sa1100_ports[idx].port.mapbase = _Ser3UTCR0; 680 sa1100_ports[idx].port.irq = IRQ_Ser3UART; 681 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; 682 break; 683 684 default: 685 printk(KERN_ERR "%s: bad port number %d\n", __func__, port); 686 } 687 } 688 689 690 #ifdef CONFIG_SERIAL_SA1100_CONSOLE 691 static void sa1100_console_putchar(struct uart_port *port, int ch) 692 { 693 struct sa1100_port *sport = 694 container_of(port, struct sa1100_port, port); 695 696 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF)) 697 barrier(); 698 UART_PUT_CHAR(sport, ch); 699 } 700 701 /* 702 * Interrupts are disabled on entering 703 */ 704 static void 705 sa1100_console_write(struct console *co, const char *s, unsigned int count) 706 { 707 struct sa1100_port *sport = &sa1100_ports[co->index]; 708 unsigned int old_utcr3, status; 709 710 /* 711 * First, save UTCR3 and then disable interrupts 712 */ 713 old_utcr3 = UART_GET_UTCR3(sport); 714 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) | 715 UTCR3_TXE); 716 717 uart_console_write(&sport->port, s, count, sa1100_console_putchar); 718 719 /* 720 * Finally, wait for transmitter to become empty 721 * and restore UTCR3 722 */ 723 do { 724 status = UART_GET_UTSR1(sport); 725 } while (status & UTSR1_TBY); 726 UART_PUT_UTCR3(sport, old_utcr3); 727 } 728 729 /* 730 * If the port was already initialised (eg, by a boot loader), 731 * try to determine the current setup. 732 */ 733 static void __init 734 sa1100_console_get_options(struct sa1100_port *sport, int *baud, 735 int *parity, int *bits) 736 { 737 unsigned int utcr3; 738 739 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE); 740 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) { 741 /* ok, the port was enabled */ 742 unsigned int utcr0, quot; 743 744 utcr0 = UART_GET_UTCR0(sport); 745 746 *parity = 'n'; 747 if (utcr0 & UTCR0_PE) { 748 if (utcr0 & UTCR0_OES) 749 *parity = 'e'; 750 else 751 *parity = 'o'; 752 } 753 754 if (utcr0 & UTCR0_DSS) 755 *bits = 8; 756 else 757 *bits = 7; 758 759 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8; 760 quot &= 0xfff; 761 *baud = sport->port.uartclk / (16 * (quot + 1)); 762 } 763 } 764 765 static int __init 766 sa1100_console_setup(struct console *co, char *options) 767 { 768 struct sa1100_port *sport; 769 int baud = 9600; 770 int bits = 8; 771 int parity = 'n'; 772 int flow = 'n'; 773 774 /* 775 * Check whether an invalid uart number has been specified, and 776 * if so, search for the first available port that does have 777 * console support. 778 */ 779 if (co->index == -1 || co->index >= NR_PORTS) 780 co->index = 0; 781 sport = &sa1100_ports[co->index]; 782 783 if (options) 784 uart_parse_options(options, &baud, &parity, &bits, &flow); 785 else 786 sa1100_console_get_options(sport, &baud, &parity, &bits); 787 788 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 789 } 790 791 static struct uart_driver sa1100_reg; 792 static struct console sa1100_console = { 793 .name = "ttySA", 794 .write = sa1100_console_write, 795 .device = uart_console_device, 796 .setup = sa1100_console_setup, 797 .flags = CON_PRINTBUFFER, 798 .index = -1, 799 .data = &sa1100_reg, 800 }; 801 802 static int __init sa1100_rs_console_init(void) 803 { 804 sa1100_init_ports(); 805 register_console(&sa1100_console); 806 return 0; 807 } 808 console_initcall(sa1100_rs_console_init); 809 810 #define SA1100_CONSOLE &sa1100_console 811 #else 812 #define SA1100_CONSOLE NULL 813 #endif 814 815 static struct uart_driver sa1100_reg = { 816 .owner = THIS_MODULE, 817 .driver_name = "ttySA", 818 .dev_name = "ttySA", 819 .major = SERIAL_SA1100_MAJOR, 820 .minor = MINOR_START, 821 .nr = NR_PORTS, 822 .cons = SA1100_CONSOLE, 823 }; 824 825 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state) 826 { 827 struct sa1100_port *sport = platform_get_drvdata(dev); 828 829 if (sport) 830 uart_suspend_port(&sa1100_reg, &sport->port); 831 832 return 0; 833 } 834 835 static int sa1100_serial_resume(struct platform_device *dev) 836 { 837 struct sa1100_port *sport = platform_get_drvdata(dev); 838 839 if (sport) 840 uart_resume_port(&sa1100_reg, &sport->port); 841 842 return 0; 843 } 844 845 static int sa1100_serial_probe(struct platform_device *dev) 846 { 847 struct resource *res = dev->resource; 848 int i; 849 850 for (i = 0; i < dev->num_resources; i++, res++) 851 if (res->flags & IORESOURCE_MEM) 852 break; 853 854 if (i < dev->num_resources) { 855 for (i = 0; i < NR_PORTS; i++) { 856 if (sa1100_ports[i].port.mapbase != res->start) 857 continue; 858 859 sa1100_ports[i].port.dev = &dev->dev; 860 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port); 861 platform_set_drvdata(dev, &sa1100_ports[i]); 862 break; 863 } 864 } 865 866 return 0; 867 } 868 869 static int sa1100_serial_remove(struct platform_device *pdev) 870 { 871 struct sa1100_port *sport = platform_get_drvdata(pdev); 872 873 if (sport) 874 uart_remove_one_port(&sa1100_reg, &sport->port); 875 876 return 0; 877 } 878 879 static struct platform_driver sa11x0_serial_driver = { 880 .probe = sa1100_serial_probe, 881 .remove = sa1100_serial_remove, 882 .suspend = sa1100_serial_suspend, 883 .resume = sa1100_serial_resume, 884 .driver = { 885 .name = "sa11x0-uart", 886 }, 887 }; 888 889 static int __init sa1100_serial_init(void) 890 { 891 int ret; 892 893 printk(KERN_INFO "Serial: SA11x0 driver\n"); 894 895 sa1100_init_ports(); 896 897 ret = uart_register_driver(&sa1100_reg); 898 if (ret == 0) { 899 ret = platform_driver_register(&sa11x0_serial_driver); 900 if (ret) 901 uart_unregister_driver(&sa1100_reg); 902 } 903 return ret; 904 } 905 906 static void __exit sa1100_serial_exit(void) 907 { 908 platform_driver_unregister(&sa11x0_serial_driver); 909 uart_unregister_driver(&sa1100_reg); 910 } 911 912 module_init(sa1100_serial_init); 913 module_exit(sa1100_serial_exit); 914 915 MODULE_AUTHOR("Deep Blue Solutions Ltd"); 916 MODULE_DESCRIPTION("SA1100 generic serial port driver"); 917 MODULE_LICENSE("GPL"); 918 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR); 919 MODULE_ALIAS("platform:sa11x0-uart"); 920