1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for SA11x0 serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/ioport.h> 12 #include <linux/init.h> 13 #include <linux/console.h> 14 #include <linux/sysrq.h> 15 #include <linux/platform_data/sa11x0-serial.h> 16 #include <linux/platform_device.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/io.h> 22 23 #include <asm/irq.h> 24 #include <mach/hardware.h> 25 #include <mach/irqs.h> 26 27 #include "serial_mctrl_gpio.h" 28 29 /* We've been assigned a range on the "Low-density serial ports" major */ 30 #define SERIAL_SA1100_MAJOR 204 31 #define MINOR_START 5 32 33 #define NR_PORTS 3 34 35 #define SA1100_ISR_PASS_LIMIT 256 36 37 /* 38 * Convert from ignore_status_mask or read_status_mask to UTSR[01] 39 */ 40 #define SM_TO_UTSR0(x) ((x) & 0xff) 41 #define SM_TO_UTSR1(x) ((x) >> 8) 42 #define UTSR0_TO_SM(x) ((x)) 43 #define UTSR1_TO_SM(x) ((x) << 8) 44 45 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) 46 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) 47 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) 48 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) 49 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) 50 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) 51 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) 52 53 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0) 54 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1) 55 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2) 56 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3) 57 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0) 58 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1) 59 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR) 60 61 /* 62 * This is the size of our serial port register set. 63 */ 64 #define UART_PORT_SIZE 0x24 65 66 /* 67 * This determines how often we check the modem status signals 68 * for any change. They generally aren't connected to an IRQ 69 * so we have to poll them. We also check immediately before 70 * filling the TX fifo incase CTS has been dropped. 71 */ 72 #define MCTRL_TIMEOUT (250*HZ/1000) 73 74 struct sa1100_port { 75 struct uart_port port; 76 struct timer_list timer; 77 unsigned int old_status; 78 struct mctrl_gpios *gpios; 79 }; 80 81 /* 82 * Handle any change of modem status signal since we were last called. 83 */ 84 static void sa1100_mctrl_check(struct sa1100_port *sport) 85 { 86 unsigned int status, changed; 87 88 status = sport->port.ops->get_mctrl(&sport->port); 89 changed = status ^ sport->old_status; 90 91 if (changed == 0) 92 return; 93 94 sport->old_status = status; 95 96 if (changed & TIOCM_RI) 97 sport->port.icount.rng++; 98 if (changed & TIOCM_DSR) 99 sport->port.icount.dsr++; 100 if (changed & TIOCM_CAR) 101 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 102 if (changed & TIOCM_CTS) 103 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 104 105 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 106 } 107 108 /* 109 * This is our per-port timeout handler, for checking the 110 * modem status signals. 111 */ 112 static void sa1100_timeout(struct timer_list *t) 113 { 114 struct sa1100_port *sport = from_timer(sport, t, timer); 115 unsigned long flags; 116 117 if (sport->port.state) { 118 spin_lock_irqsave(&sport->port.lock, flags); 119 sa1100_mctrl_check(sport); 120 spin_unlock_irqrestore(&sport->port.lock, flags); 121 122 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 123 } 124 } 125 126 /* 127 * interrupts disabled on entry 128 */ 129 static void sa1100_stop_tx(struct uart_port *port) 130 { 131 struct sa1100_port *sport = 132 container_of(port, struct sa1100_port, port); 133 u32 utcr3; 134 135 utcr3 = UART_GET_UTCR3(sport); 136 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE); 137 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS); 138 } 139 140 /* 141 * port locked and interrupts disabled 142 */ 143 static void sa1100_start_tx(struct uart_port *port) 144 { 145 struct sa1100_port *sport = 146 container_of(port, struct sa1100_port, port); 147 u32 utcr3; 148 149 utcr3 = UART_GET_UTCR3(sport); 150 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS); 151 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE); 152 } 153 154 /* 155 * Interrupts enabled 156 */ 157 static void sa1100_stop_rx(struct uart_port *port) 158 { 159 struct sa1100_port *sport = 160 container_of(port, struct sa1100_port, port); 161 u32 utcr3; 162 163 utcr3 = UART_GET_UTCR3(sport); 164 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE); 165 } 166 167 /* 168 * Set the modem control timer to fire immediately. 169 */ 170 static void sa1100_enable_ms(struct uart_port *port) 171 { 172 struct sa1100_port *sport = 173 container_of(port, struct sa1100_port, port); 174 175 mod_timer(&sport->timer, jiffies); 176 177 mctrl_gpio_enable_ms(sport->gpios); 178 } 179 180 static void 181 sa1100_rx_chars(struct sa1100_port *sport) 182 { 183 unsigned int status, ch, flg; 184 185 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | 186 UTSR0_TO_SM(UART_GET_UTSR0(sport)); 187 while (status & UTSR1_TO_SM(UTSR1_RNE)) { 188 ch = UART_GET_CHAR(sport); 189 190 sport->port.icount.rx++; 191 192 flg = TTY_NORMAL; 193 194 /* 195 * note that the error handling code is 196 * out of the main execution path 197 */ 198 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) { 199 if (status & UTSR1_TO_SM(UTSR1_PRE)) 200 sport->port.icount.parity++; 201 else if (status & UTSR1_TO_SM(UTSR1_FRE)) 202 sport->port.icount.frame++; 203 if (status & UTSR1_TO_SM(UTSR1_ROR)) 204 sport->port.icount.overrun++; 205 206 status &= sport->port.read_status_mask; 207 208 if (status & UTSR1_TO_SM(UTSR1_PRE)) 209 flg = TTY_PARITY; 210 else if (status & UTSR1_TO_SM(UTSR1_FRE)) 211 flg = TTY_FRAME; 212 213 sport->port.sysrq = 0; 214 } 215 216 if (uart_handle_sysrq_char(&sport->port, ch)) 217 goto ignore_char; 218 219 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg); 220 221 ignore_char: 222 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | 223 UTSR0_TO_SM(UART_GET_UTSR0(sport)); 224 } 225 226 tty_flip_buffer_push(&sport->port.state->port); 227 } 228 229 static void sa1100_tx_chars(struct sa1100_port *sport) 230 { 231 struct circ_buf *xmit = &sport->port.state->xmit; 232 233 if (sport->port.x_char) { 234 UART_PUT_CHAR(sport, sport->port.x_char); 235 sport->port.icount.tx++; 236 sport->port.x_char = 0; 237 return; 238 } 239 240 /* 241 * Check the modem control lines before 242 * transmitting anything. 243 */ 244 sa1100_mctrl_check(sport); 245 246 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 247 sa1100_stop_tx(&sport->port); 248 return; 249 } 250 251 /* 252 * Tried using FIFO (not checking TNF) for fifo fill: 253 * still had the '4 bytes repeated' problem. 254 */ 255 while (UART_GET_UTSR1(sport) & UTSR1_TNF) { 256 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]); 257 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 258 sport->port.icount.tx++; 259 if (uart_circ_empty(xmit)) 260 break; 261 } 262 263 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 264 uart_write_wakeup(&sport->port); 265 266 if (uart_circ_empty(xmit)) 267 sa1100_stop_tx(&sport->port); 268 } 269 270 static irqreturn_t sa1100_int(int irq, void *dev_id) 271 { 272 struct sa1100_port *sport = dev_id; 273 unsigned int status, pass_counter = 0; 274 275 spin_lock(&sport->port.lock); 276 status = UART_GET_UTSR0(sport); 277 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; 278 do { 279 if (status & (UTSR0_RFS | UTSR0_RID)) { 280 /* Clear the receiver idle bit, if set */ 281 if (status & UTSR0_RID) 282 UART_PUT_UTSR0(sport, UTSR0_RID); 283 sa1100_rx_chars(sport); 284 } 285 286 /* Clear the relevant break bits */ 287 if (status & (UTSR0_RBB | UTSR0_REB)) 288 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB)); 289 290 if (status & UTSR0_RBB) 291 sport->port.icount.brk++; 292 293 if (status & UTSR0_REB) 294 uart_handle_break(&sport->port); 295 296 if (status & UTSR0_TFS) 297 sa1100_tx_chars(sport); 298 if (pass_counter++ > SA1100_ISR_PASS_LIMIT) 299 break; 300 status = UART_GET_UTSR0(sport); 301 status &= SM_TO_UTSR0(sport->port.read_status_mask) | 302 ~UTSR0_TFS; 303 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); 304 spin_unlock(&sport->port.lock); 305 306 return IRQ_HANDLED; 307 } 308 309 /* 310 * Return TIOCSER_TEMT when transmitter is not busy. 311 */ 312 static unsigned int sa1100_tx_empty(struct uart_port *port) 313 { 314 struct sa1100_port *sport = 315 container_of(port, struct sa1100_port, port); 316 317 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT; 318 } 319 320 static unsigned int sa1100_get_mctrl(struct uart_port *port) 321 { 322 struct sa1100_port *sport = 323 container_of(port, struct sa1100_port, port); 324 int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 325 326 mctrl_gpio_get(sport->gpios, &ret); 327 328 return ret; 329 } 330 331 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl) 332 { 333 struct sa1100_port *sport = 334 container_of(port, struct sa1100_port, port); 335 336 mctrl_gpio_set(sport->gpios, mctrl); 337 } 338 339 /* 340 * Interrupts always disabled. 341 */ 342 static void sa1100_break_ctl(struct uart_port *port, int break_state) 343 { 344 struct sa1100_port *sport = 345 container_of(port, struct sa1100_port, port); 346 unsigned long flags; 347 unsigned int utcr3; 348 349 spin_lock_irqsave(&sport->port.lock, flags); 350 utcr3 = UART_GET_UTCR3(sport); 351 if (break_state == -1) 352 utcr3 |= UTCR3_BRK; 353 else 354 utcr3 &= ~UTCR3_BRK; 355 UART_PUT_UTCR3(sport, utcr3); 356 spin_unlock_irqrestore(&sport->port.lock, flags); 357 } 358 359 static int sa1100_startup(struct uart_port *port) 360 { 361 struct sa1100_port *sport = 362 container_of(port, struct sa1100_port, port); 363 int retval; 364 365 /* 366 * Allocate the IRQ 367 */ 368 retval = request_irq(sport->port.irq, sa1100_int, 0, 369 "sa11x0-uart", sport); 370 if (retval) 371 return retval; 372 373 /* 374 * Finally, clear and enable interrupts 375 */ 376 UART_PUT_UTSR0(sport, -1); 377 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE); 378 379 /* 380 * Enable modem status interrupts 381 */ 382 spin_lock_irq(&sport->port.lock); 383 sa1100_enable_ms(&sport->port); 384 spin_unlock_irq(&sport->port.lock); 385 386 return 0; 387 } 388 389 static void sa1100_shutdown(struct uart_port *port) 390 { 391 struct sa1100_port *sport = 392 container_of(port, struct sa1100_port, port); 393 394 /* 395 * Stop our timer. 396 */ 397 del_timer_sync(&sport->timer); 398 399 /* 400 * Free the interrupt 401 */ 402 free_irq(sport->port.irq, sport); 403 404 /* 405 * Disable all interrupts, port and break condition. 406 */ 407 UART_PUT_UTCR3(sport, 0); 408 } 409 410 static void 411 sa1100_set_termios(struct uart_port *port, struct ktermios *termios, 412 const struct ktermios *old) 413 { 414 struct sa1100_port *sport = 415 container_of(port, struct sa1100_port, port); 416 unsigned long flags; 417 unsigned int utcr0, old_utcr3, baud, quot; 418 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 419 420 /* 421 * We only support CS7 and CS8. 422 */ 423 while ((termios->c_cflag & CSIZE) != CS7 && 424 (termios->c_cflag & CSIZE) != CS8) { 425 termios->c_cflag &= ~CSIZE; 426 termios->c_cflag |= old_csize; 427 old_csize = CS8; 428 } 429 430 if ((termios->c_cflag & CSIZE) == CS8) 431 utcr0 = UTCR0_DSS; 432 else 433 utcr0 = 0; 434 435 if (termios->c_cflag & CSTOPB) 436 utcr0 |= UTCR0_SBS; 437 if (termios->c_cflag & PARENB) { 438 utcr0 |= UTCR0_PE; 439 if (!(termios->c_cflag & PARODD)) 440 utcr0 |= UTCR0_OES; 441 } 442 443 /* 444 * Ask the core to calculate the divisor for us. 445 */ 446 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 447 quot = uart_get_divisor(port, baud); 448 449 del_timer_sync(&sport->timer); 450 451 spin_lock_irqsave(&sport->port.lock, flags); 452 453 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); 454 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); 455 if (termios->c_iflag & INPCK) 456 sport->port.read_status_mask |= 457 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); 458 if (termios->c_iflag & (BRKINT | PARMRK)) 459 sport->port.read_status_mask |= 460 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); 461 462 /* 463 * Characters to ignore 464 */ 465 sport->port.ignore_status_mask = 0; 466 if (termios->c_iflag & IGNPAR) 467 sport->port.ignore_status_mask |= 468 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); 469 if (termios->c_iflag & IGNBRK) { 470 sport->port.ignore_status_mask |= 471 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); 472 /* 473 * If we're ignoring parity and break indicators, 474 * ignore overruns too (for real raw support). 475 */ 476 if (termios->c_iflag & IGNPAR) 477 sport->port.ignore_status_mask |= 478 UTSR1_TO_SM(UTSR1_ROR); 479 } 480 481 /* 482 * Update the per-port timeout. 483 */ 484 uart_update_timeout(port, termios->c_cflag, baud); 485 486 /* 487 * disable interrupts and drain transmitter 488 */ 489 old_utcr3 = UART_GET_UTCR3(sport); 490 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)); 491 492 while (UART_GET_UTSR1(sport) & UTSR1_TBY) 493 barrier(); 494 495 /* then, disable everything */ 496 UART_PUT_UTCR3(sport, 0); 497 498 /* set the parity, stop bits and data size */ 499 UART_PUT_UTCR0(sport, utcr0); 500 501 /* set the baud rate */ 502 quot -= 1; 503 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8)); 504 UART_PUT_UTCR2(sport, (quot & 0xff)); 505 506 UART_PUT_UTSR0(sport, -1); 507 508 UART_PUT_UTCR3(sport, old_utcr3); 509 510 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 511 sa1100_enable_ms(&sport->port); 512 513 spin_unlock_irqrestore(&sport->port.lock, flags); 514 } 515 516 static const char *sa1100_type(struct uart_port *port) 517 { 518 struct sa1100_port *sport = 519 container_of(port, struct sa1100_port, port); 520 521 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL; 522 } 523 524 /* 525 * Release the memory region(s) being used by 'port'. 526 */ 527 static void sa1100_release_port(struct uart_port *port) 528 { 529 struct sa1100_port *sport = 530 container_of(port, struct sa1100_port, port); 531 532 release_mem_region(sport->port.mapbase, UART_PORT_SIZE); 533 } 534 535 /* 536 * Request the memory region(s) being used by 'port'. 537 */ 538 static int sa1100_request_port(struct uart_port *port) 539 { 540 struct sa1100_port *sport = 541 container_of(port, struct sa1100_port, port); 542 543 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, 544 "sa11x0-uart") != NULL ? 0 : -EBUSY; 545 } 546 547 /* 548 * Configure/autoconfigure the port. 549 */ 550 static void sa1100_config_port(struct uart_port *port, int flags) 551 { 552 struct sa1100_port *sport = 553 container_of(port, struct sa1100_port, port); 554 555 if (flags & UART_CONFIG_TYPE && 556 sa1100_request_port(&sport->port) == 0) 557 sport->port.type = PORT_SA1100; 558 } 559 560 /* 561 * Verify the new serial_struct (for TIOCSSERIAL). 562 * The only change we allow are to the flags and type, and 563 * even then only between PORT_SA1100 and PORT_UNKNOWN 564 */ 565 static int 566 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser) 567 { 568 struct sa1100_port *sport = 569 container_of(port, struct sa1100_port, port); 570 int ret = 0; 571 572 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100) 573 ret = -EINVAL; 574 if (sport->port.irq != ser->irq) 575 ret = -EINVAL; 576 if (ser->io_type != SERIAL_IO_MEM) 577 ret = -EINVAL; 578 if (sport->port.uartclk / 16 != ser->baud_base) 579 ret = -EINVAL; 580 if ((void *)sport->port.mapbase != ser->iomem_base) 581 ret = -EINVAL; 582 if (sport->port.iobase != ser->port) 583 ret = -EINVAL; 584 if (ser->hub6 != 0) 585 ret = -EINVAL; 586 return ret; 587 } 588 589 static struct uart_ops sa1100_pops = { 590 .tx_empty = sa1100_tx_empty, 591 .set_mctrl = sa1100_set_mctrl, 592 .get_mctrl = sa1100_get_mctrl, 593 .stop_tx = sa1100_stop_tx, 594 .start_tx = sa1100_start_tx, 595 .stop_rx = sa1100_stop_rx, 596 .enable_ms = sa1100_enable_ms, 597 .break_ctl = sa1100_break_ctl, 598 .startup = sa1100_startup, 599 .shutdown = sa1100_shutdown, 600 .set_termios = sa1100_set_termios, 601 .type = sa1100_type, 602 .release_port = sa1100_release_port, 603 .request_port = sa1100_request_port, 604 .config_port = sa1100_config_port, 605 .verify_port = sa1100_verify_port, 606 }; 607 608 static struct sa1100_port sa1100_ports[NR_PORTS]; 609 610 /* 611 * Setup the SA1100 serial ports. Note that we don't include the IrDA 612 * port here since we have our own SIR/FIR driver (see drivers/net/irda) 613 * 614 * Note also that we support "console=ttySAx" where "x" is either 0 or 1. 615 * Which serial port this ends up being depends on the machine you're 616 * running this kernel on. I'm not convinced that this is a good idea, 617 * but that's the way it traditionally works. 618 * 619 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer 620 * used here. 621 */ 622 static void __init sa1100_init_ports(void) 623 { 624 static int first = 1; 625 int i; 626 627 if (!first) 628 return; 629 first = 0; 630 631 for (i = 0; i < NR_PORTS; i++) { 632 sa1100_ports[i].port.uartclk = 3686400; 633 sa1100_ports[i].port.ops = &sa1100_pops; 634 sa1100_ports[i].port.fifosize = 8; 635 sa1100_ports[i].port.line = i; 636 sa1100_ports[i].port.iotype = UPIO_MEM; 637 timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0); 638 } 639 640 /* 641 * make transmit lines outputs, so that when the port 642 * is closed, the output is in the MARK state. 643 */ 644 PPDR |= PPC_TXD1 | PPC_TXD3; 645 PPSR |= PPC_TXD1 | PPC_TXD3; 646 } 647 648 void sa1100_register_uart_fns(struct sa1100_port_fns *fns) 649 { 650 if (fns->get_mctrl) 651 sa1100_pops.get_mctrl = fns->get_mctrl; 652 if (fns->set_mctrl) 653 sa1100_pops.set_mctrl = fns->set_mctrl; 654 655 sa1100_pops.pm = fns->pm; 656 /* 657 * FIXME: fns->set_wake is unused - this should be called from 658 * the suspend() callback if device_may_wakeup(dev)) is set. 659 */ 660 } 661 662 void __init sa1100_register_uart(int idx, int port) 663 { 664 if (idx >= NR_PORTS) { 665 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx); 666 return; 667 } 668 669 switch (port) { 670 case 1: 671 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; 672 sa1100_ports[idx].port.mapbase = _Ser1UTCR0; 673 sa1100_ports[idx].port.irq = IRQ_Ser1UART; 674 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; 675 break; 676 677 case 2: 678 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; 679 sa1100_ports[idx].port.mapbase = _Ser2UTCR0; 680 sa1100_ports[idx].port.irq = IRQ_Ser2ICP; 681 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; 682 break; 683 684 case 3: 685 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; 686 sa1100_ports[idx].port.mapbase = _Ser3UTCR0; 687 sa1100_ports[idx].port.irq = IRQ_Ser3UART; 688 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; 689 break; 690 691 default: 692 printk(KERN_ERR "%s: bad port number %d\n", __func__, port); 693 } 694 } 695 696 697 #ifdef CONFIG_SERIAL_SA1100_CONSOLE 698 static void sa1100_console_putchar(struct uart_port *port, unsigned char ch) 699 { 700 struct sa1100_port *sport = 701 container_of(port, struct sa1100_port, port); 702 703 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF)) 704 barrier(); 705 UART_PUT_CHAR(sport, ch); 706 } 707 708 /* 709 * Interrupts are disabled on entering 710 */ 711 static void 712 sa1100_console_write(struct console *co, const char *s, unsigned int count) 713 { 714 struct sa1100_port *sport = &sa1100_ports[co->index]; 715 unsigned int old_utcr3, status; 716 717 /* 718 * First, save UTCR3 and then disable interrupts 719 */ 720 old_utcr3 = UART_GET_UTCR3(sport); 721 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) | 722 UTCR3_TXE); 723 724 uart_console_write(&sport->port, s, count, sa1100_console_putchar); 725 726 /* 727 * Finally, wait for transmitter to become empty 728 * and restore UTCR3 729 */ 730 do { 731 status = UART_GET_UTSR1(sport); 732 } while (status & UTSR1_TBY); 733 UART_PUT_UTCR3(sport, old_utcr3); 734 } 735 736 /* 737 * If the port was already initialised (eg, by a boot loader), 738 * try to determine the current setup. 739 */ 740 static void __init 741 sa1100_console_get_options(struct sa1100_port *sport, int *baud, 742 int *parity, int *bits) 743 { 744 unsigned int utcr3; 745 746 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE); 747 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) { 748 /* ok, the port was enabled */ 749 unsigned int utcr0, quot; 750 751 utcr0 = UART_GET_UTCR0(sport); 752 753 *parity = 'n'; 754 if (utcr0 & UTCR0_PE) { 755 if (utcr0 & UTCR0_OES) 756 *parity = 'e'; 757 else 758 *parity = 'o'; 759 } 760 761 if (utcr0 & UTCR0_DSS) 762 *bits = 8; 763 else 764 *bits = 7; 765 766 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8; 767 quot &= 0xfff; 768 *baud = sport->port.uartclk / (16 * (quot + 1)); 769 } 770 } 771 772 static int __init 773 sa1100_console_setup(struct console *co, char *options) 774 { 775 struct sa1100_port *sport; 776 int baud = 9600; 777 int bits = 8; 778 int parity = 'n'; 779 int flow = 'n'; 780 781 /* 782 * Check whether an invalid uart number has been specified, and 783 * if so, search for the first available port that does have 784 * console support. 785 */ 786 if (co->index == -1 || co->index >= NR_PORTS) 787 co->index = 0; 788 sport = &sa1100_ports[co->index]; 789 790 if (options) 791 uart_parse_options(options, &baud, &parity, &bits, &flow); 792 else 793 sa1100_console_get_options(sport, &baud, &parity, &bits); 794 795 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 796 } 797 798 static struct uart_driver sa1100_reg; 799 static struct console sa1100_console = { 800 .name = "ttySA", 801 .write = sa1100_console_write, 802 .device = uart_console_device, 803 .setup = sa1100_console_setup, 804 .flags = CON_PRINTBUFFER, 805 .index = -1, 806 .data = &sa1100_reg, 807 }; 808 809 static int __init sa1100_rs_console_init(void) 810 { 811 sa1100_init_ports(); 812 register_console(&sa1100_console); 813 return 0; 814 } 815 console_initcall(sa1100_rs_console_init); 816 817 #define SA1100_CONSOLE &sa1100_console 818 #else 819 #define SA1100_CONSOLE NULL 820 #endif 821 822 static struct uart_driver sa1100_reg = { 823 .owner = THIS_MODULE, 824 .driver_name = "ttySA", 825 .dev_name = "ttySA", 826 .major = SERIAL_SA1100_MAJOR, 827 .minor = MINOR_START, 828 .nr = NR_PORTS, 829 .cons = SA1100_CONSOLE, 830 }; 831 832 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state) 833 { 834 struct sa1100_port *sport = platform_get_drvdata(dev); 835 836 if (sport) 837 uart_suspend_port(&sa1100_reg, &sport->port); 838 839 return 0; 840 } 841 842 static int sa1100_serial_resume(struct platform_device *dev) 843 { 844 struct sa1100_port *sport = platform_get_drvdata(dev); 845 846 if (sport) 847 uart_resume_port(&sa1100_reg, &sport->port); 848 849 return 0; 850 } 851 852 static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev) 853 { 854 sport->port.dev = &dev->dev; 855 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE); 856 857 // mctrl_gpio_init() requires that the GPIO driver supports interrupts, 858 // but we need to support GPIO drivers for hardware that has no such 859 // interrupts. Use mctrl_gpio_init_noauto() instead. 860 sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0); 861 if (IS_ERR(sport->gpios)) { 862 int err = PTR_ERR(sport->gpios); 863 864 dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n", 865 err); 866 867 if (err == -EPROBE_DEFER) 868 return err; 869 870 sport->gpios = NULL; 871 } 872 873 platform_set_drvdata(dev, sport); 874 875 return uart_add_one_port(&sa1100_reg, &sport->port); 876 } 877 878 static int sa1100_serial_probe(struct platform_device *dev) 879 { 880 struct resource *res; 881 int i; 882 883 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 884 if (!res) 885 return -EINVAL; 886 887 for (i = 0; i < NR_PORTS; i++) 888 if (sa1100_ports[i].port.mapbase == res->start) 889 break; 890 if (i == NR_PORTS) 891 return -ENODEV; 892 893 sa1100_serial_add_one_port(&sa1100_ports[i], dev); 894 895 return 0; 896 } 897 898 static int sa1100_serial_remove(struct platform_device *pdev) 899 { 900 struct sa1100_port *sport = platform_get_drvdata(pdev); 901 902 if (sport) 903 uart_remove_one_port(&sa1100_reg, &sport->port); 904 905 return 0; 906 } 907 908 static struct platform_driver sa11x0_serial_driver = { 909 .probe = sa1100_serial_probe, 910 .remove = sa1100_serial_remove, 911 .suspend = sa1100_serial_suspend, 912 .resume = sa1100_serial_resume, 913 .driver = { 914 .name = "sa11x0-uart", 915 }, 916 }; 917 918 static int __init sa1100_serial_init(void) 919 { 920 int ret; 921 922 printk(KERN_INFO "Serial: SA11x0 driver\n"); 923 924 sa1100_init_ports(); 925 926 ret = uart_register_driver(&sa1100_reg); 927 if (ret == 0) { 928 ret = platform_driver_register(&sa11x0_serial_driver); 929 if (ret) 930 uart_unregister_driver(&sa1100_reg); 931 } 932 return ret; 933 } 934 935 static void __exit sa1100_serial_exit(void) 936 { 937 platform_driver_unregister(&sa11x0_serial_driver); 938 uart_unregister_driver(&sa1100_reg); 939 } 940 941 module_init(sa1100_serial_init); 942 module_exit(sa1100_serial_exit); 943 944 MODULE_AUTHOR("Deep Blue Solutions Ltd"); 945 MODULE_DESCRIPTION("SA1100 generic serial port driver"); 946 MODULE_LICENSE("GPL"); 947 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR); 948 MODULE_ALIAS("platform:sa11x0-uart"); 949