1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Comtrol RocketPort EXPRESS/INFINITY cards 4 * 5 * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com> 6 * 7 * Inspired by, and loosely based on: 8 * 9 * ar933x_uart.c 10 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 11 * 12 * rocketport_infinity_express-linux-1.20.tar.gz 13 * Copyright (C) 2004-2011 Comtrol, Inc. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/compiler.h> 18 #include <linux/completion.h> 19 #include <linux/console.h> 20 #include <linux/delay.h> 21 #include <linux/firmware.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/irq.h> 26 #include <linux/kernel.h> 27 #include <linux/log2.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 #include <linux/slab.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty.h> 35 #include <linux/tty_flip.h> 36 #include <linux/types.h> 37 38 #define DRV_NAME "rp2" 39 40 #define RP2_FW_NAME "rp2.fw" 41 #define RP2_UCODE_BYTES 0x3f 42 43 #define PORTS_PER_ASIC 16 44 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1) 45 46 #define UART_CLOCK 44236800 47 #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16)) 48 #define FIFO_SIZE 512 49 50 /* BAR0 registers */ 51 #define RP2_FPGA_CTL0 0x110 52 #define RP2_FPGA_CTL1 0x11c 53 #define RP2_IRQ_MASK 0x1ec 54 #define RP2_IRQ_MASK_EN_m BIT(0) 55 #define RP2_IRQ_STATUS 0x1f0 56 57 /* BAR1 registers */ 58 #define RP2_ASIC_SPACING 0x1000 59 #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING)) 60 61 #define RP2_PORT_BASE 0x000 62 #define RP2_PORT_SPACING 0x040 63 64 #define RP2_UCODE_BASE 0x400 65 #define RP2_UCODE_SPACING 0x80 66 67 #define RP2_CLK_PRESCALER 0xc00 68 #define RP2_CH_IRQ_STAT 0xc04 69 #define RP2_CH_IRQ_MASK 0xc08 70 #define RP2_ASIC_IRQ 0xd00 71 #define RP2_ASIC_IRQ_EN_m BIT(20) 72 #define RP2_GLOBAL_CMD 0xd0c 73 #define RP2_ASIC_CFG 0xd04 74 75 /* port registers */ 76 #define RP2_DATA_DWORD 0x000 77 78 #define RP2_DATA_BYTE 0x008 79 #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8) 80 #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9) 81 #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10) 82 #define RP2_DATA_BYTE_BREAK_m BIT(11) 83 84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */ 85 #define RP2_DUMMY_READ BIT(16) 86 87 #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \ 88 RP2_DATA_BYTE_ERR_OVERRUN_m | \ 89 RP2_DATA_BYTE_ERR_FRAMING_m | \ 90 RP2_DATA_BYTE_BREAK_m) 91 92 #define RP2_RX_FIFO_COUNT 0x00c 93 #define RP2_TX_FIFO_COUNT 0x00e 94 95 #define RP2_CHAN_STAT 0x010 96 #define RP2_CHAN_STAT_RXDATA_m BIT(0) 97 #define RP2_CHAN_STAT_DCD_m BIT(3) 98 #define RP2_CHAN_STAT_DSR_m BIT(4) 99 #define RP2_CHAN_STAT_CTS_m BIT(5) 100 #define RP2_CHAN_STAT_RI_m BIT(6) 101 #define RP2_CHAN_STAT_OVERRUN_m BIT(13) 102 #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16) 103 #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17) 104 #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18) 105 #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22) 106 #define RP2_CHAN_STAT_TXEMPTY_m BIT(25) 107 108 #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \ 109 RP2_CHAN_STAT_CTS_CHANGED_m | \ 110 RP2_CHAN_STAT_CD_CHANGED_m | \ 111 RP2_CHAN_STAT_RI_CHANGED_m) 112 113 #define RP2_TXRX_CTL 0x014 114 #define RP2_TXRX_CTL_MSRIRQ_m BIT(0) 115 #define RP2_TXRX_CTL_RXIRQ_m BIT(2) 116 #define RP2_TXRX_CTL_RX_TRIG_s 3 117 #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s) 118 #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s) 119 #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s) 120 #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s) 121 #define RP2_TXRX_CTL_RX_EN_m BIT(5) 122 #define RP2_TXRX_CTL_RTSFLOW_m BIT(6) 123 #define RP2_TXRX_CTL_DTRFLOW_m BIT(7) 124 #define RP2_TXRX_CTL_TX_TRIG_s 16 125 #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s) 126 #define RP2_TXRX_CTL_DSRFLOW_m BIT(18) 127 #define RP2_TXRX_CTL_TXIRQ_m BIT(19) 128 #define RP2_TXRX_CTL_CTSFLOW_m BIT(23) 129 #define RP2_TXRX_CTL_TX_EN_m BIT(24) 130 #define RP2_TXRX_CTL_RTS_m BIT(25) 131 #define RP2_TXRX_CTL_DTR_m BIT(26) 132 #define RP2_TXRX_CTL_LOOP_m BIT(27) 133 #define RP2_TXRX_CTL_BREAK_m BIT(28) 134 #define RP2_TXRX_CTL_CMSPAR_m BIT(29) 135 #define RP2_TXRX_CTL_nPARODD_m BIT(30) 136 #define RP2_TXRX_CTL_PARENB_m BIT(31) 137 138 #define RP2_UART_CTL 0x018 139 #define RP2_UART_CTL_MODE_s 0 140 #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s) 141 #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s) 142 #define RP2_UART_CTL_FLUSH_RX_m BIT(3) 143 #define RP2_UART_CTL_FLUSH_TX_m BIT(4) 144 #define RP2_UART_CTL_RESET_CH_m BIT(5) 145 #define RP2_UART_CTL_XMIT_EN_m BIT(6) 146 #define RP2_UART_CTL_DATABITS_s 8 147 #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s) 148 #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s) 149 #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s) 150 #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s) 151 #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s) 152 #define RP2_UART_CTL_STOPBITS_m BIT(10) 153 154 #define RP2_BAUD 0x01c 155 156 /* ucode registers */ 157 #define RP2_TX_SWFLOW 0x02 158 #define RP2_TX_SWFLOW_ena 0x81 159 #define RP2_TX_SWFLOW_dis 0x9d 160 161 #define RP2_RX_SWFLOW 0x0c 162 #define RP2_RX_SWFLOW_ena 0x81 163 #define RP2_RX_SWFLOW_dis 0x8d 164 165 #define RP2_RX_FIFO 0x37 166 #define RP2_RX_FIFO_ena 0x08 167 #define RP2_RX_FIFO_dis 0x81 168 169 static struct uart_driver rp2_uart_driver = { 170 .owner = THIS_MODULE, 171 .driver_name = DRV_NAME, 172 .dev_name = "ttyRP", 173 .nr = CONFIG_SERIAL_RP2_NR_UARTS, 174 }; 175 176 struct rp2_card; 177 178 struct rp2_uart_port { 179 struct uart_port port; 180 int idx; 181 int ignore_rx; 182 struct rp2_card *card; 183 void __iomem *asic_base; 184 void __iomem *base; 185 void __iomem *ucode; 186 }; 187 188 struct rp2_card { 189 struct pci_dev *pdev; 190 struct rp2_uart_port *ports; 191 int n_ports; 192 int initialized_ports; 193 int minor_start; 194 int smpte; 195 void __iomem *bar0; 196 void __iomem *bar1; 197 spinlock_t card_lock; 198 struct completion fw_loaded; 199 }; 200 201 #define RP_ID(prod) PCI_VDEVICE(RP, (prod)) 202 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0)) 203 204 static inline void rp2_decode_cap(const struct pci_device_id *id, 205 int *ports, int *smpte) 206 { 207 *ports = id->driver_data >> 8; 208 *smpte = id->driver_data & 0xff; 209 } 210 211 static DEFINE_SPINLOCK(rp2_minor_lock); 212 static int rp2_minor_next; 213 214 static int rp2_alloc_ports(int n_ports) 215 { 216 int ret = -ENOSPC; 217 218 spin_lock(&rp2_minor_lock); 219 if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) { 220 /* sorry, no support for hot unplugging individual cards */ 221 ret = rp2_minor_next; 222 rp2_minor_next += n_ports; 223 } 224 spin_unlock(&rp2_minor_lock); 225 226 return ret; 227 } 228 229 static inline struct rp2_uart_port *port_to_up(struct uart_port *port) 230 { 231 return container_of(port, struct rp2_uart_port, port); 232 } 233 234 static void rp2_rmw(struct rp2_uart_port *up, int reg, 235 u32 clr_bits, u32 set_bits) 236 { 237 u32 tmp = readl(up->base + reg); 238 tmp &= ~clr_bits; 239 tmp |= set_bits; 240 writel(tmp, up->base + reg); 241 } 242 243 static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val) 244 { 245 rp2_rmw(up, reg, val, 0); 246 } 247 248 static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val) 249 { 250 rp2_rmw(up, reg, 0, val); 251 } 252 253 static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num, 254 int is_enabled) 255 { 256 unsigned long flags, irq_mask; 257 258 spin_lock_irqsave(&up->card->card_lock, flags); 259 260 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK); 261 if (is_enabled) 262 irq_mask &= ~BIT(ch_num); 263 else 264 irq_mask |= BIT(ch_num); 265 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK); 266 267 spin_unlock_irqrestore(&up->card->card_lock, flags); 268 } 269 270 static unsigned int rp2_uart_tx_empty(struct uart_port *port) 271 { 272 struct rp2_uart_port *up = port_to_up(port); 273 unsigned long tx_fifo_bytes, flags; 274 275 /* 276 * This should probably check the transmitter, not the FIFO. 277 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is 278 * enabled. 279 */ 280 spin_lock_irqsave(&up->port.lock, flags); 281 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT); 282 spin_unlock_irqrestore(&up->port.lock, flags); 283 284 return tx_fifo_bytes ? 0 : TIOCSER_TEMT; 285 } 286 287 static unsigned int rp2_uart_get_mctrl(struct uart_port *port) 288 { 289 struct rp2_uart_port *up = port_to_up(port); 290 u32 status; 291 292 status = readl(up->base + RP2_CHAN_STAT); 293 return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) | 294 ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) | 295 ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) | 296 ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0); 297 } 298 299 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 300 { 301 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, 302 RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m, 303 ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) | 304 ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) | 305 ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0)); 306 } 307 308 static void rp2_uart_start_tx(struct uart_port *port) 309 { 310 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); 311 } 312 313 static void rp2_uart_stop_tx(struct uart_port *port) 314 { 315 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); 316 } 317 318 static void rp2_uart_stop_rx(struct uart_port *port) 319 { 320 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m); 321 } 322 323 static void rp2_uart_break_ctl(struct uart_port *port, int break_state) 324 { 325 unsigned long flags; 326 327 spin_lock_irqsave(&port->lock, flags); 328 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m, 329 break_state ? RP2_TXRX_CTL_BREAK_m : 0); 330 spin_unlock_irqrestore(&port->lock, flags); 331 } 332 333 static void rp2_uart_enable_ms(struct uart_port *port) 334 { 335 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m); 336 } 337 338 static void __rp2_uart_set_termios(struct rp2_uart_port *up, 339 unsigned long cfl, 340 unsigned long ifl, 341 unsigned int baud_div) 342 { 343 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */ 344 writew(baud_div - 1, up->base + RP2_BAUD); 345 346 /* data bits and stop bits */ 347 rp2_rmw(up, RP2_UART_CTL, 348 RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m, 349 ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) | 350 (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) | 351 (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) | 352 (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) | 353 (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0)); 354 355 /* parity and hardware flow control */ 356 rp2_rmw(up, RP2_TXRX_CTL, 357 RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m | 358 RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m | 359 RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m | 360 RP2_TXRX_CTL_CTSFLOW_m, 361 ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) | 362 ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) | 363 ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) | 364 ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m | 365 RP2_TXRX_CTL_CTSFLOW_m) : 0)); 366 367 /* XON/XOFF software flow control */ 368 writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis, 369 up->ucode + RP2_TX_SWFLOW); 370 writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis, 371 up->ucode + RP2_RX_SWFLOW); 372 } 373 374 static void rp2_uart_set_termios(struct uart_port *port, 375 struct ktermios *new, 376 struct ktermios *old) 377 { 378 struct rp2_uart_port *up = port_to_up(port); 379 unsigned long flags; 380 unsigned int baud, baud_div; 381 382 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 383 baud_div = uart_get_divisor(port, baud); 384 385 if (tty_termios_baud_rate(new)) 386 tty_termios_encode_baud_rate(new, baud, baud); 387 388 spin_lock_irqsave(&port->lock, flags); 389 390 /* ignore all characters if CREAD is not set */ 391 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ; 392 393 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div); 394 uart_update_timeout(port, new->c_cflag, baud); 395 396 spin_unlock_irqrestore(&port->lock, flags); 397 } 398 399 static void rp2_rx_chars(struct rp2_uart_port *up) 400 { 401 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT); 402 struct tty_port *port = &up->port.state->port; 403 404 for (; bytes != 0; bytes--) { 405 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ; 406 char ch = byte & 0xff; 407 408 if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) { 409 if (!uart_handle_sysrq_char(&up->port, ch)) 410 uart_insert_char(&up->port, byte, 0, ch, 411 TTY_NORMAL); 412 } else { 413 char flag = TTY_NORMAL; 414 415 if (byte & RP2_DATA_BYTE_BREAK_m) 416 flag = TTY_BREAK; 417 else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m) 418 flag = TTY_FRAME; 419 else if (byte & RP2_DATA_BYTE_ERR_PARITY_m) 420 flag = TTY_PARITY; 421 uart_insert_char(&up->port, byte, 422 RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag); 423 } 424 up->port.icount.rx++; 425 } 426 427 spin_unlock(&up->port.lock); 428 tty_flip_buffer_push(port); 429 spin_lock(&up->port.lock); 430 } 431 432 static void rp2_tx_chars(struct rp2_uart_port *up) 433 { 434 u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT); 435 struct circ_buf *xmit = &up->port.state->xmit; 436 437 if (uart_tx_stopped(&up->port)) { 438 rp2_uart_stop_tx(&up->port); 439 return; 440 } 441 442 for (; max_tx != 0; max_tx--) { 443 if (up->port.x_char) { 444 writeb(up->port.x_char, up->base + RP2_DATA_BYTE); 445 up->port.x_char = 0; 446 up->port.icount.tx++; 447 continue; 448 } 449 if (uart_circ_empty(xmit)) { 450 rp2_uart_stop_tx(&up->port); 451 break; 452 } 453 writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE); 454 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 455 up->port.icount.tx++; 456 } 457 458 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 459 uart_write_wakeup(&up->port); 460 } 461 462 static void rp2_ch_interrupt(struct rp2_uart_port *up) 463 { 464 u32 status; 465 466 spin_lock(&up->port.lock); 467 468 /* 469 * The IRQ status bits are clear-on-write. Other status bits in 470 * this register aren't, so it's harmless to write to them. 471 */ 472 status = readl(up->base + RP2_CHAN_STAT); 473 writel(status, up->base + RP2_CHAN_STAT); 474 475 if (status & RP2_CHAN_STAT_RXDATA_m) 476 rp2_rx_chars(up); 477 if (status & RP2_CHAN_STAT_TXEMPTY_m) 478 rp2_tx_chars(up); 479 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK) 480 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 481 482 spin_unlock(&up->port.lock); 483 } 484 485 static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id) 486 { 487 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); 488 int ch, handled = 0; 489 unsigned long status = readl(base + RP2_CH_IRQ_STAT) & 490 ~readl(base + RP2_CH_IRQ_MASK); 491 492 for_each_set_bit(ch, &status, PORTS_PER_ASIC) { 493 rp2_ch_interrupt(&card->ports[ch]); 494 handled++; 495 } 496 return handled; 497 } 498 499 static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id) 500 { 501 struct rp2_card *card = dev_id; 502 int handled; 503 504 handled = rp2_asic_interrupt(card, 0); 505 if (card->n_ports >= PORTS_PER_ASIC) 506 handled += rp2_asic_interrupt(card, 1); 507 508 return handled ? IRQ_HANDLED : IRQ_NONE; 509 } 510 511 static inline void rp2_flush_fifos(struct rp2_uart_port *up) 512 { 513 rp2_rmw_set(up, RP2_UART_CTL, 514 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m); 515 readl(up->base + RP2_UART_CTL); 516 udelay(10); 517 rp2_rmw_clr(up, RP2_UART_CTL, 518 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m); 519 } 520 521 static int rp2_uart_startup(struct uart_port *port) 522 { 523 struct rp2_uart_port *up = port_to_up(port); 524 525 rp2_flush_fifos(up); 526 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m); 527 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m, 528 RP2_TXRX_CTL_RX_TRIG_1); 529 rp2_rmw(up, RP2_CHAN_STAT, 0, 0); 530 rp2_mask_ch_irq(up, up->idx, 1); 531 532 return 0; 533 } 534 535 static void rp2_uart_shutdown(struct uart_port *port) 536 { 537 struct rp2_uart_port *up = port_to_up(port); 538 unsigned long flags; 539 540 rp2_uart_break_ctl(port, 0); 541 542 spin_lock_irqsave(&port->lock, flags); 543 rp2_mask_ch_irq(up, up->idx, 0); 544 rp2_rmw(up, RP2_CHAN_STAT, 0, 0); 545 spin_unlock_irqrestore(&port->lock, flags); 546 } 547 548 static const char *rp2_uart_type(struct uart_port *port) 549 { 550 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL; 551 } 552 553 static void rp2_uart_release_port(struct uart_port *port) 554 { 555 /* Nothing to release ... */ 556 } 557 558 static int rp2_uart_request_port(struct uart_port *port) 559 { 560 /* UARTs always present */ 561 return 0; 562 } 563 564 static void rp2_uart_config_port(struct uart_port *port, int flags) 565 { 566 if (flags & UART_CONFIG_TYPE) 567 port->type = PORT_RP2; 568 } 569 570 static int rp2_uart_verify_port(struct uart_port *port, 571 struct serial_struct *ser) 572 { 573 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2) 574 return -EINVAL; 575 576 return 0; 577 } 578 579 static const struct uart_ops rp2_uart_ops = { 580 .tx_empty = rp2_uart_tx_empty, 581 .set_mctrl = rp2_uart_set_mctrl, 582 .get_mctrl = rp2_uart_get_mctrl, 583 .stop_tx = rp2_uart_stop_tx, 584 .start_tx = rp2_uart_start_tx, 585 .stop_rx = rp2_uart_stop_rx, 586 .enable_ms = rp2_uart_enable_ms, 587 .break_ctl = rp2_uart_break_ctl, 588 .startup = rp2_uart_startup, 589 .shutdown = rp2_uart_shutdown, 590 .set_termios = rp2_uart_set_termios, 591 .type = rp2_uart_type, 592 .release_port = rp2_uart_release_port, 593 .request_port = rp2_uart_request_port, 594 .config_port = rp2_uart_config_port, 595 .verify_port = rp2_uart_verify_port, 596 }; 597 598 static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id) 599 { 600 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); 601 u32 clk_cfg; 602 603 writew(1, base + RP2_GLOBAL_CMD); 604 readw(base + RP2_GLOBAL_CMD); 605 msleep(100); 606 writel(0, base + RP2_CLK_PRESCALER); 607 608 /* TDM clock configuration */ 609 clk_cfg = readw(base + RP2_ASIC_CFG); 610 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9); 611 writew(clk_cfg, base + RP2_ASIC_CFG); 612 613 /* IRQ routing */ 614 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK); 615 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ); 616 } 617 618 static void rp2_init_card(struct rp2_card *card) 619 { 620 writel(4, card->bar0 + RP2_FPGA_CTL0); 621 writel(0, card->bar0 + RP2_FPGA_CTL1); 622 623 rp2_reset_asic(card, 0); 624 if (card->n_ports >= PORTS_PER_ASIC) 625 rp2_reset_asic(card, 1); 626 627 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK); 628 } 629 630 static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw) 631 { 632 int i; 633 634 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL); 635 readl(up->base + RP2_UART_CTL); 636 udelay(1); 637 638 writel(0, up->base + RP2_TXRX_CTL); 639 writel(0, up->base + RP2_UART_CTL); 640 readl(up->base + RP2_UART_CTL); 641 udelay(1); 642 643 rp2_flush_fifos(up); 644 645 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++) 646 writeb(fw->data[i], up->ucode + i); 647 648 __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV); 649 rp2_uart_set_mctrl(&up->port, 0); 650 651 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO); 652 rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m, 653 RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232); 654 rp2_rmw_set(up, RP2_TXRX_CTL, 655 RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m); 656 } 657 658 static void rp2_remove_ports(struct rp2_card *card) 659 { 660 int i; 661 662 for (i = 0; i < card->initialized_ports; i++) 663 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port); 664 card->initialized_ports = 0; 665 } 666 667 static void rp2_fw_cb(const struct firmware *fw, void *context) 668 { 669 struct rp2_card *card = context; 670 resource_size_t phys_base; 671 int i, rc = -ENOENT; 672 673 if (!fw) { 674 dev_err(&card->pdev->dev, "cannot find '%s' firmware image\n", 675 RP2_FW_NAME); 676 goto no_fw; 677 } 678 679 phys_base = pci_resource_start(card->pdev, 1); 680 681 for (i = 0; i < card->n_ports; i++) { 682 struct rp2_uart_port *rp = &card->ports[i]; 683 struct uart_port *p; 684 int j = (unsigned)i % PORTS_PER_ASIC; 685 686 rp->asic_base = card->bar1; 687 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING; 688 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING; 689 rp->card = card; 690 rp->idx = j; 691 692 p = &rp->port; 693 p->line = card->minor_start + i; 694 p->dev = &card->pdev->dev; 695 p->type = PORT_RP2; 696 p->iotype = UPIO_MEM32; 697 p->uartclk = UART_CLOCK; 698 p->regshift = 2; 699 p->fifosize = FIFO_SIZE; 700 p->ops = &rp2_uart_ops; 701 p->irq = card->pdev->irq; 702 p->membase = rp->base; 703 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING; 704 705 if (i >= PORTS_PER_ASIC) { 706 rp->asic_base += RP2_ASIC_SPACING; 707 rp->base += RP2_ASIC_SPACING; 708 rp->ucode += RP2_ASIC_SPACING; 709 p->mapbase += RP2_ASIC_SPACING; 710 } 711 712 rp2_init_port(rp, fw); 713 rc = uart_add_one_port(&rp2_uart_driver, p); 714 if (rc) { 715 dev_err(&card->pdev->dev, 716 "error registering port %d: %d\n", i, rc); 717 rp2_remove_ports(card); 718 break; 719 } 720 card->initialized_ports++; 721 } 722 723 release_firmware(fw); 724 no_fw: 725 /* 726 * rp2_fw_cb() is called from a workqueue long after rp2_probe() 727 * has already returned success. So if something failed here, 728 * we'll just leave the now-dormant device in place until somebody 729 * unbinds it. 730 */ 731 if (rc) 732 dev_warn(&card->pdev->dev, "driver initialization failed\n"); 733 734 complete(&card->fw_loaded); 735 } 736 737 static int rp2_probe(struct pci_dev *pdev, 738 const struct pci_device_id *id) 739 { 740 struct rp2_card *card; 741 struct rp2_uart_port *ports; 742 void __iomem * const *bars; 743 int rc; 744 745 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 746 if (!card) 747 return -ENOMEM; 748 pci_set_drvdata(pdev, card); 749 spin_lock_init(&card->card_lock); 750 init_completion(&card->fw_loaded); 751 752 rc = pcim_enable_device(pdev); 753 if (rc) 754 return rc; 755 756 rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME); 757 if (rc) 758 return rc; 759 760 bars = pcim_iomap_table(pdev); 761 card->bar0 = bars[0]; 762 card->bar1 = bars[1]; 763 card->pdev = pdev; 764 765 rp2_decode_cap(id, &card->n_ports, &card->smpte); 766 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports); 767 768 card->minor_start = rp2_alloc_ports(card->n_ports); 769 if (card->minor_start < 0) { 770 dev_err(&pdev->dev, 771 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n"); 772 return -EINVAL; 773 } 774 775 rp2_init_card(card); 776 777 ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports), 778 GFP_KERNEL); 779 if (!ports) 780 return -ENOMEM; 781 card->ports = ports; 782 783 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt, 784 IRQF_SHARED, DRV_NAME, card); 785 if (rc) 786 return rc; 787 788 /* 789 * Only catastrophic errors (e.g. ENOMEM) are reported here. 790 * If the FW image is missing, we'll find out in rp2_fw_cb() 791 * and print an error message. 792 */ 793 rc = request_firmware_nowait(THIS_MODULE, 1, RP2_FW_NAME, &pdev->dev, 794 GFP_KERNEL, card, rp2_fw_cb); 795 if (rc) 796 return rc; 797 dev_dbg(&pdev->dev, "waiting for firmware blob...\n"); 798 799 return 0; 800 } 801 802 static void rp2_remove(struct pci_dev *pdev) 803 { 804 struct rp2_card *card = pci_get_drvdata(pdev); 805 806 wait_for_completion(&card->fw_loaded); 807 rp2_remove_ports(card); 808 } 809 810 static const struct pci_device_id rp2_pci_tbl[] = { 811 812 /* RocketPort INFINITY cards */ 813 814 { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */ 815 { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */ 816 { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */ 817 { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */ 818 { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */ 819 { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */ 820 { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */ 821 { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */ 822 { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */ 823 { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */ 824 { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */ 825 { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */ 826 { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */ 827 { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */ 828 { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */ 829 { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */ 830 { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */ 831 832 /* RocketPort EXPRESS cards */ 833 834 { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */ 835 { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */ 836 { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */ 837 { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */ 838 { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */ 839 { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */ 840 { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */ 841 { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */ 842 { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */ 843 { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */ 844 { } 845 }; 846 MODULE_DEVICE_TABLE(pci, rp2_pci_tbl); 847 848 static struct pci_driver rp2_pci_driver = { 849 .name = DRV_NAME, 850 .id_table = rp2_pci_tbl, 851 .probe = rp2_probe, 852 .remove = rp2_remove, 853 }; 854 855 static int __init rp2_uart_init(void) 856 { 857 int rc; 858 859 rc = uart_register_driver(&rp2_uart_driver); 860 if (rc) 861 return rc; 862 863 rc = pci_register_driver(&rp2_pci_driver); 864 if (rc) { 865 uart_unregister_driver(&rp2_uart_driver); 866 return rc; 867 } 868 869 return 0; 870 } 871 872 static void __exit rp2_uart_exit(void) 873 { 874 pci_unregister_driver(&rp2_pci_driver); 875 uart_unregister_driver(&rp2_uart_driver); 876 } 877 878 module_init(rp2_uart_init); 879 module_exit(rp2_uart_exit); 880 881 MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver"); 882 MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>"); 883 MODULE_LICENSE("GPL v2"); 884 MODULE_FIRMWARE(RP2_FW_NAME); 885