1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/qcom-geni-se.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 26 /* UART specific GENI registers */ 27 #define SE_UART_LOOPBACK_CFG 0x22c 28 #define SE_UART_IO_MACRO_CTRL 0x240 29 #define SE_UART_TX_TRANS_CFG 0x25c 30 #define SE_UART_TX_WORD_LEN 0x268 31 #define SE_UART_TX_STOP_BIT_LEN 0x26c 32 #define SE_UART_TX_TRANS_LEN 0x270 33 #define SE_UART_RX_TRANS_CFG 0x280 34 #define SE_UART_RX_WORD_LEN 0x28c 35 #define SE_UART_RX_STALE_CNT 0x294 36 #define SE_UART_TX_PARITY_CFG 0x2a4 37 #define SE_UART_RX_PARITY_CFG 0x2a8 38 #define SE_UART_MANUAL_RFR 0x2ac 39 40 /* SE_UART_TRANS_CFG */ 41 #define UART_TX_PAR_EN BIT(0) 42 #define UART_CTS_MASK BIT(1) 43 44 /* SE_UART_TX_WORD_LEN */ 45 #define TX_WORD_LEN_MSK GENMASK(9, 0) 46 47 /* SE_UART_TX_STOP_BIT_LEN */ 48 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) 49 #define TX_STOP_BIT_LEN_1 0 50 #define TX_STOP_BIT_LEN_1_5 1 51 #define TX_STOP_BIT_LEN_2 2 52 53 /* SE_UART_TX_TRANS_LEN */ 54 #define TX_TRANS_LEN_MSK GENMASK(23, 0) 55 56 /* SE_UART_RX_TRANS_CFG */ 57 #define UART_RX_INS_STATUS_BIT BIT(2) 58 #define UART_RX_PAR_EN BIT(3) 59 60 /* SE_UART_RX_WORD_LEN */ 61 #define RX_WORD_LEN_MASK GENMASK(9, 0) 62 63 /* SE_UART_RX_STALE_CNT */ 64 #define RX_STALE_CNT GENMASK(23, 0) 65 66 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 67 #define PAR_CALC_EN BIT(0) 68 #define PAR_MODE_MSK GENMASK(2, 1) 69 #define PAR_MODE_SHFT 1 70 #define PAR_EVEN 0x00 71 #define PAR_ODD 0x01 72 #define PAR_SPACE 0x10 73 #define PAR_MARK 0x11 74 75 /* SE_UART_MANUAL_RFR register fields */ 76 #define UART_MANUAL_RFR_EN BIT(31) 77 #define UART_RFR_NOT_READY BIT(1) 78 #define UART_RFR_READY BIT(0) 79 80 /* UART M_CMD OP codes */ 81 #define UART_START_TX 0x1 82 #define UART_START_BREAK 0x4 83 #define UART_STOP_BREAK 0x5 84 /* UART S_CMD OP codes */ 85 #define UART_START_READ 0x1 86 #define UART_PARAM 0x1 87 88 #define UART_OVERSAMPLING 32 89 #define STALE_TIMEOUT 16 90 #define DEFAULT_BITS_PER_CHAR 10 91 #define GENI_UART_CONS_PORTS 1 92 #define GENI_UART_PORTS 3 93 #define DEF_FIFO_DEPTH_WORDS 16 94 #define DEF_TX_WM 2 95 #define DEF_FIFO_WIDTH_BITS 32 96 #define UART_RX_WM 2 97 98 /* SE_UART_LOOPBACK_CFG */ 99 #define RX_TX_SORTED BIT(0) 100 #define CTS_RTS_SORTED BIT(1) 101 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 102 103 /* UART pin swap value */ 104 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 105 #define IO_MACRO_IO0_SEL 0x3 106 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 107 #define IO_MACRO_IO2_IO3_SWAP 0x4640 108 109 /* We always configure 4 bytes per FIFO word */ 110 #define BYTES_PER_FIFO_WORD 4 111 112 struct qcom_geni_private_data { 113 /* NOTE: earlycon port will have NULL here */ 114 struct uart_driver *drv; 115 116 u32 poll_cached_bytes; 117 unsigned int poll_cached_bytes_cnt; 118 119 u32 write_cached_bytes; 120 unsigned int write_cached_bytes_cnt; 121 }; 122 123 struct qcom_geni_serial_port { 124 struct uart_port uport; 125 struct geni_se se; 126 const char *name; 127 u32 tx_fifo_depth; 128 u32 tx_fifo_width; 129 u32 rx_fifo_depth; 130 bool setup; 131 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); 132 unsigned int baud; 133 void *rx_fifo; 134 u32 loopback; 135 bool brk; 136 137 unsigned int tx_remaining; 138 int wakeup_irq; 139 bool rx_tx_swap; 140 bool cts_rts_swap; 141 142 struct qcom_geni_private_data private_data; 143 }; 144 145 static const struct uart_ops qcom_geni_console_pops; 146 static const struct uart_ops qcom_geni_uart_pops; 147 static struct uart_driver qcom_geni_console_driver; 148 static struct uart_driver qcom_geni_uart_driver; 149 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); 150 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); 151 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); 152 static void qcom_geni_serial_stop_rx(struct uart_port *uport); 153 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); 154 155 #define to_dev_port(ptr, member) \ 156 container_of(ptr, struct qcom_geni_serial_port, member) 157 158 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 159 [0] = { 160 .uport = { 161 .iotype = UPIO_MEM, 162 .ops = &qcom_geni_uart_pops, 163 .flags = UPF_BOOT_AUTOCONF, 164 .line = 0, 165 }, 166 }, 167 [1] = { 168 .uport = { 169 .iotype = UPIO_MEM, 170 .ops = &qcom_geni_uart_pops, 171 .flags = UPF_BOOT_AUTOCONF, 172 .line = 1, 173 }, 174 }, 175 [2] = { 176 .uport = { 177 .iotype = UPIO_MEM, 178 .ops = &qcom_geni_uart_pops, 179 .flags = UPF_BOOT_AUTOCONF, 180 .line = 2, 181 }, 182 }, 183 }; 184 185 static struct qcom_geni_serial_port qcom_geni_console_port = { 186 .uport = { 187 .iotype = UPIO_MEM, 188 .ops = &qcom_geni_console_pops, 189 .flags = UPF_BOOT_AUTOCONF, 190 .line = 0, 191 }, 192 }; 193 194 static int qcom_geni_serial_request_port(struct uart_port *uport) 195 { 196 struct platform_device *pdev = to_platform_device(uport->dev); 197 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 198 199 uport->membase = devm_platform_ioremap_resource(pdev, 0); 200 if (IS_ERR(uport->membase)) 201 return PTR_ERR(uport->membase); 202 port->se.base = uport->membase; 203 return 0; 204 } 205 206 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 207 { 208 if (cfg_flags & UART_CONFIG_TYPE) { 209 uport->type = PORT_MSM; 210 qcom_geni_serial_request_port(uport); 211 } 212 } 213 214 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 215 { 216 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 217 u32 geni_ios; 218 219 if (uart_console(uport)) { 220 mctrl |= TIOCM_CTS; 221 } else { 222 geni_ios = readl(uport->membase + SE_GENI_IOS); 223 if (!(geni_ios & IO2_DATA_IN)) 224 mctrl |= TIOCM_CTS; 225 } 226 227 return mctrl; 228 } 229 230 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 231 unsigned int mctrl) 232 { 233 u32 uart_manual_rfr = 0; 234 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 235 236 if (uart_console(uport)) 237 return; 238 239 if (mctrl & TIOCM_LOOP) 240 port->loopback = RX_TX_CTS_RTS_SORTED; 241 242 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 243 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 244 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 245 } 246 247 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 248 { 249 return "MSM"; 250 } 251 252 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 253 { 254 struct qcom_geni_serial_port *port; 255 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 256 257 if (line < 0 || line >= nr_ports) 258 return ERR_PTR(-ENXIO); 259 260 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 261 return port; 262 } 263 264 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 265 int offset, int field, bool set) 266 { 267 u32 reg; 268 struct qcom_geni_serial_port *port; 269 unsigned int baud; 270 unsigned int fifo_bits; 271 unsigned long timeout_us = 20000; 272 struct qcom_geni_private_data *private_data = uport->private_data; 273 274 if (private_data->drv) { 275 port = to_dev_port(uport, uport); 276 baud = port->baud; 277 if (!baud) 278 baud = 115200; 279 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 280 /* 281 * Total polling iterations based on FIFO worth of bytes to be 282 * sent at current baud. Add a little fluff to the wait. 283 */ 284 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 285 } 286 287 /* 288 * Use custom implementation instead of readl_poll_atomic since ktimer 289 * is not ready at the time of early console. 290 */ 291 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 292 while (timeout_us) { 293 reg = readl(uport->membase + offset); 294 if ((bool)(reg & field) == set) 295 return true; 296 udelay(10); 297 timeout_us -= 10; 298 } 299 return false; 300 } 301 302 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 303 { 304 u32 m_cmd; 305 306 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 307 m_cmd = UART_START_TX << M_OPCODE_SHFT; 308 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 309 } 310 311 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 312 { 313 int done; 314 u32 irq_clear = M_CMD_DONE_EN; 315 316 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 317 M_CMD_DONE_EN, true); 318 if (!done) { 319 writel(M_GENI_CMD_ABORT, uport->membase + 320 SE_GENI_M_CMD_CTRL_REG); 321 irq_clear |= M_CMD_ABORT_EN; 322 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 323 M_CMD_ABORT_EN, true); 324 } 325 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 326 } 327 328 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 329 { 330 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 331 332 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 333 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 334 S_GENI_CMD_ABORT, false); 335 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 336 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 337 } 338 339 #ifdef CONFIG_CONSOLE_POLL 340 341 static int qcom_geni_serial_get_char(struct uart_port *uport) 342 { 343 struct qcom_geni_private_data *private_data = uport->private_data; 344 u32 status; 345 u32 word_cnt; 346 int ret; 347 348 if (!private_data->poll_cached_bytes_cnt) { 349 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 350 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 351 352 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 353 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 354 355 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 356 word_cnt = status & RX_FIFO_WC_MSK; 357 if (!word_cnt) 358 return NO_POLL_CHAR; 359 360 if (word_cnt == 1 && (status & RX_LAST)) 361 /* 362 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 363 * treated as if it was BYTES_PER_FIFO_WORD. 364 */ 365 private_data->poll_cached_bytes_cnt = 366 (status & RX_LAST_BYTE_VALID_MSK) >> 367 RX_LAST_BYTE_VALID_SHFT; 368 369 if (private_data->poll_cached_bytes_cnt == 0) 370 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 371 372 private_data->poll_cached_bytes = 373 readl(uport->membase + SE_GENI_RX_FIFOn); 374 } 375 376 private_data->poll_cached_bytes_cnt--; 377 ret = private_data->poll_cached_bytes & 0xff; 378 private_data->poll_cached_bytes >>= 8; 379 380 return ret; 381 } 382 383 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 384 unsigned char c) 385 { 386 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 387 qcom_geni_serial_setup_tx(uport, 1); 388 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 389 M_TX_FIFO_WATERMARK_EN, true)); 390 writel(c, uport->membase + SE_GENI_TX_FIFOn); 391 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 392 qcom_geni_serial_poll_tx_done(uport); 393 } 394 #endif 395 396 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 397 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 398 { 399 struct qcom_geni_private_data *private_data = uport->private_data; 400 401 private_data->write_cached_bytes = 402 (private_data->write_cached_bytes >> 8) | (ch << 24); 403 private_data->write_cached_bytes_cnt++; 404 405 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 406 writel(private_data->write_cached_bytes, 407 uport->membase + SE_GENI_TX_FIFOn); 408 private_data->write_cached_bytes_cnt = 0; 409 } 410 } 411 412 static void 413 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 414 unsigned int count) 415 { 416 struct qcom_geni_private_data *private_data = uport->private_data; 417 418 int i; 419 u32 bytes_to_send = count; 420 421 for (i = 0; i < count; i++) { 422 /* 423 * uart_console_write() adds a carriage return for each newline. 424 * Account for additional bytes to be written. 425 */ 426 if (s[i] == '\n') 427 bytes_to_send++; 428 } 429 430 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 431 qcom_geni_serial_setup_tx(uport, bytes_to_send); 432 for (i = 0; i < count; ) { 433 size_t chars_to_write = 0; 434 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 435 436 /* 437 * If the WM bit never set, then the Tx state machine is not 438 * in a valid state, so break, cancel/abort any existing 439 * command. Unfortunately the current data being written is 440 * lost. 441 */ 442 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 443 M_TX_FIFO_WATERMARK_EN, true)) 444 break; 445 chars_to_write = min_t(size_t, count - i, avail / 2); 446 uart_console_write(uport, s + i, chars_to_write, 447 qcom_geni_serial_wr_char); 448 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 449 SE_GENI_M_IRQ_CLEAR); 450 i += chars_to_write; 451 } 452 453 if (private_data->write_cached_bytes_cnt) { 454 private_data->write_cached_bytes >>= BITS_PER_BYTE * 455 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 456 writel(private_data->write_cached_bytes, 457 uport->membase + SE_GENI_TX_FIFOn); 458 private_data->write_cached_bytes_cnt = 0; 459 } 460 461 qcom_geni_serial_poll_tx_done(uport); 462 } 463 464 static void qcom_geni_serial_console_write(struct console *co, const char *s, 465 unsigned int count) 466 { 467 struct uart_port *uport; 468 struct qcom_geni_serial_port *port; 469 bool locked = true; 470 unsigned long flags; 471 u32 geni_status; 472 u32 irq_en; 473 474 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 475 476 port = get_port_from_line(co->index, true); 477 if (IS_ERR(port)) 478 return; 479 480 uport = &port->uport; 481 if (oops_in_progress) 482 locked = spin_trylock_irqsave(&uport->lock, flags); 483 else 484 spin_lock_irqsave(&uport->lock, flags); 485 486 geni_status = readl(uport->membase + SE_GENI_STATUS); 487 488 /* Cancel the current write to log the fault */ 489 if (!locked) { 490 geni_se_cancel_m_cmd(&port->se); 491 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 492 M_CMD_CANCEL_EN, true)) { 493 geni_se_abort_m_cmd(&port->se); 494 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 495 M_CMD_ABORT_EN, true); 496 writel(M_CMD_ABORT_EN, uport->membase + 497 SE_GENI_M_IRQ_CLEAR); 498 } 499 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 500 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 501 /* 502 * It seems we can't interrupt existing transfers if all data 503 * has been sent, in which case we need to look for done first. 504 */ 505 qcom_geni_serial_poll_tx_done(uport); 506 507 if (!uart_circ_empty(&uport->state->xmit)) { 508 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 509 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 510 uport->membase + SE_GENI_M_IRQ_EN); 511 } 512 } 513 514 __qcom_geni_serial_console_write(uport, s, count); 515 516 if (port->tx_remaining) 517 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 518 519 if (locked) 520 spin_unlock_irqrestore(&uport->lock, flags); 521 } 522 523 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 524 { 525 u32 i; 526 unsigned char buf[sizeof(u32)]; 527 struct tty_port *tport; 528 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 529 530 tport = &uport->state->port; 531 for (i = 0; i < bytes; ) { 532 int c; 533 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 534 535 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 536 i += chunk; 537 if (drop) 538 continue; 539 540 for (c = 0; c < chunk; c++) { 541 int sysrq; 542 543 uport->icount.rx++; 544 if (port->brk && buf[c] == 0) { 545 port->brk = false; 546 if (uart_handle_break(uport)) 547 continue; 548 } 549 550 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 551 552 if (!sysrq) 553 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 554 } 555 } 556 if (!drop) 557 tty_flip_buffer_push(tport); 558 return 0; 559 } 560 #else 561 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 562 { 563 return -EPERM; 564 } 565 566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 567 568 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 569 { 570 struct tty_port *tport; 571 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 572 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; 573 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; 574 int ret; 575 576 tport = &uport->state->port; 577 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); 578 if (drop) 579 return 0; 580 581 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); 582 if (ret != bytes) { 583 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 584 __func__, ret, bytes); 585 WARN_ON_ONCE(1); 586 } 587 uport->icount.rx += ret; 588 tty_flip_buffer_push(tport); 589 return ret; 590 } 591 592 static void qcom_geni_serial_start_tx(struct uart_port *uport) 593 { 594 u32 irq_en; 595 u32 status; 596 597 status = readl(uport->membase + SE_GENI_STATUS); 598 if (status & M_GENI_CMD_ACTIVE) 599 return; 600 601 if (!qcom_geni_serial_tx_empty(uport)) 602 return; 603 604 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 605 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 606 607 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 608 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 609 } 610 611 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 612 { 613 u32 irq_en; 614 u32 status; 615 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 616 617 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 618 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 619 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 620 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 621 status = readl(uport->membase + SE_GENI_STATUS); 622 /* Possible stop tx is called multiple times. */ 623 if (!(status & M_GENI_CMD_ACTIVE)) 624 return; 625 626 geni_se_cancel_m_cmd(&port->se); 627 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 628 M_CMD_CANCEL_EN, true)) { 629 geni_se_abort_m_cmd(&port->se); 630 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 631 M_CMD_ABORT_EN, true); 632 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 633 } 634 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 635 } 636 637 static void qcom_geni_serial_start_rx(struct uart_port *uport) 638 { 639 u32 irq_en; 640 u32 status; 641 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 642 643 status = readl(uport->membase + SE_GENI_STATUS); 644 if (status & S_GENI_CMD_ACTIVE) 645 qcom_geni_serial_stop_rx(uport); 646 647 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 648 649 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 650 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 651 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 652 653 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 654 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 655 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 656 } 657 658 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 659 { 660 u32 irq_en; 661 u32 status; 662 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 663 u32 s_irq_status; 664 665 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 666 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 667 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 668 669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 670 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 671 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 672 673 status = readl(uport->membase + SE_GENI_STATUS); 674 /* Possible stop rx is called multiple times. */ 675 if (!(status & S_GENI_CMD_ACTIVE)) 676 return; 677 678 geni_se_cancel_s_cmd(&port->se); 679 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 680 S_CMD_CANCEL_EN, true); 681 /* 682 * If timeout occurs secondary engine remains active 683 * and Abort sequence is executed. 684 */ 685 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 686 /* Flush the Rx buffer */ 687 if (s_irq_status & S_RX_FIFO_LAST_EN) 688 qcom_geni_serial_handle_rx(uport, true); 689 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 690 691 status = readl(uport->membase + SE_GENI_STATUS); 692 if (status & S_GENI_CMD_ACTIVE) 693 qcom_geni_serial_abort_rx(uport); 694 } 695 696 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) 697 { 698 u32 status; 699 u32 word_cnt; 700 u32 last_word_byte_cnt; 701 u32 last_word_partial; 702 u32 total_bytes; 703 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 704 705 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 706 word_cnt = status & RX_FIFO_WC_MSK; 707 last_word_partial = status & RX_LAST; 708 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 709 RX_LAST_BYTE_VALID_SHFT; 710 711 if (!word_cnt) 712 return; 713 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 714 if (last_word_partial && last_word_byte_cnt) 715 total_bytes += last_word_byte_cnt; 716 else 717 total_bytes += BYTES_PER_FIFO_WORD; 718 port->handle_rx(uport, total_bytes, drop); 719 } 720 721 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, 722 bool active) 723 { 724 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 725 struct circ_buf *xmit = &uport->state->xmit; 726 size_t avail; 727 size_t remaining; 728 size_t pending; 729 int i; 730 u32 status; 731 u32 irq_en; 732 unsigned int chunk; 733 int tail; 734 735 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 736 737 /* Complete the current tx command before taking newly added data */ 738 if (active) 739 pending = port->tx_remaining; 740 else 741 pending = uart_circ_chars_pending(xmit); 742 743 /* All data has been transmitted and acknowledged as received */ 744 if (!pending && !status && done) { 745 qcom_geni_serial_stop_tx(uport); 746 goto out_write_wakeup; 747 } 748 749 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 750 avail *= BYTES_PER_FIFO_WORD; 751 752 tail = xmit->tail; 753 chunk = min(avail, pending); 754 if (!chunk) 755 goto out_write_wakeup; 756 757 if (!port->tx_remaining) { 758 qcom_geni_serial_setup_tx(uport, pending); 759 port->tx_remaining = pending; 760 761 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 762 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 763 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 764 uport->membase + SE_GENI_M_IRQ_EN); 765 } 766 767 remaining = chunk; 768 for (i = 0; i < chunk; ) { 769 unsigned int tx_bytes; 770 u8 buf[sizeof(u32)]; 771 int c; 772 773 memset(buf, 0, sizeof(buf)); 774 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD); 775 776 for (c = 0; c < tx_bytes ; c++) { 777 buf[c] = xmit->buf[tail++]; 778 tail &= UART_XMIT_SIZE - 1; 779 } 780 781 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 782 783 i += tx_bytes; 784 uport->icount.tx += tx_bytes; 785 remaining -= tx_bytes; 786 port->tx_remaining -= tx_bytes; 787 } 788 789 xmit->tail = tail; 790 791 /* 792 * The tx fifo watermark is level triggered and latched. Though we had 793 * cleared it in qcom_geni_serial_isr it will have already reasserted 794 * so we must clear it again here after our writes. 795 */ 796 writel(M_TX_FIFO_WATERMARK_EN, 797 uport->membase + SE_GENI_M_IRQ_CLEAR); 798 799 out_write_wakeup: 800 if (!port->tx_remaining) { 801 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 802 if (irq_en & M_TX_FIFO_WATERMARK_EN) 803 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 804 uport->membase + SE_GENI_M_IRQ_EN); 805 } 806 807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 808 uart_write_wakeup(uport); 809 } 810 811 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 812 { 813 u32 m_irq_en; 814 u32 m_irq_status; 815 u32 s_irq_status; 816 u32 geni_status; 817 struct uart_port *uport = dev; 818 bool drop_rx = false; 819 struct tty_port *tport = &uport->state->port; 820 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 821 822 if (uport->suspended) 823 return IRQ_NONE; 824 825 spin_lock(&uport->lock); 826 827 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 828 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 829 geni_status = readl(uport->membase + SE_GENI_STATUS); 830 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 831 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 832 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 833 834 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 835 goto out_unlock; 836 837 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 838 uport->icount.overrun++; 839 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 840 } 841 842 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 843 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, 844 geni_status & M_GENI_CMD_ACTIVE); 845 846 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { 847 if (s_irq_status & S_GP_IRQ_0_EN) 848 uport->icount.parity++; 849 drop_rx = true; 850 } else if (s_irq_status & S_GP_IRQ_2_EN || 851 s_irq_status & S_GP_IRQ_3_EN) { 852 uport->icount.brk++; 853 port->brk = true; 854 } 855 856 if (s_irq_status & S_RX_FIFO_WATERMARK_EN || 857 s_irq_status & S_RX_FIFO_LAST_EN) 858 qcom_geni_serial_handle_rx(uport, drop_rx); 859 860 out_unlock: 861 uart_unlock_and_check_sysrq(uport); 862 863 return IRQ_HANDLED; 864 } 865 866 static void get_tx_fifo_size(struct qcom_geni_serial_port *port) 867 { 868 struct uart_port *uport; 869 870 uport = &port->uport; 871 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 872 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 873 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 874 uport->fifosize = 875 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 876 } 877 878 879 static void qcom_geni_serial_shutdown(struct uart_port *uport) 880 { 881 disable_irq(uport->irq); 882 } 883 884 static int qcom_geni_serial_port_setup(struct uart_port *uport) 885 { 886 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 887 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 888 u32 proto; 889 u32 pin_swap; 890 891 proto = geni_se_read_proto(&port->se); 892 if (proto != GENI_SE_UART) { 893 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 894 return -ENXIO; 895 } 896 897 qcom_geni_serial_stop_rx(uport); 898 899 get_tx_fifo_size(port); 900 901 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 902 903 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 904 if (port->rx_tx_swap) { 905 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 906 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 907 } 908 if (port->cts_rts_swap) { 909 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 910 pin_swap |= IO_MACRO_IO0_SEL; 911 } 912 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 913 if (port->rx_tx_swap || port->cts_rts_swap) 914 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 915 916 /* 917 * Make an unconditional cancel on the main sequencer to reset 918 * it else we could end up in data loss scenarios. 919 */ 920 if (uart_console(uport)) 921 qcom_geni_serial_poll_tx_done(uport); 922 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 923 false, true, true); 924 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 925 geni_se_select_mode(&port->se, GENI_SE_FIFO); 926 port->setup = true; 927 928 return 0; 929 } 930 931 static int qcom_geni_serial_startup(struct uart_port *uport) 932 { 933 int ret; 934 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 935 936 if (!port->setup) { 937 ret = qcom_geni_serial_port_setup(uport); 938 if (ret) 939 return ret; 940 } 941 enable_irq(uport->irq); 942 943 return 0; 944 } 945 946 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 947 unsigned int *clk_div, unsigned int percent_tol) 948 { 949 unsigned long freq; 950 unsigned long div, maxdiv; 951 u64 mult; 952 unsigned long offset, abs_tol, achieved; 953 954 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 955 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 956 div = 1; 957 while (div <= maxdiv) { 958 mult = (u64)div * desired_clk; 959 if (mult != (unsigned long)mult) 960 break; 961 962 offset = div * abs_tol; 963 freq = clk_round_rate(clk, mult - offset); 964 965 /* Can only get lower if we're done */ 966 if (freq < mult - offset) 967 break; 968 969 /* 970 * Re-calculate div in case rounding skipped rates but we 971 * ended up at a good one, then check for a match. 972 */ 973 div = DIV_ROUND_CLOSEST(freq, desired_clk); 974 achieved = DIV_ROUND_CLOSEST(freq, div); 975 if (achieved <= desired_clk + abs_tol && 976 achieved >= desired_clk - abs_tol) { 977 *clk_div = div; 978 return freq; 979 } 980 981 div = DIV_ROUND_UP(freq, desired_clk); 982 } 983 984 return 0; 985 } 986 987 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 988 unsigned int sampling_rate, unsigned int *clk_div) 989 { 990 unsigned long ser_clk; 991 unsigned long desired_clk; 992 993 desired_clk = baud * sampling_rate; 994 if (!desired_clk) 995 return 0; 996 997 /* 998 * try to find a clock rate within 2% tolerance, then within 5% 999 */ 1000 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1001 if (!ser_clk) 1002 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1003 1004 return ser_clk; 1005 } 1006 1007 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1008 struct ktermios *termios, struct ktermios *old) 1009 { 1010 unsigned int baud; 1011 u32 bits_per_char; 1012 u32 tx_trans_cfg; 1013 u32 tx_parity_cfg; 1014 u32 rx_trans_cfg; 1015 u32 rx_parity_cfg; 1016 u32 stop_bit_len; 1017 unsigned int clk_div; 1018 u32 ser_clk_cfg; 1019 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1020 unsigned long clk_rate; 1021 u32 ver, sampling_rate; 1022 unsigned int avg_bw_core; 1023 1024 qcom_geni_serial_stop_rx(uport); 1025 /* baud rate */ 1026 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1027 port->baud = baud; 1028 1029 sampling_rate = UART_OVERSAMPLING; 1030 /* Sampling rate is halved for IP versions >= 2.5 */ 1031 ver = geni_se_get_qup_hw_version(&port->se); 1032 if (ver >= QUP_SE_VERSION_2_5) 1033 sampling_rate /= 2; 1034 1035 clk_rate = get_clk_div_rate(port->se.clk, baud, 1036 sampling_rate, &clk_div); 1037 if (!clk_rate) { 1038 dev_err(port->se.dev, 1039 "Couldn't find suitable clock rate for %u\n", 1040 baud * sampling_rate); 1041 goto out_restart_rx; 1042 } 1043 1044 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", 1045 baud * sampling_rate, clk_rate, clk_div); 1046 1047 uport->uartclk = clk_rate; 1048 dev_pm_opp_set_rate(uport->dev, clk_rate); 1049 ser_clk_cfg = SER_CLK_EN; 1050 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1051 1052 /* 1053 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1054 * only. 1055 */ 1056 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1057 : GENI_DEFAULT_BW; 1058 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1059 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1060 geni_icc_set_bw(&port->se); 1061 1062 /* parity */ 1063 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1064 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1065 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1066 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1067 if (termios->c_cflag & PARENB) { 1068 tx_trans_cfg |= UART_TX_PAR_EN; 1069 rx_trans_cfg |= UART_RX_PAR_EN; 1070 tx_parity_cfg |= PAR_CALC_EN; 1071 rx_parity_cfg |= PAR_CALC_EN; 1072 if (termios->c_cflag & PARODD) { 1073 tx_parity_cfg |= PAR_ODD; 1074 rx_parity_cfg |= PAR_ODD; 1075 } else if (termios->c_cflag & CMSPAR) { 1076 tx_parity_cfg |= PAR_SPACE; 1077 rx_parity_cfg |= PAR_SPACE; 1078 } else { 1079 tx_parity_cfg |= PAR_EVEN; 1080 rx_parity_cfg |= PAR_EVEN; 1081 } 1082 } else { 1083 tx_trans_cfg &= ~UART_TX_PAR_EN; 1084 rx_trans_cfg &= ~UART_RX_PAR_EN; 1085 tx_parity_cfg &= ~PAR_CALC_EN; 1086 rx_parity_cfg &= ~PAR_CALC_EN; 1087 } 1088 1089 /* bits per char */ 1090 bits_per_char = tty_get_char_size(termios->c_cflag); 1091 1092 /* stop bits */ 1093 if (termios->c_cflag & CSTOPB) 1094 stop_bit_len = TX_STOP_BIT_LEN_2; 1095 else 1096 stop_bit_len = TX_STOP_BIT_LEN_1; 1097 1098 /* flow control, clear the CTS_MASK bit if using flow control. */ 1099 if (termios->c_cflag & CRTSCTS) 1100 tx_trans_cfg &= ~UART_CTS_MASK; 1101 else 1102 tx_trans_cfg |= UART_CTS_MASK; 1103 1104 if (baud) 1105 uart_update_timeout(uport, termios->c_cflag, baud); 1106 1107 if (!uart_console(uport)) 1108 writel(port->loopback, 1109 uport->membase + SE_UART_LOOPBACK_CFG); 1110 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1111 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1112 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1113 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1114 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1115 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1116 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1117 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1118 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1119 out_restart_rx: 1120 qcom_geni_serial_start_rx(uport); 1121 } 1122 1123 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 1124 { 1125 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1126 } 1127 1128 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1129 static int qcom_geni_console_setup(struct console *co, char *options) 1130 { 1131 struct uart_port *uport; 1132 struct qcom_geni_serial_port *port; 1133 int baud = 115200; 1134 int bits = 8; 1135 int parity = 'n'; 1136 int flow = 'n'; 1137 int ret; 1138 1139 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1140 return -ENXIO; 1141 1142 port = get_port_from_line(co->index, true); 1143 if (IS_ERR(port)) { 1144 pr_err("Invalid line %d\n", co->index); 1145 return PTR_ERR(port); 1146 } 1147 1148 uport = &port->uport; 1149 1150 if (unlikely(!uport->membase)) 1151 return -ENXIO; 1152 1153 if (!port->setup) { 1154 ret = qcom_geni_serial_port_setup(uport); 1155 if (ret) 1156 return ret; 1157 } 1158 1159 if (options) 1160 uart_parse_options(options, &baud, &parity, &bits, &flow); 1161 1162 return uart_set_options(uport, co, baud, parity, bits, flow); 1163 } 1164 1165 static void qcom_geni_serial_earlycon_write(struct console *con, 1166 const char *s, unsigned int n) 1167 { 1168 struct earlycon_device *dev = con->data; 1169 1170 __qcom_geni_serial_console_write(&dev->port, s, n); 1171 } 1172 1173 #ifdef CONFIG_CONSOLE_POLL 1174 static int qcom_geni_serial_earlycon_read(struct console *con, 1175 char *s, unsigned int n) 1176 { 1177 struct earlycon_device *dev = con->data; 1178 struct uart_port *uport = &dev->port; 1179 int num_read = 0; 1180 int ch; 1181 1182 while (num_read < n) { 1183 ch = qcom_geni_serial_get_char(uport); 1184 if (ch == NO_POLL_CHAR) 1185 break; 1186 s[num_read++] = ch; 1187 } 1188 1189 return num_read; 1190 } 1191 1192 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1193 struct console *con) 1194 { 1195 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1196 con->read = qcom_geni_serial_earlycon_read; 1197 } 1198 #else 1199 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1200 struct console *con) { } 1201 #endif 1202 1203 static struct qcom_geni_private_data earlycon_private_data; 1204 1205 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1206 const char *opt) 1207 { 1208 struct uart_port *uport = &dev->port; 1209 u32 tx_trans_cfg; 1210 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1211 u32 rx_trans_cfg = 0; 1212 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1213 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1214 u32 bits_per_char; 1215 struct geni_se se; 1216 1217 if (!uport->membase) 1218 return -EINVAL; 1219 1220 uport->private_data = &earlycon_private_data; 1221 1222 memset(&se, 0, sizeof(se)); 1223 se.base = uport->membase; 1224 if (geni_se_read_proto(&se) != GENI_SE_UART) 1225 return -ENXIO; 1226 /* 1227 * Ignore Flow control. 1228 * n = 8. 1229 */ 1230 tx_trans_cfg = UART_CTS_MASK; 1231 bits_per_char = BITS_PER_BYTE; 1232 1233 /* 1234 * Make an unconditional cancel on the main sequencer to reset 1235 * it else we could end up in data loss scenarios. 1236 */ 1237 qcom_geni_serial_poll_tx_done(uport); 1238 qcom_geni_serial_abort_rx(uport); 1239 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1240 false, true, true); 1241 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1242 geni_se_select_mode(&se, GENI_SE_FIFO); 1243 1244 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1245 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1246 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1247 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1248 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1249 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1250 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1251 1252 dev->con->write = qcom_geni_serial_earlycon_write; 1253 dev->con->setup = NULL; 1254 qcom_geni_serial_enable_early_read(&se, dev->con); 1255 1256 return 0; 1257 } 1258 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1259 qcom_geni_serial_earlycon_setup); 1260 1261 static int __init console_register(struct uart_driver *drv) 1262 { 1263 return uart_register_driver(drv); 1264 } 1265 1266 static void console_unregister(struct uart_driver *drv) 1267 { 1268 uart_unregister_driver(drv); 1269 } 1270 1271 static struct console cons_ops = { 1272 .name = "ttyMSM", 1273 .write = qcom_geni_serial_console_write, 1274 .device = uart_console_device, 1275 .setup = qcom_geni_console_setup, 1276 .flags = CON_PRINTBUFFER, 1277 .index = -1, 1278 .data = &qcom_geni_console_driver, 1279 }; 1280 1281 static struct uart_driver qcom_geni_console_driver = { 1282 .owner = THIS_MODULE, 1283 .driver_name = "qcom_geni_console", 1284 .dev_name = "ttyMSM", 1285 .nr = GENI_UART_CONS_PORTS, 1286 .cons = &cons_ops, 1287 }; 1288 #else 1289 static int console_register(struct uart_driver *drv) 1290 { 1291 return 0; 1292 } 1293 1294 static void console_unregister(struct uart_driver *drv) 1295 { 1296 } 1297 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1298 1299 static struct uart_driver qcom_geni_uart_driver = { 1300 .owner = THIS_MODULE, 1301 .driver_name = "qcom_geni_uart", 1302 .dev_name = "ttyHS", 1303 .nr = GENI_UART_PORTS, 1304 }; 1305 1306 static void qcom_geni_serial_pm(struct uart_port *uport, 1307 unsigned int new_state, unsigned int old_state) 1308 { 1309 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1310 1311 /* If we've never been called, treat it as off */ 1312 if (old_state == UART_PM_STATE_UNDEFINED) 1313 old_state = UART_PM_STATE_OFF; 1314 1315 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1316 geni_icc_enable(&port->se); 1317 geni_se_resources_on(&port->se); 1318 } else if (new_state == UART_PM_STATE_OFF && 1319 old_state == UART_PM_STATE_ON) { 1320 geni_se_resources_off(&port->se); 1321 geni_icc_disable(&port->se); 1322 } 1323 } 1324 1325 static const struct uart_ops qcom_geni_console_pops = { 1326 .tx_empty = qcom_geni_serial_tx_empty, 1327 .stop_tx = qcom_geni_serial_stop_tx, 1328 .start_tx = qcom_geni_serial_start_tx, 1329 .stop_rx = qcom_geni_serial_stop_rx, 1330 .start_rx = qcom_geni_serial_start_rx, 1331 .set_termios = qcom_geni_serial_set_termios, 1332 .startup = qcom_geni_serial_startup, 1333 .request_port = qcom_geni_serial_request_port, 1334 .config_port = qcom_geni_serial_config_port, 1335 .shutdown = qcom_geni_serial_shutdown, 1336 .type = qcom_geni_serial_get_type, 1337 .set_mctrl = qcom_geni_serial_set_mctrl, 1338 .get_mctrl = qcom_geni_serial_get_mctrl, 1339 #ifdef CONFIG_CONSOLE_POLL 1340 .poll_get_char = qcom_geni_serial_get_char, 1341 .poll_put_char = qcom_geni_serial_poll_put_char, 1342 #endif 1343 .pm = qcom_geni_serial_pm, 1344 }; 1345 1346 static const struct uart_ops qcom_geni_uart_pops = { 1347 .tx_empty = qcom_geni_serial_tx_empty, 1348 .stop_tx = qcom_geni_serial_stop_tx, 1349 .start_tx = qcom_geni_serial_start_tx, 1350 .stop_rx = qcom_geni_serial_stop_rx, 1351 .set_termios = qcom_geni_serial_set_termios, 1352 .startup = qcom_geni_serial_startup, 1353 .request_port = qcom_geni_serial_request_port, 1354 .config_port = qcom_geni_serial_config_port, 1355 .shutdown = qcom_geni_serial_shutdown, 1356 .type = qcom_geni_serial_get_type, 1357 .set_mctrl = qcom_geni_serial_set_mctrl, 1358 .get_mctrl = qcom_geni_serial_get_mctrl, 1359 .pm = qcom_geni_serial_pm, 1360 }; 1361 1362 static int qcom_geni_serial_probe(struct platform_device *pdev) 1363 { 1364 int ret = 0; 1365 int line; 1366 struct qcom_geni_serial_port *port; 1367 struct uart_port *uport; 1368 struct resource *res; 1369 int irq; 1370 bool console = false; 1371 struct uart_driver *drv; 1372 1373 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) 1374 console = true; 1375 1376 if (console) { 1377 drv = &qcom_geni_console_driver; 1378 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1379 } else { 1380 drv = &qcom_geni_uart_driver; 1381 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1382 if (line == -ENODEV) /* compat with non-standard aliases */ 1383 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1384 } 1385 1386 port = get_port_from_line(line, console); 1387 if (IS_ERR(port)) { 1388 dev_err(&pdev->dev, "Invalid line %d\n", line); 1389 return PTR_ERR(port); 1390 } 1391 1392 uport = &port->uport; 1393 /* Don't allow 2 drivers to access the same port */ 1394 if (uport->private_data) 1395 return -ENODEV; 1396 1397 uport->dev = &pdev->dev; 1398 port->se.dev = &pdev->dev; 1399 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1400 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1401 if (IS_ERR(port->se.clk)) { 1402 ret = PTR_ERR(port->se.clk); 1403 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1404 return ret; 1405 } 1406 1407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1408 if (!res) 1409 return -EINVAL; 1410 uport->mapbase = res->start; 1411 1412 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1413 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1414 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1415 1416 if (!console) { 1417 port->rx_fifo = devm_kcalloc(uport->dev, 1418 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); 1419 if (!port->rx_fifo) 1420 return -ENOMEM; 1421 } 1422 1423 ret = geni_icc_get(&port->se, NULL); 1424 if (ret) 1425 return ret; 1426 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1427 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1428 1429 /* Set BW for register access */ 1430 ret = geni_icc_set_bw(&port->se); 1431 if (ret) 1432 return ret; 1433 1434 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1435 "qcom_geni_serial_%s%d", 1436 uart_console(uport) ? "console" : "uart", uport->line); 1437 if (!port->name) 1438 return -ENOMEM; 1439 1440 irq = platform_get_irq(pdev, 0); 1441 if (irq < 0) 1442 return irq; 1443 uport->irq = irq; 1444 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1445 1446 if (!console) 1447 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1448 1449 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1450 port->rx_tx_swap = true; 1451 1452 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1453 port->cts_rts_swap = true; 1454 1455 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1456 if (ret) 1457 return ret; 1458 /* OPP table is optional */ 1459 ret = devm_pm_opp_of_add_table(&pdev->dev); 1460 if (ret && ret != -ENODEV) { 1461 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1462 return ret; 1463 } 1464 1465 port->private_data.drv = drv; 1466 uport->private_data = &port->private_data; 1467 platform_set_drvdata(pdev, port); 1468 port->handle_rx = console ? handle_rx_console : handle_rx_uart; 1469 1470 ret = uart_add_one_port(drv, uport); 1471 if (ret) 1472 return ret; 1473 1474 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1475 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1476 IRQF_TRIGGER_HIGH, port->name, uport); 1477 if (ret) { 1478 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1479 uart_remove_one_port(drv, uport); 1480 return ret; 1481 } 1482 1483 /* 1484 * Set pm_runtime status as ACTIVE so that wakeup_irq gets 1485 * enabled/disabled from dev_pm_arm_wake_irq during system 1486 * suspend/resume respectively. 1487 */ 1488 pm_runtime_set_active(&pdev->dev); 1489 1490 if (port->wakeup_irq > 0) { 1491 device_init_wakeup(&pdev->dev, true); 1492 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1493 port->wakeup_irq); 1494 if (ret) { 1495 device_init_wakeup(&pdev->dev, false); 1496 uart_remove_one_port(drv, uport); 1497 return ret; 1498 } 1499 } 1500 1501 return 0; 1502 } 1503 1504 static int qcom_geni_serial_remove(struct platform_device *pdev) 1505 { 1506 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1507 struct uart_driver *drv = port->private_data.drv; 1508 1509 dev_pm_clear_wake_irq(&pdev->dev); 1510 device_init_wakeup(&pdev->dev, false); 1511 uart_remove_one_port(drv, &port->uport); 1512 1513 return 0; 1514 } 1515 1516 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev) 1517 { 1518 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1519 struct uart_port *uport = &port->uport; 1520 struct qcom_geni_private_data *private_data = uport->private_data; 1521 1522 /* 1523 * This is done so we can hit the lowest possible state in suspend 1524 * even with no_console_suspend 1525 */ 1526 if (uart_console(uport)) { 1527 geni_icc_set_tag(&port->se, 0x3); 1528 geni_icc_set_bw(&port->se); 1529 } 1530 return uart_suspend_port(private_data->drv, uport); 1531 } 1532 1533 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev) 1534 { 1535 int ret; 1536 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1537 struct uart_port *uport = &port->uport; 1538 struct qcom_geni_private_data *private_data = uport->private_data; 1539 1540 ret = uart_resume_port(private_data->drv, uport); 1541 if (uart_console(uport)) { 1542 geni_icc_set_tag(&port->se, 0x7); 1543 geni_icc_set_bw(&port->se); 1544 } 1545 return ret; 1546 } 1547 1548 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1549 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1550 qcom_geni_serial_sys_resume) 1551 }; 1552 1553 static const struct of_device_id qcom_geni_serial_match_table[] = { 1554 { .compatible = "qcom,geni-debug-uart", }, 1555 { .compatible = "qcom,geni-uart", }, 1556 {} 1557 }; 1558 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1559 1560 static struct platform_driver qcom_geni_serial_platform_driver = { 1561 .remove = qcom_geni_serial_remove, 1562 .probe = qcom_geni_serial_probe, 1563 .driver = { 1564 .name = "qcom_geni_serial", 1565 .of_match_table = qcom_geni_serial_match_table, 1566 .pm = &qcom_geni_serial_pm_ops, 1567 }, 1568 }; 1569 1570 static int __init qcom_geni_serial_init(void) 1571 { 1572 int ret; 1573 1574 ret = console_register(&qcom_geni_console_driver); 1575 if (ret) 1576 return ret; 1577 1578 ret = uart_register_driver(&qcom_geni_uart_driver); 1579 if (ret) { 1580 console_unregister(&qcom_geni_console_driver); 1581 return ret; 1582 } 1583 1584 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1585 if (ret) { 1586 console_unregister(&qcom_geni_console_driver); 1587 uart_unregister_driver(&qcom_geni_uart_driver); 1588 } 1589 return ret; 1590 } 1591 module_init(qcom_geni_serial_init); 1592 1593 static void __exit qcom_geni_serial_exit(void) 1594 { 1595 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1596 console_unregister(&qcom_geni_console_driver); 1597 uart_unregister_driver(&qcom_geni_uart_driver); 1598 } 1599 module_exit(qcom_geni_serial_exit); 1600 1601 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1602 MODULE_LICENSE("GPL v2"); 1603