1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/console.h> 6 #include <linux/io.h> 7 #include <linux/iopoll.h> 8 #include <linux/irq.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/qcom-geni-se.h> 16 #include <linux/serial.h> 17 #include <linux/serial_core.h> 18 #include <linux/slab.h> 19 #include <linux/tty.h> 20 #include <linux/tty_flip.h> 21 22 /* UART specific GENI registers */ 23 #define SE_UART_LOOPBACK_CFG 0x22c 24 #define SE_UART_IO_MACRO_CTRL 0x240 25 #define SE_UART_TX_TRANS_CFG 0x25c 26 #define SE_UART_TX_WORD_LEN 0x268 27 #define SE_UART_TX_STOP_BIT_LEN 0x26c 28 #define SE_UART_TX_TRANS_LEN 0x270 29 #define SE_UART_RX_TRANS_CFG 0x280 30 #define SE_UART_RX_WORD_LEN 0x28c 31 #define SE_UART_RX_STALE_CNT 0x294 32 #define SE_UART_TX_PARITY_CFG 0x2a4 33 #define SE_UART_RX_PARITY_CFG 0x2a8 34 #define SE_UART_MANUAL_RFR 0x2ac 35 36 /* SE_UART_TRANS_CFG */ 37 #define UART_TX_PAR_EN BIT(0) 38 #define UART_CTS_MASK BIT(1) 39 40 /* SE_UART_TX_WORD_LEN */ 41 #define TX_WORD_LEN_MSK GENMASK(9, 0) 42 43 /* SE_UART_TX_STOP_BIT_LEN */ 44 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) 45 #define TX_STOP_BIT_LEN_1 0 46 #define TX_STOP_BIT_LEN_1_5 1 47 #define TX_STOP_BIT_LEN_2 2 48 49 /* SE_UART_TX_TRANS_LEN */ 50 #define TX_TRANS_LEN_MSK GENMASK(23, 0) 51 52 /* SE_UART_RX_TRANS_CFG */ 53 #define UART_RX_INS_STATUS_BIT BIT(2) 54 #define UART_RX_PAR_EN BIT(3) 55 56 /* SE_UART_RX_WORD_LEN */ 57 #define RX_WORD_LEN_MASK GENMASK(9, 0) 58 59 /* SE_UART_RX_STALE_CNT */ 60 #define RX_STALE_CNT GENMASK(23, 0) 61 62 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 63 #define PAR_CALC_EN BIT(0) 64 #define PAR_MODE_MSK GENMASK(2, 1) 65 #define PAR_MODE_SHFT 1 66 #define PAR_EVEN 0x00 67 #define PAR_ODD 0x01 68 #define PAR_SPACE 0x10 69 #define PAR_MARK 0x11 70 71 /* SE_UART_MANUAL_RFR register fields */ 72 #define UART_MANUAL_RFR_EN BIT(31) 73 #define UART_RFR_NOT_READY BIT(1) 74 #define UART_RFR_READY BIT(0) 75 76 /* UART M_CMD OP codes */ 77 #define UART_START_TX 0x1 78 #define UART_START_BREAK 0x4 79 #define UART_STOP_BREAK 0x5 80 /* UART S_CMD OP codes */ 81 #define UART_START_READ 0x1 82 #define UART_PARAM 0x1 83 84 #define UART_OVERSAMPLING 32 85 #define STALE_TIMEOUT 16 86 #define DEFAULT_BITS_PER_CHAR 10 87 #define GENI_UART_CONS_PORTS 1 88 #define GENI_UART_PORTS 3 89 #define DEF_FIFO_DEPTH_WORDS 16 90 #define DEF_TX_WM 2 91 #define DEF_FIFO_WIDTH_BITS 32 92 #define UART_RX_WM 2 93 94 /* SE_UART_LOOPBACK_CFG */ 95 #define RX_TX_SORTED BIT(0) 96 #define CTS_RTS_SORTED BIT(1) 97 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 98 99 /* UART pin swap value */ 100 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 101 #define IO_MACRO_IO0_SEL 0x3 102 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 103 #define IO_MACRO_IO2_IO3_SWAP 0x4640 104 105 #ifdef CONFIG_CONSOLE_POLL 106 #define CONSOLE_RX_BYTES_PW 1 107 #else 108 #define CONSOLE_RX_BYTES_PW 4 109 #endif 110 111 struct qcom_geni_serial_port { 112 struct uart_port uport; 113 struct geni_se se; 114 const char *name; 115 u32 tx_fifo_depth; 116 u32 tx_fifo_width; 117 u32 rx_fifo_depth; 118 bool setup; 119 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); 120 unsigned int baud; 121 unsigned int tx_bytes_pw; 122 unsigned int rx_bytes_pw; 123 void *rx_fifo; 124 u32 loopback; 125 bool brk; 126 127 unsigned int tx_remaining; 128 int wakeup_irq; 129 bool rx_tx_swap; 130 bool cts_rts_swap; 131 }; 132 133 static const struct uart_ops qcom_geni_console_pops; 134 static const struct uart_ops qcom_geni_uart_pops; 135 static struct uart_driver qcom_geni_console_driver; 136 static struct uart_driver qcom_geni_uart_driver; 137 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); 138 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); 139 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); 140 static void qcom_geni_serial_stop_rx(struct uart_port *uport); 141 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); 142 143 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 144 32000000, 48000000, 51200000, 64000000, 145 80000000, 96000000, 100000000, 146 102400000, 112000000, 120000000, 147 128000000}; 148 149 #define to_dev_port(ptr, member) \ 150 container_of(ptr, struct qcom_geni_serial_port, member) 151 152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 153 [0] = { 154 .uport = { 155 .iotype = UPIO_MEM, 156 .ops = &qcom_geni_uart_pops, 157 .flags = UPF_BOOT_AUTOCONF, 158 .line = 0, 159 }, 160 }, 161 [1] = { 162 .uport = { 163 .iotype = UPIO_MEM, 164 .ops = &qcom_geni_uart_pops, 165 .flags = UPF_BOOT_AUTOCONF, 166 .line = 1, 167 }, 168 }, 169 [2] = { 170 .uport = { 171 .iotype = UPIO_MEM, 172 .ops = &qcom_geni_uart_pops, 173 .flags = UPF_BOOT_AUTOCONF, 174 .line = 2, 175 }, 176 }, 177 }; 178 179 static struct qcom_geni_serial_port qcom_geni_console_port = { 180 .uport = { 181 .iotype = UPIO_MEM, 182 .ops = &qcom_geni_console_pops, 183 .flags = UPF_BOOT_AUTOCONF, 184 .line = 0, 185 }, 186 }; 187 188 static int qcom_geni_serial_request_port(struct uart_port *uport) 189 { 190 struct platform_device *pdev = to_platform_device(uport->dev); 191 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 192 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); 194 if (IS_ERR(uport->membase)) 195 return PTR_ERR(uport->membase); 196 port->se.base = uport->membase; 197 return 0; 198 } 199 200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 201 { 202 if (cfg_flags & UART_CONFIG_TYPE) { 203 uport->type = PORT_MSM; 204 qcom_geni_serial_request_port(uport); 205 } 206 } 207 208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 209 { 210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 211 u32 geni_ios; 212 213 if (uart_console(uport)) { 214 mctrl |= TIOCM_CTS; 215 } else { 216 geni_ios = readl(uport->membase + SE_GENI_IOS); 217 if (!(geni_ios & IO2_DATA_IN)) 218 mctrl |= TIOCM_CTS; 219 } 220 221 return mctrl; 222 } 223 224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 225 unsigned int mctrl) 226 { 227 u32 uart_manual_rfr = 0; 228 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 229 230 if (uart_console(uport)) 231 return; 232 233 if (mctrl & TIOCM_LOOP) 234 port->loopback = RX_TX_CTS_RTS_SORTED; 235 236 if (!(mctrl & TIOCM_RTS)) 237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 239 } 240 241 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 242 { 243 return "MSM"; 244 } 245 246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 247 { 248 struct qcom_geni_serial_port *port; 249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 250 251 if (line < 0 || line >= nr_ports) 252 return ERR_PTR(-ENXIO); 253 254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 255 return port; 256 } 257 258 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 259 int offset, int field, bool set) 260 { 261 u32 reg; 262 struct qcom_geni_serial_port *port; 263 unsigned int baud; 264 unsigned int fifo_bits; 265 unsigned long timeout_us = 20000; 266 267 if (uport->private_data) { 268 port = to_dev_port(uport, uport); 269 baud = port->baud; 270 if (!baud) 271 baud = 115200; 272 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 273 /* 274 * Total polling iterations based on FIFO worth of bytes to be 275 * sent at current baud. Add a little fluff to the wait. 276 */ 277 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 278 } 279 280 /* 281 * Use custom implementation instead of readl_poll_atomic since ktimer 282 * is not ready at the time of early console. 283 */ 284 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 285 while (timeout_us) { 286 reg = readl(uport->membase + offset); 287 if ((bool)(reg & field) == set) 288 return true; 289 udelay(10); 290 timeout_us -= 10; 291 } 292 return false; 293 } 294 295 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 296 { 297 u32 m_cmd; 298 299 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 300 m_cmd = UART_START_TX << M_OPCODE_SHFT; 301 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 302 } 303 304 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 305 { 306 int done; 307 u32 irq_clear = M_CMD_DONE_EN; 308 309 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 310 M_CMD_DONE_EN, true); 311 if (!done) { 312 writel(M_GENI_CMD_ABORT, uport->membase + 313 SE_GENI_M_CMD_CTRL_REG); 314 irq_clear |= M_CMD_ABORT_EN; 315 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 316 M_CMD_ABORT_EN, true); 317 } 318 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 319 } 320 321 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 322 { 323 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 324 325 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 326 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 327 S_GENI_CMD_ABORT, false); 328 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 329 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 330 } 331 332 #ifdef CONFIG_CONSOLE_POLL 333 static int qcom_geni_serial_get_char(struct uart_port *uport) 334 { 335 u32 rx_fifo; 336 u32 status; 337 338 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 339 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 340 341 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 342 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 343 344 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 345 if (!(status & RX_FIFO_WC_MSK)) 346 return NO_POLL_CHAR; 347 348 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn); 349 return rx_fifo & 0xff; 350 } 351 352 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 353 unsigned char c) 354 { 355 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 356 qcom_geni_serial_setup_tx(uport, 1); 357 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 358 M_TX_FIFO_WATERMARK_EN, true)); 359 writel(c, uport->membase + SE_GENI_TX_FIFOn); 360 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 361 qcom_geni_serial_poll_tx_done(uport); 362 } 363 #endif 364 365 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 366 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch) 367 { 368 writel(ch, uport->membase + SE_GENI_TX_FIFOn); 369 } 370 371 static void 372 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 373 unsigned int count) 374 { 375 int i; 376 u32 bytes_to_send = count; 377 378 for (i = 0; i < count; i++) { 379 /* 380 * uart_console_write() adds a carriage return for each newline. 381 * Account for additional bytes to be written. 382 */ 383 if (s[i] == '\n') 384 bytes_to_send++; 385 } 386 387 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 388 qcom_geni_serial_setup_tx(uport, bytes_to_send); 389 for (i = 0; i < count; ) { 390 size_t chars_to_write = 0; 391 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 392 393 /* 394 * If the WM bit never set, then the Tx state machine is not 395 * in a valid state, so break, cancel/abort any existing 396 * command. Unfortunately the current data being written is 397 * lost. 398 */ 399 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 400 M_TX_FIFO_WATERMARK_EN, true)) 401 break; 402 chars_to_write = min_t(size_t, count - i, avail / 2); 403 uart_console_write(uport, s + i, chars_to_write, 404 qcom_geni_serial_wr_char); 405 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 406 SE_GENI_M_IRQ_CLEAR); 407 i += chars_to_write; 408 } 409 qcom_geni_serial_poll_tx_done(uport); 410 } 411 412 static void qcom_geni_serial_console_write(struct console *co, const char *s, 413 unsigned int count) 414 { 415 struct uart_port *uport; 416 struct qcom_geni_serial_port *port; 417 bool locked = true; 418 unsigned long flags; 419 u32 geni_status; 420 u32 irq_en; 421 422 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 423 424 port = get_port_from_line(co->index, true); 425 if (IS_ERR(port)) 426 return; 427 428 uport = &port->uport; 429 if (oops_in_progress) 430 locked = spin_trylock_irqsave(&uport->lock, flags); 431 else 432 spin_lock_irqsave(&uport->lock, flags); 433 434 geni_status = readl(uport->membase + SE_GENI_STATUS); 435 436 /* Cancel the current write to log the fault */ 437 if (!locked) { 438 geni_se_cancel_m_cmd(&port->se); 439 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 440 M_CMD_CANCEL_EN, true)) { 441 geni_se_abort_m_cmd(&port->se); 442 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 443 M_CMD_ABORT_EN, true); 444 writel(M_CMD_ABORT_EN, uport->membase + 445 SE_GENI_M_IRQ_CLEAR); 446 } 447 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 448 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 449 /* 450 * It seems we can't interrupt existing transfers if all data 451 * has been sent, in which case we need to look for done first. 452 */ 453 qcom_geni_serial_poll_tx_done(uport); 454 455 if (uart_circ_chars_pending(&uport->state->xmit)) { 456 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 457 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 458 uport->membase + SE_GENI_M_IRQ_EN); 459 } 460 } 461 462 __qcom_geni_serial_console_write(uport, s, count); 463 464 if (port->tx_remaining) 465 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 466 467 if (locked) 468 spin_unlock_irqrestore(&uport->lock, flags); 469 } 470 471 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 472 { 473 u32 i; 474 unsigned char buf[sizeof(u32)]; 475 struct tty_port *tport; 476 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 477 478 tport = &uport->state->port; 479 for (i = 0; i < bytes; ) { 480 int c; 481 int chunk = min_t(int, bytes - i, port->rx_bytes_pw); 482 483 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 484 i += chunk; 485 if (drop) 486 continue; 487 488 for (c = 0; c < chunk; c++) { 489 int sysrq; 490 491 uport->icount.rx++; 492 if (port->brk && buf[c] == 0) { 493 port->brk = false; 494 if (uart_handle_break(uport)) 495 continue; 496 } 497 498 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 499 500 if (!sysrq) 501 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 502 } 503 } 504 if (!drop) 505 tty_flip_buffer_push(tport); 506 return 0; 507 } 508 #else 509 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 510 { 511 return -EPERM; 512 } 513 514 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 515 516 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 517 { 518 struct tty_port *tport; 519 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 520 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; 521 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; 522 int ret; 523 524 tport = &uport->state->port; 525 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); 526 if (drop) 527 return 0; 528 529 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); 530 if (ret != bytes) { 531 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 532 __func__, ret, bytes); 533 WARN_ON_ONCE(1); 534 } 535 uport->icount.rx += ret; 536 tty_flip_buffer_push(tport); 537 return ret; 538 } 539 540 static void qcom_geni_serial_start_tx(struct uart_port *uport) 541 { 542 u32 irq_en; 543 u32 status; 544 545 status = readl(uport->membase + SE_GENI_STATUS); 546 if (status & M_GENI_CMD_ACTIVE) 547 return; 548 549 if (!qcom_geni_serial_tx_empty(uport)) 550 return; 551 552 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 553 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 554 555 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 556 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 557 } 558 559 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 560 { 561 u32 irq_en; 562 u32 status; 563 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 564 565 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 566 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 567 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 568 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 569 status = readl(uport->membase + SE_GENI_STATUS); 570 /* Possible stop tx is called multiple times. */ 571 if (!(status & M_GENI_CMD_ACTIVE)) 572 return; 573 574 geni_se_cancel_m_cmd(&port->se); 575 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 576 M_CMD_CANCEL_EN, true)) { 577 geni_se_abort_m_cmd(&port->se); 578 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 579 M_CMD_ABORT_EN, true); 580 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 581 } 582 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 583 } 584 585 static void qcom_geni_serial_start_rx(struct uart_port *uport) 586 { 587 u32 irq_en; 588 u32 status; 589 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 590 591 status = readl(uport->membase + SE_GENI_STATUS); 592 if (status & S_GENI_CMD_ACTIVE) 593 qcom_geni_serial_stop_rx(uport); 594 595 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 596 597 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 598 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 599 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 600 601 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 602 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 603 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 604 } 605 606 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 607 { 608 u32 irq_en; 609 u32 status; 610 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 611 u32 s_irq_status; 612 613 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 614 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 615 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 616 617 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 618 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 619 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 620 621 status = readl(uport->membase + SE_GENI_STATUS); 622 /* Possible stop rx is called multiple times. */ 623 if (!(status & S_GENI_CMD_ACTIVE)) 624 return; 625 626 geni_se_cancel_s_cmd(&port->se); 627 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 628 S_CMD_CANCEL_EN, true); 629 /* 630 * If timeout occurs secondary engine remains active 631 * and Abort sequence is executed. 632 */ 633 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 634 /* Flush the Rx buffer */ 635 if (s_irq_status & S_RX_FIFO_LAST_EN) 636 qcom_geni_serial_handle_rx(uport, true); 637 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 638 639 status = readl(uport->membase + SE_GENI_STATUS); 640 if (status & S_GENI_CMD_ACTIVE) 641 qcom_geni_serial_abort_rx(uport); 642 } 643 644 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) 645 { 646 u32 status; 647 u32 word_cnt; 648 u32 last_word_byte_cnt; 649 u32 last_word_partial; 650 u32 total_bytes; 651 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 652 653 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 654 word_cnt = status & RX_FIFO_WC_MSK; 655 last_word_partial = status & RX_LAST; 656 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 657 RX_LAST_BYTE_VALID_SHFT; 658 659 if (!word_cnt) 660 return; 661 total_bytes = port->rx_bytes_pw * (word_cnt - 1); 662 if (last_word_partial && last_word_byte_cnt) 663 total_bytes += last_word_byte_cnt; 664 else 665 total_bytes += port->rx_bytes_pw; 666 port->handle_rx(uport, total_bytes, drop); 667 } 668 669 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, 670 bool active) 671 { 672 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 673 struct circ_buf *xmit = &uport->state->xmit; 674 size_t avail; 675 size_t remaining; 676 size_t pending; 677 int i; 678 u32 status; 679 u32 irq_en; 680 unsigned int chunk; 681 int tail; 682 683 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 684 685 /* Complete the current tx command before taking newly added data */ 686 if (active) 687 pending = port->tx_remaining; 688 else 689 pending = uart_circ_chars_pending(xmit); 690 691 /* All data has been transmitted and acknowledged as received */ 692 if (!pending && !status && done) { 693 qcom_geni_serial_stop_tx(uport); 694 goto out_write_wakeup; 695 } 696 697 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 698 avail *= port->tx_bytes_pw; 699 700 tail = xmit->tail; 701 chunk = min(avail, pending); 702 if (!chunk) 703 goto out_write_wakeup; 704 705 if (!port->tx_remaining) { 706 qcom_geni_serial_setup_tx(uport, pending); 707 port->tx_remaining = pending; 708 709 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 710 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 711 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 712 uport->membase + SE_GENI_M_IRQ_EN); 713 } 714 715 remaining = chunk; 716 for (i = 0; i < chunk; ) { 717 unsigned int tx_bytes; 718 u8 buf[sizeof(u32)]; 719 int c; 720 721 memset(buf, 0, ARRAY_SIZE(buf)); 722 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw); 723 724 for (c = 0; c < tx_bytes ; c++) { 725 buf[c] = xmit->buf[tail++]; 726 tail &= UART_XMIT_SIZE - 1; 727 } 728 729 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 730 731 i += tx_bytes; 732 uport->icount.tx += tx_bytes; 733 remaining -= tx_bytes; 734 port->tx_remaining -= tx_bytes; 735 } 736 737 xmit->tail = tail; 738 739 /* 740 * The tx fifo watermark is level triggered and latched. Though we had 741 * cleared it in qcom_geni_serial_isr it will have already reasserted 742 * so we must clear it again here after our writes. 743 */ 744 writel(M_TX_FIFO_WATERMARK_EN, 745 uport->membase + SE_GENI_M_IRQ_CLEAR); 746 747 out_write_wakeup: 748 if (!port->tx_remaining) { 749 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 750 if (irq_en & M_TX_FIFO_WATERMARK_EN) 751 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 752 uport->membase + SE_GENI_M_IRQ_EN); 753 } 754 755 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 756 uart_write_wakeup(uport); 757 } 758 759 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 760 { 761 u32 m_irq_en; 762 u32 m_irq_status; 763 u32 s_irq_status; 764 u32 geni_status; 765 struct uart_port *uport = dev; 766 unsigned long flags; 767 bool drop_rx = false; 768 struct tty_port *tport = &uport->state->port; 769 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 770 771 if (uport->suspended) 772 return IRQ_NONE; 773 774 spin_lock_irqsave(&uport->lock, flags); 775 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 776 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 777 geni_status = readl(uport->membase + SE_GENI_STATUS); 778 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 779 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 780 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 781 782 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 783 goto out_unlock; 784 785 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 786 uport->icount.overrun++; 787 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 788 } 789 790 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 791 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, 792 geni_status & M_GENI_CMD_ACTIVE); 793 794 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { 795 if (s_irq_status & S_GP_IRQ_0_EN) 796 uport->icount.parity++; 797 drop_rx = true; 798 } else if (s_irq_status & S_GP_IRQ_2_EN || 799 s_irq_status & S_GP_IRQ_3_EN) { 800 uport->icount.brk++; 801 port->brk = true; 802 } 803 804 if (s_irq_status & S_RX_FIFO_WATERMARK_EN || 805 s_irq_status & S_RX_FIFO_LAST_EN) 806 qcom_geni_serial_handle_rx(uport, drop_rx); 807 808 out_unlock: 809 uart_unlock_and_check_sysrq(uport, flags); 810 811 return IRQ_HANDLED; 812 } 813 814 static void get_tx_fifo_size(struct qcom_geni_serial_port *port) 815 { 816 struct uart_port *uport; 817 818 uport = &port->uport; 819 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 820 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 821 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 822 uport->fifosize = 823 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 824 } 825 826 827 static void qcom_geni_serial_shutdown(struct uart_port *uport) 828 { 829 disable_irq(uport->irq); 830 } 831 832 static int qcom_geni_serial_port_setup(struct uart_port *uport) 833 { 834 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 835 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 836 u32 proto; 837 u32 pin_swap; 838 839 if (uart_console(uport)) { 840 port->tx_bytes_pw = 1; 841 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW; 842 } else { 843 port->tx_bytes_pw = 4; 844 port->rx_bytes_pw = 4; 845 } 846 847 proto = geni_se_read_proto(&port->se); 848 if (proto != GENI_SE_UART) { 849 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 850 return -ENXIO; 851 } 852 853 qcom_geni_serial_stop_rx(uport); 854 855 get_tx_fifo_size(port); 856 857 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 858 859 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 860 if (port->rx_tx_swap) { 861 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 862 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 863 } 864 if (port->cts_rts_swap) { 865 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 866 pin_swap |= IO_MACRO_IO0_SEL; 867 } 868 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 869 if (port->rx_tx_swap || port->cts_rts_swap) 870 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 871 872 /* 873 * Make an unconditional cancel on the main sequencer to reset 874 * it else we could end up in data loss scenarios. 875 */ 876 if (uart_console(uport)) 877 qcom_geni_serial_poll_tx_done(uport); 878 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw, 879 false, true, false); 880 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw, 881 false, false, true); 882 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 883 geni_se_select_mode(&port->se, GENI_SE_FIFO); 884 port->setup = true; 885 886 return 0; 887 } 888 889 static int qcom_geni_serial_startup(struct uart_port *uport) 890 { 891 int ret; 892 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 893 894 if (!port->setup) { 895 ret = qcom_geni_serial_port_setup(uport); 896 if (ret) 897 return ret; 898 } 899 enable_irq(uport->irq); 900 901 return 0; 902 } 903 904 static unsigned long get_clk_cfg(unsigned long clk_freq) 905 { 906 int i; 907 908 for (i = 0; i < ARRAY_SIZE(root_freq); i++) { 909 if (!(root_freq[i] % clk_freq)) 910 return root_freq[i]; 911 } 912 return 0; 913 } 914 915 static unsigned long get_clk_div_rate(unsigned int baud, 916 unsigned int sampling_rate, unsigned int *clk_div) 917 { 918 unsigned long ser_clk; 919 unsigned long desired_clk; 920 921 desired_clk = baud * sampling_rate; 922 ser_clk = get_clk_cfg(desired_clk); 923 if (!ser_clk) { 924 pr_err("%s: Can't find matching DFS entry for baud %d\n", 925 __func__, baud); 926 return ser_clk; 927 } 928 929 *clk_div = ser_clk / desired_clk; 930 return ser_clk; 931 } 932 933 static void qcom_geni_serial_set_termios(struct uart_port *uport, 934 struct ktermios *termios, struct ktermios *old) 935 { 936 unsigned int baud; 937 u32 bits_per_char; 938 u32 tx_trans_cfg; 939 u32 tx_parity_cfg; 940 u32 rx_trans_cfg; 941 u32 rx_parity_cfg; 942 u32 stop_bit_len; 943 unsigned int clk_div; 944 u32 ser_clk_cfg; 945 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 946 unsigned long clk_rate; 947 u32 ver, sampling_rate; 948 949 qcom_geni_serial_stop_rx(uport); 950 /* baud rate */ 951 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 952 port->baud = baud; 953 954 sampling_rate = UART_OVERSAMPLING; 955 /* Sampling rate is halved for IP versions >= 2.5 */ 956 ver = geni_se_get_qup_hw_version(&port->se); 957 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5) 958 sampling_rate /= 2; 959 960 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div); 961 if (!clk_rate) 962 goto out_restart_rx; 963 964 uport->uartclk = clk_rate; 965 clk_set_rate(port->se.clk, clk_rate); 966 ser_clk_cfg = SER_CLK_EN; 967 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 968 969 /* parity */ 970 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 971 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 972 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 973 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 974 if (termios->c_cflag & PARENB) { 975 tx_trans_cfg |= UART_TX_PAR_EN; 976 rx_trans_cfg |= UART_RX_PAR_EN; 977 tx_parity_cfg |= PAR_CALC_EN; 978 rx_parity_cfg |= PAR_CALC_EN; 979 if (termios->c_cflag & PARODD) { 980 tx_parity_cfg |= PAR_ODD; 981 rx_parity_cfg |= PAR_ODD; 982 } else if (termios->c_cflag & CMSPAR) { 983 tx_parity_cfg |= PAR_SPACE; 984 rx_parity_cfg |= PAR_SPACE; 985 } else { 986 tx_parity_cfg |= PAR_EVEN; 987 rx_parity_cfg |= PAR_EVEN; 988 } 989 } else { 990 tx_trans_cfg &= ~UART_TX_PAR_EN; 991 rx_trans_cfg &= ~UART_RX_PAR_EN; 992 tx_parity_cfg &= ~PAR_CALC_EN; 993 rx_parity_cfg &= ~PAR_CALC_EN; 994 } 995 996 /* bits per char */ 997 switch (termios->c_cflag & CSIZE) { 998 case CS5: 999 bits_per_char = 5; 1000 break; 1001 case CS6: 1002 bits_per_char = 6; 1003 break; 1004 case CS7: 1005 bits_per_char = 7; 1006 break; 1007 case CS8: 1008 default: 1009 bits_per_char = 8; 1010 break; 1011 } 1012 1013 /* stop bits */ 1014 if (termios->c_cflag & CSTOPB) 1015 stop_bit_len = TX_STOP_BIT_LEN_2; 1016 else 1017 stop_bit_len = TX_STOP_BIT_LEN_1; 1018 1019 /* flow control, clear the CTS_MASK bit if using flow control. */ 1020 if (termios->c_cflag & CRTSCTS) 1021 tx_trans_cfg &= ~UART_CTS_MASK; 1022 else 1023 tx_trans_cfg |= UART_CTS_MASK; 1024 1025 if (baud) 1026 uart_update_timeout(uport, termios->c_cflag, baud); 1027 1028 if (!uart_console(uport)) 1029 writel(port->loopback, 1030 uport->membase + SE_UART_LOOPBACK_CFG); 1031 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1032 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1033 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1034 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1035 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1036 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1037 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1038 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1039 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1040 out_restart_rx: 1041 qcom_geni_serial_start_rx(uport); 1042 } 1043 1044 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 1045 { 1046 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1047 } 1048 1049 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1050 static int __init qcom_geni_console_setup(struct console *co, char *options) 1051 { 1052 struct uart_port *uport; 1053 struct qcom_geni_serial_port *port; 1054 int baud = 9600; 1055 int bits = 8; 1056 int parity = 'n'; 1057 int flow = 'n'; 1058 int ret; 1059 1060 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1061 return -ENXIO; 1062 1063 port = get_port_from_line(co->index, true); 1064 if (IS_ERR(port)) { 1065 pr_err("Invalid line %d\n", co->index); 1066 return PTR_ERR(port); 1067 } 1068 1069 uport = &port->uport; 1070 1071 if (unlikely(!uport->membase)) 1072 return -ENXIO; 1073 1074 if (!port->setup) { 1075 ret = qcom_geni_serial_port_setup(uport); 1076 if (ret) 1077 return ret; 1078 } 1079 1080 if (options) 1081 uart_parse_options(options, &baud, &parity, &bits, &flow); 1082 1083 return uart_set_options(uport, co, baud, parity, bits, flow); 1084 } 1085 1086 static void qcom_geni_serial_earlycon_write(struct console *con, 1087 const char *s, unsigned int n) 1088 { 1089 struct earlycon_device *dev = con->data; 1090 1091 __qcom_geni_serial_console_write(&dev->port, s, n); 1092 } 1093 1094 #ifdef CONFIG_CONSOLE_POLL 1095 static int qcom_geni_serial_earlycon_read(struct console *con, 1096 char *s, unsigned int n) 1097 { 1098 struct earlycon_device *dev = con->data; 1099 struct uart_port *uport = &dev->port; 1100 int num_read = 0; 1101 int ch; 1102 1103 while (num_read < n) { 1104 ch = qcom_geni_serial_get_char(uport); 1105 if (ch == NO_POLL_CHAR) 1106 break; 1107 s[num_read++] = ch; 1108 } 1109 1110 return num_read; 1111 } 1112 1113 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1114 struct console *con) 1115 { 1116 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1117 con->read = qcom_geni_serial_earlycon_read; 1118 } 1119 #else 1120 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1121 struct console *con) { } 1122 #endif 1123 1124 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1125 const char *opt) 1126 { 1127 struct uart_port *uport = &dev->port; 1128 u32 tx_trans_cfg; 1129 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1130 u32 rx_trans_cfg = 0; 1131 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1132 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1133 u32 bits_per_char; 1134 struct geni_se se; 1135 1136 if (!uport->membase) 1137 return -EINVAL; 1138 1139 memset(&se, 0, sizeof(se)); 1140 se.base = uport->membase; 1141 if (geni_se_read_proto(&se) != GENI_SE_UART) 1142 return -ENXIO; 1143 /* 1144 * Ignore Flow control. 1145 * n = 8. 1146 */ 1147 tx_trans_cfg = UART_CTS_MASK; 1148 bits_per_char = BITS_PER_BYTE; 1149 1150 /* 1151 * Make an unconditional cancel on the main sequencer to reset 1152 * it else we could end up in data loss scenarios. 1153 */ 1154 qcom_geni_serial_poll_tx_done(uport); 1155 qcom_geni_serial_abort_rx(uport); 1156 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false); 1157 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1158 geni_se_select_mode(&se, GENI_SE_FIFO); 1159 1160 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1161 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1162 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1163 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1164 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1165 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1166 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1167 1168 dev->con->write = qcom_geni_serial_earlycon_write; 1169 dev->con->setup = NULL; 1170 qcom_geni_serial_enable_early_read(&se, dev->con); 1171 1172 return 0; 1173 } 1174 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1175 qcom_geni_serial_earlycon_setup); 1176 1177 static int __init console_register(struct uart_driver *drv) 1178 { 1179 return uart_register_driver(drv); 1180 } 1181 1182 static void console_unregister(struct uart_driver *drv) 1183 { 1184 uart_unregister_driver(drv); 1185 } 1186 1187 static struct console cons_ops = { 1188 .name = "ttyMSM", 1189 .write = qcom_geni_serial_console_write, 1190 .device = uart_console_device, 1191 .setup = qcom_geni_console_setup, 1192 .flags = CON_PRINTBUFFER, 1193 .index = -1, 1194 .data = &qcom_geni_console_driver, 1195 }; 1196 1197 static struct uart_driver qcom_geni_console_driver = { 1198 .owner = THIS_MODULE, 1199 .driver_name = "qcom_geni_console", 1200 .dev_name = "ttyMSM", 1201 .nr = GENI_UART_CONS_PORTS, 1202 .cons = &cons_ops, 1203 }; 1204 #else 1205 static int console_register(struct uart_driver *drv) 1206 { 1207 return 0; 1208 } 1209 1210 static void console_unregister(struct uart_driver *drv) 1211 { 1212 } 1213 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1214 1215 static struct uart_driver qcom_geni_uart_driver = { 1216 .owner = THIS_MODULE, 1217 .driver_name = "qcom_geni_uart", 1218 .dev_name = "ttyHS", 1219 .nr = GENI_UART_PORTS, 1220 }; 1221 1222 static void qcom_geni_serial_pm(struct uart_port *uport, 1223 unsigned int new_state, unsigned int old_state) 1224 { 1225 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1226 1227 /* If we've never been called, treat it as off */ 1228 if (old_state == UART_PM_STATE_UNDEFINED) 1229 old_state = UART_PM_STATE_OFF; 1230 1231 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) 1232 geni_se_resources_on(&port->se); 1233 else if (new_state == UART_PM_STATE_OFF && 1234 old_state == UART_PM_STATE_ON) 1235 geni_se_resources_off(&port->se); 1236 } 1237 1238 static const struct uart_ops qcom_geni_console_pops = { 1239 .tx_empty = qcom_geni_serial_tx_empty, 1240 .stop_tx = qcom_geni_serial_stop_tx, 1241 .start_tx = qcom_geni_serial_start_tx, 1242 .stop_rx = qcom_geni_serial_stop_rx, 1243 .set_termios = qcom_geni_serial_set_termios, 1244 .startup = qcom_geni_serial_startup, 1245 .request_port = qcom_geni_serial_request_port, 1246 .config_port = qcom_geni_serial_config_port, 1247 .shutdown = qcom_geni_serial_shutdown, 1248 .type = qcom_geni_serial_get_type, 1249 .set_mctrl = qcom_geni_serial_set_mctrl, 1250 .get_mctrl = qcom_geni_serial_get_mctrl, 1251 #ifdef CONFIG_CONSOLE_POLL 1252 .poll_get_char = qcom_geni_serial_get_char, 1253 .poll_put_char = qcom_geni_serial_poll_put_char, 1254 #endif 1255 .pm = qcom_geni_serial_pm, 1256 }; 1257 1258 static const struct uart_ops qcom_geni_uart_pops = { 1259 .tx_empty = qcom_geni_serial_tx_empty, 1260 .stop_tx = qcom_geni_serial_stop_tx, 1261 .start_tx = qcom_geni_serial_start_tx, 1262 .stop_rx = qcom_geni_serial_stop_rx, 1263 .set_termios = qcom_geni_serial_set_termios, 1264 .startup = qcom_geni_serial_startup, 1265 .request_port = qcom_geni_serial_request_port, 1266 .config_port = qcom_geni_serial_config_port, 1267 .shutdown = qcom_geni_serial_shutdown, 1268 .type = qcom_geni_serial_get_type, 1269 .set_mctrl = qcom_geni_serial_set_mctrl, 1270 .get_mctrl = qcom_geni_serial_get_mctrl, 1271 .pm = qcom_geni_serial_pm, 1272 }; 1273 1274 static int qcom_geni_serial_probe(struct platform_device *pdev) 1275 { 1276 int ret = 0; 1277 int line = -1; 1278 struct qcom_geni_serial_port *port; 1279 struct uart_port *uport; 1280 struct resource *res; 1281 int irq; 1282 bool console = false; 1283 struct uart_driver *drv; 1284 1285 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) 1286 console = true; 1287 1288 if (console) { 1289 drv = &qcom_geni_console_driver; 1290 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1291 } else { 1292 drv = &qcom_geni_uart_driver; 1293 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1294 } 1295 1296 port = get_port_from_line(line, console); 1297 if (IS_ERR(port)) { 1298 dev_err(&pdev->dev, "Invalid line %d\n", line); 1299 return PTR_ERR(port); 1300 } 1301 1302 uport = &port->uport; 1303 /* Don't allow 2 drivers to access the same port */ 1304 if (uport->private_data) 1305 return -ENODEV; 1306 1307 uport->dev = &pdev->dev; 1308 port->se.dev = &pdev->dev; 1309 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1310 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1311 if (IS_ERR(port->se.clk)) { 1312 ret = PTR_ERR(port->se.clk); 1313 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1314 return ret; 1315 } 1316 1317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1318 if (!res) 1319 return -EINVAL; 1320 uport->mapbase = res->start; 1321 1322 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1323 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1324 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1325 1326 if (!console) { 1327 port->rx_fifo = devm_kcalloc(uport->dev, 1328 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); 1329 if (!port->rx_fifo) 1330 return -ENOMEM; 1331 } 1332 1333 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1334 "qcom_geni_serial_%s%d", 1335 uart_console(uport) ? "console" : "uart", uport->line); 1336 if (!port->name) 1337 return -ENOMEM; 1338 1339 irq = platform_get_irq(pdev, 0); 1340 if (irq < 0) 1341 return irq; 1342 uport->irq = irq; 1343 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1344 1345 if (!console) 1346 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1347 1348 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1349 port->rx_tx_swap = true; 1350 1351 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1352 port->cts_rts_swap = true; 1353 1354 uport->private_data = drv; 1355 platform_set_drvdata(pdev, port); 1356 port->handle_rx = console ? handle_rx_console : handle_rx_uart; 1357 1358 ret = uart_add_one_port(drv, uport); 1359 if (ret) 1360 return ret; 1361 1362 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1363 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1364 IRQF_TRIGGER_HIGH, port->name, uport); 1365 if (ret) { 1366 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1367 uart_remove_one_port(drv, uport); 1368 return ret; 1369 } 1370 1371 /* 1372 * Set pm_runtime status as ACTIVE so that wakeup_irq gets 1373 * enabled/disabled from dev_pm_arm_wake_irq during system 1374 * suspend/resume respectively. 1375 */ 1376 pm_runtime_set_active(&pdev->dev); 1377 1378 if (port->wakeup_irq > 0) { 1379 device_init_wakeup(&pdev->dev, true); 1380 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1381 port->wakeup_irq); 1382 if (ret) { 1383 device_init_wakeup(&pdev->dev, false); 1384 uart_remove_one_port(drv, uport); 1385 return ret; 1386 } 1387 } 1388 1389 return 0; 1390 } 1391 1392 static int qcom_geni_serial_remove(struct platform_device *pdev) 1393 { 1394 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1395 struct uart_driver *drv = port->uport.private_data; 1396 1397 dev_pm_clear_wake_irq(&pdev->dev); 1398 device_init_wakeup(&pdev->dev, false); 1399 uart_remove_one_port(drv, &port->uport); 1400 1401 return 0; 1402 } 1403 1404 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev) 1405 { 1406 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1407 struct uart_port *uport = &port->uport; 1408 1409 return uart_suspend_port(uport->private_data, uport); 1410 } 1411 1412 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev) 1413 { 1414 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1415 struct uart_port *uport = &port->uport; 1416 1417 return uart_resume_port(uport->private_data, uport); 1418 } 1419 1420 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1421 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1422 qcom_geni_serial_sys_resume) 1423 }; 1424 1425 static const struct of_device_id qcom_geni_serial_match_table[] = { 1426 { .compatible = "qcom,geni-debug-uart", }, 1427 { .compatible = "qcom,geni-uart", }, 1428 {} 1429 }; 1430 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1431 1432 static struct platform_driver qcom_geni_serial_platform_driver = { 1433 .remove = qcom_geni_serial_remove, 1434 .probe = qcom_geni_serial_probe, 1435 .driver = { 1436 .name = "qcom_geni_serial", 1437 .of_match_table = qcom_geni_serial_match_table, 1438 .pm = &qcom_geni_serial_pm_ops, 1439 }, 1440 }; 1441 1442 static int __init qcom_geni_serial_init(void) 1443 { 1444 int ret; 1445 1446 ret = console_register(&qcom_geni_console_driver); 1447 if (ret) 1448 return ret; 1449 1450 ret = uart_register_driver(&qcom_geni_uart_driver); 1451 if (ret) { 1452 console_unregister(&qcom_geni_console_driver); 1453 return ret; 1454 } 1455 1456 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1457 if (ret) { 1458 console_unregister(&qcom_geni_console_driver); 1459 uart_unregister_driver(&qcom_geni_uart_driver); 1460 } 1461 return ret; 1462 } 1463 module_init(qcom_geni_serial_init); 1464 1465 static void __exit qcom_geni_serial_exit(void) 1466 { 1467 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1468 console_unregister(&qcom_geni_console_driver); 1469 uart_unregister_driver(&qcom_geni_uart_driver); 1470 } 1471 module_exit(qcom_geni_serial_exit); 1472 1473 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1474 MODULE_LICENSE("GPL v2"); 1475