1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3 
4 #if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5 # define SUPPORT_SYSRQ
6 #endif
7 
8 #include <linux/clk.h>
9 #include <linux/console.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/qcom-geni-se.h>
17 #include <linux/serial.h>
18 #include <linux/serial_core.h>
19 #include <linux/slab.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 
23 /* UART specific GENI registers */
24 #define SE_UART_LOOPBACK_CFG		0x22c
25 #define SE_UART_TX_TRANS_CFG		0x25c
26 #define SE_UART_TX_WORD_LEN		0x268
27 #define SE_UART_TX_STOP_BIT_LEN		0x26c
28 #define SE_UART_TX_TRANS_LEN		0x270
29 #define SE_UART_RX_TRANS_CFG		0x280
30 #define SE_UART_RX_WORD_LEN		0x28c
31 #define SE_UART_RX_STALE_CNT		0x294
32 #define SE_UART_TX_PARITY_CFG		0x2a4
33 #define SE_UART_RX_PARITY_CFG		0x2a8
34 #define SE_UART_MANUAL_RFR		0x2ac
35 
36 /* SE_UART_TRANS_CFG */
37 #define UART_TX_PAR_EN		BIT(0)
38 #define UART_CTS_MASK		BIT(1)
39 
40 /* SE_UART_TX_WORD_LEN */
41 #define TX_WORD_LEN_MSK		GENMASK(9, 0)
42 
43 /* SE_UART_TX_STOP_BIT_LEN */
44 #define TX_STOP_BIT_LEN_MSK	GENMASK(23, 0)
45 #define TX_STOP_BIT_LEN_1	0
46 #define TX_STOP_BIT_LEN_1_5	1
47 #define TX_STOP_BIT_LEN_2	2
48 
49 /* SE_UART_TX_TRANS_LEN */
50 #define TX_TRANS_LEN_MSK	GENMASK(23, 0)
51 
52 /* SE_UART_RX_TRANS_CFG */
53 #define UART_RX_INS_STATUS_BIT	BIT(2)
54 #define UART_RX_PAR_EN		BIT(3)
55 
56 /* SE_UART_RX_WORD_LEN */
57 #define RX_WORD_LEN_MASK	GENMASK(9, 0)
58 
59 /* SE_UART_RX_STALE_CNT */
60 #define RX_STALE_CNT		GENMASK(23, 0)
61 
62 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
63 #define PAR_CALC_EN		BIT(0)
64 #define PAR_MODE_MSK		GENMASK(2, 1)
65 #define PAR_MODE_SHFT		1
66 #define PAR_EVEN		0x00
67 #define PAR_ODD			0x01
68 #define PAR_SPACE		0x10
69 #define PAR_MARK		0x11
70 
71 /* SE_UART_MANUAL_RFR register fields */
72 #define UART_MANUAL_RFR_EN	BIT(31)
73 #define UART_RFR_NOT_READY	BIT(1)
74 #define UART_RFR_READY		BIT(0)
75 
76 /* UART M_CMD OP codes */
77 #define UART_START_TX		0x1
78 #define UART_START_BREAK	0x4
79 #define UART_STOP_BREAK		0x5
80 /* UART S_CMD OP codes */
81 #define UART_START_READ		0x1
82 #define UART_PARAM		0x1
83 
84 #define UART_OVERSAMPLING	32
85 #define STALE_TIMEOUT		16
86 #define DEFAULT_BITS_PER_CHAR	10
87 #define GENI_UART_CONS_PORTS	1
88 #define GENI_UART_PORTS		3
89 #define DEF_FIFO_DEPTH_WORDS	16
90 #define DEF_TX_WM		2
91 #define DEF_FIFO_WIDTH_BITS	32
92 #define UART_CONSOLE_RX_WM	2
93 #define MAX_LOOPBACK_CFG	3
94 
95 #ifdef CONFIG_CONSOLE_POLL
96 #define CONSOLE_RX_BYTES_PW 1
97 #else
98 #define CONSOLE_RX_BYTES_PW 4
99 #endif
100 
101 struct qcom_geni_serial_port {
102 	struct uart_port uport;
103 	struct geni_se se;
104 	char name[20];
105 	u32 tx_fifo_depth;
106 	u32 tx_fifo_width;
107 	u32 rx_fifo_depth;
108 	u32 tx_wm;
109 	u32 rx_wm;
110 	u32 rx_rfr;
111 	enum geni_se_xfer_mode xfer_mode;
112 	bool setup;
113 	int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
114 	unsigned int baud;
115 	unsigned int tx_bytes_pw;
116 	unsigned int rx_bytes_pw;
117 	u32 *rx_fifo;
118 	u32 loopback;
119 	bool brk;
120 
121 	unsigned int tx_remaining;
122 };
123 
124 static const struct uart_ops qcom_geni_console_pops;
125 static const struct uart_ops qcom_geni_uart_pops;
126 static struct uart_driver qcom_geni_console_driver;
127 static struct uart_driver qcom_geni_uart_driver;
128 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
129 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
130 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
131 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
132 
133 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
134 					32000000, 48000000, 64000000, 80000000,
135 					96000000, 100000000, 102400000,
136 					112000000, 120000000, 128000000};
137 
138 #define to_dev_port(ptr, member) \
139 		container_of(ptr, struct qcom_geni_serial_port, member)
140 
141 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
142 	[0] = {
143 		.uport = {
144 				.iotype = UPIO_MEM,
145 				.ops = &qcom_geni_uart_pops,
146 				.flags = UPF_BOOT_AUTOCONF,
147 				.line = 0,
148 		},
149 	},
150 	[1] = {
151 		.uport = {
152 				.iotype = UPIO_MEM,
153 				.ops = &qcom_geni_uart_pops,
154 				.flags = UPF_BOOT_AUTOCONF,
155 				.line = 1,
156 		},
157 	},
158 	[2] = {
159 		.uport = {
160 				.iotype = UPIO_MEM,
161 				.ops = &qcom_geni_uart_pops,
162 				.flags = UPF_BOOT_AUTOCONF,
163 				.line = 2,
164 		},
165 	},
166 };
167 
168 static ssize_t loopback_show(struct device *dev,
169 				struct device_attribute *attr, char *buf)
170 {
171 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
172 
173 	return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
174 }
175 
176 static ssize_t loopback_store(struct device *dev,
177 				struct device_attribute *attr, const char *buf,
178 				size_t size)
179 {
180 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
181 	u32 loopback;
182 
183 	if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
184 		dev_err(dev, "Invalid input\n");
185 		return -EINVAL;
186 	}
187 	port->loopback = loopback;
188 	return size;
189 }
190 static DEVICE_ATTR_RW(loopback);
191 
192 static struct qcom_geni_serial_port qcom_geni_console_port = {
193 	.uport = {
194 		.iotype = UPIO_MEM,
195 		.ops = &qcom_geni_console_pops,
196 		.flags = UPF_BOOT_AUTOCONF,
197 		.line = 0,
198 	},
199 };
200 
201 static int qcom_geni_serial_request_port(struct uart_port *uport)
202 {
203 	struct platform_device *pdev = to_platform_device(uport->dev);
204 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
205 	struct resource *res;
206 
207 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 	uport->membase = devm_ioremap_resource(&pdev->dev, res);
209 	if (IS_ERR(uport->membase))
210 		return PTR_ERR(uport->membase);
211 	port->se.base = uport->membase;
212 	return 0;
213 }
214 
215 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
216 {
217 	if (cfg_flags & UART_CONFIG_TYPE) {
218 		uport->type = PORT_MSM;
219 		qcom_geni_serial_request_port(uport);
220 	}
221 }
222 
223 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
224 {
225 	unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
226 	u32 geni_ios;
227 
228 	if (uart_console(uport) || !uart_cts_enabled(uport)) {
229 		mctrl |= TIOCM_CTS;
230 	} else {
231 		geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS);
232 		if (!(geni_ios & IO2_DATA_IN))
233 			mctrl |= TIOCM_CTS;
234 	}
235 
236 	return mctrl;
237 }
238 
239 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
240 							unsigned int mctrl)
241 {
242 	u32 uart_manual_rfr = 0;
243 
244 	if (uart_console(uport) || !uart_cts_enabled(uport))
245 		return;
246 
247 	if (!(mctrl & TIOCM_RTS))
248 		uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
249 	writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
250 }
251 
252 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
253 {
254 	return "MSM";
255 }
256 
257 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
258 {
259 	struct qcom_geni_serial_port *port;
260 	int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
261 
262 	if (line < 0 || line >= nr_ports)
263 		return ERR_PTR(-ENXIO);
264 
265 	port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
266 	return port;
267 }
268 
269 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
270 				int offset, int field, bool set)
271 {
272 	u32 reg;
273 	struct qcom_geni_serial_port *port;
274 	unsigned int baud;
275 	unsigned int fifo_bits;
276 	unsigned long timeout_us = 20000;
277 
278 	/* Ensure polling is not re-ordered before the prior writes/reads */
279 	mb();
280 
281 	if (uport->private_data) {
282 		port = to_dev_port(uport, uport);
283 		baud = port->baud;
284 		if (!baud)
285 			baud = 115200;
286 		fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
287 		/*
288 		 * Total polling iterations based on FIFO worth of bytes to be
289 		 * sent at current baud. Add a little fluff to the wait.
290 		 */
291 		timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
292 	}
293 
294 	/*
295 	 * Use custom implementation instead of readl_poll_atomic since ktimer
296 	 * is not ready at the time of early console.
297 	 */
298 	timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
299 	while (timeout_us) {
300 		reg = readl_relaxed(uport->membase + offset);
301 		if ((bool)(reg & field) == set)
302 			return true;
303 		udelay(10);
304 		timeout_us -= 10;
305 	}
306 	return false;
307 }
308 
309 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
310 {
311 	u32 m_cmd;
312 
313 	writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
314 	m_cmd = UART_START_TX << M_OPCODE_SHFT;
315 	writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
316 }
317 
318 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
319 {
320 	int done;
321 	u32 irq_clear = M_CMD_DONE_EN;
322 
323 	done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
324 						M_CMD_DONE_EN, true);
325 	if (!done) {
326 		writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
327 						SE_GENI_M_CMD_CTRL_REG);
328 		irq_clear |= M_CMD_ABORT_EN;
329 		qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
330 							M_CMD_ABORT_EN, true);
331 	}
332 	writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
333 }
334 
335 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
336 {
337 	u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
338 
339 	writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
340 	qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
341 					S_GENI_CMD_ABORT, false);
342 	writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
343 	writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
344 }
345 
346 #ifdef CONFIG_CONSOLE_POLL
347 static int qcom_geni_serial_get_char(struct uart_port *uport)
348 {
349 	u32 rx_fifo;
350 	u32 status;
351 
352 	status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
353 	writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
354 
355 	status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
356 	writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
357 
358 	/*
359 	 * Ensure the writes to clear interrupts is not re-ordered after
360 	 * reading the data.
361 	 */
362 	mb();
363 
364 	status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
365 	if (!(status & RX_FIFO_WC_MSK))
366 		return NO_POLL_CHAR;
367 
368 	rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
369 	return rx_fifo & 0xff;
370 }
371 
372 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
373 							unsigned char c)
374 {
375 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
376 
377 	writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
378 	qcom_geni_serial_setup_tx(uport, 1);
379 	WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
380 						M_TX_FIFO_WATERMARK_EN, true));
381 	writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
382 	writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
383 							SE_GENI_M_IRQ_CLEAR);
384 	qcom_geni_serial_poll_tx_done(uport);
385 }
386 #endif
387 
388 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
389 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
390 {
391 	writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
392 }
393 
394 static void
395 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
396 				 unsigned int count)
397 {
398 	int i;
399 	u32 bytes_to_send = count;
400 
401 	for (i = 0; i < count; i++) {
402 		/*
403 		 * uart_console_write() adds a carriage return for each newline.
404 		 * Account for additional bytes to be written.
405 		 */
406 		if (s[i] == '\n')
407 			bytes_to_send++;
408 	}
409 
410 	writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
411 	qcom_geni_serial_setup_tx(uport, bytes_to_send);
412 	for (i = 0; i < count; ) {
413 		size_t chars_to_write = 0;
414 		size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
415 
416 		/*
417 		 * If the WM bit never set, then the Tx state machine is not
418 		 * in a valid state, so break, cancel/abort any existing
419 		 * command. Unfortunately the current data being written is
420 		 * lost.
421 		 */
422 		if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
423 						M_TX_FIFO_WATERMARK_EN, true))
424 			break;
425 		chars_to_write = min_t(size_t, count - i, avail / 2);
426 		uart_console_write(uport, s + i, chars_to_write,
427 						qcom_geni_serial_wr_char);
428 		writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
429 							SE_GENI_M_IRQ_CLEAR);
430 		i += chars_to_write;
431 	}
432 	qcom_geni_serial_poll_tx_done(uport);
433 }
434 
435 static void qcom_geni_serial_console_write(struct console *co, const char *s,
436 			      unsigned int count)
437 {
438 	struct uart_port *uport;
439 	struct qcom_geni_serial_port *port;
440 	bool locked = true;
441 	unsigned long flags;
442 	u32 geni_status;
443 
444 	WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
445 
446 	port = get_port_from_line(co->index, true);
447 	if (IS_ERR(port))
448 		return;
449 
450 	uport = &port->uport;
451 	if (oops_in_progress)
452 		locked = spin_trylock_irqsave(&uport->lock, flags);
453 	else
454 		spin_lock_irqsave(&uport->lock, flags);
455 
456 	geni_status = readl_relaxed(uport->membase + SE_GENI_STATUS);
457 
458 	/* Cancel the current write to log the fault */
459 	if (!locked) {
460 		geni_se_cancel_m_cmd(&port->se);
461 		if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
462 						M_CMD_CANCEL_EN, true)) {
463 			geni_se_abort_m_cmd(&port->se);
464 			qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
465 							M_CMD_ABORT_EN, true);
466 			writel_relaxed(M_CMD_ABORT_EN, uport->membase +
467 							SE_GENI_M_IRQ_CLEAR);
468 		}
469 		writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
470 							SE_GENI_M_IRQ_CLEAR);
471 	} else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
472 		/*
473 		 * It seems we can't interrupt existing transfers if all data
474 		 * has been sent, in which case we need to look for done first.
475 		 */
476 		qcom_geni_serial_poll_tx_done(uport);
477 	}
478 
479 	__qcom_geni_serial_console_write(uport, s, count);
480 
481 	if (port->tx_remaining)
482 		qcom_geni_serial_setup_tx(uport, port->tx_remaining);
483 
484 	if (locked)
485 		spin_unlock_irqrestore(&uport->lock, flags);
486 }
487 
488 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
489 {
490 	u32 i;
491 	unsigned char buf[sizeof(u32)];
492 	struct tty_port *tport;
493 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
494 
495 	tport = &uport->state->port;
496 	for (i = 0; i < bytes; ) {
497 		int c;
498 		int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
499 
500 		ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
501 		i += chunk;
502 		if (drop)
503 			continue;
504 
505 		for (c = 0; c < chunk; c++) {
506 			int sysrq;
507 
508 			uport->icount.rx++;
509 			if (port->brk && buf[c] == 0) {
510 				port->brk = false;
511 				if (uart_handle_break(uport))
512 					continue;
513 			}
514 
515 			sysrq = uart_prepare_sysrq_char(uport, buf[c]);
516 
517 			if (!sysrq)
518 				tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
519 		}
520 	}
521 	if (!drop)
522 		tty_flip_buffer_push(tport);
523 	return 0;
524 }
525 #else
526 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
527 {
528 	return -EPERM;
529 }
530 
531 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
532 
533 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
534 {
535 	unsigned char *buf;
536 	struct tty_port *tport;
537 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
538 	u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
539 	u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
540 	int ret;
541 
542 	tport = &uport->state->port;
543 	ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
544 	if (drop)
545 		return 0;
546 
547 	buf = (unsigned char *)port->rx_fifo;
548 	ret = tty_insert_flip_string(tport, buf, bytes);
549 	if (ret != bytes) {
550 		dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
551 				__func__, ret, bytes);
552 		WARN_ON_ONCE(1);
553 	}
554 	uport->icount.rx += ret;
555 	tty_flip_buffer_push(tport);
556 	return ret;
557 }
558 
559 static void qcom_geni_serial_start_tx(struct uart_port *uport)
560 {
561 	u32 irq_en;
562 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
563 	u32 status;
564 
565 	if (port->xfer_mode == GENI_SE_FIFO) {
566 		/*
567 		 * readl ensures reading & writing of IRQ_EN register
568 		 * is not re-ordered before checking the status of the
569 		 * Serial Engine.
570 		 */
571 		status = readl(uport->membase + SE_GENI_STATUS);
572 		if (status & M_GENI_CMD_ACTIVE)
573 			return;
574 
575 		if (!qcom_geni_serial_tx_empty(uport))
576 			return;
577 
578 		irq_en = readl_relaxed(uport->membase +	SE_GENI_M_IRQ_EN);
579 		irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
580 
581 		writel_relaxed(port->tx_wm, uport->membase +
582 						SE_GENI_TX_WATERMARK_REG);
583 		writel_relaxed(irq_en, uport->membase +	SE_GENI_M_IRQ_EN);
584 	}
585 }
586 
587 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
588 {
589 	u32 irq_en;
590 	u32 status;
591 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
592 
593 	irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
594 	irq_en &= ~M_CMD_DONE_EN;
595 	if (port->xfer_mode == GENI_SE_FIFO) {
596 		irq_en &= ~M_TX_FIFO_WATERMARK_EN;
597 		writel_relaxed(0, uport->membase +
598 				     SE_GENI_TX_WATERMARK_REG);
599 	}
600 	writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
601 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
602 	/* Possible stop tx is called multiple times. */
603 	if (!(status & M_GENI_CMD_ACTIVE))
604 		return;
605 
606 	/*
607 	 * Ensure cancel command write is not re-ordered before checking
608 	 * the status of the Primary Sequencer.
609 	 */
610 	mb();
611 
612 	geni_se_cancel_m_cmd(&port->se);
613 	if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
614 						M_CMD_CANCEL_EN, true)) {
615 		geni_se_abort_m_cmd(&port->se);
616 		qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
617 						M_CMD_ABORT_EN, true);
618 		writel_relaxed(M_CMD_ABORT_EN, uport->membase +
619 							SE_GENI_M_IRQ_CLEAR);
620 	}
621 	writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
622 }
623 
624 static void qcom_geni_serial_start_rx(struct uart_port *uport)
625 {
626 	u32 irq_en;
627 	u32 status;
628 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
629 
630 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
631 	if (status & S_GENI_CMD_ACTIVE)
632 		qcom_geni_serial_stop_rx(uport);
633 
634 	/*
635 	 * Ensure setup command write is not re-ordered before checking
636 	 * the status of the Secondary Sequencer.
637 	 */
638 	mb();
639 
640 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
641 
642 	if (port->xfer_mode == GENI_SE_FIFO) {
643 		irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
644 		irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
645 		writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
646 
647 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
648 		irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
649 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
650 	}
651 }
652 
653 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
654 {
655 	u32 irq_en;
656 	u32 status;
657 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
658 	u32 irq_clear = S_CMD_DONE_EN;
659 
660 	if (port->xfer_mode == GENI_SE_FIFO) {
661 		irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
662 		irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
663 		writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
664 
665 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
666 		irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
667 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
668 	}
669 
670 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
671 	/* Possible stop rx is called multiple times. */
672 	if (!(status & S_GENI_CMD_ACTIVE))
673 		return;
674 
675 	/*
676 	 * Ensure cancel command write is not re-ordered before checking
677 	 * the status of the Secondary Sequencer.
678 	 */
679 	mb();
680 
681 	geni_se_cancel_s_cmd(&port->se);
682 	qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
683 					S_GENI_CMD_CANCEL, false);
684 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
685 	writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
686 	if (status & S_GENI_CMD_ACTIVE)
687 		qcom_geni_serial_abort_rx(uport);
688 }
689 
690 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
691 {
692 	u32 status;
693 	u32 word_cnt;
694 	u32 last_word_byte_cnt;
695 	u32 last_word_partial;
696 	u32 total_bytes;
697 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
698 
699 	status = readl_relaxed(uport->membase +	SE_GENI_RX_FIFO_STATUS);
700 	word_cnt = status & RX_FIFO_WC_MSK;
701 	last_word_partial = status & RX_LAST;
702 	last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
703 						RX_LAST_BYTE_VALID_SHFT;
704 
705 	if (!word_cnt)
706 		return;
707 	total_bytes = port->rx_bytes_pw * (word_cnt - 1);
708 	if (last_word_partial && last_word_byte_cnt)
709 		total_bytes += last_word_byte_cnt;
710 	else
711 		total_bytes += port->rx_bytes_pw;
712 	port->handle_rx(uport, total_bytes, drop);
713 }
714 
715 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
716 		bool active)
717 {
718 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
719 	struct circ_buf *xmit = &uport->state->xmit;
720 	size_t avail;
721 	size_t remaining;
722 	size_t pending;
723 	int i;
724 	u32 status;
725 	u32 irq_en;
726 	unsigned int chunk;
727 	int tail;
728 
729 	status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
730 
731 	/* Complete the current tx command before taking newly added data */
732 	if (active)
733 		pending = port->tx_remaining;
734 	else
735 		pending = uart_circ_chars_pending(xmit);
736 
737 	/* All data has been transmitted and acknowledged as received */
738 	if (!pending && !status && done) {
739 		qcom_geni_serial_stop_tx(uport);
740 		goto out_write_wakeup;
741 	}
742 
743 	avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
744 	avail *= port->tx_bytes_pw;
745 
746 	tail = xmit->tail;
747 	chunk = min3(avail, pending, (size_t)(UART_XMIT_SIZE - tail));
748 	if (!chunk)
749 		goto out_write_wakeup;
750 
751 	if (!port->tx_remaining) {
752 		qcom_geni_serial_setup_tx(uport, pending);
753 		port->tx_remaining = pending;
754 
755 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
756 		if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
757 			writel_relaxed(irq_en | M_TX_FIFO_WATERMARK_EN,
758 					uport->membase + SE_GENI_M_IRQ_EN);
759 	}
760 
761 	remaining = chunk;
762 	for (i = 0; i < chunk; ) {
763 		unsigned int tx_bytes;
764 		u8 buf[sizeof(u32)];
765 		int c;
766 
767 		memset(buf, 0, ARRAY_SIZE(buf));
768 		tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
769 		for (c = 0; c < tx_bytes ; c++)
770 			buf[c] = xmit->buf[tail + c];
771 
772 		iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
773 
774 		i += tx_bytes;
775 		tail += tx_bytes;
776 		uport->icount.tx += tx_bytes;
777 		remaining -= tx_bytes;
778 		port->tx_remaining -= tx_bytes;
779 	}
780 
781 	xmit->tail = tail & (UART_XMIT_SIZE - 1);
782 
783 	/*
784 	 * The tx fifo watermark is level triggered and latched. Though we had
785 	 * cleared it in qcom_geni_serial_isr it will have already reasserted
786 	 * so we must clear it again here after our writes.
787 	 */
788 	writel_relaxed(M_TX_FIFO_WATERMARK_EN,
789 			uport->membase + SE_GENI_M_IRQ_CLEAR);
790 
791 out_write_wakeup:
792 	if (!port->tx_remaining) {
793 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
794 		if (irq_en & M_TX_FIFO_WATERMARK_EN)
795 			writel_relaxed(irq_en & ~M_TX_FIFO_WATERMARK_EN,
796 					uport->membase + SE_GENI_M_IRQ_EN);
797 	}
798 
799 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
800 		uart_write_wakeup(uport);
801 }
802 
803 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
804 {
805 	unsigned int m_irq_status;
806 	unsigned int s_irq_status;
807 	unsigned int geni_status;
808 	struct uart_port *uport = dev;
809 	unsigned long flags;
810 	unsigned int m_irq_en;
811 	bool drop_rx = false;
812 	struct tty_port *tport = &uport->state->port;
813 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
814 
815 	if (uport->suspended)
816 		return IRQ_NONE;
817 
818 	spin_lock_irqsave(&uport->lock, flags);
819 	m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
820 	s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
821 	geni_status = readl_relaxed(uport->membase + SE_GENI_STATUS);
822 	m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
823 	writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
824 	writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
825 
826 	if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
827 		goto out_unlock;
828 
829 	if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
830 		uport->icount.overrun++;
831 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
832 	}
833 
834 	if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
835 		qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
836 					geni_status & M_GENI_CMD_ACTIVE);
837 
838 	if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
839 		if (s_irq_status & S_GP_IRQ_0_EN)
840 			uport->icount.parity++;
841 		drop_rx = true;
842 	} else if (s_irq_status & S_GP_IRQ_2_EN ||
843 					s_irq_status & S_GP_IRQ_3_EN) {
844 		uport->icount.brk++;
845 		port->brk = true;
846 	}
847 
848 	if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
849 					s_irq_status & S_RX_FIFO_LAST_EN)
850 		qcom_geni_serial_handle_rx(uport, drop_rx);
851 
852 out_unlock:
853 	uart_unlock_and_check_sysrq(uport, flags);
854 
855 	return IRQ_HANDLED;
856 }
857 
858 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
859 {
860 	struct uart_port *uport;
861 
862 	uport = &port->uport;
863 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
864 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
865 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
866 	uport->fifosize =
867 		(port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
868 }
869 
870 static void set_rfr_wm(struct qcom_geni_serial_port *port)
871 {
872 	/*
873 	 * Set RFR (Flow off) to FIFO_DEPTH - 2.
874 	 * RX WM level at 10% RX_FIFO_DEPTH.
875 	 * TX WM level at 10% TX_FIFO_DEPTH.
876 	 */
877 	port->rx_rfr = port->rx_fifo_depth - 2;
878 	port->rx_wm = UART_CONSOLE_RX_WM;
879 	port->tx_wm = DEF_TX_WM;
880 }
881 
882 static void qcom_geni_serial_shutdown(struct uart_port *uport)
883 {
884 	unsigned long flags;
885 
886 	/* Stop the console before stopping the current tx */
887 	if (uart_console(uport))
888 		console_stop(uport->cons);
889 
890 	free_irq(uport->irq, uport);
891 	spin_lock_irqsave(&uport->lock, flags);
892 	qcom_geni_serial_stop_tx(uport);
893 	qcom_geni_serial_stop_rx(uport);
894 	spin_unlock_irqrestore(&uport->lock, flags);
895 }
896 
897 static int qcom_geni_serial_port_setup(struct uart_port *uport)
898 {
899 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
900 	unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
901 	u32 proto;
902 
903 	if (uart_console(uport)) {
904 		port->tx_bytes_pw = 1;
905 		port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
906 	} else {
907 		port->tx_bytes_pw = 4;
908 		port->rx_bytes_pw = 4;
909 	}
910 
911 	proto = geni_se_read_proto(&port->se);
912 	if (proto != GENI_SE_UART) {
913 		dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
914 		return -ENXIO;
915 	}
916 
917 	qcom_geni_serial_stop_rx(uport);
918 
919 	get_tx_fifo_size(port);
920 
921 	set_rfr_wm(port);
922 	writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
923 	/*
924 	 * Make an unconditional cancel on the main sequencer to reset
925 	 * it else we could end up in data loss scenarios.
926 	 */
927 	port->xfer_mode = GENI_SE_FIFO;
928 	if (uart_console(uport))
929 		qcom_geni_serial_poll_tx_done(uport);
930 	geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
931 						false, true, false);
932 	geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
933 						false, false, true);
934 	geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
935 	geni_se_select_mode(&port->se, port->xfer_mode);
936 	if (!uart_console(uport)) {
937 		port->rx_fifo = devm_kcalloc(uport->dev,
938 			port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
939 		if (!port->rx_fifo)
940 			return -ENOMEM;
941 	}
942 	port->setup = true;
943 
944 	return 0;
945 }
946 
947 static int qcom_geni_serial_startup(struct uart_port *uport)
948 {
949 	int ret;
950 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
951 
952 	scnprintf(port->name, sizeof(port->name),
953 		  "qcom_serial_%s%d",
954 		(uart_console(uport) ? "console" : "uart"), uport->line);
955 
956 	if (!port->setup) {
957 		ret = qcom_geni_serial_port_setup(uport);
958 		if (ret)
959 			return ret;
960 	}
961 
962 	ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
963 							port->name, uport);
964 	if (ret)
965 		dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
966 	return ret;
967 }
968 
969 static unsigned long get_clk_cfg(unsigned long clk_freq)
970 {
971 	int i;
972 
973 	for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
974 		if (!(root_freq[i] % clk_freq))
975 			return root_freq[i];
976 	}
977 	return 0;
978 }
979 
980 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
981 {
982 	unsigned long ser_clk;
983 	unsigned long desired_clk;
984 
985 	desired_clk = baud * UART_OVERSAMPLING;
986 	ser_clk = get_clk_cfg(desired_clk);
987 	if (!ser_clk) {
988 		pr_err("%s: Can't find matching DFS entry for baud %d\n",
989 								__func__, baud);
990 		return ser_clk;
991 	}
992 
993 	*clk_div = ser_clk / desired_clk;
994 	return ser_clk;
995 }
996 
997 static void qcom_geni_serial_set_termios(struct uart_port *uport,
998 				struct ktermios *termios, struct ktermios *old)
999 {
1000 	unsigned int baud;
1001 	unsigned int bits_per_char;
1002 	unsigned int tx_trans_cfg;
1003 	unsigned int tx_parity_cfg;
1004 	unsigned int rx_trans_cfg;
1005 	unsigned int rx_parity_cfg;
1006 	unsigned int stop_bit_len;
1007 	unsigned int clk_div;
1008 	unsigned long ser_clk_cfg;
1009 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1010 	unsigned long clk_rate;
1011 
1012 	qcom_geni_serial_stop_rx(uport);
1013 	/* baud rate */
1014 	baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1015 	port->baud = baud;
1016 	clk_rate = get_clk_div_rate(baud, &clk_div);
1017 	if (!clk_rate)
1018 		goto out_restart_rx;
1019 
1020 	uport->uartclk = clk_rate;
1021 	clk_set_rate(port->se.clk, clk_rate);
1022 	ser_clk_cfg = SER_CLK_EN;
1023 	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1024 
1025 	/* parity */
1026 	tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
1027 	tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
1028 	rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
1029 	rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
1030 	if (termios->c_cflag & PARENB) {
1031 		tx_trans_cfg |= UART_TX_PAR_EN;
1032 		rx_trans_cfg |= UART_RX_PAR_EN;
1033 		tx_parity_cfg |= PAR_CALC_EN;
1034 		rx_parity_cfg |= PAR_CALC_EN;
1035 		if (termios->c_cflag & PARODD) {
1036 			tx_parity_cfg |= PAR_ODD;
1037 			rx_parity_cfg |= PAR_ODD;
1038 		} else if (termios->c_cflag & CMSPAR) {
1039 			tx_parity_cfg |= PAR_SPACE;
1040 			rx_parity_cfg |= PAR_SPACE;
1041 		} else {
1042 			tx_parity_cfg |= PAR_EVEN;
1043 			rx_parity_cfg |= PAR_EVEN;
1044 		}
1045 	} else {
1046 		tx_trans_cfg &= ~UART_TX_PAR_EN;
1047 		rx_trans_cfg &= ~UART_RX_PAR_EN;
1048 		tx_parity_cfg &= ~PAR_CALC_EN;
1049 		rx_parity_cfg &= ~PAR_CALC_EN;
1050 	}
1051 
1052 	/* bits per char */
1053 	switch (termios->c_cflag & CSIZE) {
1054 	case CS5:
1055 		bits_per_char = 5;
1056 		break;
1057 	case CS6:
1058 		bits_per_char = 6;
1059 		break;
1060 	case CS7:
1061 		bits_per_char = 7;
1062 		break;
1063 	case CS8:
1064 	default:
1065 		bits_per_char = 8;
1066 		break;
1067 	}
1068 
1069 	/* stop bits */
1070 	if (termios->c_cflag & CSTOPB)
1071 		stop_bit_len = TX_STOP_BIT_LEN_2;
1072 	else
1073 		stop_bit_len = TX_STOP_BIT_LEN_1;
1074 
1075 	/* flow control, clear the CTS_MASK bit if using flow control. */
1076 	if (termios->c_cflag & CRTSCTS)
1077 		tx_trans_cfg &= ~UART_CTS_MASK;
1078 	else
1079 		tx_trans_cfg |= UART_CTS_MASK;
1080 
1081 	if (baud)
1082 		uart_update_timeout(uport, termios->c_cflag, baud);
1083 
1084 	if (!uart_console(uport))
1085 		writel_relaxed(port->loopback,
1086 				uport->membase + SE_UART_LOOPBACK_CFG);
1087 	writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1088 	writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1089 	writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1090 	writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1091 	writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1092 	writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1093 	writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1094 	writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1095 	writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1096 out_restart_rx:
1097 	qcom_geni_serial_start_rx(uport);
1098 }
1099 
1100 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1101 {
1102 	return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1103 }
1104 
1105 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1106 static int __init qcom_geni_console_setup(struct console *co, char *options)
1107 {
1108 	struct uart_port *uport;
1109 	struct qcom_geni_serial_port *port;
1110 	int baud;
1111 	int bits = 8;
1112 	int parity = 'n';
1113 	int flow = 'n';
1114 	int ret;
1115 
1116 	if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1117 		return -ENXIO;
1118 
1119 	port = get_port_from_line(co->index, true);
1120 	if (IS_ERR(port)) {
1121 		pr_err("Invalid line %d\n", co->index);
1122 		return PTR_ERR(port);
1123 	}
1124 
1125 	uport = &port->uport;
1126 
1127 	if (unlikely(!uport->membase))
1128 		return -ENXIO;
1129 
1130 	if (!port->setup) {
1131 		ret = qcom_geni_serial_port_setup(uport);
1132 		if (ret)
1133 			return ret;
1134 	}
1135 
1136 	if (options)
1137 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1138 
1139 	return uart_set_options(uport, co, baud, parity, bits, flow);
1140 }
1141 
1142 static void qcom_geni_serial_earlycon_write(struct console *con,
1143 					const char *s, unsigned int n)
1144 {
1145 	struct earlycon_device *dev = con->data;
1146 
1147 	__qcom_geni_serial_console_write(&dev->port, s, n);
1148 }
1149 
1150 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1151 								const char *opt)
1152 {
1153 	struct uart_port *uport = &dev->port;
1154 	u32 tx_trans_cfg;
1155 	u32 tx_parity_cfg = 0;	/* Disable Tx Parity */
1156 	u32 rx_trans_cfg = 0;
1157 	u32 rx_parity_cfg = 0;	/* Disable Rx Parity */
1158 	u32 stop_bit_len = 0;	/* Default stop bit length - 1 bit */
1159 	u32 bits_per_char;
1160 	struct geni_se se;
1161 
1162 	if (!uport->membase)
1163 		return -EINVAL;
1164 
1165 	memset(&se, 0, sizeof(se));
1166 	se.base = uport->membase;
1167 	if (geni_se_read_proto(&se) != GENI_SE_UART)
1168 		return -ENXIO;
1169 	/*
1170 	 * Ignore Flow control.
1171 	 * n = 8.
1172 	 */
1173 	tx_trans_cfg = UART_CTS_MASK;
1174 	bits_per_char = BITS_PER_BYTE;
1175 
1176 	/*
1177 	 * Make an unconditional cancel on the main sequencer to reset
1178 	 * it else we could end up in data loss scenarios.
1179 	 */
1180 	qcom_geni_serial_poll_tx_done(uport);
1181 	qcom_geni_serial_abort_rx(uport);
1182 	geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1183 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1184 	geni_se_select_mode(&se, GENI_SE_FIFO);
1185 
1186 	writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1187 	writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1188 	writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1189 	writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1190 	writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1191 	writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1192 	writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1193 
1194 	dev->con->write = qcom_geni_serial_earlycon_write;
1195 	dev->con->setup = NULL;
1196 	return 0;
1197 }
1198 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1199 				qcom_geni_serial_earlycon_setup);
1200 
1201 static int __init console_register(struct uart_driver *drv)
1202 {
1203 	return uart_register_driver(drv);
1204 }
1205 
1206 static void console_unregister(struct uart_driver *drv)
1207 {
1208 	uart_unregister_driver(drv);
1209 }
1210 
1211 static struct console cons_ops = {
1212 	.name = "ttyMSM",
1213 	.write = qcom_geni_serial_console_write,
1214 	.device = uart_console_device,
1215 	.setup = qcom_geni_console_setup,
1216 	.flags = CON_PRINTBUFFER,
1217 	.index = -1,
1218 	.data = &qcom_geni_console_driver,
1219 };
1220 
1221 static struct uart_driver qcom_geni_console_driver = {
1222 	.owner = THIS_MODULE,
1223 	.driver_name = "qcom_geni_console",
1224 	.dev_name = "ttyMSM",
1225 	.nr =  GENI_UART_CONS_PORTS,
1226 	.cons = &cons_ops,
1227 };
1228 #else
1229 static int console_register(struct uart_driver *drv)
1230 {
1231 	return 0;
1232 }
1233 
1234 static void console_unregister(struct uart_driver *drv)
1235 {
1236 }
1237 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1238 
1239 static struct uart_driver qcom_geni_uart_driver = {
1240 	.owner = THIS_MODULE,
1241 	.driver_name = "qcom_geni_uart",
1242 	.dev_name = "ttyHS",
1243 	.nr =  GENI_UART_PORTS,
1244 };
1245 
1246 static void qcom_geni_serial_pm(struct uart_port *uport,
1247 		unsigned int new_state, unsigned int old_state)
1248 {
1249 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1250 
1251 	/* If we've never been called, treat it as off */
1252 	if (old_state == UART_PM_STATE_UNDEFINED)
1253 		old_state = UART_PM_STATE_OFF;
1254 
1255 	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1256 		geni_se_resources_on(&port->se);
1257 	else if (new_state == UART_PM_STATE_OFF &&
1258 			old_state == UART_PM_STATE_ON)
1259 		geni_se_resources_off(&port->se);
1260 }
1261 
1262 static const struct uart_ops qcom_geni_console_pops = {
1263 	.tx_empty = qcom_geni_serial_tx_empty,
1264 	.stop_tx = qcom_geni_serial_stop_tx,
1265 	.start_tx = qcom_geni_serial_start_tx,
1266 	.stop_rx = qcom_geni_serial_stop_rx,
1267 	.set_termios = qcom_geni_serial_set_termios,
1268 	.startup = qcom_geni_serial_startup,
1269 	.request_port = qcom_geni_serial_request_port,
1270 	.config_port = qcom_geni_serial_config_port,
1271 	.shutdown = qcom_geni_serial_shutdown,
1272 	.type = qcom_geni_serial_get_type,
1273 	.set_mctrl = qcom_geni_serial_set_mctrl,
1274 	.get_mctrl = qcom_geni_serial_get_mctrl,
1275 #ifdef CONFIG_CONSOLE_POLL
1276 	.poll_get_char	= qcom_geni_serial_get_char,
1277 	.poll_put_char	= qcom_geni_serial_poll_put_char,
1278 #endif
1279 	.pm = qcom_geni_serial_pm,
1280 };
1281 
1282 static const struct uart_ops qcom_geni_uart_pops = {
1283 	.tx_empty = qcom_geni_serial_tx_empty,
1284 	.stop_tx = qcom_geni_serial_stop_tx,
1285 	.start_tx = qcom_geni_serial_start_tx,
1286 	.stop_rx = qcom_geni_serial_stop_rx,
1287 	.set_termios = qcom_geni_serial_set_termios,
1288 	.startup = qcom_geni_serial_startup,
1289 	.request_port = qcom_geni_serial_request_port,
1290 	.config_port = qcom_geni_serial_config_port,
1291 	.shutdown = qcom_geni_serial_shutdown,
1292 	.type = qcom_geni_serial_get_type,
1293 	.set_mctrl = qcom_geni_serial_set_mctrl,
1294 	.get_mctrl = qcom_geni_serial_get_mctrl,
1295 	.pm = qcom_geni_serial_pm,
1296 };
1297 
1298 static int qcom_geni_serial_probe(struct platform_device *pdev)
1299 {
1300 	int ret = 0;
1301 	int line = -1;
1302 	struct qcom_geni_serial_port *port;
1303 	struct uart_port *uport;
1304 	struct resource *res;
1305 	int irq;
1306 	bool console = false;
1307 	struct uart_driver *drv;
1308 
1309 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1310 		console = true;
1311 
1312 	if (console) {
1313 		drv = &qcom_geni_console_driver;
1314 		line = of_alias_get_id(pdev->dev.of_node, "serial");
1315 	} else {
1316 		drv = &qcom_geni_uart_driver;
1317 		line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1318 	}
1319 
1320 	port = get_port_from_line(line, console);
1321 	if (IS_ERR(port)) {
1322 		dev_err(&pdev->dev, "Invalid line %d\n", line);
1323 		return PTR_ERR(port);
1324 	}
1325 
1326 	uport = &port->uport;
1327 	/* Don't allow 2 drivers to access the same port */
1328 	if (uport->private_data)
1329 		return -ENODEV;
1330 
1331 	uport->dev = &pdev->dev;
1332 	port->se.dev = &pdev->dev;
1333 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1334 	port->se.clk = devm_clk_get(&pdev->dev, "se");
1335 	if (IS_ERR(port->se.clk)) {
1336 		ret = PTR_ERR(port->se.clk);
1337 		dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1338 		return ret;
1339 	}
1340 
1341 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1342 	if (!res)
1343 		return -EINVAL;
1344 	uport->mapbase = res->start;
1345 
1346 	port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1347 	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1348 	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1349 
1350 	irq = platform_get_irq(pdev, 0);
1351 	if (irq < 0) {
1352 		dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1353 		return irq;
1354 	}
1355 	uport->irq = irq;
1356 
1357 	uport->private_data = drv;
1358 	platform_set_drvdata(pdev, port);
1359 	port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1360 	if (!console)
1361 		device_create_file(uport->dev, &dev_attr_loopback);
1362 	return uart_add_one_port(drv, uport);
1363 }
1364 
1365 static int qcom_geni_serial_remove(struct platform_device *pdev)
1366 {
1367 	struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1368 	struct uart_driver *drv = port->uport.private_data;
1369 
1370 	uart_remove_one_port(drv, &port->uport);
1371 	return 0;
1372 }
1373 
1374 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1375 {
1376 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1377 	struct uart_port *uport = &port->uport;
1378 
1379 	return uart_suspend_port(uport->private_data, uport);
1380 }
1381 
1382 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1383 {
1384 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1385 	struct uart_port *uport = &port->uport;
1386 
1387 	return uart_resume_port(uport->private_data, uport);
1388 }
1389 
1390 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1391 	SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1392 					qcom_geni_serial_sys_resume)
1393 };
1394 
1395 static const struct of_device_id qcom_geni_serial_match_table[] = {
1396 	{ .compatible = "qcom,geni-debug-uart", },
1397 	{ .compatible = "qcom,geni-uart", },
1398 	{}
1399 };
1400 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1401 
1402 static struct platform_driver qcom_geni_serial_platform_driver = {
1403 	.remove = qcom_geni_serial_remove,
1404 	.probe = qcom_geni_serial_probe,
1405 	.driver = {
1406 		.name = "qcom_geni_serial",
1407 		.of_match_table = qcom_geni_serial_match_table,
1408 		.pm = &qcom_geni_serial_pm_ops,
1409 	},
1410 };
1411 
1412 static int __init qcom_geni_serial_init(void)
1413 {
1414 	int ret;
1415 
1416 	ret = console_register(&qcom_geni_console_driver);
1417 	if (ret)
1418 		return ret;
1419 
1420 	ret = uart_register_driver(&qcom_geni_uart_driver);
1421 	if (ret) {
1422 		console_unregister(&qcom_geni_console_driver);
1423 		return ret;
1424 	}
1425 
1426 	ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1427 	if (ret) {
1428 		console_unregister(&qcom_geni_console_driver);
1429 		uart_unregister_driver(&qcom_geni_uart_driver);
1430 	}
1431 	return ret;
1432 }
1433 module_init(qcom_geni_serial_init);
1434 
1435 static void __exit qcom_geni_serial_exit(void)
1436 {
1437 	platform_driver_unregister(&qcom_geni_serial_platform_driver);
1438 	console_unregister(&qcom_geni_console_driver);
1439 	uart_unregister_driver(&qcom_geni_uart_driver);
1440 }
1441 module_exit(qcom_geni_serial_exit);
1442 
1443 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1444 MODULE_LICENSE("GPL v2");
1445