1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3 
4 #if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5 # define SUPPORT_SYSRQ
6 #endif
7 
8 #include <linux/clk.h>
9 #include <linux/console.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/qcom-geni-se.h>
17 #include <linux/serial.h>
18 #include <linux/serial_core.h>
19 #include <linux/slab.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 
23 /* UART specific GENI registers */
24 #define SE_UART_LOOPBACK_CFG		0x22c
25 #define SE_UART_TX_TRANS_CFG		0x25c
26 #define SE_UART_TX_WORD_LEN		0x268
27 #define SE_UART_TX_STOP_BIT_LEN		0x26c
28 #define SE_UART_TX_TRANS_LEN		0x270
29 #define SE_UART_RX_TRANS_CFG		0x280
30 #define SE_UART_RX_WORD_LEN		0x28c
31 #define SE_UART_RX_STALE_CNT		0x294
32 #define SE_UART_TX_PARITY_CFG		0x2a4
33 #define SE_UART_RX_PARITY_CFG		0x2a8
34 #define SE_UART_MANUAL_RFR		0x2ac
35 
36 /* SE_UART_TRANS_CFG */
37 #define UART_TX_PAR_EN		BIT(0)
38 #define UART_CTS_MASK		BIT(1)
39 
40 /* SE_UART_TX_WORD_LEN */
41 #define TX_WORD_LEN_MSK		GENMASK(9, 0)
42 
43 /* SE_UART_TX_STOP_BIT_LEN */
44 #define TX_STOP_BIT_LEN_MSK	GENMASK(23, 0)
45 #define TX_STOP_BIT_LEN_1	0
46 #define TX_STOP_BIT_LEN_1_5	1
47 #define TX_STOP_BIT_LEN_2	2
48 
49 /* SE_UART_TX_TRANS_LEN */
50 #define TX_TRANS_LEN_MSK	GENMASK(23, 0)
51 
52 /* SE_UART_RX_TRANS_CFG */
53 #define UART_RX_INS_STATUS_BIT	BIT(2)
54 #define UART_RX_PAR_EN		BIT(3)
55 
56 /* SE_UART_RX_WORD_LEN */
57 #define RX_WORD_LEN_MASK	GENMASK(9, 0)
58 
59 /* SE_UART_RX_STALE_CNT */
60 #define RX_STALE_CNT		GENMASK(23, 0)
61 
62 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
63 #define PAR_CALC_EN		BIT(0)
64 #define PAR_MODE_MSK		GENMASK(2, 1)
65 #define PAR_MODE_SHFT		1
66 #define PAR_EVEN		0x00
67 #define PAR_ODD			0x01
68 #define PAR_SPACE		0x10
69 #define PAR_MARK		0x11
70 
71 /* SE_UART_MANUAL_RFR register fields */
72 #define UART_MANUAL_RFR_EN	BIT(31)
73 #define UART_RFR_NOT_READY	BIT(1)
74 #define UART_RFR_READY		BIT(0)
75 
76 /* UART M_CMD OP codes */
77 #define UART_START_TX		0x1
78 #define UART_START_BREAK	0x4
79 #define UART_STOP_BREAK		0x5
80 /* UART S_CMD OP codes */
81 #define UART_START_READ		0x1
82 #define UART_PARAM		0x1
83 
84 #define UART_OVERSAMPLING	32
85 #define STALE_TIMEOUT		16
86 #define DEFAULT_BITS_PER_CHAR	10
87 #define GENI_UART_CONS_PORTS	1
88 #define GENI_UART_PORTS		3
89 #define DEF_FIFO_DEPTH_WORDS	16
90 #define DEF_TX_WM		2
91 #define DEF_FIFO_WIDTH_BITS	32
92 #define UART_CONSOLE_RX_WM	2
93 #define MAX_LOOPBACK_CFG	3
94 
95 #ifdef CONFIG_CONSOLE_POLL
96 #define CONSOLE_RX_BYTES_PW 1
97 #else
98 #define CONSOLE_RX_BYTES_PW 4
99 #endif
100 
101 struct qcom_geni_serial_port {
102 	struct uart_port uport;
103 	struct geni_se se;
104 	char name[20];
105 	u32 tx_fifo_depth;
106 	u32 tx_fifo_width;
107 	u32 rx_fifo_depth;
108 	u32 tx_wm;
109 	u32 rx_wm;
110 	u32 rx_rfr;
111 	enum geni_se_xfer_mode xfer_mode;
112 	bool setup;
113 	int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
114 	unsigned int baud;
115 	unsigned int tx_bytes_pw;
116 	unsigned int rx_bytes_pw;
117 	u32 *rx_fifo;
118 	u32 loopback;
119 	bool brk;
120 
121 	unsigned int tx_remaining;
122 };
123 
124 static const struct uart_ops qcom_geni_console_pops;
125 static const struct uart_ops qcom_geni_uart_pops;
126 static struct uart_driver qcom_geni_console_driver;
127 static struct uart_driver qcom_geni_uart_driver;
128 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
129 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
130 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
131 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
132 
133 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
134 					32000000, 48000000, 64000000, 80000000,
135 					96000000, 100000000, 102400000,
136 					112000000, 120000000, 128000000};
137 
138 #define to_dev_port(ptr, member) \
139 		container_of(ptr, struct qcom_geni_serial_port, member)
140 
141 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
142 	[0] = {
143 		.uport = {
144 				.iotype = UPIO_MEM,
145 				.ops = &qcom_geni_uart_pops,
146 				.flags = UPF_BOOT_AUTOCONF,
147 				.line = 0,
148 		},
149 	},
150 	[1] = {
151 		.uport = {
152 				.iotype = UPIO_MEM,
153 				.ops = &qcom_geni_uart_pops,
154 				.flags = UPF_BOOT_AUTOCONF,
155 				.line = 1,
156 		},
157 	},
158 	[2] = {
159 		.uport = {
160 				.iotype = UPIO_MEM,
161 				.ops = &qcom_geni_uart_pops,
162 				.flags = UPF_BOOT_AUTOCONF,
163 				.line = 2,
164 		},
165 	},
166 };
167 
168 static ssize_t loopback_show(struct device *dev,
169 				struct device_attribute *attr, char *buf)
170 {
171 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
172 
173 	return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
174 }
175 
176 static ssize_t loopback_store(struct device *dev,
177 				struct device_attribute *attr, const char *buf,
178 				size_t size)
179 {
180 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
181 	u32 loopback;
182 
183 	if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
184 		dev_err(dev, "Invalid input\n");
185 		return -EINVAL;
186 	}
187 	port->loopback = loopback;
188 	return size;
189 }
190 static DEVICE_ATTR_RW(loopback);
191 
192 static struct qcom_geni_serial_port qcom_geni_console_port = {
193 	.uport = {
194 		.iotype = UPIO_MEM,
195 		.ops = &qcom_geni_console_pops,
196 		.flags = UPF_BOOT_AUTOCONF,
197 		.line = 0,
198 	},
199 };
200 
201 static int qcom_geni_serial_request_port(struct uart_port *uport)
202 {
203 	struct platform_device *pdev = to_platform_device(uport->dev);
204 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
205 	struct resource *res;
206 
207 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 	uport->membase = devm_ioremap_resource(&pdev->dev, res);
209 	if (IS_ERR(uport->membase))
210 		return PTR_ERR(uport->membase);
211 	port->se.base = uport->membase;
212 	return 0;
213 }
214 
215 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
216 {
217 	if (cfg_flags & UART_CONFIG_TYPE) {
218 		uport->type = PORT_MSM;
219 		qcom_geni_serial_request_port(uport);
220 	}
221 }
222 
223 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
224 {
225 	unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
226 	u32 geni_ios;
227 
228 	if (uart_console(uport) || !uart_cts_enabled(uport)) {
229 		mctrl |= TIOCM_CTS;
230 	} else {
231 		geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS);
232 		if (!(geni_ios & IO2_DATA_IN))
233 			mctrl |= TIOCM_CTS;
234 	}
235 
236 	return mctrl;
237 }
238 
239 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
240 							unsigned int mctrl)
241 {
242 	u32 uart_manual_rfr = 0;
243 
244 	if (uart_console(uport) || !uart_cts_enabled(uport))
245 		return;
246 
247 	if (!(mctrl & TIOCM_RTS))
248 		uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
249 	writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
250 }
251 
252 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
253 {
254 	return "MSM";
255 }
256 
257 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
258 {
259 	struct qcom_geni_serial_port *port;
260 	int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
261 
262 	if (line < 0 || line >= nr_ports)
263 		return ERR_PTR(-ENXIO);
264 
265 	port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
266 	return port;
267 }
268 
269 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
270 				int offset, int field, bool set)
271 {
272 	u32 reg;
273 	struct qcom_geni_serial_port *port;
274 	unsigned int baud;
275 	unsigned int fifo_bits;
276 	unsigned long timeout_us = 20000;
277 
278 	/* Ensure polling is not re-ordered before the prior writes/reads */
279 	mb();
280 
281 	if (uport->private_data) {
282 		port = to_dev_port(uport, uport);
283 		baud = port->baud;
284 		if (!baud)
285 			baud = 115200;
286 		fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
287 		/*
288 		 * Total polling iterations based on FIFO worth of bytes to be
289 		 * sent at current baud. Add a little fluff to the wait.
290 		 */
291 		timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
292 	}
293 
294 	/*
295 	 * Use custom implementation instead of readl_poll_atomic since ktimer
296 	 * is not ready at the time of early console.
297 	 */
298 	timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
299 	while (timeout_us) {
300 		reg = readl_relaxed(uport->membase + offset);
301 		if ((bool)(reg & field) == set)
302 			return true;
303 		udelay(10);
304 		timeout_us -= 10;
305 	}
306 	return false;
307 }
308 
309 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
310 {
311 	u32 m_cmd;
312 
313 	writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
314 	m_cmd = UART_START_TX << M_OPCODE_SHFT;
315 	writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
316 }
317 
318 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
319 {
320 	int done;
321 	u32 irq_clear = M_CMD_DONE_EN;
322 
323 	done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
324 						M_CMD_DONE_EN, true);
325 	if (!done) {
326 		writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
327 						SE_GENI_M_CMD_CTRL_REG);
328 		irq_clear |= M_CMD_ABORT_EN;
329 		qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
330 							M_CMD_ABORT_EN, true);
331 	}
332 	writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
333 }
334 
335 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
336 {
337 	u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
338 
339 	writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
340 	qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
341 					S_GENI_CMD_ABORT, false);
342 	writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
343 	writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
344 }
345 
346 #ifdef CONFIG_CONSOLE_POLL
347 static int qcom_geni_serial_get_char(struct uart_port *uport)
348 {
349 	u32 rx_fifo;
350 	u32 status;
351 
352 	status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
353 	writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
354 
355 	status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
356 	writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
357 
358 	/*
359 	 * Ensure the writes to clear interrupts is not re-ordered after
360 	 * reading the data.
361 	 */
362 	mb();
363 
364 	status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
365 	if (!(status & RX_FIFO_WC_MSK))
366 		return NO_POLL_CHAR;
367 
368 	rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
369 	return rx_fifo & 0xff;
370 }
371 
372 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
373 							unsigned char c)
374 {
375 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
376 
377 	writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
378 	qcom_geni_serial_setup_tx(uport, 1);
379 	WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
380 						M_TX_FIFO_WATERMARK_EN, true));
381 	writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
382 	writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
383 							SE_GENI_M_IRQ_CLEAR);
384 	qcom_geni_serial_poll_tx_done(uport);
385 }
386 #endif
387 
388 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
389 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
390 {
391 	writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
392 }
393 
394 static void
395 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
396 				 unsigned int count)
397 {
398 	int i;
399 	u32 bytes_to_send = count;
400 
401 	for (i = 0; i < count; i++) {
402 		/*
403 		 * uart_console_write() adds a carriage return for each newline.
404 		 * Account for additional bytes to be written.
405 		 */
406 		if (s[i] == '\n')
407 			bytes_to_send++;
408 	}
409 
410 	writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
411 	qcom_geni_serial_setup_tx(uport, bytes_to_send);
412 	for (i = 0; i < count; ) {
413 		size_t chars_to_write = 0;
414 		size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
415 
416 		/*
417 		 * If the WM bit never set, then the Tx state machine is not
418 		 * in a valid state, so break, cancel/abort any existing
419 		 * command. Unfortunately the current data being written is
420 		 * lost.
421 		 */
422 		if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
423 						M_TX_FIFO_WATERMARK_EN, true))
424 			break;
425 		chars_to_write = min_t(size_t, count - i, avail / 2);
426 		uart_console_write(uport, s + i, chars_to_write,
427 						qcom_geni_serial_wr_char);
428 		writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
429 							SE_GENI_M_IRQ_CLEAR);
430 		i += chars_to_write;
431 	}
432 	qcom_geni_serial_poll_tx_done(uport);
433 }
434 
435 static void qcom_geni_serial_console_write(struct console *co, const char *s,
436 			      unsigned int count)
437 {
438 	struct uart_port *uport;
439 	struct qcom_geni_serial_port *port;
440 	bool locked = true;
441 	unsigned long flags;
442 	u32 geni_status;
443 	u32 irq_en;
444 
445 	WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
446 
447 	port = get_port_from_line(co->index, true);
448 	if (IS_ERR(port))
449 		return;
450 
451 	uport = &port->uport;
452 	if (oops_in_progress)
453 		locked = spin_trylock_irqsave(&uport->lock, flags);
454 	else
455 		spin_lock_irqsave(&uport->lock, flags);
456 
457 	geni_status = readl_relaxed(uport->membase + SE_GENI_STATUS);
458 
459 	/* Cancel the current write to log the fault */
460 	if (!locked) {
461 		geni_se_cancel_m_cmd(&port->se);
462 		if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
463 						M_CMD_CANCEL_EN, true)) {
464 			geni_se_abort_m_cmd(&port->se);
465 			qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
466 							M_CMD_ABORT_EN, true);
467 			writel_relaxed(M_CMD_ABORT_EN, uport->membase +
468 							SE_GENI_M_IRQ_CLEAR);
469 		}
470 		writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
471 							SE_GENI_M_IRQ_CLEAR);
472 	} else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
473 		/*
474 		 * It seems we can't interrupt existing transfers if all data
475 		 * has been sent, in which case we need to look for done first.
476 		 */
477 		qcom_geni_serial_poll_tx_done(uport);
478 
479 		if (uart_circ_chars_pending(&uport->state->xmit)) {
480 			irq_en = readl_relaxed(uport->membase +
481 					SE_GENI_M_IRQ_EN);
482 			writel_relaxed(irq_en | M_TX_FIFO_WATERMARK_EN,
483 					uport->membase + SE_GENI_M_IRQ_EN);
484 		}
485 	}
486 
487 	__qcom_geni_serial_console_write(uport, s, count);
488 
489 	if (port->tx_remaining)
490 		qcom_geni_serial_setup_tx(uport, port->tx_remaining);
491 
492 	if (locked)
493 		spin_unlock_irqrestore(&uport->lock, flags);
494 }
495 
496 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
497 {
498 	u32 i;
499 	unsigned char buf[sizeof(u32)];
500 	struct tty_port *tport;
501 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
502 
503 	tport = &uport->state->port;
504 	for (i = 0; i < bytes; ) {
505 		int c;
506 		int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
507 
508 		ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
509 		i += chunk;
510 		if (drop)
511 			continue;
512 
513 		for (c = 0; c < chunk; c++) {
514 			int sysrq;
515 
516 			uport->icount.rx++;
517 			if (port->brk && buf[c] == 0) {
518 				port->brk = false;
519 				if (uart_handle_break(uport))
520 					continue;
521 			}
522 
523 			sysrq = uart_prepare_sysrq_char(uport, buf[c]);
524 
525 			if (!sysrq)
526 				tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
527 		}
528 	}
529 	if (!drop)
530 		tty_flip_buffer_push(tport);
531 	return 0;
532 }
533 #else
534 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
535 {
536 	return -EPERM;
537 }
538 
539 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
540 
541 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
542 {
543 	unsigned char *buf;
544 	struct tty_port *tport;
545 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
546 	u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
547 	u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
548 	int ret;
549 
550 	tport = &uport->state->port;
551 	ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
552 	if (drop)
553 		return 0;
554 
555 	buf = (unsigned char *)port->rx_fifo;
556 	ret = tty_insert_flip_string(tport, buf, bytes);
557 	if (ret != bytes) {
558 		dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
559 				__func__, ret, bytes);
560 		WARN_ON_ONCE(1);
561 	}
562 	uport->icount.rx += ret;
563 	tty_flip_buffer_push(tport);
564 	return ret;
565 }
566 
567 static void qcom_geni_serial_start_tx(struct uart_port *uport)
568 {
569 	u32 irq_en;
570 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
571 	u32 status;
572 
573 	if (port->xfer_mode == GENI_SE_FIFO) {
574 		/*
575 		 * readl ensures reading & writing of IRQ_EN register
576 		 * is not re-ordered before checking the status of the
577 		 * Serial Engine.
578 		 */
579 		status = readl(uport->membase + SE_GENI_STATUS);
580 		if (status & M_GENI_CMD_ACTIVE)
581 			return;
582 
583 		if (!qcom_geni_serial_tx_empty(uport))
584 			return;
585 
586 		irq_en = readl_relaxed(uport->membase +	SE_GENI_M_IRQ_EN);
587 		irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
588 
589 		writel_relaxed(port->tx_wm, uport->membase +
590 						SE_GENI_TX_WATERMARK_REG);
591 		writel_relaxed(irq_en, uport->membase +	SE_GENI_M_IRQ_EN);
592 	}
593 }
594 
595 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
596 {
597 	u32 irq_en;
598 	u32 status;
599 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
600 
601 	irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
602 	irq_en &= ~M_CMD_DONE_EN;
603 	if (port->xfer_mode == GENI_SE_FIFO) {
604 		irq_en &= ~M_TX_FIFO_WATERMARK_EN;
605 		writel_relaxed(0, uport->membase +
606 				     SE_GENI_TX_WATERMARK_REG);
607 	}
608 	writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
609 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
610 	/* Possible stop tx is called multiple times. */
611 	if (!(status & M_GENI_CMD_ACTIVE))
612 		return;
613 
614 	/*
615 	 * Ensure cancel command write is not re-ordered before checking
616 	 * the status of the Primary Sequencer.
617 	 */
618 	mb();
619 
620 	geni_se_cancel_m_cmd(&port->se);
621 	if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
622 						M_CMD_CANCEL_EN, true)) {
623 		geni_se_abort_m_cmd(&port->se);
624 		qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
625 						M_CMD_ABORT_EN, true);
626 		writel_relaxed(M_CMD_ABORT_EN, uport->membase +
627 							SE_GENI_M_IRQ_CLEAR);
628 	}
629 	writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
630 }
631 
632 static void qcom_geni_serial_start_rx(struct uart_port *uport)
633 {
634 	u32 irq_en;
635 	u32 status;
636 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
637 
638 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
639 	if (status & S_GENI_CMD_ACTIVE)
640 		qcom_geni_serial_stop_rx(uport);
641 
642 	/*
643 	 * Ensure setup command write is not re-ordered before checking
644 	 * the status of the Secondary Sequencer.
645 	 */
646 	mb();
647 
648 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
649 
650 	if (port->xfer_mode == GENI_SE_FIFO) {
651 		irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
652 		irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
653 		writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
654 
655 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
656 		irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
657 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
658 	}
659 }
660 
661 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
662 {
663 	u32 irq_en;
664 	u32 status;
665 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
666 	u32 irq_clear = S_CMD_DONE_EN;
667 
668 	if (port->xfer_mode == GENI_SE_FIFO) {
669 		irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
670 		irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
671 		writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
672 
673 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
674 		irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
675 		writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
676 	}
677 
678 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
679 	/* Possible stop rx is called multiple times. */
680 	if (!(status & S_GENI_CMD_ACTIVE))
681 		return;
682 
683 	/*
684 	 * Ensure cancel command write is not re-ordered before checking
685 	 * the status of the Secondary Sequencer.
686 	 */
687 	mb();
688 
689 	geni_se_cancel_s_cmd(&port->se);
690 	qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
691 					S_GENI_CMD_CANCEL, false);
692 	status = readl_relaxed(uport->membase + SE_GENI_STATUS);
693 	writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
694 	if (status & S_GENI_CMD_ACTIVE)
695 		qcom_geni_serial_abort_rx(uport);
696 }
697 
698 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
699 {
700 	u32 status;
701 	u32 word_cnt;
702 	u32 last_word_byte_cnt;
703 	u32 last_word_partial;
704 	u32 total_bytes;
705 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
706 
707 	status = readl_relaxed(uport->membase +	SE_GENI_RX_FIFO_STATUS);
708 	word_cnt = status & RX_FIFO_WC_MSK;
709 	last_word_partial = status & RX_LAST;
710 	last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
711 						RX_LAST_BYTE_VALID_SHFT;
712 
713 	if (!word_cnt)
714 		return;
715 	total_bytes = port->rx_bytes_pw * (word_cnt - 1);
716 	if (last_word_partial && last_word_byte_cnt)
717 		total_bytes += last_word_byte_cnt;
718 	else
719 		total_bytes += port->rx_bytes_pw;
720 	port->handle_rx(uport, total_bytes, drop);
721 }
722 
723 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
724 		bool active)
725 {
726 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
727 	struct circ_buf *xmit = &uport->state->xmit;
728 	size_t avail;
729 	size_t remaining;
730 	size_t pending;
731 	int i;
732 	u32 status;
733 	u32 irq_en;
734 	unsigned int chunk;
735 	int tail;
736 
737 	status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
738 
739 	/* Complete the current tx command before taking newly added data */
740 	if (active)
741 		pending = port->tx_remaining;
742 	else
743 		pending = uart_circ_chars_pending(xmit);
744 
745 	/* All data has been transmitted and acknowledged as received */
746 	if (!pending && !status && done) {
747 		qcom_geni_serial_stop_tx(uport);
748 		goto out_write_wakeup;
749 	}
750 
751 	avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
752 	avail *= port->tx_bytes_pw;
753 
754 	tail = xmit->tail;
755 	chunk = min(avail, pending);
756 	if (!chunk)
757 		goto out_write_wakeup;
758 
759 	if (!port->tx_remaining) {
760 		qcom_geni_serial_setup_tx(uport, pending);
761 		port->tx_remaining = pending;
762 
763 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
764 		if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
765 			writel_relaxed(irq_en | M_TX_FIFO_WATERMARK_EN,
766 					uport->membase + SE_GENI_M_IRQ_EN);
767 	}
768 
769 	remaining = chunk;
770 	for (i = 0; i < chunk; ) {
771 		unsigned int tx_bytes;
772 		u8 buf[sizeof(u32)];
773 		int c;
774 
775 		memset(buf, 0, ARRAY_SIZE(buf));
776 		tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
777 
778 		for (c = 0; c < tx_bytes ; c++) {
779 			buf[c] = xmit->buf[tail++];
780 			tail &= UART_XMIT_SIZE - 1;
781 		}
782 
783 		iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
784 
785 		i += tx_bytes;
786 		uport->icount.tx += tx_bytes;
787 		remaining -= tx_bytes;
788 		port->tx_remaining -= tx_bytes;
789 	}
790 
791 	xmit->tail = tail;
792 
793 	/*
794 	 * The tx fifo watermark is level triggered and latched. Though we had
795 	 * cleared it in qcom_geni_serial_isr it will have already reasserted
796 	 * so we must clear it again here after our writes.
797 	 */
798 	writel_relaxed(M_TX_FIFO_WATERMARK_EN,
799 			uport->membase + SE_GENI_M_IRQ_CLEAR);
800 
801 out_write_wakeup:
802 	if (!port->tx_remaining) {
803 		irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
804 		if (irq_en & M_TX_FIFO_WATERMARK_EN)
805 			writel_relaxed(irq_en & ~M_TX_FIFO_WATERMARK_EN,
806 					uport->membase + SE_GENI_M_IRQ_EN);
807 	}
808 
809 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
810 		uart_write_wakeup(uport);
811 }
812 
813 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
814 {
815 	unsigned int m_irq_status;
816 	unsigned int s_irq_status;
817 	unsigned int geni_status;
818 	struct uart_port *uport = dev;
819 	unsigned long flags;
820 	unsigned int m_irq_en;
821 	bool drop_rx = false;
822 	struct tty_port *tport = &uport->state->port;
823 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
824 
825 	if (uport->suspended)
826 		return IRQ_NONE;
827 
828 	spin_lock_irqsave(&uport->lock, flags);
829 	m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
830 	s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
831 	geni_status = readl_relaxed(uport->membase + SE_GENI_STATUS);
832 	m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
833 	writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
834 	writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
835 
836 	if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
837 		goto out_unlock;
838 
839 	if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
840 		uport->icount.overrun++;
841 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
842 	}
843 
844 	if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
845 		qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
846 					geni_status & M_GENI_CMD_ACTIVE);
847 
848 	if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
849 		if (s_irq_status & S_GP_IRQ_0_EN)
850 			uport->icount.parity++;
851 		drop_rx = true;
852 	} else if (s_irq_status & S_GP_IRQ_2_EN ||
853 					s_irq_status & S_GP_IRQ_3_EN) {
854 		uport->icount.brk++;
855 		port->brk = true;
856 	}
857 
858 	if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
859 					s_irq_status & S_RX_FIFO_LAST_EN)
860 		qcom_geni_serial_handle_rx(uport, drop_rx);
861 
862 out_unlock:
863 	uart_unlock_and_check_sysrq(uport, flags);
864 
865 	return IRQ_HANDLED;
866 }
867 
868 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
869 {
870 	struct uart_port *uport;
871 
872 	uport = &port->uport;
873 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
874 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
875 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
876 	uport->fifosize =
877 		(port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
878 }
879 
880 static void set_rfr_wm(struct qcom_geni_serial_port *port)
881 {
882 	/*
883 	 * Set RFR (Flow off) to FIFO_DEPTH - 2.
884 	 * RX WM level at 10% RX_FIFO_DEPTH.
885 	 * TX WM level at 10% TX_FIFO_DEPTH.
886 	 */
887 	port->rx_rfr = port->rx_fifo_depth - 2;
888 	port->rx_wm = UART_CONSOLE_RX_WM;
889 	port->tx_wm = DEF_TX_WM;
890 }
891 
892 static void qcom_geni_serial_shutdown(struct uart_port *uport)
893 {
894 	unsigned long flags;
895 
896 	/* Stop the console before stopping the current tx */
897 	if (uart_console(uport))
898 		console_stop(uport->cons);
899 
900 	free_irq(uport->irq, uport);
901 	spin_lock_irqsave(&uport->lock, flags);
902 	qcom_geni_serial_stop_tx(uport);
903 	qcom_geni_serial_stop_rx(uport);
904 	spin_unlock_irqrestore(&uport->lock, flags);
905 }
906 
907 static int qcom_geni_serial_port_setup(struct uart_port *uport)
908 {
909 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
910 	unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
911 	u32 proto;
912 
913 	if (uart_console(uport)) {
914 		port->tx_bytes_pw = 1;
915 		port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
916 	} else {
917 		port->tx_bytes_pw = 4;
918 		port->rx_bytes_pw = 4;
919 	}
920 
921 	proto = geni_se_read_proto(&port->se);
922 	if (proto != GENI_SE_UART) {
923 		dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
924 		return -ENXIO;
925 	}
926 
927 	qcom_geni_serial_stop_rx(uport);
928 
929 	get_tx_fifo_size(port);
930 
931 	set_rfr_wm(port);
932 	writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
933 	/*
934 	 * Make an unconditional cancel on the main sequencer to reset
935 	 * it else we could end up in data loss scenarios.
936 	 */
937 	port->xfer_mode = GENI_SE_FIFO;
938 	if (uart_console(uport))
939 		qcom_geni_serial_poll_tx_done(uport);
940 	geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
941 						false, true, false);
942 	geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
943 						false, false, true);
944 	geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
945 	geni_se_select_mode(&port->se, port->xfer_mode);
946 	if (!uart_console(uport)) {
947 		port->rx_fifo = devm_kcalloc(uport->dev,
948 			port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
949 		if (!port->rx_fifo)
950 			return -ENOMEM;
951 	}
952 	port->setup = true;
953 
954 	return 0;
955 }
956 
957 static int qcom_geni_serial_startup(struct uart_port *uport)
958 {
959 	int ret;
960 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
961 
962 	scnprintf(port->name, sizeof(port->name),
963 		  "qcom_serial_%s%d",
964 		(uart_console(uport) ? "console" : "uart"), uport->line);
965 
966 	if (!port->setup) {
967 		ret = qcom_geni_serial_port_setup(uport);
968 		if (ret)
969 			return ret;
970 	}
971 
972 	ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
973 							port->name, uport);
974 	if (ret)
975 		dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
976 	return ret;
977 }
978 
979 static unsigned long get_clk_cfg(unsigned long clk_freq)
980 {
981 	int i;
982 
983 	for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
984 		if (!(root_freq[i] % clk_freq))
985 			return root_freq[i];
986 	}
987 	return 0;
988 }
989 
990 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
991 {
992 	unsigned long ser_clk;
993 	unsigned long desired_clk;
994 
995 	desired_clk = baud * UART_OVERSAMPLING;
996 	ser_clk = get_clk_cfg(desired_clk);
997 	if (!ser_clk) {
998 		pr_err("%s: Can't find matching DFS entry for baud %d\n",
999 								__func__, baud);
1000 		return ser_clk;
1001 	}
1002 
1003 	*clk_div = ser_clk / desired_clk;
1004 	return ser_clk;
1005 }
1006 
1007 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1008 				struct ktermios *termios, struct ktermios *old)
1009 {
1010 	unsigned int baud;
1011 	unsigned int bits_per_char;
1012 	unsigned int tx_trans_cfg;
1013 	unsigned int tx_parity_cfg;
1014 	unsigned int rx_trans_cfg;
1015 	unsigned int rx_parity_cfg;
1016 	unsigned int stop_bit_len;
1017 	unsigned int clk_div;
1018 	unsigned long ser_clk_cfg;
1019 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1020 	unsigned long clk_rate;
1021 
1022 	qcom_geni_serial_stop_rx(uport);
1023 	/* baud rate */
1024 	baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1025 	port->baud = baud;
1026 	clk_rate = get_clk_div_rate(baud, &clk_div);
1027 	if (!clk_rate)
1028 		goto out_restart_rx;
1029 
1030 	uport->uartclk = clk_rate;
1031 	clk_set_rate(port->se.clk, clk_rate);
1032 	ser_clk_cfg = SER_CLK_EN;
1033 	ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1034 
1035 	/* parity */
1036 	tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
1037 	tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
1038 	rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
1039 	rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
1040 	if (termios->c_cflag & PARENB) {
1041 		tx_trans_cfg |= UART_TX_PAR_EN;
1042 		rx_trans_cfg |= UART_RX_PAR_EN;
1043 		tx_parity_cfg |= PAR_CALC_EN;
1044 		rx_parity_cfg |= PAR_CALC_EN;
1045 		if (termios->c_cflag & PARODD) {
1046 			tx_parity_cfg |= PAR_ODD;
1047 			rx_parity_cfg |= PAR_ODD;
1048 		} else if (termios->c_cflag & CMSPAR) {
1049 			tx_parity_cfg |= PAR_SPACE;
1050 			rx_parity_cfg |= PAR_SPACE;
1051 		} else {
1052 			tx_parity_cfg |= PAR_EVEN;
1053 			rx_parity_cfg |= PAR_EVEN;
1054 		}
1055 	} else {
1056 		tx_trans_cfg &= ~UART_TX_PAR_EN;
1057 		rx_trans_cfg &= ~UART_RX_PAR_EN;
1058 		tx_parity_cfg &= ~PAR_CALC_EN;
1059 		rx_parity_cfg &= ~PAR_CALC_EN;
1060 	}
1061 
1062 	/* bits per char */
1063 	switch (termios->c_cflag & CSIZE) {
1064 	case CS5:
1065 		bits_per_char = 5;
1066 		break;
1067 	case CS6:
1068 		bits_per_char = 6;
1069 		break;
1070 	case CS7:
1071 		bits_per_char = 7;
1072 		break;
1073 	case CS8:
1074 	default:
1075 		bits_per_char = 8;
1076 		break;
1077 	}
1078 
1079 	/* stop bits */
1080 	if (termios->c_cflag & CSTOPB)
1081 		stop_bit_len = TX_STOP_BIT_LEN_2;
1082 	else
1083 		stop_bit_len = TX_STOP_BIT_LEN_1;
1084 
1085 	/* flow control, clear the CTS_MASK bit if using flow control. */
1086 	if (termios->c_cflag & CRTSCTS)
1087 		tx_trans_cfg &= ~UART_CTS_MASK;
1088 	else
1089 		tx_trans_cfg |= UART_CTS_MASK;
1090 
1091 	if (baud)
1092 		uart_update_timeout(uport, termios->c_cflag, baud);
1093 
1094 	if (!uart_console(uport))
1095 		writel_relaxed(port->loopback,
1096 				uport->membase + SE_UART_LOOPBACK_CFG);
1097 	writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1098 	writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1099 	writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1100 	writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1101 	writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1102 	writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1103 	writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1104 	writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1105 	writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1106 out_restart_rx:
1107 	qcom_geni_serial_start_rx(uport);
1108 }
1109 
1110 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1111 {
1112 	return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1113 }
1114 
1115 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1116 static int __init qcom_geni_console_setup(struct console *co, char *options)
1117 {
1118 	struct uart_port *uport;
1119 	struct qcom_geni_serial_port *port;
1120 	int baud;
1121 	int bits = 8;
1122 	int parity = 'n';
1123 	int flow = 'n';
1124 	int ret;
1125 
1126 	if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1127 		return -ENXIO;
1128 
1129 	port = get_port_from_line(co->index, true);
1130 	if (IS_ERR(port)) {
1131 		pr_err("Invalid line %d\n", co->index);
1132 		return PTR_ERR(port);
1133 	}
1134 
1135 	uport = &port->uport;
1136 
1137 	if (unlikely(!uport->membase))
1138 		return -ENXIO;
1139 
1140 	if (!port->setup) {
1141 		ret = qcom_geni_serial_port_setup(uport);
1142 		if (ret)
1143 			return ret;
1144 	}
1145 
1146 	if (options)
1147 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1148 
1149 	return uart_set_options(uport, co, baud, parity, bits, flow);
1150 }
1151 
1152 static void qcom_geni_serial_earlycon_write(struct console *con,
1153 					const char *s, unsigned int n)
1154 {
1155 	struct earlycon_device *dev = con->data;
1156 
1157 	__qcom_geni_serial_console_write(&dev->port, s, n);
1158 }
1159 
1160 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1161 								const char *opt)
1162 {
1163 	struct uart_port *uport = &dev->port;
1164 	u32 tx_trans_cfg;
1165 	u32 tx_parity_cfg = 0;	/* Disable Tx Parity */
1166 	u32 rx_trans_cfg = 0;
1167 	u32 rx_parity_cfg = 0;	/* Disable Rx Parity */
1168 	u32 stop_bit_len = 0;	/* Default stop bit length - 1 bit */
1169 	u32 bits_per_char;
1170 	struct geni_se se;
1171 
1172 	if (!uport->membase)
1173 		return -EINVAL;
1174 
1175 	memset(&se, 0, sizeof(se));
1176 	se.base = uport->membase;
1177 	if (geni_se_read_proto(&se) != GENI_SE_UART)
1178 		return -ENXIO;
1179 	/*
1180 	 * Ignore Flow control.
1181 	 * n = 8.
1182 	 */
1183 	tx_trans_cfg = UART_CTS_MASK;
1184 	bits_per_char = BITS_PER_BYTE;
1185 
1186 	/*
1187 	 * Make an unconditional cancel on the main sequencer to reset
1188 	 * it else we could end up in data loss scenarios.
1189 	 */
1190 	qcom_geni_serial_poll_tx_done(uport);
1191 	qcom_geni_serial_abort_rx(uport);
1192 	geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1193 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1194 	geni_se_select_mode(&se, GENI_SE_FIFO);
1195 
1196 	writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1197 	writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1198 	writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1199 	writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1200 	writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1201 	writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1202 	writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1203 
1204 	dev->con->write = qcom_geni_serial_earlycon_write;
1205 	dev->con->setup = NULL;
1206 	return 0;
1207 }
1208 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1209 				qcom_geni_serial_earlycon_setup);
1210 
1211 static int __init console_register(struct uart_driver *drv)
1212 {
1213 	return uart_register_driver(drv);
1214 }
1215 
1216 static void console_unregister(struct uart_driver *drv)
1217 {
1218 	uart_unregister_driver(drv);
1219 }
1220 
1221 static struct console cons_ops = {
1222 	.name = "ttyMSM",
1223 	.write = qcom_geni_serial_console_write,
1224 	.device = uart_console_device,
1225 	.setup = qcom_geni_console_setup,
1226 	.flags = CON_PRINTBUFFER,
1227 	.index = -1,
1228 	.data = &qcom_geni_console_driver,
1229 };
1230 
1231 static struct uart_driver qcom_geni_console_driver = {
1232 	.owner = THIS_MODULE,
1233 	.driver_name = "qcom_geni_console",
1234 	.dev_name = "ttyMSM",
1235 	.nr =  GENI_UART_CONS_PORTS,
1236 	.cons = &cons_ops,
1237 };
1238 #else
1239 static int console_register(struct uart_driver *drv)
1240 {
1241 	return 0;
1242 }
1243 
1244 static void console_unregister(struct uart_driver *drv)
1245 {
1246 }
1247 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1248 
1249 static struct uart_driver qcom_geni_uart_driver = {
1250 	.owner = THIS_MODULE,
1251 	.driver_name = "qcom_geni_uart",
1252 	.dev_name = "ttyHS",
1253 	.nr =  GENI_UART_PORTS,
1254 };
1255 
1256 static void qcom_geni_serial_pm(struct uart_port *uport,
1257 		unsigned int new_state, unsigned int old_state)
1258 {
1259 	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1260 
1261 	/* If we've never been called, treat it as off */
1262 	if (old_state == UART_PM_STATE_UNDEFINED)
1263 		old_state = UART_PM_STATE_OFF;
1264 
1265 	if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1266 		geni_se_resources_on(&port->se);
1267 	else if (new_state == UART_PM_STATE_OFF &&
1268 			old_state == UART_PM_STATE_ON)
1269 		geni_se_resources_off(&port->se);
1270 }
1271 
1272 static const struct uart_ops qcom_geni_console_pops = {
1273 	.tx_empty = qcom_geni_serial_tx_empty,
1274 	.stop_tx = qcom_geni_serial_stop_tx,
1275 	.start_tx = qcom_geni_serial_start_tx,
1276 	.stop_rx = qcom_geni_serial_stop_rx,
1277 	.set_termios = qcom_geni_serial_set_termios,
1278 	.startup = qcom_geni_serial_startup,
1279 	.request_port = qcom_geni_serial_request_port,
1280 	.config_port = qcom_geni_serial_config_port,
1281 	.shutdown = qcom_geni_serial_shutdown,
1282 	.type = qcom_geni_serial_get_type,
1283 	.set_mctrl = qcom_geni_serial_set_mctrl,
1284 	.get_mctrl = qcom_geni_serial_get_mctrl,
1285 #ifdef CONFIG_CONSOLE_POLL
1286 	.poll_get_char	= qcom_geni_serial_get_char,
1287 	.poll_put_char	= qcom_geni_serial_poll_put_char,
1288 #endif
1289 	.pm = qcom_geni_serial_pm,
1290 };
1291 
1292 static const struct uart_ops qcom_geni_uart_pops = {
1293 	.tx_empty = qcom_geni_serial_tx_empty,
1294 	.stop_tx = qcom_geni_serial_stop_tx,
1295 	.start_tx = qcom_geni_serial_start_tx,
1296 	.stop_rx = qcom_geni_serial_stop_rx,
1297 	.set_termios = qcom_geni_serial_set_termios,
1298 	.startup = qcom_geni_serial_startup,
1299 	.request_port = qcom_geni_serial_request_port,
1300 	.config_port = qcom_geni_serial_config_port,
1301 	.shutdown = qcom_geni_serial_shutdown,
1302 	.type = qcom_geni_serial_get_type,
1303 	.set_mctrl = qcom_geni_serial_set_mctrl,
1304 	.get_mctrl = qcom_geni_serial_get_mctrl,
1305 	.pm = qcom_geni_serial_pm,
1306 };
1307 
1308 static int qcom_geni_serial_probe(struct platform_device *pdev)
1309 {
1310 	int ret = 0;
1311 	int line = -1;
1312 	struct qcom_geni_serial_port *port;
1313 	struct uart_port *uport;
1314 	struct resource *res;
1315 	int irq;
1316 	bool console = false;
1317 	struct uart_driver *drv;
1318 
1319 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1320 		console = true;
1321 
1322 	if (console) {
1323 		drv = &qcom_geni_console_driver;
1324 		line = of_alias_get_id(pdev->dev.of_node, "serial");
1325 	} else {
1326 		drv = &qcom_geni_uart_driver;
1327 		line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1328 	}
1329 
1330 	port = get_port_from_line(line, console);
1331 	if (IS_ERR(port)) {
1332 		dev_err(&pdev->dev, "Invalid line %d\n", line);
1333 		return PTR_ERR(port);
1334 	}
1335 
1336 	uport = &port->uport;
1337 	/* Don't allow 2 drivers to access the same port */
1338 	if (uport->private_data)
1339 		return -ENODEV;
1340 
1341 	uport->dev = &pdev->dev;
1342 	port->se.dev = &pdev->dev;
1343 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1344 	port->se.clk = devm_clk_get(&pdev->dev, "se");
1345 	if (IS_ERR(port->se.clk)) {
1346 		ret = PTR_ERR(port->se.clk);
1347 		dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1348 		return ret;
1349 	}
1350 
1351 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352 	if (!res)
1353 		return -EINVAL;
1354 	uport->mapbase = res->start;
1355 
1356 	port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1357 	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1358 	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1359 
1360 	irq = platform_get_irq(pdev, 0);
1361 	if (irq < 0) {
1362 		dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1363 		return irq;
1364 	}
1365 	uport->irq = irq;
1366 
1367 	uport->private_data = drv;
1368 	platform_set_drvdata(pdev, port);
1369 	port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1370 	if (!console)
1371 		device_create_file(uport->dev, &dev_attr_loopback);
1372 	return uart_add_one_port(drv, uport);
1373 }
1374 
1375 static int qcom_geni_serial_remove(struct platform_device *pdev)
1376 {
1377 	struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1378 	struct uart_driver *drv = port->uport.private_data;
1379 
1380 	uart_remove_one_port(drv, &port->uport);
1381 	return 0;
1382 }
1383 
1384 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1385 {
1386 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1387 	struct uart_port *uport = &port->uport;
1388 
1389 	return uart_suspend_port(uport->private_data, uport);
1390 }
1391 
1392 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1393 {
1394 	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1395 	struct uart_port *uport = &port->uport;
1396 
1397 	return uart_resume_port(uport->private_data, uport);
1398 }
1399 
1400 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1401 	SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1402 					qcom_geni_serial_sys_resume)
1403 };
1404 
1405 static const struct of_device_id qcom_geni_serial_match_table[] = {
1406 	{ .compatible = "qcom,geni-debug-uart", },
1407 	{ .compatible = "qcom,geni-uart", },
1408 	{}
1409 };
1410 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1411 
1412 static struct platform_driver qcom_geni_serial_platform_driver = {
1413 	.remove = qcom_geni_serial_remove,
1414 	.probe = qcom_geni_serial_probe,
1415 	.driver = {
1416 		.name = "qcom_geni_serial",
1417 		.of_match_table = qcom_geni_serial_match_table,
1418 		.pm = &qcom_geni_serial_pm_ops,
1419 	},
1420 };
1421 
1422 static int __init qcom_geni_serial_init(void)
1423 {
1424 	int ret;
1425 
1426 	ret = console_register(&qcom_geni_console_driver);
1427 	if (ret)
1428 		return ret;
1429 
1430 	ret = uart_register_driver(&qcom_geni_uart_driver);
1431 	if (ret) {
1432 		console_unregister(&qcom_geni_console_driver);
1433 		return ret;
1434 	}
1435 
1436 	ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1437 	if (ret) {
1438 		console_unregister(&qcom_geni_console_driver);
1439 		uart_unregister_driver(&qcom_geni_uart_driver);
1440 	}
1441 	return ret;
1442 }
1443 module_init(qcom_geni_serial_init);
1444 
1445 static void __exit qcom_geni_serial_exit(void)
1446 {
1447 	platform_driver_unregister(&qcom_geni_serial_platform_driver);
1448 	console_unregister(&qcom_geni_console_driver);
1449 	uart_unregister_driver(&qcom_geni_uart_driver);
1450 }
1451 module_exit(qcom_geni_serial_exit);
1452 
1453 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1454 MODULE_LICENSE("GPL v2");
1455