1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 5 # define SUPPORT_SYSRQ 6 #endif 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/qcom-geni-se.h> 19 #include <linux/serial.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 25 /* UART specific GENI registers */ 26 #define SE_UART_LOOPBACK_CFG 0x22c 27 #define SE_UART_TX_TRANS_CFG 0x25c 28 #define SE_UART_TX_WORD_LEN 0x268 29 #define SE_UART_TX_STOP_BIT_LEN 0x26c 30 #define SE_UART_TX_TRANS_LEN 0x270 31 #define SE_UART_RX_TRANS_CFG 0x280 32 #define SE_UART_RX_WORD_LEN 0x28c 33 #define SE_UART_RX_STALE_CNT 0x294 34 #define SE_UART_TX_PARITY_CFG 0x2a4 35 #define SE_UART_RX_PARITY_CFG 0x2a8 36 #define SE_UART_MANUAL_RFR 0x2ac 37 38 /* SE_UART_TRANS_CFG */ 39 #define UART_TX_PAR_EN BIT(0) 40 #define UART_CTS_MASK BIT(1) 41 42 /* SE_UART_TX_WORD_LEN */ 43 #define TX_WORD_LEN_MSK GENMASK(9, 0) 44 45 /* SE_UART_TX_STOP_BIT_LEN */ 46 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) 47 #define TX_STOP_BIT_LEN_1 0 48 #define TX_STOP_BIT_LEN_1_5 1 49 #define TX_STOP_BIT_LEN_2 2 50 51 /* SE_UART_TX_TRANS_LEN */ 52 #define TX_TRANS_LEN_MSK GENMASK(23, 0) 53 54 /* SE_UART_RX_TRANS_CFG */ 55 #define UART_RX_INS_STATUS_BIT BIT(2) 56 #define UART_RX_PAR_EN BIT(3) 57 58 /* SE_UART_RX_WORD_LEN */ 59 #define RX_WORD_LEN_MASK GENMASK(9, 0) 60 61 /* SE_UART_RX_STALE_CNT */ 62 #define RX_STALE_CNT GENMASK(23, 0) 63 64 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 65 #define PAR_CALC_EN BIT(0) 66 #define PAR_MODE_MSK GENMASK(2, 1) 67 #define PAR_MODE_SHFT 1 68 #define PAR_EVEN 0x00 69 #define PAR_ODD 0x01 70 #define PAR_SPACE 0x10 71 #define PAR_MARK 0x11 72 73 /* SE_UART_MANUAL_RFR register fields */ 74 #define UART_MANUAL_RFR_EN BIT(31) 75 #define UART_RFR_NOT_READY BIT(1) 76 #define UART_RFR_READY BIT(0) 77 78 /* UART M_CMD OP codes */ 79 #define UART_START_TX 0x1 80 #define UART_START_BREAK 0x4 81 #define UART_STOP_BREAK 0x5 82 /* UART S_CMD OP codes */ 83 #define UART_START_READ 0x1 84 #define UART_PARAM 0x1 85 86 #define UART_OVERSAMPLING 32 87 #define STALE_TIMEOUT 16 88 #define DEFAULT_BITS_PER_CHAR 10 89 #define GENI_UART_CONS_PORTS 1 90 #define GENI_UART_PORTS 3 91 #define DEF_FIFO_DEPTH_WORDS 16 92 #define DEF_TX_WM 2 93 #define DEF_FIFO_WIDTH_BITS 32 94 #define UART_RX_WM 2 95 #define MAX_LOOPBACK_CFG 3 96 97 #ifdef CONFIG_CONSOLE_POLL 98 #define CONSOLE_RX_BYTES_PW 1 99 #else 100 #define CONSOLE_RX_BYTES_PW 4 101 #endif 102 103 struct qcom_geni_serial_port { 104 struct uart_port uport; 105 struct geni_se se; 106 char name[20]; 107 u32 tx_fifo_depth; 108 u32 tx_fifo_width; 109 u32 rx_fifo_depth; 110 bool setup; 111 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); 112 unsigned int baud; 113 unsigned int tx_bytes_pw; 114 unsigned int rx_bytes_pw; 115 u32 *rx_fifo; 116 u32 loopback; 117 bool brk; 118 119 unsigned int tx_remaining; 120 int wakeup_irq; 121 }; 122 123 static const struct uart_ops qcom_geni_console_pops; 124 static const struct uart_ops qcom_geni_uart_pops; 125 static struct uart_driver qcom_geni_console_driver; 126 static struct uart_driver qcom_geni_uart_driver; 127 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); 128 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); 129 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); 130 static void qcom_geni_serial_stop_rx(struct uart_port *uport); 131 132 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 133 32000000, 48000000, 64000000, 80000000, 134 96000000, 100000000, 102400000, 135 112000000, 120000000, 128000000}; 136 137 #define to_dev_port(ptr, member) \ 138 container_of(ptr, struct qcom_geni_serial_port, member) 139 140 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 141 [0] = { 142 .uport = { 143 .iotype = UPIO_MEM, 144 .ops = &qcom_geni_uart_pops, 145 .flags = UPF_BOOT_AUTOCONF, 146 .line = 0, 147 }, 148 }, 149 [1] = { 150 .uport = { 151 .iotype = UPIO_MEM, 152 .ops = &qcom_geni_uart_pops, 153 .flags = UPF_BOOT_AUTOCONF, 154 .line = 1, 155 }, 156 }, 157 [2] = { 158 .uport = { 159 .iotype = UPIO_MEM, 160 .ops = &qcom_geni_uart_pops, 161 .flags = UPF_BOOT_AUTOCONF, 162 .line = 2, 163 }, 164 }, 165 }; 166 167 static ssize_t loopback_show(struct device *dev, 168 struct device_attribute *attr, char *buf) 169 { 170 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 171 172 return snprintf(buf, sizeof(u32), "%d\n", port->loopback); 173 } 174 175 static ssize_t loopback_store(struct device *dev, 176 struct device_attribute *attr, const char *buf, 177 size_t size) 178 { 179 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 180 u32 loopback; 181 182 if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) { 183 dev_err(dev, "Invalid input\n"); 184 return -EINVAL; 185 } 186 port->loopback = loopback; 187 return size; 188 } 189 static DEVICE_ATTR_RW(loopback); 190 191 static struct qcom_geni_serial_port qcom_geni_console_port = { 192 .uport = { 193 .iotype = UPIO_MEM, 194 .ops = &qcom_geni_console_pops, 195 .flags = UPF_BOOT_AUTOCONF, 196 .line = 0, 197 }, 198 }; 199 200 static int qcom_geni_serial_request_port(struct uart_port *uport) 201 { 202 struct platform_device *pdev = to_platform_device(uport->dev); 203 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 204 205 uport->membase = devm_platform_ioremap_resource(pdev, 0); 206 if (IS_ERR(uport->membase)) 207 return PTR_ERR(uport->membase); 208 port->se.base = uport->membase; 209 return 0; 210 } 211 212 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 213 { 214 if (cfg_flags & UART_CONFIG_TYPE) { 215 uport->type = PORT_MSM; 216 qcom_geni_serial_request_port(uport); 217 } 218 } 219 220 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 221 { 222 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 223 u32 geni_ios; 224 225 if (uart_console(uport)) { 226 mctrl |= TIOCM_CTS; 227 } else { 228 geni_ios = readl(uport->membase + SE_GENI_IOS); 229 if (!(geni_ios & IO2_DATA_IN)) 230 mctrl |= TIOCM_CTS; 231 } 232 233 return mctrl; 234 } 235 236 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 237 unsigned int mctrl) 238 { 239 u32 uart_manual_rfr = 0; 240 241 if (uart_console(uport)) 242 return; 243 244 if (!(mctrl & TIOCM_RTS)) 245 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 246 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 247 } 248 249 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 250 { 251 return "MSM"; 252 } 253 254 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 255 { 256 struct qcom_geni_serial_port *port; 257 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 258 259 if (line < 0 || line >= nr_ports) 260 return ERR_PTR(-ENXIO); 261 262 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 263 return port; 264 } 265 266 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 267 int offset, int field, bool set) 268 { 269 u32 reg; 270 struct qcom_geni_serial_port *port; 271 unsigned int baud; 272 unsigned int fifo_bits; 273 unsigned long timeout_us = 20000; 274 275 if (uport->private_data) { 276 port = to_dev_port(uport, uport); 277 baud = port->baud; 278 if (!baud) 279 baud = 115200; 280 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 281 /* 282 * Total polling iterations based on FIFO worth of bytes to be 283 * sent at current baud. Add a little fluff to the wait. 284 */ 285 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 286 } 287 288 /* 289 * Use custom implementation instead of readl_poll_atomic since ktimer 290 * is not ready at the time of early console. 291 */ 292 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 293 while (timeout_us) { 294 reg = readl(uport->membase + offset); 295 if ((bool)(reg & field) == set) 296 return true; 297 udelay(10); 298 timeout_us -= 10; 299 } 300 return false; 301 } 302 303 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 304 { 305 u32 m_cmd; 306 307 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 308 m_cmd = UART_START_TX << M_OPCODE_SHFT; 309 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 310 } 311 312 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 313 { 314 int done; 315 u32 irq_clear = M_CMD_DONE_EN; 316 317 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 318 M_CMD_DONE_EN, true); 319 if (!done) { 320 writel(M_GENI_CMD_ABORT, uport->membase + 321 SE_GENI_M_CMD_CTRL_REG); 322 irq_clear |= M_CMD_ABORT_EN; 323 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 324 M_CMD_ABORT_EN, true); 325 } 326 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 327 } 328 329 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 330 { 331 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 332 333 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 334 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 335 S_GENI_CMD_ABORT, false); 336 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 337 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 338 } 339 340 #ifdef CONFIG_CONSOLE_POLL 341 static int qcom_geni_serial_get_char(struct uart_port *uport) 342 { 343 u32 rx_fifo; 344 u32 status; 345 346 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 347 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 348 349 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 350 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 351 352 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 353 if (!(status & RX_FIFO_WC_MSK)) 354 return NO_POLL_CHAR; 355 356 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn); 357 return rx_fifo & 0xff; 358 } 359 360 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 361 unsigned char c) 362 { 363 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 364 qcom_geni_serial_setup_tx(uport, 1); 365 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 366 M_TX_FIFO_WATERMARK_EN, true)); 367 writel(c, uport->membase + SE_GENI_TX_FIFOn); 368 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 369 qcom_geni_serial_poll_tx_done(uport); 370 } 371 #endif 372 373 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 374 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch) 375 { 376 writel(ch, uport->membase + SE_GENI_TX_FIFOn); 377 } 378 379 static void 380 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 381 unsigned int count) 382 { 383 int i; 384 u32 bytes_to_send = count; 385 386 for (i = 0; i < count; i++) { 387 /* 388 * uart_console_write() adds a carriage return for each newline. 389 * Account for additional bytes to be written. 390 */ 391 if (s[i] == '\n') 392 bytes_to_send++; 393 } 394 395 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 396 qcom_geni_serial_setup_tx(uport, bytes_to_send); 397 for (i = 0; i < count; ) { 398 size_t chars_to_write = 0; 399 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 400 401 /* 402 * If the WM bit never set, then the Tx state machine is not 403 * in a valid state, so break, cancel/abort any existing 404 * command. Unfortunately the current data being written is 405 * lost. 406 */ 407 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 408 M_TX_FIFO_WATERMARK_EN, true)) 409 break; 410 chars_to_write = min_t(size_t, count - i, avail / 2); 411 uart_console_write(uport, s + i, chars_to_write, 412 qcom_geni_serial_wr_char); 413 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 414 SE_GENI_M_IRQ_CLEAR); 415 i += chars_to_write; 416 } 417 qcom_geni_serial_poll_tx_done(uport); 418 } 419 420 static void qcom_geni_serial_console_write(struct console *co, const char *s, 421 unsigned int count) 422 { 423 struct uart_port *uport; 424 struct qcom_geni_serial_port *port; 425 bool locked = true; 426 unsigned long flags; 427 u32 geni_status; 428 u32 irq_en; 429 430 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 431 432 port = get_port_from_line(co->index, true); 433 if (IS_ERR(port)) 434 return; 435 436 uport = &port->uport; 437 if (oops_in_progress) 438 locked = spin_trylock_irqsave(&uport->lock, flags); 439 else 440 spin_lock_irqsave(&uport->lock, flags); 441 442 geni_status = readl(uport->membase + SE_GENI_STATUS); 443 444 /* Cancel the current write to log the fault */ 445 if (!locked) { 446 geni_se_cancel_m_cmd(&port->se); 447 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 448 M_CMD_CANCEL_EN, true)) { 449 geni_se_abort_m_cmd(&port->se); 450 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 451 M_CMD_ABORT_EN, true); 452 writel(M_CMD_ABORT_EN, uport->membase + 453 SE_GENI_M_IRQ_CLEAR); 454 } 455 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 456 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 457 /* 458 * It seems we can't interrupt existing transfers if all data 459 * has been sent, in which case we need to look for done first. 460 */ 461 qcom_geni_serial_poll_tx_done(uport); 462 463 if (uart_circ_chars_pending(&uport->state->xmit)) { 464 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 465 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 466 uport->membase + SE_GENI_M_IRQ_EN); 467 } 468 } 469 470 __qcom_geni_serial_console_write(uport, s, count); 471 472 if (port->tx_remaining) 473 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 474 475 if (locked) 476 spin_unlock_irqrestore(&uport->lock, flags); 477 } 478 479 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 480 { 481 u32 i; 482 unsigned char buf[sizeof(u32)]; 483 struct tty_port *tport; 484 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 485 486 tport = &uport->state->port; 487 for (i = 0; i < bytes; ) { 488 int c; 489 int chunk = min_t(int, bytes - i, port->rx_bytes_pw); 490 491 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 492 i += chunk; 493 if (drop) 494 continue; 495 496 for (c = 0; c < chunk; c++) { 497 int sysrq; 498 499 uport->icount.rx++; 500 if (port->brk && buf[c] == 0) { 501 port->brk = false; 502 if (uart_handle_break(uport)) 503 continue; 504 } 505 506 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 507 508 if (!sysrq) 509 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 510 } 511 } 512 if (!drop) 513 tty_flip_buffer_push(tport); 514 return 0; 515 } 516 #else 517 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 518 { 519 return -EPERM; 520 } 521 522 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 523 524 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 525 { 526 unsigned char *buf; 527 struct tty_port *tport; 528 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 529 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; 530 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; 531 int ret; 532 533 tport = &uport->state->port; 534 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); 535 if (drop) 536 return 0; 537 538 buf = (unsigned char *)port->rx_fifo; 539 ret = tty_insert_flip_string(tport, buf, bytes); 540 if (ret != bytes) { 541 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 542 __func__, ret, bytes); 543 WARN_ON_ONCE(1); 544 } 545 uport->icount.rx += ret; 546 tty_flip_buffer_push(tport); 547 return ret; 548 } 549 550 static void qcom_geni_serial_start_tx(struct uart_port *uport) 551 { 552 u32 irq_en; 553 u32 status; 554 555 status = readl(uport->membase + SE_GENI_STATUS); 556 if (status & M_GENI_CMD_ACTIVE) 557 return; 558 559 if (!qcom_geni_serial_tx_empty(uport)) 560 return; 561 562 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 563 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 564 565 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 566 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 567 } 568 569 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 570 { 571 u32 irq_en; 572 u32 status; 573 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 574 575 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 576 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 577 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 578 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 579 status = readl(uport->membase + SE_GENI_STATUS); 580 /* Possible stop tx is called multiple times. */ 581 if (!(status & M_GENI_CMD_ACTIVE)) 582 return; 583 584 geni_se_cancel_m_cmd(&port->se); 585 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 586 M_CMD_CANCEL_EN, true)) { 587 geni_se_abort_m_cmd(&port->se); 588 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 589 M_CMD_ABORT_EN, true); 590 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 591 } 592 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 593 } 594 595 static void qcom_geni_serial_start_rx(struct uart_port *uport) 596 { 597 u32 irq_en; 598 u32 status; 599 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 600 601 status = readl(uport->membase + SE_GENI_STATUS); 602 if (status & S_GENI_CMD_ACTIVE) 603 qcom_geni_serial_stop_rx(uport); 604 605 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 606 607 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 608 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 609 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 610 611 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 612 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 613 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 614 } 615 616 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 617 { 618 u32 irq_en; 619 u32 status; 620 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 621 u32 irq_clear = S_CMD_DONE_EN; 622 623 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 624 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 625 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 626 627 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 628 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 629 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 630 631 status = readl(uport->membase + SE_GENI_STATUS); 632 /* Possible stop rx is called multiple times. */ 633 if (!(status & S_GENI_CMD_ACTIVE)) 634 return; 635 636 geni_se_cancel_s_cmd(&port->se); 637 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 638 S_GENI_CMD_CANCEL, false); 639 status = readl(uport->membase + SE_GENI_STATUS); 640 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 641 if (status & S_GENI_CMD_ACTIVE) 642 qcom_geni_serial_abort_rx(uport); 643 } 644 645 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) 646 { 647 u32 status; 648 u32 word_cnt; 649 u32 last_word_byte_cnt; 650 u32 last_word_partial; 651 u32 total_bytes; 652 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 653 654 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 655 word_cnt = status & RX_FIFO_WC_MSK; 656 last_word_partial = status & RX_LAST; 657 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 658 RX_LAST_BYTE_VALID_SHFT; 659 660 if (!word_cnt) 661 return; 662 total_bytes = port->rx_bytes_pw * (word_cnt - 1); 663 if (last_word_partial && last_word_byte_cnt) 664 total_bytes += last_word_byte_cnt; 665 else 666 total_bytes += port->rx_bytes_pw; 667 port->handle_rx(uport, total_bytes, drop); 668 } 669 670 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, 671 bool active) 672 { 673 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 674 struct circ_buf *xmit = &uport->state->xmit; 675 size_t avail; 676 size_t remaining; 677 size_t pending; 678 int i; 679 u32 status; 680 u32 irq_en; 681 unsigned int chunk; 682 int tail; 683 684 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 685 686 /* Complete the current tx command before taking newly added data */ 687 if (active) 688 pending = port->tx_remaining; 689 else 690 pending = uart_circ_chars_pending(xmit); 691 692 /* All data has been transmitted and acknowledged as received */ 693 if (!pending && !status && done) { 694 qcom_geni_serial_stop_tx(uport); 695 goto out_write_wakeup; 696 } 697 698 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 699 avail *= port->tx_bytes_pw; 700 701 tail = xmit->tail; 702 chunk = min(avail, pending); 703 if (!chunk) 704 goto out_write_wakeup; 705 706 if (!port->tx_remaining) { 707 qcom_geni_serial_setup_tx(uport, pending); 708 port->tx_remaining = pending; 709 710 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 711 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 712 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 713 uport->membase + SE_GENI_M_IRQ_EN); 714 } 715 716 remaining = chunk; 717 for (i = 0; i < chunk; ) { 718 unsigned int tx_bytes; 719 u8 buf[sizeof(u32)]; 720 int c; 721 722 memset(buf, 0, ARRAY_SIZE(buf)); 723 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw); 724 725 for (c = 0; c < tx_bytes ; c++) { 726 buf[c] = xmit->buf[tail++]; 727 tail &= UART_XMIT_SIZE - 1; 728 } 729 730 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 731 732 i += tx_bytes; 733 uport->icount.tx += tx_bytes; 734 remaining -= tx_bytes; 735 port->tx_remaining -= tx_bytes; 736 } 737 738 xmit->tail = tail; 739 740 /* 741 * The tx fifo watermark is level triggered and latched. Though we had 742 * cleared it in qcom_geni_serial_isr it will have already reasserted 743 * so we must clear it again here after our writes. 744 */ 745 writel(M_TX_FIFO_WATERMARK_EN, 746 uport->membase + SE_GENI_M_IRQ_CLEAR); 747 748 out_write_wakeup: 749 if (!port->tx_remaining) { 750 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 751 if (irq_en & M_TX_FIFO_WATERMARK_EN) 752 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 753 uport->membase + SE_GENI_M_IRQ_EN); 754 } 755 756 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 757 uart_write_wakeup(uport); 758 } 759 760 static irqreturn_t qcom_geni_serial_wakeup_isr(int isr, void *dev) 761 { 762 struct uart_port *uport = dev; 763 764 pm_wakeup_event(uport->dev, 2000); 765 766 return IRQ_HANDLED; 767 } 768 769 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 770 { 771 u32 m_irq_en; 772 u32 m_irq_status; 773 u32 s_irq_status; 774 u32 geni_status; 775 struct uart_port *uport = dev; 776 unsigned long flags; 777 bool drop_rx = false; 778 struct tty_port *tport = &uport->state->port; 779 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 780 781 if (uport->suspended) 782 return IRQ_NONE; 783 784 spin_lock_irqsave(&uport->lock, flags); 785 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 786 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 787 geni_status = readl(uport->membase + SE_GENI_STATUS); 788 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 789 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 790 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 791 792 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 793 goto out_unlock; 794 795 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 796 uport->icount.overrun++; 797 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 798 } 799 800 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 801 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, 802 geni_status & M_GENI_CMD_ACTIVE); 803 804 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { 805 if (s_irq_status & S_GP_IRQ_0_EN) 806 uport->icount.parity++; 807 drop_rx = true; 808 } else if (s_irq_status & S_GP_IRQ_2_EN || 809 s_irq_status & S_GP_IRQ_3_EN) { 810 uport->icount.brk++; 811 port->brk = true; 812 } 813 814 if (s_irq_status & S_RX_FIFO_WATERMARK_EN || 815 s_irq_status & S_RX_FIFO_LAST_EN) 816 qcom_geni_serial_handle_rx(uport, drop_rx); 817 818 out_unlock: 819 uart_unlock_and_check_sysrq(uport, flags); 820 821 return IRQ_HANDLED; 822 } 823 824 static void get_tx_fifo_size(struct qcom_geni_serial_port *port) 825 { 826 struct uart_port *uport; 827 828 uport = &port->uport; 829 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 830 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 831 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 832 uport->fifosize = 833 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 834 } 835 836 837 static void qcom_geni_serial_shutdown(struct uart_port *uport) 838 { 839 unsigned long flags; 840 841 /* Stop the console before stopping the current tx */ 842 if (uart_console(uport)) 843 console_stop(uport->cons); 844 845 disable_irq(uport->irq); 846 spin_lock_irqsave(&uport->lock, flags); 847 qcom_geni_serial_stop_tx(uport); 848 qcom_geni_serial_stop_rx(uport); 849 spin_unlock_irqrestore(&uport->lock, flags); 850 } 851 852 static int qcom_geni_serial_port_setup(struct uart_port *uport) 853 { 854 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 855 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 856 u32 proto; 857 858 if (uart_console(uport)) { 859 port->tx_bytes_pw = 1; 860 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW; 861 } else { 862 port->tx_bytes_pw = 4; 863 port->rx_bytes_pw = 4; 864 } 865 866 proto = geni_se_read_proto(&port->se); 867 if (proto != GENI_SE_UART) { 868 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 869 return -ENXIO; 870 } 871 872 qcom_geni_serial_stop_rx(uport); 873 874 get_tx_fifo_size(port); 875 876 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 877 /* 878 * Make an unconditional cancel on the main sequencer to reset 879 * it else we could end up in data loss scenarios. 880 */ 881 if (uart_console(uport)) 882 qcom_geni_serial_poll_tx_done(uport); 883 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw, 884 false, true, false); 885 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw, 886 false, false, true); 887 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 888 geni_se_select_mode(&port->se, GENI_SE_FIFO); 889 if (!uart_console(uport)) { 890 port->rx_fifo = devm_kcalloc(uport->dev, 891 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); 892 if (!port->rx_fifo) 893 return -ENOMEM; 894 } 895 port->setup = true; 896 897 return 0; 898 } 899 900 static int qcom_geni_serial_startup(struct uart_port *uport) 901 { 902 int ret; 903 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 904 905 if (!port->setup) { 906 ret = qcom_geni_serial_port_setup(uport); 907 if (ret) 908 return ret; 909 } 910 enable_irq(uport->irq); 911 912 return 0; 913 } 914 915 static unsigned long get_clk_cfg(unsigned long clk_freq) 916 { 917 int i; 918 919 for (i = 0; i < ARRAY_SIZE(root_freq); i++) { 920 if (!(root_freq[i] % clk_freq)) 921 return root_freq[i]; 922 } 923 return 0; 924 } 925 926 static unsigned long get_clk_div_rate(unsigned int baud, 927 unsigned int sampling_rate, unsigned int *clk_div) 928 { 929 unsigned long ser_clk; 930 unsigned long desired_clk; 931 932 desired_clk = baud * sampling_rate; 933 ser_clk = get_clk_cfg(desired_clk); 934 if (!ser_clk) { 935 pr_err("%s: Can't find matching DFS entry for baud %d\n", 936 __func__, baud); 937 return ser_clk; 938 } 939 940 *clk_div = ser_clk / desired_clk; 941 return ser_clk; 942 } 943 944 static void qcom_geni_serial_set_termios(struct uart_port *uport, 945 struct ktermios *termios, struct ktermios *old) 946 { 947 unsigned int baud; 948 u32 bits_per_char; 949 u32 tx_trans_cfg; 950 u32 tx_parity_cfg; 951 u32 rx_trans_cfg; 952 u32 rx_parity_cfg; 953 u32 stop_bit_len; 954 unsigned int clk_div; 955 u32 ser_clk_cfg; 956 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 957 unsigned long clk_rate; 958 u32 ver, sampling_rate; 959 960 qcom_geni_serial_stop_rx(uport); 961 /* baud rate */ 962 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 963 port->baud = baud; 964 965 sampling_rate = UART_OVERSAMPLING; 966 /* Sampling rate is halved for IP versions >= 2.5 */ 967 ver = geni_se_get_qup_hw_version(&port->se); 968 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5) 969 sampling_rate /= 2; 970 971 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div); 972 if (!clk_rate) 973 goto out_restart_rx; 974 975 uport->uartclk = clk_rate; 976 clk_set_rate(port->se.clk, clk_rate); 977 ser_clk_cfg = SER_CLK_EN; 978 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 979 980 /* parity */ 981 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 982 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 983 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 984 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 985 if (termios->c_cflag & PARENB) { 986 tx_trans_cfg |= UART_TX_PAR_EN; 987 rx_trans_cfg |= UART_RX_PAR_EN; 988 tx_parity_cfg |= PAR_CALC_EN; 989 rx_parity_cfg |= PAR_CALC_EN; 990 if (termios->c_cflag & PARODD) { 991 tx_parity_cfg |= PAR_ODD; 992 rx_parity_cfg |= PAR_ODD; 993 } else if (termios->c_cflag & CMSPAR) { 994 tx_parity_cfg |= PAR_SPACE; 995 rx_parity_cfg |= PAR_SPACE; 996 } else { 997 tx_parity_cfg |= PAR_EVEN; 998 rx_parity_cfg |= PAR_EVEN; 999 } 1000 } else { 1001 tx_trans_cfg &= ~UART_TX_PAR_EN; 1002 rx_trans_cfg &= ~UART_RX_PAR_EN; 1003 tx_parity_cfg &= ~PAR_CALC_EN; 1004 rx_parity_cfg &= ~PAR_CALC_EN; 1005 } 1006 1007 /* bits per char */ 1008 switch (termios->c_cflag & CSIZE) { 1009 case CS5: 1010 bits_per_char = 5; 1011 break; 1012 case CS6: 1013 bits_per_char = 6; 1014 break; 1015 case CS7: 1016 bits_per_char = 7; 1017 break; 1018 case CS8: 1019 default: 1020 bits_per_char = 8; 1021 break; 1022 } 1023 1024 /* stop bits */ 1025 if (termios->c_cflag & CSTOPB) 1026 stop_bit_len = TX_STOP_BIT_LEN_2; 1027 else 1028 stop_bit_len = TX_STOP_BIT_LEN_1; 1029 1030 /* flow control, clear the CTS_MASK bit if using flow control. */ 1031 if (termios->c_cflag & CRTSCTS) 1032 tx_trans_cfg &= ~UART_CTS_MASK; 1033 else 1034 tx_trans_cfg |= UART_CTS_MASK; 1035 1036 if (baud) 1037 uart_update_timeout(uport, termios->c_cflag, baud); 1038 1039 if (!uart_console(uport)) 1040 writel(port->loopback, 1041 uport->membase + SE_UART_LOOPBACK_CFG); 1042 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1043 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1044 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1045 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1046 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1047 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1048 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1049 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1050 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1051 out_restart_rx: 1052 qcom_geni_serial_start_rx(uport); 1053 } 1054 1055 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 1056 { 1057 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1058 } 1059 1060 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1061 static int __init qcom_geni_console_setup(struct console *co, char *options) 1062 { 1063 struct uart_port *uport; 1064 struct qcom_geni_serial_port *port; 1065 int baud = 9600; 1066 int bits = 8; 1067 int parity = 'n'; 1068 int flow = 'n'; 1069 int ret; 1070 1071 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1072 return -ENXIO; 1073 1074 port = get_port_from_line(co->index, true); 1075 if (IS_ERR(port)) { 1076 pr_err("Invalid line %d\n", co->index); 1077 return PTR_ERR(port); 1078 } 1079 1080 uport = &port->uport; 1081 1082 if (unlikely(!uport->membase)) 1083 return -ENXIO; 1084 1085 if (!port->setup) { 1086 ret = qcom_geni_serial_port_setup(uport); 1087 if (ret) 1088 return ret; 1089 } 1090 1091 if (options) 1092 uart_parse_options(options, &baud, &parity, &bits, &flow); 1093 1094 return uart_set_options(uport, co, baud, parity, bits, flow); 1095 } 1096 1097 static void qcom_geni_serial_earlycon_write(struct console *con, 1098 const char *s, unsigned int n) 1099 { 1100 struct earlycon_device *dev = con->data; 1101 1102 __qcom_geni_serial_console_write(&dev->port, s, n); 1103 } 1104 1105 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1106 const char *opt) 1107 { 1108 struct uart_port *uport = &dev->port; 1109 u32 tx_trans_cfg; 1110 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1111 u32 rx_trans_cfg = 0; 1112 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1113 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1114 u32 bits_per_char; 1115 struct geni_se se; 1116 1117 if (!uport->membase) 1118 return -EINVAL; 1119 1120 memset(&se, 0, sizeof(se)); 1121 se.base = uport->membase; 1122 if (geni_se_read_proto(&se) != GENI_SE_UART) 1123 return -ENXIO; 1124 /* 1125 * Ignore Flow control. 1126 * n = 8. 1127 */ 1128 tx_trans_cfg = UART_CTS_MASK; 1129 bits_per_char = BITS_PER_BYTE; 1130 1131 /* 1132 * Make an unconditional cancel on the main sequencer to reset 1133 * it else we could end up in data loss scenarios. 1134 */ 1135 qcom_geni_serial_poll_tx_done(uport); 1136 qcom_geni_serial_abort_rx(uport); 1137 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false); 1138 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1139 geni_se_select_mode(&se, GENI_SE_FIFO); 1140 1141 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1142 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1143 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1144 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1145 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1146 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1147 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1148 1149 dev->con->write = qcom_geni_serial_earlycon_write; 1150 dev->con->setup = NULL; 1151 return 0; 1152 } 1153 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1154 qcom_geni_serial_earlycon_setup); 1155 1156 static int __init console_register(struct uart_driver *drv) 1157 { 1158 return uart_register_driver(drv); 1159 } 1160 1161 static void console_unregister(struct uart_driver *drv) 1162 { 1163 uart_unregister_driver(drv); 1164 } 1165 1166 static struct console cons_ops = { 1167 .name = "ttyMSM", 1168 .write = qcom_geni_serial_console_write, 1169 .device = uart_console_device, 1170 .setup = qcom_geni_console_setup, 1171 .flags = CON_PRINTBUFFER, 1172 .index = -1, 1173 .data = &qcom_geni_console_driver, 1174 }; 1175 1176 static struct uart_driver qcom_geni_console_driver = { 1177 .owner = THIS_MODULE, 1178 .driver_name = "qcom_geni_console", 1179 .dev_name = "ttyMSM", 1180 .nr = GENI_UART_CONS_PORTS, 1181 .cons = &cons_ops, 1182 }; 1183 #else 1184 static int console_register(struct uart_driver *drv) 1185 { 1186 return 0; 1187 } 1188 1189 static void console_unregister(struct uart_driver *drv) 1190 { 1191 } 1192 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1193 1194 static struct uart_driver qcom_geni_uart_driver = { 1195 .owner = THIS_MODULE, 1196 .driver_name = "qcom_geni_uart", 1197 .dev_name = "ttyHS", 1198 .nr = GENI_UART_PORTS, 1199 }; 1200 1201 static void qcom_geni_serial_pm(struct uart_port *uport, 1202 unsigned int new_state, unsigned int old_state) 1203 { 1204 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1205 1206 /* If we've never been called, treat it as off */ 1207 if (old_state == UART_PM_STATE_UNDEFINED) 1208 old_state = UART_PM_STATE_OFF; 1209 1210 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) 1211 geni_se_resources_on(&port->se); 1212 else if (new_state == UART_PM_STATE_OFF && 1213 old_state == UART_PM_STATE_ON) 1214 geni_se_resources_off(&port->se); 1215 } 1216 1217 static const struct uart_ops qcom_geni_console_pops = { 1218 .tx_empty = qcom_geni_serial_tx_empty, 1219 .stop_tx = qcom_geni_serial_stop_tx, 1220 .start_tx = qcom_geni_serial_start_tx, 1221 .stop_rx = qcom_geni_serial_stop_rx, 1222 .set_termios = qcom_geni_serial_set_termios, 1223 .startup = qcom_geni_serial_startup, 1224 .request_port = qcom_geni_serial_request_port, 1225 .config_port = qcom_geni_serial_config_port, 1226 .shutdown = qcom_geni_serial_shutdown, 1227 .type = qcom_geni_serial_get_type, 1228 .set_mctrl = qcom_geni_serial_set_mctrl, 1229 .get_mctrl = qcom_geni_serial_get_mctrl, 1230 #ifdef CONFIG_CONSOLE_POLL 1231 .poll_get_char = qcom_geni_serial_get_char, 1232 .poll_put_char = qcom_geni_serial_poll_put_char, 1233 #endif 1234 .pm = qcom_geni_serial_pm, 1235 }; 1236 1237 static const struct uart_ops qcom_geni_uart_pops = { 1238 .tx_empty = qcom_geni_serial_tx_empty, 1239 .stop_tx = qcom_geni_serial_stop_tx, 1240 .start_tx = qcom_geni_serial_start_tx, 1241 .stop_rx = qcom_geni_serial_stop_rx, 1242 .set_termios = qcom_geni_serial_set_termios, 1243 .startup = qcom_geni_serial_startup, 1244 .request_port = qcom_geni_serial_request_port, 1245 .config_port = qcom_geni_serial_config_port, 1246 .shutdown = qcom_geni_serial_shutdown, 1247 .type = qcom_geni_serial_get_type, 1248 .set_mctrl = qcom_geni_serial_set_mctrl, 1249 .get_mctrl = qcom_geni_serial_get_mctrl, 1250 .pm = qcom_geni_serial_pm, 1251 }; 1252 1253 static int qcom_geni_serial_probe(struct platform_device *pdev) 1254 { 1255 int ret = 0; 1256 int line = -1; 1257 struct qcom_geni_serial_port *port; 1258 struct uart_port *uport; 1259 struct resource *res; 1260 int irq; 1261 bool console = false; 1262 struct uart_driver *drv; 1263 1264 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) 1265 console = true; 1266 1267 if (console) { 1268 drv = &qcom_geni_console_driver; 1269 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1270 } else { 1271 drv = &qcom_geni_uart_driver; 1272 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1273 } 1274 1275 port = get_port_from_line(line, console); 1276 if (IS_ERR(port)) { 1277 dev_err(&pdev->dev, "Invalid line %d\n", line); 1278 return PTR_ERR(port); 1279 } 1280 1281 uport = &port->uport; 1282 /* Don't allow 2 drivers to access the same port */ 1283 if (uport->private_data) 1284 return -ENODEV; 1285 1286 uport->dev = &pdev->dev; 1287 port->se.dev = &pdev->dev; 1288 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1289 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1290 if (IS_ERR(port->se.clk)) { 1291 ret = PTR_ERR(port->se.clk); 1292 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1293 return ret; 1294 } 1295 1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1297 if (!res) 1298 return -EINVAL; 1299 uport->mapbase = res->start; 1300 1301 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1302 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1303 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1304 1305 scnprintf(port->name, sizeof(port->name), "qcom_geni_serial_%s%d", 1306 (uart_console(uport) ? "console" : "uart"), uport->line); 1307 irq = platform_get_irq(pdev, 0); 1308 if (irq < 0) 1309 return irq; 1310 uport->irq = irq; 1311 1312 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1313 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1314 IRQF_TRIGGER_HIGH, port->name, uport); 1315 if (ret) { 1316 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1317 return ret; 1318 } 1319 1320 if (!console) { 1321 port->wakeup_irq = platform_get_irq(pdev, 1); 1322 if (port->wakeup_irq < 0) { 1323 dev_err(&pdev->dev, "Failed to get wakeup IRQ %d\n", 1324 port->wakeup_irq); 1325 } else { 1326 irq_set_status_flags(port->wakeup_irq, IRQ_NOAUTOEN); 1327 ret = devm_request_irq(uport->dev, port->wakeup_irq, 1328 qcom_geni_serial_wakeup_isr, 1329 IRQF_TRIGGER_FALLING, "uart_wakeup", uport); 1330 if (ret) { 1331 dev_err(uport->dev, "Failed to register wakeup IRQ ret %d\n", 1332 ret); 1333 return ret; 1334 } 1335 1336 device_init_wakeup(&pdev->dev, true); 1337 ret = dev_pm_set_wake_irq(&pdev->dev, port->wakeup_irq); 1338 if (unlikely(ret)) 1339 dev_err(uport->dev, "%s:Failed to set IRQ wake:%d\n", 1340 __func__, ret); 1341 } 1342 } 1343 uport->private_data = drv; 1344 platform_set_drvdata(pdev, port); 1345 port->handle_rx = console ? handle_rx_console : handle_rx_uart; 1346 if (!console) 1347 device_create_file(uport->dev, &dev_attr_loopback); 1348 return uart_add_one_port(drv, uport); 1349 } 1350 1351 static int qcom_geni_serial_remove(struct platform_device *pdev) 1352 { 1353 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1354 struct uart_driver *drv = port->uport.private_data; 1355 1356 uart_remove_one_port(drv, &port->uport); 1357 return 0; 1358 } 1359 1360 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev) 1361 { 1362 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1363 struct uart_port *uport = &port->uport; 1364 1365 uart_suspend_port(uport->private_data, uport); 1366 1367 if (port->wakeup_irq > 0) 1368 enable_irq(port->wakeup_irq); 1369 1370 return 0; 1371 } 1372 1373 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev) 1374 { 1375 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1376 struct uart_port *uport = &port->uport; 1377 1378 if (port->wakeup_irq > 0) 1379 disable_irq(port->wakeup_irq); 1380 1381 return uart_resume_port(uport->private_data, uport); 1382 } 1383 1384 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1385 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1386 qcom_geni_serial_sys_resume) 1387 }; 1388 1389 static const struct of_device_id qcom_geni_serial_match_table[] = { 1390 { .compatible = "qcom,geni-debug-uart", }, 1391 { .compatible = "qcom,geni-uart", }, 1392 {} 1393 }; 1394 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1395 1396 static struct platform_driver qcom_geni_serial_platform_driver = { 1397 .remove = qcom_geni_serial_remove, 1398 .probe = qcom_geni_serial_probe, 1399 .driver = { 1400 .name = "qcom_geni_serial", 1401 .of_match_table = qcom_geni_serial_match_table, 1402 .pm = &qcom_geni_serial_pm_ops, 1403 }, 1404 }; 1405 1406 static int __init qcom_geni_serial_init(void) 1407 { 1408 int ret; 1409 1410 ret = console_register(&qcom_geni_console_driver); 1411 if (ret) 1412 return ret; 1413 1414 ret = uart_register_driver(&qcom_geni_uart_driver); 1415 if (ret) { 1416 console_unregister(&qcom_geni_console_driver); 1417 return ret; 1418 } 1419 1420 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1421 if (ret) { 1422 console_unregister(&qcom_geni_console_driver); 1423 uart_unregister_driver(&qcom_geni_uart_driver); 1424 } 1425 return ret; 1426 } 1427 module_init(qcom_geni_serial_init); 1428 1429 static void __exit qcom_geni_serial_exit(void) 1430 { 1431 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1432 console_unregister(&qcom_geni_console_driver); 1433 uart_unregister_driver(&qcom_geni_uart_driver); 1434 } 1435 module_exit(qcom_geni_serial_exit); 1436 1437 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1438 MODULE_LICENSE("GPL v2"); 1439