1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_opp.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/soc/qcom/geni-se.h> 19 #include <linux/serial.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <dt-bindings/interconnect/qcom,icc.h> 25 26 /* UART specific GENI registers */ 27 #define SE_UART_LOOPBACK_CFG 0x22c 28 #define SE_UART_IO_MACRO_CTRL 0x240 29 #define SE_UART_TX_TRANS_CFG 0x25c 30 #define SE_UART_TX_WORD_LEN 0x268 31 #define SE_UART_TX_STOP_BIT_LEN 0x26c 32 #define SE_UART_TX_TRANS_LEN 0x270 33 #define SE_UART_RX_TRANS_CFG 0x280 34 #define SE_UART_RX_WORD_LEN 0x28c 35 #define SE_UART_RX_STALE_CNT 0x294 36 #define SE_UART_TX_PARITY_CFG 0x2a4 37 #define SE_UART_RX_PARITY_CFG 0x2a8 38 #define SE_UART_MANUAL_RFR 0x2ac 39 40 /* SE_UART_TRANS_CFG */ 41 #define UART_TX_PAR_EN BIT(0) 42 #define UART_CTS_MASK BIT(1) 43 44 /* SE_UART_TX_STOP_BIT_LEN */ 45 #define TX_STOP_BIT_LEN_1 0 46 #define TX_STOP_BIT_LEN_2 2 47 48 /* SE_UART_RX_TRANS_CFG */ 49 #define UART_RX_PAR_EN BIT(3) 50 51 /* SE_UART_RX_WORD_LEN */ 52 #define RX_WORD_LEN_MASK GENMASK(9, 0) 53 54 /* SE_UART_RX_STALE_CNT */ 55 #define RX_STALE_CNT GENMASK(23, 0) 56 57 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 58 #define PAR_CALC_EN BIT(0) 59 #define PAR_EVEN 0x00 60 #define PAR_ODD 0x01 61 #define PAR_SPACE 0x10 62 63 /* SE_UART_MANUAL_RFR register fields */ 64 #define UART_MANUAL_RFR_EN BIT(31) 65 #define UART_RFR_NOT_READY BIT(1) 66 #define UART_RFR_READY BIT(0) 67 68 /* UART M_CMD OP codes */ 69 #define UART_START_TX 0x1 70 /* UART S_CMD OP codes */ 71 #define UART_START_READ 0x1 72 #define UART_PARAM 0x1 73 #define UART_PARAM_RFR_OPEN BIT(7) 74 75 #define UART_OVERSAMPLING 32 76 #define STALE_TIMEOUT 16 77 #define DEFAULT_BITS_PER_CHAR 10 78 #define GENI_UART_CONS_PORTS 1 79 #define GENI_UART_PORTS 3 80 #define DEF_FIFO_DEPTH_WORDS 16 81 #define DEF_TX_WM 2 82 #define DEF_FIFO_WIDTH_BITS 32 83 #define UART_RX_WM 2 84 85 /* SE_UART_LOOPBACK_CFG */ 86 #define RX_TX_SORTED BIT(0) 87 #define CTS_RTS_SORTED BIT(1) 88 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 89 90 /* UART pin swap value */ 91 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 92 #define IO_MACRO_IO0_SEL 0x3 93 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 94 #define IO_MACRO_IO2_IO3_SWAP 0x4640 95 96 /* We always configure 4 bytes per FIFO word */ 97 #define BYTES_PER_FIFO_WORD 4U 98 99 #define DMA_RX_BUF_SIZE 2048 100 101 struct qcom_geni_device_data { 102 bool console; 103 enum geni_se_xfer_mode mode; 104 }; 105 106 struct qcom_geni_private_data { 107 /* NOTE: earlycon port will have NULL here */ 108 struct uart_driver *drv; 109 110 u32 poll_cached_bytes; 111 unsigned int poll_cached_bytes_cnt; 112 113 u32 write_cached_bytes; 114 unsigned int write_cached_bytes_cnt; 115 }; 116 117 struct qcom_geni_serial_port { 118 struct uart_port uport; 119 struct geni_se se; 120 const char *name; 121 u32 tx_fifo_depth; 122 u32 tx_fifo_width; 123 u32 rx_fifo_depth; 124 dma_addr_t tx_dma_addr; 125 dma_addr_t rx_dma_addr; 126 bool setup; 127 unsigned long poll_timeout_us; 128 unsigned long clk_rate; 129 void *rx_buf; 130 u32 loopback; 131 bool brk; 132 133 unsigned int tx_remaining; 134 int wakeup_irq; 135 bool rx_tx_swap; 136 bool cts_rts_swap; 137 138 struct qcom_geni_private_data private_data; 139 const struct qcom_geni_device_data *dev_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 147 static int qcom_geni_serial_port_setup(struct uart_port *uport); 148 149 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 150 { 151 return container_of(uport, struct qcom_geni_serial_port, uport); 152 } 153 154 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 155 [0] = { 156 .uport = { 157 .iotype = UPIO_MEM, 158 .ops = &qcom_geni_uart_pops, 159 .flags = UPF_BOOT_AUTOCONF, 160 .line = 0, 161 }, 162 }, 163 [1] = { 164 .uport = { 165 .iotype = UPIO_MEM, 166 .ops = &qcom_geni_uart_pops, 167 .flags = UPF_BOOT_AUTOCONF, 168 .line = 1, 169 }, 170 }, 171 [2] = { 172 .uport = { 173 .iotype = UPIO_MEM, 174 .ops = &qcom_geni_uart_pops, 175 .flags = UPF_BOOT_AUTOCONF, 176 .line = 2, 177 }, 178 }, 179 }; 180 181 static struct qcom_geni_serial_port qcom_geni_console_port = { 182 .uport = { 183 .iotype = UPIO_MEM, 184 .ops = &qcom_geni_console_pops, 185 .flags = UPF_BOOT_AUTOCONF, 186 .line = 0, 187 }, 188 }; 189 190 static int qcom_geni_serial_request_port(struct uart_port *uport) 191 { 192 struct platform_device *pdev = to_platform_device(uport->dev); 193 struct qcom_geni_serial_port *port = to_dev_port(uport); 194 195 uport->membase = devm_platform_ioremap_resource(pdev, 0); 196 if (IS_ERR(uport->membase)) 197 return PTR_ERR(uport->membase); 198 port->se.base = uport->membase; 199 return 0; 200 } 201 202 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 203 { 204 if (cfg_flags & UART_CONFIG_TYPE) { 205 uport->type = PORT_MSM; 206 qcom_geni_serial_request_port(uport); 207 } 208 } 209 210 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 211 { 212 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 213 u32 geni_ios; 214 215 if (uart_console(uport)) { 216 mctrl |= TIOCM_CTS; 217 } else { 218 geni_ios = readl(uport->membase + SE_GENI_IOS); 219 if (!(geni_ios & IO2_DATA_IN)) 220 mctrl |= TIOCM_CTS; 221 } 222 223 return mctrl; 224 } 225 226 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 227 unsigned int mctrl) 228 { 229 u32 uart_manual_rfr = 0; 230 struct qcom_geni_serial_port *port = to_dev_port(uport); 231 232 if (uart_console(uport)) 233 return; 234 235 if (mctrl & TIOCM_LOOP) 236 port->loopback = RX_TX_CTS_RTS_SORTED; 237 238 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 239 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 240 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 241 } 242 243 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 244 { 245 return "MSM"; 246 } 247 248 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 249 { 250 struct qcom_geni_serial_port *port; 251 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 252 253 if (line < 0 || line >= nr_ports) 254 return ERR_PTR(-ENXIO); 255 256 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 257 return port; 258 } 259 260 static bool qcom_geni_serial_main_active(struct uart_port *uport) 261 { 262 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 263 } 264 265 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 266 { 267 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 268 } 269 270 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 271 int offset, int field, bool set) 272 { 273 u32 reg; 274 struct qcom_geni_serial_port *port; 275 unsigned long timeout_us = 20000; 276 struct qcom_geni_private_data *private_data = uport->private_data; 277 278 if (private_data->drv) { 279 port = to_dev_port(uport); 280 if (port->poll_timeout_us) 281 timeout_us = port->poll_timeout_us; 282 } 283 284 /* 285 * Use custom implementation instead of readl_poll_atomic since ktimer 286 * is not ready at the time of early console. 287 */ 288 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 289 while (timeout_us) { 290 reg = readl(uport->membase + offset); 291 if ((bool)(reg & field) == set) 292 return true; 293 udelay(10); 294 timeout_us -= 10; 295 } 296 return false; 297 } 298 299 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 300 { 301 u32 m_cmd; 302 303 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 304 m_cmd = UART_START_TX << M_OPCODE_SHFT; 305 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 306 } 307 308 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 309 { 310 int done; 311 u32 irq_clear = M_CMD_DONE_EN; 312 313 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 314 M_CMD_DONE_EN, true); 315 if (!done) { 316 writel(M_GENI_CMD_ABORT, uport->membase + 317 SE_GENI_M_CMD_CTRL_REG); 318 irq_clear |= M_CMD_ABORT_EN; 319 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 320 M_CMD_ABORT_EN, true); 321 } 322 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 323 } 324 325 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 326 { 327 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 328 329 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 330 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 331 S_GENI_CMD_ABORT, false); 332 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 333 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 334 } 335 336 #ifdef CONFIG_CONSOLE_POLL 337 static int qcom_geni_serial_get_char(struct uart_port *uport) 338 { 339 struct qcom_geni_private_data *private_data = uport->private_data; 340 u32 status; 341 u32 word_cnt; 342 int ret; 343 344 if (!private_data->poll_cached_bytes_cnt) { 345 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 346 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 347 348 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 349 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 350 351 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 352 word_cnt = status & RX_FIFO_WC_MSK; 353 if (!word_cnt) 354 return NO_POLL_CHAR; 355 356 if (word_cnt == 1 && (status & RX_LAST)) 357 /* 358 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 359 * treated as if it was BYTES_PER_FIFO_WORD. 360 */ 361 private_data->poll_cached_bytes_cnt = 362 (status & RX_LAST_BYTE_VALID_MSK) >> 363 RX_LAST_BYTE_VALID_SHFT; 364 365 if (private_data->poll_cached_bytes_cnt == 0) 366 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 367 368 private_data->poll_cached_bytes = 369 readl(uport->membase + SE_GENI_RX_FIFOn); 370 } 371 372 private_data->poll_cached_bytes_cnt--; 373 ret = private_data->poll_cached_bytes & 0xff; 374 private_data->poll_cached_bytes >>= 8; 375 376 return ret; 377 } 378 379 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 380 unsigned char c) 381 { 382 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 383 qcom_geni_serial_setup_tx(uport, 1); 384 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 385 M_TX_FIFO_WATERMARK_EN, true)); 386 writel(c, uport->membase + SE_GENI_TX_FIFOn); 387 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 388 qcom_geni_serial_poll_tx_done(uport); 389 } 390 391 static int qcom_geni_serial_poll_init(struct uart_port *uport) 392 { 393 struct qcom_geni_serial_port *port = to_dev_port(uport); 394 int ret; 395 396 if (!port->setup) { 397 ret = qcom_geni_serial_port_setup(uport); 398 if (ret) 399 return ret; 400 } 401 402 if (!qcom_geni_serial_secondary_active(uport)) 403 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 404 405 return 0; 406 } 407 #endif 408 409 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 410 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 411 { 412 struct qcom_geni_private_data *private_data = uport->private_data; 413 414 private_data->write_cached_bytes = 415 (private_data->write_cached_bytes >> 8) | (ch << 24); 416 private_data->write_cached_bytes_cnt++; 417 418 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 419 writel(private_data->write_cached_bytes, 420 uport->membase + SE_GENI_TX_FIFOn); 421 private_data->write_cached_bytes_cnt = 0; 422 } 423 } 424 425 static void 426 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 427 unsigned int count) 428 { 429 struct qcom_geni_private_data *private_data = uport->private_data; 430 431 int i; 432 u32 bytes_to_send = count; 433 434 for (i = 0; i < count; i++) { 435 /* 436 * uart_console_write() adds a carriage return for each newline. 437 * Account for additional bytes to be written. 438 */ 439 if (s[i] == '\n') 440 bytes_to_send++; 441 } 442 443 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 444 qcom_geni_serial_setup_tx(uport, bytes_to_send); 445 for (i = 0; i < count; ) { 446 size_t chars_to_write = 0; 447 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 448 449 /* 450 * If the WM bit never set, then the Tx state machine is not 451 * in a valid state, so break, cancel/abort any existing 452 * command. Unfortunately the current data being written is 453 * lost. 454 */ 455 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 456 M_TX_FIFO_WATERMARK_EN, true)) 457 break; 458 chars_to_write = min_t(size_t, count - i, avail / 2); 459 uart_console_write(uport, s + i, chars_to_write, 460 qcom_geni_serial_wr_char); 461 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 462 SE_GENI_M_IRQ_CLEAR); 463 i += chars_to_write; 464 } 465 466 if (private_data->write_cached_bytes_cnt) { 467 private_data->write_cached_bytes >>= BITS_PER_BYTE * 468 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 469 writel(private_data->write_cached_bytes, 470 uport->membase + SE_GENI_TX_FIFOn); 471 private_data->write_cached_bytes_cnt = 0; 472 } 473 474 qcom_geni_serial_poll_tx_done(uport); 475 } 476 477 static void qcom_geni_serial_console_write(struct console *co, const char *s, 478 unsigned int count) 479 { 480 struct uart_port *uport; 481 struct qcom_geni_serial_port *port; 482 bool locked = true; 483 unsigned long flags; 484 u32 geni_status; 485 u32 irq_en; 486 487 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 488 489 port = get_port_from_line(co->index, true); 490 if (IS_ERR(port)) 491 return; 492 493 uport = &port->uport; 494 if (oops_in_progress) 495 locked = spin_trylock_irqsave(&uport->lock, flags); 496 else 497 spin_lock_irqsave(&uport->lock, flags); 498 499 geni_status = readl(uport->membase + SE_GENI_STATUS); 500 501 /* Cancel the current write to log the fault */ 502 if (!locked) { 503 geni_se_cancel_m_cmd(&port->se); 504 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 505 M_CMD_CANCEL_EN, true)) { 506 geni_se_abort_m_cmd(&port->se); 507 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 508 M_CMD_ABORT_EN, true); 509 writel(M_CMD_ABORT_EN, uport->membase + 510 SE_GENI_M_IRQ_CLEAR); 511 } 512 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 513 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 514 /* 515 * It seems we can't interrupt existing transfers if all data 516 * has been sent, in which case we need to look for done first. 517 */ 518 qcom_geni_serial_poll_tx_done(uport); 519 520 if (!uart_circ_empty(&uport->state->xmit)) { 521 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 522 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 523 uport->membase + SE_GENI_M_IRQ_EN); 524 } 525 } 526 527 __qcom_geni_serial_console_write(uport, s, count); 528 529 if (port->tx_remaining) 530 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 531 532 if (locked) 533 spin_unlock_irqrestore(&uport->lock, flags); 534 } 535 536 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 537 { 538 u32 i; 539 unsigned char buf[sizeof(u32)]; 540 struct tty_port *tport; 541 struct qcom_geni_serial_port *port = to_dev_port(uport); 542 543 tport = &uport->state->port; 544 for (i = 0; i < bytes; ) { 545 int c; 546 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 547 548 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 549 i += chunk; 550 if (drop) 551 continue; 552 553 for (c = 0; c < chunk; c++) { 554 int sysrq; 555 556 uport->icount.rx++; 557 if (port->brk && buf[c] == 0) { 558 port->brk = false; 559 if (uart_handle_break(uport)) 560 continue; 561 } 562 563 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 564 565 if (!sysrq) 566 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 567 } 568 } 569 if (!drop) 570 tty_flip_buffer_push(tport); 571 } 572 #else 573 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 574 { 575 576 } 577 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 578 579 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 580 { 581 struct qcom_geni_serial_port *port = to_dev_port(uport); 582 struct tty_port *tport = &uport->state->port; 583 int ret; 584 585 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 586 if (ret != bytes) { 587 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 588 __func__, ret, bytes); 589 WARN_ON_ONCE(1); 590 } 591 uport->icount.rx += ret; 592 tty_flip_buffer_push(tport); 593 } 594 595 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 596 { 597 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 598 } 599 600 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 601 { 602 struct qcom_geni_serial_port *port = to_dev_port(uport); 603 bool done; 604 605 if (!qcom_geni_serial_main_active(uport)) 606 return; 607 608 if (port->tx_dma_addr) { 609 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 610 port->tx_remaining); 611 port->tx_dma_addr = 0; 612 port->tx_remaining = 0; 613 } 614 615 geni_se_cancel_m_cmd(&port->se); 616 617 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 618 M_CMD_CANCEL_EN, true); 619 if (!done) { 620 geni_se_abort_m_cmd(&port->se); 621 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 622 M_CMD_ABORT_EN, true); 623 if (!done) 624 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 625 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 626 } 627 628 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 629 } 630 631 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 632 { 633 struct qcom_geni_serial_port *port = to_dev_port(uport); 634 struct circ_buf *xmit = &uport->state->xmit; 635 unsigned int xmit_size; 636 int ret; 637 638 if (port->tx_dma_addr) 639 return; 640 641 if (uart_circ_empty(xmit)) 642 return; 643 644 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 645 646 qcom_geni_serial_setup_tx(uport, xmit_size); 647 648 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], 649 xmit_size, &port->tx_dma_addr); 650 if (ret) { 651 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 652 qcom_geni_serial_stop_tx_dma(uport); 653 return; 654 } 655 656 port->tx_remaining = xmit_size; 657 } 658 659 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 660 { 661 u32 irq_en; 662 663 if (qcom_geni_serial_main_active(uport) || 664 !qcom_geni_serial_tx_empty(uport)) 665 return; 666 667 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 668 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 669 670 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 671 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 672 } 673 674 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 675 { 676 u32 irq_en; 677 struct qcom_geni_serial_port *port = to_dev_port(uport); 678 679 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 680 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 681 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 682 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 683 /* Possible stop tx is called multiple times. */ 684 if (!qcom_geni_serial_main_active(uport)) 685 return; 686 687 geni_se_cancel_m_cmd(&port->se); 688 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 689 M_CMD_CANCEL_EN, true)) { 690 geni_se_abort_m_cmd(&port->se); 691 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 692 M_CMD_ABORT_EN, true); 693 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 694 } 695 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 696 } 697 698 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 699 { 700 u32 status; 701 u32 word_cnt; 702 u32 last_word_byte_cnt; 703 u32 last_word_partial; 704 u32 total_bytes; 705 706 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 707 word_cnt = status & RX_FIFO_WC_MSK; 708 last_word_partial = status & RX_LAST; 709 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 710 RX_LAST_BYTE_VALID_SHFT; 711 712 if (!word_cnt) 713 return; 714 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 715 if (last_word_partial && last_word_byte_cnt) 716 total_bytes += last_word_byte_cnt; 717 else 718 total_bytes += BYTES_PER_FIFO_WORD; 719 handle_rx_console(uport, total_bytes, drop); 720 } 721 722 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 723 { 724 u32 irq_en; 725 struct qcom_geni_serial_port *port = to_dev_port(uport); 726 u32 s_irq_status; 727 728 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 729 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 730 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 731 732 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 733 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 734 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 735 736 if (!qcom_geni_serial_secondary_active(uport)) 737 return; 738 739 geni_se_cancel_s_cmd(&port->se); 740 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 741 S_CMD_CANCEL_EN, true); 742 /* 743 * If timeout occurs secondary engine remains active 744 * and Abort sequence is executed. 745 */ 746 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 747 /* Flush the Rx buffer */ 748 if (s_irq_status & S_RX_FIFO_LAST_EN) 749 qcom_geni_serial_handle_rx_fifo(uport, true); 750 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 751 752 if (qcom_geni_serial_secondary_active(uport)) 753 qcom_geni_serial_abort_rx(uport); 754 } 755 756 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 757 { 758 u32 irq_en; 759 struct qcom_geni_serial_port *port = to_dev_port(uport); 760 761 if (qcom_geni_serial_secondary_active(uport)) 762 qcom_geni_serial_stop_rx_fifo(uport); 763 764 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 765 766 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 767 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 768 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 769 770 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 771 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 772 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 773 } 774 775 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 776 { 777 struct qcom_geni_serial_port *port = to_dev_port(uport); 778 bool done; 779 780 if (!qcom_geni_serial_secondary_active(uport)) 781 return; 782 783 geni_se_cancel_s_cmd(&port->se); 784 done = qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 785 RX_EOT, true); 786 if (done) { 787 writel(RX_EOT | RX_DMA_DONE, 788 uport->membase + SE_DMA_RX_IRQ_CLR); 789 } else { 790 qcom_geni_serial_abort_rx(uport); 791 792 writel(1, uport->membase + SE_DMA_RX_FSM_RST); 793 qcom_geni_serial_poll_bit(uport, SE_DMA_RX_IRQ_STAT, 794 RX_RESET_DONE, true); 795 writel(RX_RESET_DONE | RX_DMA_DONE, 796 uport->membase + SE_DMA_RX_IRQ_CLR); 797 } 798 799 if (port->rx_dma_addr) { 800 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 801 DMA_RX_BUF_SIZE); 802 port->rx_dma_addr = 0; 803 } 804 } 805 806 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 807 { 808 struct qcom_geni_serial_port *port = to_dev_port(uport); 809 int ret; 810 811 if (qcom_geni_serial_secondary_active(uport)) 812 qcom_geni_serial_stop_rx_dma(uport); 813 814 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 815 816 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 817 DMA_RX_BUF_SIZE, 818 &port->rx_dma_addr); 819 if (ret) { 820 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 821 qcom_geni_serial_stop_rx_dma(uport); 822 } 823 } 824 825 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 826 { 827 struct qcom_geni_serial_port *port = to_dev_port(uport); 828 u32 rx_in; 829 int ret; 830 831 if (!qcom_geni_serial_secondary_active(uport)) 832 return; 833 834 if (!port->rx_dma_addr) 835 return; 836 837 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 838 port->rx_dma_addr = 0; 839 840 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 841 if (!rx_in) { 842 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 843 return; 844 } 845 846 if (!drop) 847 handle_rx_uart(uport, rx_in, drop); 848 849 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 850 DMA_RX_BUF_SIZE, 851 &port->rx_dma_addr); 852 if (ret) { 853 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 854 qcom_geni_serial_stop_rx_dma(uport); 855 } 856 } 857 858 static void qcom_geni_serial_start_rx(struct uart_port *uport) 859 { 860 uport->ops->start_rx(uport); 861 } 862 863 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 864 { 865 uport->ops->stop_rx(uport); 866 } 867 868 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 869 { 870 uport->ops->stop_tx(uport); 871 } 872 873 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 874 unsigned int chunk) 875 { 876 struct qcom_geni_serial_port *port = to_dev_port(uport); 877 struct circ_buf *xmit = &uport->state->xmit; 878 unsigned int tx_bytes, c, remaining = chunk; 879 u8 buf[BYTES_PER_FIFO_WORD]; 880 881 while (remaining) { 882 memset(buf, 0, sizeof(buf)); 883 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 884 885 for (c = 0; c < tx_bytes ; c++) { 886 buf[c] = xmit->buf[xmit->tail]; 887 uart_xmit_advance(uport, 1); 888 } 889 890 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 891 892 remaining -= tx_bytes; 893 port->tx_remaining -= tx_bytes; 894 } 895 } 896 897 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 898 bool done, bool active) 899 { 900 struct qcom_geni_serial_port *port = to_dev_port(uport); 901 struct circ_buf *xmit = &uport->state->xmit; 902 size_t avail; 903 size_t pending; 904 u32 status; 905 u32 irq_en; 906 unsigned int chunk; 907 908 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 909 910 /* Complete the current tx command before taking newly added data */ 911 if (active) 912 pending = port->tx_remaining; 913 else 914 pending = uart_circ_chars_pending(xmit); 915 916 /* All data has been transmitted and acknowledged as received */ 917 if (!pending && !status && done) { 918 qcom_geni_serial_stop_tx_fifo(uport); 919 goto out_write_wakeup; 920 } 921 922 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 923 avail *= BYTES_PER_FIFO_WORD; 924 925 chunk = min(avail, pending); 926 if (!chunk) 927 goto out_write_wakeup; 928 929 if (!port->tx_remaining) { 930 qcom_geni_serial_setup_tx(uport, pending); 931 port->tx_remaining = pending; 932 933 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 934 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 935 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 936 uport->membase + SE_GENI_M_IRQ_EN); 937 } 938 939 qcom_geni_serial_send_chunk_fifo(uport, chunk); 940 941 /* 942 * The tx fifo watermark is level triggered and latched. Though we had 943 * cleared it in qcom_geni_serial_isr it will have already reasserted 944 * so we must clear it again here after our writes. 945 */ 946 writel(M_TX_FIFO_WATERMARK_EN, 947 uport->membase + SE_GENI_M_IRQ_CLEAR); 948 949 out_write_wakeup: 950 if (!port->tx_remaining) { 951 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 952 if (irq_en & M_TX_FIFO_WATERMARK_EN) 953 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 954 uport->membase + SE_GENI_M_IRQ_EN); 955 } 956 957 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 958 uart_write_wakeup(uport); 959 } 960 961 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 962 { 963 struct qcom_geni_serial_port *port = to_dev_port(uport); 964 struct circ_buf *xmit = &uport->state->xmit; 965 966 uart_xmit_advance(uport, port->tx_remaining); 967 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 968 port->tx_dma_addr = 0; 969 port->tx_remaining = 0; 970 971 if (!uart_circ_empty(xmit)) 972 qcom_geni_serial_start_tx_dma(uport); 973 974 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 975 uart_write_wakeup(uport); 976 } 977 978 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 979 { 980 u32 m_irq_en; 981 u32 m_irq_status; 982 u32 s_irq_status; 983 u32 geni_status; 984 u32 dma; 985 u32 dma_tx_status; 986 u32 dma_rx_status; 987 struct uart_port *uport = dev; 988 bool drop_rx = false; 989 struct tty_port *tport = &uport->state->port; 990 struct qcom_geni_serial_port *port = to_dev_port(uport); 991 992 if (uport->suspended) 993 return IRQ_NONE; 994 995 spin_lock(&uport->lock); 996 997 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 998 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 999 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 1000 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 1001 geni_status = readl(uport->membase + SE_GENI_STATUS); 1002 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 1003 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 1004 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 1005 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 1006 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 1007 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 1008 1009 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 1010 goto out_unlock; 1011 1012 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 1013 uport->icount.overrun++; 1014 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1015 } 1016 1017 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 1018 if (s_irq_status & S_GP_IRQ_0_EN) 1019 uport->icount.parity++; 1020 drop_rx = true; 1021 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1022 uport->icount.brk++; 1023 port->brk = true; 1024 } 1025 1026 if (dma) { 1027 if (dma_tx_status & TX_DMA_DONE) 1028 qcom_geni_serial_handle_tx_dma(uport); 1029 1030 if (dma_rx_status) { 1031 if (dma_rx_status & RX_RESET_DONE) 1032 goto out_unlock; 1033 1034 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1035 uport->icount.parity++; 1036 drop_rx = true; 1037 } 1038 1039 if (dma_rx_status & RX_DMA_BREAK) 1040 uport->icount.brk++; 1041 1042 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1043 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1044 } 1045 } else { 1046 if (m_irq_status & m_irq_en & 1047 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1048 qcom_geni_serial_handle_tx_fifo(uport, 1049 m_irq_status & M_CMD_DONE_EN, 1050 geni_status & M_GENI_CMD_ACTIVE); 1051 1052 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1053 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1054 } 1055 1056 out_unlock: 1057 uart_unlock_and_check_sysrq(uport); 1058 1059 return IRQ_HANDLED; 1060 } 1061 1062 static int setup_fifos(struct qcom_geni_serial_port *port) 1063 { 1064 struct uart_port *uport; 1065 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1066 1067 uport = &port->uport; 1068 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1069 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1070 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1071 uport->fifosize = 1072 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1073 1074 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1075 /* 1076 * Use krealloc rather than krealloc_array because rx_buf is 1077 * accessed as 1 byte entries as well as 4 byte entries so it's 1078 * not necessarily an array. 1079 */ 1080 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1081 port->rx_fifo_depth * sizeof(u32), 1082 GFP_KERNEL); 1083 if (!port->rx_buf) 1084 return -ENOMEM; 1085 } 1086 1087 return 0; 1088 } 1089 1090 1091 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1092 { 1093 disable_irq(uport->irq); 1094 1095 if (uart_console(uport)) 1096 return; 1097 1098 qcom_geni_serial_stop_tx(uport); 1099 qcom_geni_serial_stop_rx(uport); 1100 } 1101 1102 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1103 { 1104 struct qcom_geni_serial_port *port = to_dev_port(uport); 1105 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1106 u32 proto; 1107 u32 pin_swap; 1108 int ret; 1109 1110 proto = geni_se_read_proto(&port->se); 1111 if (proto != GENI_SE_UART) { 1112 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1113 return -ENXIO; 1114 } 1115 1116 qcom_geni_serial_stop_rx(uport); 1117 1118 ret = setup_fifos(port); 1119 if (ret) 1120 return ret; 1121 1122 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1123 1124 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1125 if (port->rx_tx_swap) { 1126 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1127 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1128 } 1129 if (port->cts_rts_swap) { 1130 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1131 pin_swap |= IO_MACRO_IO0_SEL; 1132 } 1133 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1134 if (port->rx_tx_swap || port->cts_rts_swap) 1135 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1136 1137 /* 1138 * Make an unconditional cancel on the main sequencer to reset 1139 * it else we could end up in data loss scenarios. 1140 */ 1141 if (uart_console(uport)) 1142 qcom_geni_serial_poll_tx_done(uport); 1143 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1144 false, true, true); 1145 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1146 geni_se_select_mode(&port->se, port->dev_data->mode); 1147 port->setup = true; 1148 1149 return 0; 1150 } 1151 1152 static int qcom_geni_serial_startup(struct uart_port *uport) 1153 { 1154 int ret; 1155 struct qcom_geni_serial_port *port = to_dev_port(uport); 1156 1157 if (!port->setup) { 1158 ret = qcom_geni_serial_port_setup(uport); 1159 if (ret) 1160 return ret; 1161 } 1162 1163 uart_port_lock_irq(uport); 1164 qcom_geni_serial_start_rx(uport); 1165 uart_port_unlock_irq(uport); 1166 1167 enable_irq(uport->irq); 1168 1169 return 0; 1170 } 1171 1172 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1173 unsigned int *clk_div, unsigned int percent_tol) 1174 { 1175 unsigned long freq; 1176 unsigned long div, maxdiv; 1177 u64 mult; 1178 unsigned long offset, abs_tol, achieved; 1179 1180 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1181 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1182 div = 1; 1183 while (div <= maxdiv) { 1184 mult = (u64)div * desired_clk; 1185 if (mult != (unsigned long)mult) 1186 break; 1187 1188 offset = div * abs_tol; 1189 freq = clk_round_rate(clk, mult - offset); 1190 1191 /* Can only get lower if we're done */ 1192 if (freq < mult - offset) 1193 break; 1194 1195 /* 1196 * Re-calculate div in case rounding skipped rates but we 1197 * ended up at a good one, then check for a match. 1198 */ 1199 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1200 achieved = DIV_ROUND_CLOSEST(freq, div); 1201 if (achieved <= desired_clk + abs_tol && 1202 achieved >= desired_clk - abs_tol) { 1203 *clk_div = div; 1204 return freq; 1205 } 1206 1207 div = DIV_ROUND_UP(freq, desired_clk); 1208 } 1209 1210 return 0; 1211 } 1212 1213 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1214 unsigned int sampling_rate, unsigned int *clk_div) 1215 { 1216 unsigned long ser_clk; 1217 unsigned long desired_clk; 1218 1219 desired_clk = baud * sampling_rate; 1220 if (!desired_clk) 1221 return 0; 1222 1223 /* 1224 * try to find a clock rate within 2% tolerance, then within 5% 1225 */ 1226 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1227 if (!ser_clk) 1228 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1229 1230 return ser_clk; 1231 } 1232 1233 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1234 struct ktermios *termios, 1235 const struct ktermios *old) 1236 { 1237 unsigned int baud; 1238 u32 bits_per_char; 1239 u32 tx_trans_cfg; 1240 u32 tx_parity_cfg; 1241 u32 rx_trans_cfg; 1242 u32 rx_parity_cfg; 1243 u32 stop_bit_len; 1244 unsigned int clk_div; 1245 u32 ser_clk_cfg; 1246 struct qcom_geni_serial_port *port = to_dev_port(uport); 1247 unsigned long clk_rate; 1248 u32 ver, sampling_rate; 1249 unsigned int avg_bw_core; 1250 unsigned long timeout; 1251 1252 /* baud rate */ 1253 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1254 1255 sampling_rate = UART_OVERSAMPLING; 1256 /* Sampling rate is halved for IP versions >= 2.5 */ 1257 ver = geni_se_get_qup_hw_version(&port->se); 1258 if (ver >= QUP_SE_VERSION_2_5) 1259 sampling_rate /= 2; 1260 1261 clk_rate = get_clk_div_rate(port->se.clk, baud, 1262 sampling_rate, &clk_div); 1263 if (!clk_rate) { 1264 dev_err(port->se.dev, 1265 "Couldn't find suitable clock rate for %u\n", 1266 baud * sampling_rate); 1267 return; 1268 } 1269 1270 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", 1271 baud * sampling_rate, clk_rate, clk_div); 1272 1273 uport->uartclk = clk_rate; 1274 port->clk_rate = clk_rate; 1275 dev_pm_opp_set_rate(uport->dev, clk_rate); 1276 ser_clk_cfg = SER_CLK_EN; 1277 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1278 1279 /* 1280 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1281 * only. 1282 */ 1283 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1284 : GENI_DEFAULT_BW; 1285 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1286 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1287 geni_icc_set_bw(&port->se); 1288 1289 /* parity */ 1290 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1291 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1292 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1293 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1294 if (termios->c_cflag & PARENB) { 1295 tx_trans_cfg |= UART_TX_PAR_EN; 1296 rx_trans_cfg |= UART_RX_PAR_EN; 1297 tx_parity_cfg |= PAR_CALC_EN; 1298 rx_parity_cfg |= PAR_CALC_EN; 1299 if (termios->c_cflag & PARODD) { 1300 tx_parity_cfg |= PAR_ODD; 1301 rx_parity_cfg |= PAR_ODD; 1302 } else if (termios->c_cflag & CMSPAR) { 1303 tx_parity_cfg |= PAR_SPACE; 1304 rx_parity_cfg |= PAR_SPACE; 1305 } else { 1306 tx_parity_cfg |= PAR_EVEN; 1307 rx_parity_cfg |= PAR_EVEN; 1308 } 1309 } else { 1310 tx_trans_cfg &= ~UART_TX_PAR_EN; 1311 rx_trans_cfg &= ~UART_RX_PAR_EN; 1312 tx_parity_cfg &= ~PAR_CALC_EN; 1313 rx_parity_cfg &= ~PAR_CALC_EN; 1314 } 1315 1316 /* bits per char */ 1317 bits_per_char = tty_get_char_size(termios->c_cflag); 1318 1319 /* stop bits */ 1320 if (termios->c_cflag & CSTOPB) 1321 stop_bit_len = TX_STOP_BIT_LEN_2; 1322 else 1323 stop_bit_len = TX_STOP_BIT_LEN_1; 1324 1325 /* flow control, clear the CTS_MASK bit if using flow control. */ 1326 if (termios->c_cflag & CRTSCTS) 1327 tx_trans_cfg &= ~UART_CTS_MASK; 1328 else 1329 tx_trans_cfg |= UART_CTS_MASK; 1330 1331 if (baud) { 1332 uart_update_timeout(uport, termios->c_cflag, baud); 1333 1334 /* 1335 * Make sure that qcom_geni_serial_poll_bitfield() waits for 1336 * the FIFO, two-word intermediate transfer register and shift 1337 * register to clear. 1338 * 1339 * Note that uart_fifo_timeout() also adds a 20 ms margin. 1340 */ 1341 timeout = jiffies_to_usecs(uart_fifo_timeout(uport)); 1342 timeout += 3 * timeout / port->tx_fifo_depth; 1343 WRITE_ONCE(port->poll_timeout_us, timeout); 1344 } 1345 1346 if (!uart_console(uport)) 1347 writel(port->loopback, 1348 uport->membase + SE_UART_LOOPBACK_CFG); 1349 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1350 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1351 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1352 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1353 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1354 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1355 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1356 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1357 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1358 } 1359 1360 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1361 static int qcom_geni_console_setup(struct console *co, char *options) 1362 { 1363 struct uart_port *uport; 1364 struct qcom_geni_serial_port *port; 1365 int baud = 115200; 1366 int bits = 8; 1367 int parity = 'n'; 1368 int flow = 'n'; 1369 int ret; 1370 1371 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1372 return -ENXIO; 1373 1374 port = get_port_from_line(co->index, true); 1375 if (IS_ERR(port)) { 1376 pr_err("Invalid line %d\n", co->index); 1377 return PTR_ERR(port); 1378 } 1379 1380 uport = &port->uport; 1381 1382 if (unlikely(!uport->membase)) 1383 return -ENXIO; 1384 1385 if (!port->setup) { 1386 ret = qcom_geni_serial_port_setup(uport); 1387 if (ret) 1388 return ret; 1389 } 1390 1391 if (options) 1392 uart_parse_options(options, &baud, &parity, &bits, &flow); 1393 1394 return uart_set_options(uport, co, baud, parity, bits, flow); 1395 } 1396 1397 static void qcom_geni_serial_earlycon_write(struct console *con, 1398 const char *s, unsigned int n) 1399 { 1400 struct earlycon_device *dev = con->data; 1401 1402 __qcom_geni_serial_console_write(&dev->port, s, n); 1403 } 1404 1405 #ifdef CONFIG_CONSOLE_POLL 1406 static int qcom_geni_serial_earlycon_read(struct console *con, 1407 char *s, unsigned int n) 1408 { 1409 struct earlycon_device *dev = con->data; 1410 struct uart_port *uport = &dev->port; 1411 int num_read = 0; 1412 int ch; 1413 1414 while (num_read < n) { 1415 ch = qcom_geni_serial_get_char(uport); 1416 if (ch == NO_POLL_CHAR) 1417 break; 1418 s[num_read++] = ch; 1419 } 1420 1421 return num_read; 1422 } 1423 1424 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1425 struct console *con) 1426 { 1427 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1428 con->read = qcom_geni_serial_earlycon_read; 1429 } 1430 #else 1431 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1432 struct console *con) { } 1433 #endif 1434 1435 static struct qcom_geni_private_data earlycon_private_data; 1436 1437 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1438 const char *opt) 1439 { 1440 struct uart_port *uport = &dev->port; 1441 u32 tx_trans_cfg; 1442 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1443 u32 rx_trans_cfg = 0; 1444 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1445 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1446 u32 bits_per_char; 1447 struct geni_se se; 1448 1449 if (!uport->membase) 1450 return -EINVAL; 1451 1452 uport->private_data = &earlycon_private_data; 1453 1454 memset(&se, 0, sizeof(se)); 1455 se.base = uport->membase; 1456 if (geni_se_read_proto(&se) != GENI_SE_UART) 1457 return -ENXIO; 1458 /* 1459 * Ignore Flow control. 1460 * n = 8. 1461 */ 1462 tx_trans_cfg = UART_CTS_MASK; 1463 bits_per_char = BITS_PER_BYTE; 1464 1465 /* 1466 * Make an unconditional cancel on the main sequencer to reset 1467 * it else we could end up in data loss scenarios. 1468 */ 1469 qcom_geni_serial_poll_tx_done(uport); 1470 qcom_geni_serial_abort_rx(uport); 1471 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1472 false, true, true); 1473 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1474 geni_se_select_mode(&se, GENI_SE_FIFO); 1475 1476 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1477 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1478 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1479 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1480 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1481 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1482 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1483 1484 dev->con->write = qcom_geni_serial_earlycon_write; 1485 dev->con->setup = NULL; 1486 qcom_geni_serial_enable_early_read(&se, dev->con); 1487 1488 return 0; 1489 } 1490 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1491 qcom_geni_serial_earlycon_setup); 1492 1493 static int __init console_register(struct uart_driver *drv) 1494 { 1495 return uart_register_driver(drv); 1496 } 1497 1498 static void console_unregister(struct uart_driver *drv) 1499 { 1500 uart_unregister_driver(drv); 1501 } 1502 1503 static struct console cons_ops = { 1504 .name = "ttyMSM", 1505 .write = qcom_geni_serial_console_write, 1506 .device = uart_console_device, 1507 .setup = qcom_geni_console_setup, 1508 .flags = CON_PRINTBUFFER, 1509 .index = -1, 1510 .data = &qcom_geni_console_driver, 1511 }; 1512 1513 static struct uart_driver qcom_geni_console_driver = { 1514 .owner = THIS_MODULE, 1515 .driver_name = "qcom_geni_console", 1516 .dev_name = "ttyMSM", 1517 .nr = GENI_UART_CONS_PORTS, 1518 .cons = &cons_ops, 1519 }; 1520 #else 1521 static int console_register(struct uart_driver *drv) 1522 { 1523 return 0; 1524 } 1525 1526 static void console_unregister(struct uart_driver *drv) 1527 { 1528 } 1529 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1530 1531 static struct uart_driver qcom_geni_uart_driver = { 1532 .owner = THIS_MODULE, 1533 .driver_name = "qcom_geni_uart", 1534 .dev_name = "ttyHS", 1535 .nr = GENI_UART_PORTS, 1536 }; 1537 1538 static void qcom_geni_serial_pm(struct uart_port *uport, 1539 unsigned int new_state, unsigned int old_state) 1540 { 1541 struct qcom_geni_serial_port *port = to_dev_port(uport); 1542 1543 /* If we've never been called, treat it as off */ 1544 if (old_state == UART_PM_STATE_UNDEFINED) 1545 old_state = UART_PM_STATE_OFF; 1546 1547 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1548 geni_icc_enable(&port->se); 1549 if (port->clk_rate) 1550 dev_pm_opp_set_rate(uport->dev, port->clk_rate); 1551 geni_se_resources_on(&port->se); 1552 } else if (new_state == UART_PM_STATE_OFF && 1553 old_state == UART_PM_STATE_ON) { 1554 geni_se_resources_off(&port->se); 1555 dev_pm_opp_set_rate(uport->dev, 0); 1556 geni_icc_disable(&port->se); 1557 } 1558 } 1559 1560 static const struct uart_ops qcom_geni_console_pops = { 1561 .tx_empty = qcom_geni_serial_tx_empty, 1562 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1563 .start_tx = qcom_geni_serial_start_tx_fifo, 1564 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1565 .start_rx = qcom_geni_serial_start_rx_fifo, 1566 .set_termios = qcom_geni_serial_set_termios, 1567 .startup = qcom_geni_serial_startup, 1568 .request_port = qcom_geni_serial_request_port, 1569 .config_port = qcom_geni_serial_config_port, 1570 .shutdown = qcom_geni_serial_shutdown, 1571 .type = qcom_geni_serial_get_type, 1572 .set_mctrl = qcom_geni_serial_set_mctrl, 1573 .get_mctrl = qcom_geni_serial_get_mctrl, 1574 #ifdef CONFIG_CONSOLE_POLL 1575 .poll_get_char = qcom_geni_serial_get_char, 1576 .poll_put_char = qcom_geni_serial_poll_put_char, 1577 .poll_init = qcom_geni_serial_poll_init, 1578 #endif 1579 .pm = qcom_geni_serial_pm, 1580 }; 1581 1582 static const struct uart_ops qcom_geni_uart_pops = { 1583 .tx_empty = qcom_geni_serial_tx_empty, 1584 .stop_tx = qcom_geni_serial_stop_tx_dma, 1585 .start_tx = qcom_geni_serial_start_tx_dma, 1586 .start_rx = qcom_geni_serial_start_rx_dma, 1587 .stop_rx = qcom_geni_serial_stop_rx_dma, 1588 .set_termios = qcom_geni_serial_set_termios, 1589 .startup = qcom_geni_serial_startup, 1590 .request_port = qcom_geni_serial_request_port, 1591 .config_port = qcom_geni_serial_config_port, 1592 .shutdown = qcom_geni_serial_shutdown, 1593 .type = qcom_geni_serial_get_type, 1594 .set_mctrl = qcom_geni_serial_set_mctrl, 1595 .get_mctrl = qcom_geni_serial_get_mctrl, 1596 .pm = qcom_geni_serial_pm, 1597 }; 1598 1599 static int qcom_geni_serial_probe(struct platform_device *pdev) 1600 { 1601 int ret = 0; 1602 int line; 1603 struct qcom_geni_serial_port *port; 1604 struct uart_port *uport; 1605 struct resource *res; 1606 int irq; 1607 struct uart_driver *drv; 1608 const struct qcom_geni_device_data *data; 1609 1610 data = of_device_get_match_data(&pdev->dev); 1611 if (!data) 1612 return -EINVAL; 1613 1614 if (data->console) { 1615 drv = &qcom_geni_console_driver; 1616 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1617 } else { 1618 drv = &qcom_geni_uart_driver; 1619 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1620 if (line == -ENODEV) /* compat with non-standard aliases */ 1621 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1622 } 1623 1624 port = get_port_from_line(line, data->console); 1625 if (IS_ERR(port)) { 1626 dev_err(&pdev->dev, "Invalid line %d\n", line); 1627 return PTR_ERR(port); 1628 } 1629 1630 uport = &port->uport; 1631 /* Don't allow 2 drivers to access the same port */ 1632 if (uport->private_data) 1633 return -ENODEV; 1634 1635 uport->dev = &pdev->dev; 1636 port->dev_data = data; 1637 port->se.dev = &pdev->dev; 1638 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1639 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1640 if (IS_ERR(port->se.clk)) { 1641 ret = PTR_ERR(port->se.clk); 1642 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1643 return ret; 1644 } 1645 1646 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1647 if (!res) 1648 return -EINVAL; 1649 uport->mapbase = res->start; 1650 1651 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1652 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1653 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1654 1655 if (!data->console) { 1656 port->rx_buf = devm_kzalloc(uport->dev, 1657 DMA_RX_BUF_SIZE, GFP_KERNEL); 1658 if (!port->rx_buf) 1659 return -ENOMEM; 1660 } 1661 1662 ret = geni_icc_get(&port->se, NULL); 1663 if (ret) 1664 return ret; 1665 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1666 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1667 1668 /* Set BW for register access */ 1669 ret = geni_icc_set_bw(&port->se); 1670 if (ret) 1671 return ret; 1672 1673 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1674 "qcom_geni_serial_%s%d", 1675 uart_console(uport) ? "console" : "uart", uport->line); 1676 if (!port->name) 1677 return -ENOMEM; 1678 1679 irq = platform_get_irq(pdev, 0); 1680 if (irq < 0) 1681 return irq; 1682 uport->irq = irq; 1683 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1684 1685 if (!data->console) 1686 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1687 1688 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1689 port->rx_tx_swap = true; 1690 1691 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1692 port->cts_rts_swap = true; 1693 1694 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1695 if (ret) 1696 return ret; 1697 /* OPP table is optional */ 1698 ret = devm_pm_opp_of_add_table(&pdev->dev); 1699 if (ret && ret != -ENODEV) { 1700 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1701 return ret; 1702 } 1703 1704 port->private_data.drv = drv; 1705 uport->private_data = &port->private_data; 1706 platform_set_drvdata(pdev, port); 1707 1708 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1709 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1710 IRQF_TRIGGER_HIGH, port->name, uport); 1711 if (ret) { 1712 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1713 return ret; 1714 } 1715 1716 ret = uart_add_one_port(drv, uport); 1717 if (ret) 1718 return ret; 1719 1720 if (port->wakeup_irq > 0) { 1721 device_init_wakeup(&pdev->dev, true); 1722 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1723 port->wakeup_irq); 1724 if (ret) { 1725 device_init_wakeup(&pdev->dev, false); 1726 uart_remove_one_port(drv, uport); 1727 return ret; 1728 } 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int qcom_geni_serial_remove(struct platform_device *pdev) 1735 { 1736 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1737 struct uart_driver *drv = port->private_data.drv; 1738 1739 dev_pm_clear_wake_irq(&pdev->dev); 1740 device_init_wakeup(&pdev->dev, false); 1741 uart_remove_one_port(drv, &port->uport); 1742 1743 return 0; 1744 } 1745 1746 static int qcom_geni_serial_sys_suspend(struct device *dev) 1747 { 1748 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1749 struct uart_port *uport = &port->uport; 1750 struct qcom_geni_private_data *private_data = uport->private_data; 1751 1752 /* 1753 * This is done so we can hit the lowest possible state in suspend 1754 * even with no_console_suspend 1755 */ 1756 if (uart_console(uport)) { 1757 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1758 geni_icc_set_bw(&port->se); 1759 } 1760 return uart_suspend_port(private_data->drv, uport); 1761 } 1762 1763 static int qcom_geni_serial_sys_resume(struct device *dev) 1764 { 1765 int ret; 1766 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1767 struct uart_port *uport = &port->uport; 1768 struct qcom_geni_private_data *private_data = uport->private_data; 1769 1770 ret = uart_resume_port(private_data->drv, uport); 1771 if (uart_console(uport)) { 1772 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1773 geni_icc_set_bw(&port->se); 1774 } 1775 return ret; 1776 } 1777 1778 static const struct qcom_geni_device_data qcom_geni_console_data = { 1779 .console = true, 1780 .mode = GENI_SE_FIFO, 1781 }; 1782 1783 static const struct qcom_geni_device_data qcom_geni_uart_data = { 1784 .console = false, 1785 .mode = GENI_SE_DMA, 1786 }; 1787 1788 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1789 SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1790 qcom_geni_serial_sys_resume) 1791 }; 1792 1793 static const struct of_device_id qcom_geni_serial_match_table[] = { 1794 { 1795 .compatible = "qcom,geni-debug-uart", 1796 .data = &qcom_geni_console_data, 1797 }, 1798 { 1799 .compatible = "qcom,geni-uart", 1800 .data = &qcom_geni_uart_data, 1801 }, 1802 {} 1803 }; 1804 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1805 1806 static struct platform_driver qcom_geni_serial_platform_driver = { 1807 .remove = qcom_geni_serial_remove, 1808 .probe = qcom_geni_serial_probe, 1809 .driver = { 1810 .name = "qcom_geni_serial", 1811 .of_match_table = qcom_geni_serial_match_table, 1812 .pm = &qcom_geni_serial_pm_ops, 1813 }, 1814 }; 1815 1816 static int __init qcom_geni_serial_init(void) 1817 { 1818 int ret; 1819 1820 ret = console_register(&qcom_geni_console_driver); 1821 if (ret) 1822 return ret; 1823 1824 ret = uart_register_driver(&qcom_geni_uart_driver); 1825 if (ret) { 1826 console_unregister(&qcom_geni_console_driver); 1827 return ret; 1828 } 1829 1830 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1831 if (ret) { 1832 console_unregister(&qcom_geni_console_driver); 1833 uart_unregister_driver(&qcom_geni_uart_driver); 1834 } 1835 return ret; 1836 } 1837 module_init(qcom_geni_serial_init); 1838 1839 static void __exit qcom_geni_serial_exit(void) 1840 { 1841 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1842 console_unregister(&qcom_geni_console_driver); 1843 uart_unregister_driver(&qcom_geni_uart_driver); 1844 } 1845 module_exit(qcom_geni_serial_exit); 1846 1847 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1848 MODULE_LICENSE("GPL v2"); 1849