1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/console.h> 6 #include <linux/io.h> 7 #include <linux/iopoll.h> 8 #include <linux/irq.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/pm_opp.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/pm_wakeirq.h> 16 #include <linux/qcom-geni-se.h> 17 #include <linux/serial.h> 18 #include <linux/serial_core.h> 19 #include <linux/slab.h> 20 #include <linux/tty.h> 21 #include <linux/tty_flip.h> 22 23 /* UART specific GENI registers */ 24 #define SE_UART_LOOPBACK_CFG 0x22c 25 #define SE_UART_IO_MACRO_CTRL 0x240 26 #define SE_UART_TX_TRANS_CFG 0x25c 27 #define SE_UART_TX_WORD_LEN 0x268 28 #define SE_UART_TX_STOP_BIT_LEN 0x26c 29 #define SE_UART_TX_TRANS_LEN 0x270 30 #define SE_UART_RX_TRANS_CFG 0x280 31 #define SE_UART_RX_WORD_LEN 0x28c 32 #define SE_UART_RX_STALE_CNT 0x294 33 #define SE_UART_TX_PARITY_CFG 0x2a4 34 #define SE_UART_RX_PARITY_CFG 0x2a8 35 #define SE_UART_MANUAL_RFR 0x2ac 36 37 /* SE_UART_TRANS_CFG */ 38 #define UART_TX_PAR_EN BIT(0) 39 #define UART_CTS_MASK BIT(1) 40 41 /* SE_UART_TX_WORD_LEN */ 42 #define TX_WORD_LEN_MSK GENMASK(9, 0) 43 44 /* SE_UART_TX_STOP_BIT_LEN */ 45 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) 46 #define TX_STOP_BIT_LEN_1 0 47 #define TX_STOP_BIT_LEN_1_5 1 48 #define TX_STOP_BIT_LEN_2 2 49 50 /* SE_UART_TX_TRANS_LEN */ 51 #define TX_TRANS_LEN_MSK GENMASK(23, 0) 52 53 /* SE_UART_RX_TRANS_CFG */ 54 #define UART_RX_INS_STATUS_BIT BIT(2) 55 #define UART_RX_PAR_EN BIT(3) 56 57 /* SE_UART_RX_WORD_LEN */ 58 #define RX_WORD_LEN_MASK GENMASK(9, 0) 59 60 /* SE_UART_RX_STALE_CNT */ 61 #define RX_STALE_CNT GENMASK(23, 0) 62 63 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 64 #define PAR_CALC_EN BIT(0) 65 #define PAR_MODE_MSK GENMASK(2, 1) 66 #define PAR_MODE_SHFT 1 67 #define PAR_EVEN 0x00 68 #define PAR_ODD 0x01 69 #define PAR_SPACE 0x10 70 #define PAR_MARK 0x11 71 72 /* SE_UART_MANUAL_RFR register fields */ 73 #define UART_MANUAL_RFR_EN BIT(31) 74 #define UART_RFR_NOT_READY BIT(1) 75 #define UART_RFR_READY BIT(0) 76 77 /* UART M_CMD OP codes */ 78 #define UART_START_TX 0x1 79 #define UART_START_BREAK 0x4 80 #define UART_STOP_BREAK 0x5 81 /* UART S_CMD OP codes */ 82 #define UART_START_READ 0x1 83 #define UART_PARAM 0x1 84 85 #define UART_OVERSAMPLING 32 86 #define STALE_TIMEOUT 16 87 #define DEFAULT_BITS_PER_CHAR 10 88 #define GENI_UART_CONS_PORTS 1 89 #define GENI_UART_PORTS 3 90 #define DEF_FIFO_DEPTH_WORDS 16 91 #define DEF_TX_WM 2 92 #define DEF_FIFO_WIDTH_BITS 32 93 #define UART_RX_WM 2 94 95 /* SE_UART_LOOPBACK_CFG */ 96 #define RX_TX_SORTED BIT(0) 97 #define CTS_RTS_SORTED BIT(1) 98 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 99 100 /* UART pin swap value */ 101 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 102 #define IO_MACRO_IO0_SEL 0x3 103 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 104 #define IO_MACRO_IO2_IO3_SWAP 0x4640 105 106 /* We always configure 4 bytes per FIFO word */ 107 #define BYTES_PER_FIFO_WORD 4 108 109 struct qcom_geni_private_data { 110 /* NOTE: earlycon port will have NULL here */ 111 struct uart_driver *drv; 112 113 u32 poll_cached_bytes; 114 unsigned int poll_cached_bytes_cnt; 115 116 u32 write_cached_bytes; 117 unsigned int write_cached_bytes_cnt; 118 }; 119 120 struct qcom_geni_serial_port { 121 struct uart_port uport; 122 struct geni_se se; 123 const char *name; 124 u32 tx_fifo_depth; 125 u32 tx_fifo_width; 126 u32 rx_fifo_depth; 127 bool setup; 128 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); 129 unsigned int baud; 130 void *rx_fifo; 131 u32 loopback; 132 bool brk; 133 134 unsigned int tx_remaining; 135 int wakeup_irq; 136 bool rx_tx_swap; 137 bool cts_rts_swap; 138 139 struct qcom_geni_private_data private_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); 147 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); 148 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); 149 static void qcom_geni_serial_stop_rx(struct uart_port *uport); 150 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); 151 152 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 153 32000000, 48000000, 51200000, 64000000, 154 80000000, 96000000, 100000000, 155 102400000, 112000000, 120000000, 156 128000000}; 157 158 #define to_dev_port(ptr, member) \ 159 container_of(ptr, struct qcom_geni_serial_port, member) 160 161 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 162 [0] = { 163 .uport = { 164 .iotype = UPIO_MEM, 165 .ops = &qcom_geni_uart_pops, 166 .flags = UPF_BOOT_AUTOCONF, 167 .line = 0, 168 }, 169 }, 170 [1] = { 171 .uport = { 172 .iotype = UPIO_MEM, 173 .ops = &qcom_geni_uart_pops, 174 .flags = UPF_BOOT_AUTOCONF, 175 .line = 1, 176 }, 177 }, 178 [2] = { 179 .uport = { 180 .iotype = UPIO_MEM, 181 .ops = &qcom_geni_uart_pops, 182 .flags = UPF_BOOT_AUTOCONF, 183 .line = 2, 184 }, 185 }, 186 }; 187 188 static struct qcom_geni_serial_port qcom_geni_console_port = { 189 .uport = { 190 .iotype = UPIO_MEM, 191 .ops = &qcom_geni_console_pops, 192 .flags = UPF_BOOT_AUTOCONF, 193 .line = 0, 194 }, 195 }; 196 197 static int qcom_geni_serial_request_port(struct uart_port *uport) 198 { 199 struct platform_device *pdev = to_platform_device(uport->dev); 200 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 201 202 uport->membase = devm_platform_ioremap_resource(pdev, 0); 203 if (IS_ERR(uport->membase)) 204 return PTR_ERR(uport->membase); 205 port->se.base = uport->membase; 206 return 0; 207 } 208 209 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 210 { 211 if (cfg_flags & UART_CONFIG_TYPE) { 212 uport->type = PORT_MSM; 213 qcom_geni_serial_request_port(uport); 214 } 215 } 216 217 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 218 { 219 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 220 u32 geni_ios; 221 222 if (uart_console(uport)) { 223 mctrl |= TIOCM_CTS; 224 } else { 225 geni_ios = readl(uport->membase + SE_GENI_IOS); 226 if (!(geni_ios & IO2_DATA_IN)) 227 mctrl |= TIOCM_CTS; 228 } 229 230 return mctrl; 231 } 232 233 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 234 unsigned int mctrl) 235 { 236 u32 uart_manual_rfr = 0; 237 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 238 239 if (uart_console(uport)) 240 return; 241 242 if (mctrl & TIOCM_LOOP) 243 port->loopback = RX_TX_CTS_RTS_SORTED; 244 245 if (!(mctrl & TIOCM_RTS)) 246 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 248 } 249 250 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 251 { 252 return "MSM"; 253 } 254 255 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 256 { 257 struct qcom_geni_serial_port *port; 258 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 259 260 if (line < 0 || line >= nr_ports) 261 return ERR_PTR(-ENXIO); 262 263 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 264 return port; 265 } 266 267 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 268 int offset, int field, bool set) 269 { 270 u32 reg; 271 struct qcom_geni_serial_port *port; 272 unsigned int baud; 273 unsigned int fifo_bits; 274 unsigned long timeout_us = 20000; 275 struct qcom_geni_private_data *private_data = uport->private_data; 276 277 if (private_data->drv) { 278 port = to_dev_port(uport, uport); 279 baud = port->baud; 280 if (!baud) 281 baud = 115200; 282 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 283 /* 284 * Total polling iterations based on FIFO worth of bytes to be 285 * sent at current baud. Add a little fluff to the wait. 286 */ 287 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 288 } 289 290 /* 291 * Use custom implementation instead of readl_poll_atomic since ktimer 292 * is not ready at the time of early console. 293 */ 294 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 295 while (timeout_us) { 296 reg = readl(uport->membase + offset); 297 if ((bool)(reg & field) == set) 298 return true; 299 udelay(10); 300 timeout_us -= 10; 301 } 302 return false; 303 } 304 305 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 306 { 307 u32 m_cmd; 308 309 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 310 m_cmd = UART_START_TX << M_OPCODE_SHFT; 311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 312 } 313 314 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 315 { 316 int done; 317 u32 irq_clear = M_CMD_DONE_EN; 318 319 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 320 M_CMD_DONE_EN, true); 321 if (!done) { 322 writel(M_GENI_CMD_ABORT, uport->membase + 323 SE_GENI_M_CMD_CTRL_REG); 324 irq_clear |= M_CMD_ABORT_EN; 325 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 326 M_CMD_ABORT_EN, true); 327 } 328 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 329 } 330 331 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 332 { 333 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 334 335 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 336 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 337 S_GENI_CMD_ABORT, false); 338 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 339 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 340 } 341 342 #ifdef CONFIG_CONSOLE_POLL 343 344 static int qcom_geni_serial_get_char(struct uart_port *uport) 345 { 346 struct qcom_geni_private_data *private_data = uport->private_data; 347 u32 status; 348 u32 word_cnt; 349 int ret; 350 351 if (!private_data->poll_cached_bytes_cnt) { 352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 354 355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 357 358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 359 word_cnt = status & RX_FIFO_WC_MSK; 360 if (!word_cnt) 361 return NO_POLL_CHAR; 362 363 if (word_cnt == 1 && (status & RX_LAST)) 364 private_data->poll_cached_bytes_cnt = 365 (status & RX_LAST_BYTE_VALID_MSK) >> 366 RX_LAST_BYTE_VALID_SHFT; 367 else 368 private_data->poll_cached_bytes_cnt = 4; 369 370 private_data->poll_cached_bytes = 371 readl(uport->membase + SE_GENI_RX_FIFOn); 372 } 373 374 private_data->poll_cached_bytes_cnt--; 375 ret = private_data->poll_cached_bytes & 0xff; 376 private_data->poll_cached_bytes >>= 8; 377 378 return ret; 379 } 380 381 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 382 unsigned char c) 383 { 384 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 385 qcom_geni_serial_setup_tx(uport, 1); 386 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 387 M_TX_FIFO_WATERMARK_EN, true)); 388 writel(c, uport->membase + SE_GENI_TX_FIFOn); 389 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 390 qcom_geni_serial_poll_tx_done(uport); 391 } 392 #endif 393 394 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 395 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch) 396 { 397 struct qcom_geni_private_data *private_data = uport->private_data; 398 399 private_data->write_cached_bytes = 400 (private_data->write_cached_bytes >> 8) | (ch << 24); 401 private_data->write_cached_bytes_cnt++; 402 403 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 404 writel(private_data->write_cached_bytes, 405 uport->membase + SE_GENI_TX_FIFOn); 406 private_data->write_cached_bytes_cnt = 0; 407 } 408 } 409 410 static void 411 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 412 unsigned int count) 413 { 414 struct qcom_geni_private_data *private_data = uport->private_data; 415 416 int i; 417 u32 bytes_to_send = count; 418 419 for (i = 0; i < count; i++) { 420 /* 421 * uart_console_write() adds a carriage return for each newline. 422 * Account for additional bytes to be written. 423 */ 424 if (s[i] == '\n') 425 bytes_to_send++; 426 } 427 428 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 429 qcom_geni_serial_setup_tx(uport, bytes_to_send); 430 for (i = 0; i < count; ) { 431 size_t chars_to_write = 0; 432 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 433 434 /* 435 * If the WM bit never set, then the Tx state machine is not 436 * in a valid state, so break, cancel/abort any existing 437 * command. Unfortunately the current data being written is 438 * lost. 439 */ 440 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 441 M_TX_FIFO_WATERMARK_EN, true)) 442 break; 443 chars_to_write = min_t(size_t, count - i, avail / 2); 444 uart_console_write(uport, s + i, chars_to_write, 445 qcom_geni_serial_wr_char); 446 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 447 SE_GENI_M_IRQ_CLEAR); 448 i += chars_to_write; 449 } 450 451 if (private_data->write_cached_bytes_cnt) { 452 private_data->write_cached_bytes >>= BITS_PER_BYTE * 453 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 454 writel(private_data->write_cached_bytes, 455 uport->membase + SE_GENI_TX_FIFOn); 456 private_data->write_cached_bytes_cnt = 0; 457 } 458 459 qcom_geni_serial_poll_tx_done(uport); 460 } 461 462 static void qcom_geni_serial_console_write(struct console *co, const char *s, 463 unsigned int count) 464 { 465 struct uart_port *uport; 466 struct qcom_geni_serial_port *port; 467 bool locked = true; 468 unsigned long flags; 469 u32 geni_status; 470 u32 irq_en; 471 472 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 473 474 port = get_port_from_line(co->index, true); 475 if (IS_ERR(port)) 476 return; 477 478 uport = &port->uport; 479 if (oops_in_progress) 480 locked = spin_trylock_irqsave(&uport->lock, flags); 481 else 482 spin_lock_irqsave(&uport->lock, flags); 483 484 geni_status = readl(uport->membase + SE_GENI_STATUS); 485 486 /* Cancel the current write to log the fault */ 487 if (!locked) { 488 geni_se_cancel_m_cmd(&port->se); 489 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 490 M_CMD_CANCEL_EN, true)) { 491 geni_se_abort_m_cmd(&port->se); 492 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 493 M_CMD_ABORT_EN, true); 494 writel(M_CMD_ABORT_EN, uport->membase + 495 SE_GENI_M_IRQ_CLEAR); 496 } 497 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 498 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 499 /* 500 * It seems we can't interrupt existing transfers if all data 501 * has been sent, in which case we need to look for done first. 502 */ 503 qcom_geni_serial_poll_tx_done(uport); 504 505 if (uart_circ_chars_pending(&uport->state->xmit)) { 506 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 507 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 508 uport->membase + SE_GENI_M_IRQ_EN); 509 } 510 } 511 512 __qcom_geni_serial_console_write(uport, s, count); 513 514 if (port->tx_remaining) 515 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 516 517 if (locked) 518 spin_unlock_irqrestore(&uport->lock, flags); 519 } 520 521 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 522 { 523 u32 i; 524 unsigned char buf[sizeof(u32)]; 525 struct tty_port *tport; 526 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 527 528 tport = &uport->state->port; 529 for (i = 0; i < bytes; ) { 530 int c; 531 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 532 533 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 534 i += chunk; 535 if (drop) 536 continue; 537 538 for (c = 0; c < chunk; c++) { 539 int sysrq; 540 541 uport->icount.rx++; 542 if (port->brk && buf[c] == 0) { 543 port->brk = false; 544 if (uart_handle_break(uport)) 545 continue; 546 } 547 548 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 549 550 if (!sysrq) 551 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 552 } 553 } 554 if (!drop) 555 tty_flip_buffer_push(tport); 556 return 0; 557 } 558 #else 559 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 560 { 561 return -EPERM; 562 } 563 564 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 565 566 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 567 { 568 struct tty_port *tport; 569 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 570 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; 571 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; 572 int ret; 573 574 tport = &uport->state->port; 575 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); 576 if (drop) 577 return 0; 578 579 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); 580 if (ret != bytes) { 581 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 582 __func__, ret, bytes); 583 WARN_ON_ONCE(1); 584 } 585 uport->icount.rx += ret; 586 tty_flip_buffer_push(tport); 587 return ret; 588 } 589 590 static void qcom_geni_serial_start_tx(struct uart_port *uport) 591 { 592 u32 irq_en; 593 u32 status; 594 595 status = readl(uport->membase + SE_GENI_STATUS); 596 if (status & M_GENI_CMD_ACTIVE) 597 return; 598 599 if (!qcom_geni_serial_tx_empty(uport)) 600 return; 601 602 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 603 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 604 605 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 606 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 607 } 608 609 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 610 { 611 u32 irq_en; 612 u32 status; 613 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 614 615 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 616 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 617 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 618 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 619 status = readl(uport->membase + SE_GENI_STATUS); 620 /* Possible stop tx is called multiple times. */ 621 if (!(status & M_GENI_CMD_ACTIVE)) 622 return; 623 624 geni_se_cancel_m_cmd(&port->se); 625 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 626 M_CMD_CANCEL_EN, true)) { 627 geni_se_abort_m_cmd(&port->se); 628 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 629 M_CMD_ABORT_EN, true); 630 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 631 } 632 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 633 } 634 635 static void qcom_geni_serial_start_rx(struct uart_port *uport) 636 { 637 u32 irq_en; 638 u32 status; 639 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 640 641 status = readl(uport->membase + SE_GENI_STATUS); 642 if (status & S_GENI_CMD_ACTIVE) 643 qcom_geni_serial_stop_rx(uport); 644 645 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 646 647 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 648 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 649 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 650 651 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 652 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 653 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 654 } 655 656 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 657 { 658 u32 irq_en; 659 u32 status; 660 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 661 u32 s_irq_status; 662 663 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 664 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 665 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 666 667 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 668 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 669 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 670 671 status = readl(uport->membase + SE_GENI_STATUS); 672 /* Possible stop rx is called multiple times. */ 673 if (!(status & S_GENI_CMD_ACTIVE)) 674 return; 675 676 geni_se_cancel_s_cmd(&port->se); 677 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 678 S_CMD_CANCEL_EN, true); 679 /* 680 * If timeout occurs secondary engine remains active 681 * and Abort sequence is executed. 682 */ 683 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 684 /* Flush the Rx buffer */ 685 if (s_irq_status & S_RX_FIFO_LAST_EN) 686 qcom_geni_serial_handle_rx(uport, true); 687 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 688 689 status = readl(uport->membase + SE_GENI_STATUS); 690 if (status & S_GENI_CMD_ACTIVE) 691 qcom_geni_serial_abort_rx(uport); 692 } 693 694 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) 695 { 696 u32 status; 697 u32 word_cnt; 698 u32 last_word_byte_cnt; 699 u32 last_word_partial; 700 u32 total_bytes; 701 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 702 703 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 704 word_cnt = status & RX_FIFO_WC_MSK; 705 last_word_partial = status & RX_LAST; 706 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 707 RX_LAST_BYTE_VALID_SHFT; 708 709 if (!word_cnt) 710 return; 711 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 712 if (last_word_partial && last_word_byte_cnt) 713 total_bytes += last_word_byte_cnt; 714 else 715 total_bytes += BYTES_PER_FIFO_WORD; 716 port->handle_rx(uport, total_bytes, drop); 717 } 718 719 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, 720 bool active) 721 { 722 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 723 struct circ_buf *xmit = &uport->state->xmit; 724 size_t avail; 725 size_t remaining; 726 size_t pending; 727 int i; 728 u32 status; 729 u32 irq_en; 730 unsigned int chunk; 731 int tail; 732 733 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 734 735 /* Complete the current tx command before taking newly added data */ 736 if (active) 737 pending = port->tx_remaining; 738 else 739 pending = uart_circ_chars_pending(xmit); 740 741 /* All data has been transmitted and acknowledged as received */ 742 if (!pending && !status && done) { 743 qcom_geni_serial_stop_tx(uport); 744 goto out_write_wakeup; 745 } 746 747 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 748 avail *= BYTES_PER_FIFO_WORD; 749 750 tail = xmit->tail; 751 chunk = min(avail, pending); 752 if (!chunk) 753 goto out_write_wakeup; 754 755 if (!port->tx_remaining) { 756 qcom_geni_serial_setup_tx(uport, pending); 757 port->tx_remaining = pending; 758 759 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 760 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 761 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 762 uport->membase + SE_GENI_M_IRQ_EN); 763 } 764 765 remaining = chunk; 766 for (i = 0; i < chunk; ) { 767 unsigned int tx_bytes; 768 u8 buf[sizeof(u32)]; 769 int c; 770 771 memset(buf, 0, sizeof(buf)); 772 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD); 773 774 for (c = 0; c < tx_bytes ; c++) { 775 buf[c] = xmit->buf[tail++]; 776 tail &= UART_XMIT_SIZE - 1; 777 } 778 779 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 780 781 i += tx_bytes; 782 uport->icount.tx += tx_bytes; 783 remaining -= tx_bytes; 784 port->tx_remaining -= tx_bytes; 785 } 786 787 xmit->tail = tail; 788 789 /* 790 * The tx fifo watermark is level triggered and latched. Though we had 791 * cleared it in qcom_geni_serial_isr it will have already reasserted 792 * so we must clear it again here after our writes. 793 */ 794 writel(M_TX_FIFO_WATERMARK_EN, 795 uport->membase + SE_GENI_M_IRQ_CLEAR); 796 797 out_write_wakeup: 798 if (!port->tx_remaining) { 799 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 800 if (irq_en & M_TX_FIFO_WATERMARK_EN) 801 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 802 uport->membase + SE_GENI_M_IRQ_EN); 803 } 804 805 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 806 uart_write_wakeup(uport); 807 } 808 809 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 810 { 811 u32 m_irq_en; 812 u32 m_irq_status; 813 u32 s_irq_status; 814 u32 geni_status; 815 struct uart_port *uport = dev; 816 unsigned long flags; 817 bool drop_rx = false; 818 struct tty_port *tport = &uport->state->port; 819 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 820 821 if (uport->suspended) 822 return IRQ_NONE; 823 824 spin_lock_irqsave(&uport->lock, flags); 825 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 826 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 827 geni_status = readl(uport->membase + SE_GENI_STATUS); 828 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 829 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 830 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 831 832 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 833 goto out_unlock; 834 835 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 836 uport->icount.overrun++; 837 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 838 } 839 840 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 841 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, 842 geni_status & M_GENI_CMD_ACTIVE); 843 844 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { 845 if (s_irq_status & S_GP_IRQ_0_EN) 846 uport->icount.parity++; 847 drop_rx = true; 848 } else if (s_irq_status & S_GP_IRQ_2_EN || 849 s_irq_status & S_GP_IRQ_3_EN) { 850 uport->icount.brk++; 851 port->brk = true; 852 } 853 854 if (s_irq_status & S_RX_FIFO_WATERMARK_EN || 855 s_irq_status & S_RX_FIFO_LAST_EN) 856 qcom_geni_serial_handle_rx(uport, drop_rx); 857 858 out_unlock: 859 uart_unlock_and_check_sysrq(uport, flags); 860 861 return IRQ_HANDLED; 862 } 863 864 static void get_tx_fifo_size(struct qcom_geni_serial_port *port) 865 { 866 struct uart_port *uport; 867 868 uport = &port->uport; 869 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 870 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 871 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 872 uport->fifosize = 873 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 874 } 875 876 877 static void qcom_geni_serial_shutdown(struct uart_port *uport) 878 { 879 disable_irq(uport->irq); 880 } 881 882 static int qcom_geni_serial_port_setup(struct uart_port *uport) 883 { 884 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 885 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 886 u32 proto; 887 u32 pin_swap; 888 889 proto = geni_se_read_proto(&port->se); 890 if (proto != GENI_SE_UART) { 891 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 892 return -ENXIO; 893 } 894 895 qcom_geni_serial_stop_rx(uport); 896 897 get_tx_fifo_size(port); 898 899 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 900 901 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 902 if (port->rx_tx_swap) { 903 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 904 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 905 } 906 if (port->cts_rts_swap) { 907 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 908 pin_swap |= IO_MACRO_IO0_SEL; 909 } 910 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 911 if (port->rx_tx_swap || port->cts_rts_swap) 912 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 913 914 /* 915 * Make an unconditional cancel on the main sequencer to reset 916 * it else we could end up in data loss scenarios. 917 */ 918 if (uart_console(uport)) 919 qcom_geni_serial_poll_tx_done(uport); 920 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 921 false, true, true); 922 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 923 geni_se_select_mode(&port->se, GENI_SE_FIFO); 924 port->setup = true; 925 926 return 0; 927 } 928 929 static int qcom_geni_serial_startup(struct uart_port *uport) 930 { 931 int ret; 932 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 933 934 if (!port->setup) { 935 ret = qcom_geni_serial_port_setup(uport); 936 if (ret) 937 return ret; 938 } 939 enable_irq(uport->irq); 940 941 return 0; 942 } 943 944 static unsigned long get_clk_cfg(unsigned long clk_freq) 945 { 946 int i; 947 948 for (i = 0; i < ARRAY_SIZE(root_freq); i++) { 949 if (!(root_freq[i] % clk_freq)) 950 return root_freq[i]; 951 } 952 return 0; 953 } 954 955 static unsigned long get_clk_div_rate(unsigned int baud, 956 unsigned int sampling_rate, unsigned int *clk_div) 957 { 958 unsigned long ser_clk; 959 unsigned long desired_clk; 960 961 desired_clk = baud * sampling_rate; 962 ser_clk = get_clk_cfg(desired_clk); 963 if (!ser_clk) { 964 pr_err("%s: Can't find matching DFS entry for baud %d\n", 965 __func__, baud); 966 return ser_clk; 967 } 968 969 *clk_div = ser_clk / desired_clk; 970 return ser_clk; 971 } 972 973 static void qcom_geni_serial_set_termios(struct uart_port *uport, 974 struct ktermios *termios, struct ktermios *old) 975 { 976 unsigned int baud; 977 u32 bits_per_char; 978 u32 tx_trans_cfg; 979 u32 tx_parity_cfg; 980 u32 rx_trans_cfg; 981 u32 rx_parity_cfg; 982 u32 stop_bit_len; 983 unsigned int clk_div; 984 u32 ser_clk_cfg; 985 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 986 unsigned long clk_rate; 987 u32 ver, sampling_rate; 988 unsigned int avg_bw_core; 989 990 qcom_geni_serial_stop_rx(uport); 991 /* baud rate */ 992 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 993 port->baud = baud; 994 995 sampling_rate = UART_OVERSAMPLING; 996 /* Sampling rate is halved for IP versions >= 2.5 */ 997 ver = geni_se_get_qup_hw_version(&port->se); 998 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5) 999 sampling_rate /= 2; 1000 1001 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div); 1002 if (!clk_rate) 1003 goto out_restart_rx; 1004 1005 uport->uartclk = clk_rate; 1006 dev_pm_opp_set_rate(uport->dev, clk_rate); 1007 ser_clk_cfg = SER_CLK_EN; 1008 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1009 1010 /* 1011 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1012 * only. 1013 */ 1014 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1015 : GENI_DEFAULT_BW; 1016 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1017 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1018 geni_icc_set_bw(&port->se); 1019 1020 /* parity */ 1021 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1022 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1023 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1024 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1025 if (termios->c_cflag & PARENB) { 1026 tx_trans_cfg |= UART_TX_PAR_EN; 1027 rx_trans_cfg |= UART_RX_PAR_EN; 1028 tx_parity_cfg |= PAR_CALC_EN; 1029 rx_parity_cfg |= PAR_CALC_EN; 1030 if (termios->c_cflag & PARODD) { 1031 tx_parity_cfg |= PAR_ODD; 1032 rx_parity_cfg |= PAR_ODD; 1033 } else if (termios->c_cflag & CMSPAR) { 1034 tx_parity_cfg |= PAR_SPACE; 1035 rx_parity_cfg |= PAR_SPACE; 1036 } else { 1037 tx_parity_cfg |= PAR_EVEN; 1038 rx_parity_cfg |= PAR_EVEN; 1039 } 1040 } else { 1041 tx_trans_cfg &= ~UART_TX_PAR_EN; 1042 rx_trans_cfg &= ~UART_RX_PAR_EN; 1043 tx_parity_cfg &= ~PAR_CALC_EN; 1044 rx_parity_cfg &= ~PAR_CALC_EN; 1045 } 1046 1047 /* bits per char */ 1048 switch (termios->c_cflag & CSIZE) { 1049 case CS5: 1050 bits_per_char = 5; 1051 break; 1052 case CS6: 1053 bits_per_char = 6; 1054 break; 1055 case CS7: 1056 bits_per_char = 7; 1057 break; 1058 case CS8: 1059 default: 1060 bits_per_char = 8; 1061 break; 1062 } 1063 1064 /* stop bits */ 1065 if (termios->c_cflag & CSTOPB) 1066 stop_bit_len = TX_STOP_BIT_LEN_2; 1067 else 1068 stop_bit_len = TX_STOP_BIT_LEN_1; 1069 1070 /* flow control, clear the CTS_MASK bit if using flow control. */ 1071 if (termios->c_cflag & CRTSCTS) 1072 tx_trans_cfg &= ~UART_CTS_MASK; 1073 else 1074 tx_trans_cfg |= UART_CTS_MASK; 1075 1076 if (baud) 1077 uart_update_timeout(uport, termios->c_cflag, baud); 1078 1079 if (!uart_console(uport)) 1080 writel(port->loopback, 1081 uport->membase + SE_UART_LOOPBACK_CFG); 1082 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1083 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1084 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1085 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1086 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1087 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1088 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1089 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1090 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1091 out_restart_rx: 1092 qcom_geni_serial_start_rx(uport); 1093 } 1094 1095 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 1096 { 1097 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1098 } 1099 1100 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1101 static int __init qcom_geni_console_setup(struct console *co, char *options) 1102 { 1103 struct uart_port *uport; 1104 struct qcom_geni_serial_port *port; 1105 int baud = 9600; 1106 int bits = 8; 1107 int parity = 'n'; 1108 int flow = 'n'; 1109 int ret; 1110 1111 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1112 return -ENXIO; 1113 1114 port = get_port_from_line(co->index, true); 1115 if (IS_ERR(port)) { 1116 pr_err("Invalid line %d\n", co->index); 1117 return PTR_ERR(port); 1118 } 1119 1120 uport = &port->uport; 1121 1122 if (unlikely(!uport->membase)) 1123 return -ENXIO; 1124 1125 if (!port->setup) { 1126 ret = qcom_geni_serial_port_setup(uport); 1127 if (ret) 1128 return ret; 1129 } 1130 1131 if (options) 1132 uart_parse_options(options, &baud, &parity, &bits, &flow); 1133 1134 return uart_set_options(uport, co, baud, parity, bits, flow); 1135 } 1136 1137 static void qcom_geni_serial_earlycon_write(struct console *con, 1138 const char *s, unsigned int n) 1139 { 1140 struct earlycon_device *dev = con->data; 1141 1142 __qcom_geni_serial_console_write(&dev->port, s, n); 1143 } 1144 1145 #ifdef CONFIG_CONSOLE_POLL 1146 static int qcom_geni_serial_earlycon_read(struct console *con, 1147 char *s, unsigned int n) 1148 { 1149 struct earlycon_device *dev = con->data; 1150 struct uart_port *uport = &dev->port; 1151 int num_read = 0; 1152 int ch; 1153 1154 while (num_read < n) { 1155 ch = qcom_geni_serial_get_char(uport); 1156 if (ch == NO_POLL_CHAR) 1157 break; 1158 s[num_read++] = ch; 1159 } 1160 1161 return num_read; 1162 } 1163 1164 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1165 struct console *con) 1166 { 1167 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1168 con->read = qcom_geni_serial_earlycon_read; 1169 } 1170 #else 1171 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1172 struct console *con) { } 1173 #endif 1174 1175 static int qcom_geni_serial_earlycon_exit(struct console *con) 1176 { 1177 geni_remove_earlycon_icc_vote(); 1178 return 0; 1179 } 1180 1181 static struct qcom_geni_private_data earlycon_private_data; 1182 1183 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1184 const char *opt) 1185 { 1186 struct uart_port *uport = &dev->port; 1187 u32 tx_trans_cfg; 1188 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1189 u32 rx_trans_cfg = 0; 1190 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1191 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1192 u32 bits_per_char; 1193 struct geni_se se; 1194 1195 if (!uport->membase) 1196 return -EINVAL; 1197 1198 uport->private_data = &earlycon_private_data; 1199 1200 memset(&se, 0, sizeof(se)); 1201 se.base = uport->membase; 1202 if (geni_se_read_proto(&se) != GENI_SE_UART) 1203 return -ENXIO; 1204 /* 1205 * Ignore Flow control. 1206 * n = 8. 1207 */ 1208 tx_trans_cfg = UART_CTS_MASK; 1209 bits_per_char = BITS_PER_BYTE; 1210 1211 /* 1212 * Make an unconditional cancel on the main sequencer to reset 1213 * it else we could end up in data loss scenarios. 1214 */ 1215 qcom_geni_serial_poll_tx_done(uport); 1216 qcom_geni_serial_abort_rx(uport); 1217 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1218 false, true, true); 1219 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1220 geni_se_select_mode(&se, GENI_SE_FIFO); 1221 1222 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1223 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1224 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1225 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1226 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1227 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1228 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1229 1230 dev->con->write = qcom_geni_serial_earlycon_write; 1231 dev->con->exit = qcom_geni_serial_earlycon_exit; 1232 dev->con->setup = NULL; 1233 qcom_geni_serial_enable_early_read(&se, dev->con); 1234 1235 return 0; 1236 } 1237 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1238 qcom_geni_serial_earlycon_setup); 1239 1240 static int __init console_register(struct uart_driver *drv) 1241 { 1242 return uart_register_driver(drv); 1243 } 1244 1245 static void console_unregister(struct uart_driver *drv) 1246 { 1247 uart_unregister_driver(drv); 1248 } 1249 1250 static struct console cons_ops = { 1251 .name = "ttyMSM", 1252 .write = qcom_geni_serial_console_write, 1253 .device = uart_console_device, 1254 .setup = qcom_geni_console_setup, 1255 .flags = CON_PRINTBUFFER, 1256 .index = -1, 1257 .data = &qcom_geni_console_driver, 1258 }; 1259 1260 static struct uart_driver qcom_geni_console_driver = { 1261 .owner = THIS_MODULE, 1262 .driver_name = "qcom_geni_console", 1263 .dev_name = "ttyMSM", 1264 .nr = GENI_UART_CONS_PORTS, 1265 .cons = &cons_ops, 1266 }; 1267 #else 1268 static int console_register(struct uart_driver *drv) 1269 { 1270 return 0; 1271 } 1272 1273 static void console_unregister(struct uart_driver *drv) 1274 { 1275 } 1276 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1277 1278 static struct uart_driver qcom_geni_uart_driver = { 1279 .owner = THIS_MODULE, 1280 .driver_name = "qcom_geni_uart", 1281 .dev_name = "ttyHS", 1282 .nr = GENI_UART_PORTS, 1283 }; 1284 1285 static void qcom_geni_serial_pm(struct uart_port *uport, 1286 unsigned int new_state, unsigned int old_state) 1287 { 1288 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1289 1290 /* If we've never been called, treat it as off */ 1291 if (old_state == UART_PM_STATE_UNDEFINED) 1292 old_state = UART_PM_STATE_OFF; 1293 1294 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1295 geni_icc_enable(&port->se); 1296 geni_se_resources_on(&port->se); 1297 } else if (new_state == UART_PM_STATE_OFF && 1298 old_state == UART_PM_STATE_ON) { 1299 geni_se_resources_off(&port->se); 1300 geni_icc_disable(&port->se); 1301 } 1302 } 1303 1304 static const struct uart_ops qcom_geni_console_pops = { 1305 .tx_empty = qcom_geni_serial_tx_empty, 1306 .stop_tx = qcom_geni_serial_stop_tx, 1307 .start_tx = qcom_geni_serial_start_tx, 1308 .stop_rx = qcom_geni_serial_stop_rx, 1309 .set_termios = qcom_geni_serial_set_termios, 1310 .startup = qcom_geni_serial_startup, 1311 .request_port = qcom_geni_serial_request_port, 1312 .config_port = qcom_geni_serial_config_port, 1313 .shutdown = qcom_geni_serial_shutdown, 1314 .type = qcom_geni_serial_get_type, 1315 .set_mctrl = qcom_geni_serial_set_mctrl, 1316 .get_mctrl = qcom_geni_serial_get_mctrl, 1317 #ifdef CONFIG_CONSOLE_POLL 1318 .poll_get_char = qcom_geni_serial_get_char, 1319 .poll_put_char = qcom_geni_serial_poll_put_char, 1320 #endif 1321 .pm = qcom_geni_serial_pm, 1322 }; 1323 1324 static const struct uart_ops qcom_geni_uart_pops = { 1325 .tx_empty = qcom_geni_serial_tx_empty, 1326 .stop_tx = qcom_geni_serial_stop_tx, 1327 .start_tx = qcom_geni_serial_start_tx, 1328 .stop_rx = qcom_geni_serial_stop_rx, 1329 .set_termios = qcom_geni_serial_set_termios, 1330 .startup = qcom_geni_serial_startup, 1331 .request_port = qcom_geni_serial_request_port, 1332 .config_port = qcom_geni_serial_config_port, 1333 .shutdown = qcom_geni_serial_shutdown, 1334 .type = qcom_geni_serial_get_type, 1335 .set_mctrl = qcom_geni_serial_set_mctrl, 1336 .get_mctrl = qcom_geni_serial_get_mctrl, 1337 .pm = qcom_geni_serial_pm, 1338 }; 1339 1340 static int qcom_geni_serial_probe(struct platform_device *pdev) 1341 { 1342 int ret = 0; 1343 int line = -1; 1344 struct qcom_geni_serial_port *port; 1345 struct uart_port *uport; 1346 struct resource *res; 1347 int irq; 1348 bool console = false; 1349 struct uart_driver *drv; 1350 1351 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) 1352 console = true; 1353 1354 if (console) { 1355 drv = &qcom_geni_console_driver; 1356 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1357 } else { 1358 drv = &qcom_geni_uart_driver; 1359 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1360 } 1361 1362 port = get_port_from_line(line, console); 1363 if (IS_ERR(port)) { 1364 dev_err(&pdev->dev, "Invalid line %d\n", line); 1365 return PTR_ERR(port); 1366 } 1367 1368 uport = &port->uport; 1369 /* Don't allow 2 drivers to access the same port */ 1370 if (uport->private_data) 1371 return -ENODEV; 1372 1373 uport->dev = &pdev->dev; 1374 port->se.dev = &pdev->dev; 1375 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1376 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1377 if (IS_ERR(port->se.clk)) { 1378 ret = PTR_ERR(port->se.clk); 1379 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1380 return ret; 1381 } 1382 1383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1384 if (!res) 1385 return -EINVAL; 1386 uport->mapbase = res->start; 1387 1388 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1389 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1390 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1391 1392 if (!console) { 1393 port->rx_fifo = devm_kcalloc(uport->dev, 1394 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); 1395 if (!port->rx_fifo) 1396 return -ENOMEM; 1397 } 1398 1399 ret = geni_icc_get(&port->se, NULL); 1400 if (ret) 1401 return ret; 1402 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1403 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1404 1405 /* Set BW for register access */ 1406 ret = geni_icc_set_bw(&port->se); 1407 if (ret) 1408 return ret; 1409 1410 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1411 "qcom_geni_serial_%s%d", 1412 uart_console(uport) ? "console" : "uart", uport->line); 1413 if (!port->name) 1414 return -ENOMEM; 1415 1416 irq = platform_get_irq(pdev, 0); 1417 if (irq < 0) 1418 return irq; 1419 uport->irq = irq; 1420 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1421 1422 if (!console) 1423 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1424 1425 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1426 port->rx_tx_swap = true; 1427 1428 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1429 port->cts_rts_swap = true; 1430 1431 port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); 1432 if (IS_ERR(port->se.opp_table)) 1433 return PTR_ERR(port->se.opp_table); 1434 /* OPP table is optional */ 1435 ret = dev_pm_opp_of_add_table(&pdev->dev); 1436 if (!ret) { 1437 port->se.has_opp_table = true; 1438 } else if (ret != -ENODEV) { 1439 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1440 return ret; 1441 } 1442 1443 port->private_data.drv = drv; 1444 uport->private_data = &port->private_data; 1445 platform_set_drvdata(pdev, port); 1446 port->handle_rx = console ? handle_rx_console : handle_rx_uart; 1447 1448 ret = uart_add_one_port(drv, uport); 1449 if (ret) 1450 goto err; 1451 1452 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1453 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1454 IRQF_TRIGGER_HIGH, port->name, uport); 1455 if (ret) { 1456 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1457 uart_remove_one_port(drv, uport); 1458 goto err; 1459 } 1460 1461 /* 1462 * Set pm_runtime status as ACTIVE so that wakeup_irq gets 1463 * enabled/disabled from dev_pm_arm_wake_irq during system 1464 * suspend/resume respectively. 1465 */ 1466 pm_runtime_set_active(&pdev->dev); 1467 1468 if (port->wakeup_irq > 0) { 1469 device_init_wakeup(&pdev->dev, true); 1470 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1471 port->wakeup_irq); 1472 if (ret) { 1473 device_init_wakeup(&pdev->dev, false); 1474 uart_remove_one_port(drv, uport); 1475 goto err; 1476 } 1477 } 1478 1479 return 0; 1480 err: 1481 if (port->se.has_opp_table) 1482 dev_pm_opp_of_remove_table(&pdev->dev); 1483 dev_pm_opp_put_clkname(port->se.opp_table); 1484 return ret; 1485 } 1486 1487 static int qcom_geni_serial_remove(struct platform_device *pdev) 1488 { 1489 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1490 struct uart_driver *drv = port->private_data.drv; 1491 1492 if (port->se.has_opp_table) 1493 dev_pm_opp_of_remove_table(&pdev->dev); 1494 dev_pm_opp_put_clkname(port->se.opp_table); 1495 dev_pm_clear_wake_irq(&pdev->dev); 1496 device_init_wakeup(&pdev->dev, false); 1497 uart_remove_one_port(drv, &port->uport); 1498 1499 return 0; 1500 } 1501 1502 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev) 1503 { 1504 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1505 struct uart_port *uport = &port->uport; 1506 struct qcom_geni_private_data *private_data = uport->private_data; 1507 1508 /* 1509 * This is done so we can hit the lowest possible state in suspend 1510 * even with no_console_suspend 1511 */ 1512 if (uart_console(uport)) { 1513 geni_icc_set_tag(&port->se, 0x3); 1514 geni_icc_set_bw(&port->se); 1515 } 1516 return uart_suspend_port(private_data->drv, uport); 1517 } 1518 1519 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev) 1520 { 1521 int ret; 1522 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1523 struct uart_port *uport = &port->uport; 1524 struct qcom_geni_private_data *private_data = uport->private_data; 1525 1526 ret = uart_resume_port(private_data->drv, uport); 1527 if (uart_console(uport)) { 1528 geni_icc_set_tag(&port->se, 0x7); 1529 geni_icc_set_bw(&port->se); 1530 } 1531 return ret; 1532 } 1533 1534 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1535 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, 1536 qcom_geni_serial_sys_resume) 1537 }; 1538 1539 static const struct of_device_id qcom_geni_serial_match_table[] = { 1540 { .compatible = "qcom,geni-debug-uart", }, 1541 { .compatible = "qcom,geni-uart", }, 1542 {} 1543 }; 1544 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1545 1546 static struct platform_driver qcom_geni_serial_platform_driver = { 1547 .remove = qcom_geni_serial_remove, 1548 .probe = qcom_geni_serial_probe, 1549 .driver = { 1550 .name = "qcom_geni_serial", 1551 .of_match_table = qcom_geni_serial_match_table, 1552 .pm = &qcom_geni_serial_pm_ops, 1553 }, 1554 }; 1555 1556 static int __init qcom_geni_serial_init(void) 1557 { 1558 int ret; 1559 1560 ret = console_register(&qcom_geni_console_driver); 1561 if (ret) 1562 return ret; 1563 1564 ret = uart_register_driver(&qcom_geni_uart_driver); 1565 if (ret) { 1566 console_unregister(&qcom_geni_console_driver); 1567 return ret; 1568 } 1569 1570 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1571 if (ret) { 1572 console_unregister(&qcom_geni_console_driver); 1573 uart_unregister_driver(&qcom_geni_uart_driver); 1574 } 1575 return ret; 1576 } 1577 module_init(qcom_geni_serial_init); 1578 1579 static void __exit qcom_geni_serial_exit(void) 1580 { 1581 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1582 console_unregister(&qcom_geni_console_driver); 1583 uart_unregister_driver(&qcom_geni_uart_driver); 1584 } 1585 module_exit(qcom_geni_serial_exit); 1586 1587 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1588 MODULE_LICENSE("GPL v2"); 1589