1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/soc/qcom/geni-se.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <dt-bindings/interconnect/qcom,icc.h> 26 27 /* UART specific GENI registers */ 28 #define SE_UART_LOOPBACK_CFG 0x22c 29 #define SE_UART_IO_MACRO_CTRL 0x240 30 #define SE_UART_TX_TRANS_CFG 0x25c 31 #define SE_UART_TX_WORD_LEN 0x268 32 #define SE_UART_TX_STOP_BIT_LEN 0x26c 33 #define SE_UART_TX_TRANS_LEN 0x270 34 #define SE_UART_RX_TRANS_CFG 0x280 35 #define SE_UART_RX_WORD_LEN 0x28c 36 #define SE_UART_RX_STALE_CNT 0x294 37 #define SE_UART_TX_PARITY_CFG 0x2a4 38 #define SE_UART_RX_PARITY_CFG 0x2a8 39 #define SE_UART_MANUAL_RFR 0x2ac 40 41 /* SE_UART_TRANS_CFG */ 42 #define UART_TX_PAR_EN BIT(0) 43 #define UART_CTS_MASK BIT(1) 44 45 /* SE_UART_TX_STOP_BIT_LEN */ 46 #define TX_STOP_BIT_LEN_1 0 47 #define TX_STOP_BIT_LEN_2 2 48 49 /* SE_UART_RX_TRANS_CFG */ 50 #define UART_RX_PAR_EN BIT(3) 51 52 /* SE_UART_RX_WORD_LEN */ 53 #define RX_WORD_LEN_MASK GENMASK(9, 0) 54 55 /* SE_UART_RX_STALE_CNT */ 56 #define RX_STALE_CNT GENMASK(23, 0) 57 58 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 59 #define PAR_CALC_EN BIT(0) 60 #define PAR_EVEN 0x00 61 #define PAR_ODD 0x01 62 #define PAR_SPACE 0x10 63 64 /* SE_UART_MANUAL_RFR register fields */ 65 #define UART_MANUAL_RFR_EN BIT(31) 66 #define UART_RFR_NOT_READY BIT(1) 67 #define UART_RFR_READY BIT(0) 68 69 /* UART M_CMD OP codes */ 70 #define UART_START_TX 0x1 71 /* UART S_CMD OP codes */ 72 #define UART_START_READ 0x1 73 #define UART_PARAM 0x1 74 #define UART_PARAM_RFR_OPEN BIT(7) 75 76 #define UART_OVERSAMPLING 32 77 #define STALE_TIMEOUT 16 78 #define DEFAULT_BITS_PER_CHAR 10 79 #define GENI_UART_CONS_PORTS 1 80 #define GENI_UART_PORTS 3 81 #define DEF_FIFO_DEPTH_WORDS 16 82 #define DEF_TX_WM 2 83 #define DEF_FIFO_WIDTH_BITS 32 84 #define UART_RX_WM 2 85 86 /* SE_UART_LOOPBACK_CFG */ 87 #define RX_TX_SORTED BIT(0) 88 #define CTS_RTS_SORTED BIT(1) 89 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 90 91 /* UART pin swap value */ 92 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 93 #define IO_MACRO_IO0_SEL 0x3 94 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 95 #define IO_MACRO_IO2_IO3_SWAP 0x4640 96 97 /* We always configure 4 bytes per FIFO word */ 98 #define BYTES_PER_FIFO_WORD 4U 99 100 #define DMA_RX_BUF_SIZE 2048 101 102 struct qcom_geni_device_data { 103 bool console; 104 enum geni_se_xfer_mode mode; 105 }; 106 107 struct qcom_geni_private_data { 108 /* NOTE: earlycon port will have NULL here */ 109 struct uart_driver *drv; 110 111 u32 poll_cached_bytes; 112 unsigned int poll_cached_bytes_cnt; 113 114 u32 write_cached_bytes; 115 unsigned int write_cached_bytes_cnt; 116 }; 117 118 struct qcom_geni_serial_port { 119 struct uart_port uport; 120 struct geni_se se; 121 const char *name; 122 u32 tx_fifo_depth; 123 u32 tx_fifo_width; 124 u32 rx_fifo_depth; 125 dma_addr_t tx_dma_addr; 126 dma_addr_t rx_dma_addr; 127 bool setup; 128 unsigned int baud; 129 void *rx_buf; 130 u32 loopback; 131 bool brk; 132 133 unsigned int tx_remaining; 134 int wakeup_irq; 135 bool rx_tx_swap; 136 bool cts_rts_swap; 137 138 struct qcom_geni_private_data private_data; 139 const struct qcom_geni_device_data *dev_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 148 { 149 return container_of(uport, struct qcom_geni_serial_port, uport); 150 } 151 152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 153 [0] = { 154 .uport = { 155 .iotype = UPIO_MEM, 156 .ops = &qcom_geni_uart_pops, 157 .flags = UPF_BOOT_AUTOCONF, 158 .line = 0, 159 }, 160 }, 161 [1] = { 162 .uport = { 163 .iotype = UPIO_MEM, 164 .ops = &qcom_geni_uart_pops, 165 .flags = UPF_BOOT_AUTOCONF, 166 .line = 1, 167 }, 168 }, 169 [2] = { 170 .uport = { 171 .iotype = UPIO_MEM, 172 .ops = &qcom_geni_uart_pops, 173 .flags = UPF_BOOT_AUTOCONF, 174 .line = 2, 175 }, 176 }, 177 }; 178 179 static struct qcom_geni_serial_port qcom_geni_console_port = { 180 .uport = { 181 .iotype = UPIO_MEM, 182 .ops = &qcom_geni_console_pops, 183 .flags = UPF_BOOT_AUTOCONF, 184 .line = 0, 185 }, 186 }; 187 188 static int qcom_geni_serial_request_port(struct uart_port *uport) 189 { 190 struct platform_device *pdev = to_platform_device(uport->dev); 191 struct qcom_geni_serial_port *port = to_dev_port(uport); 192 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); 194 if (IS_ERR(uport->membase)) 195 return PTR_ERR(uport->membase); 196 port->se.base = uport->membase; 197 return 0; 198 } 199 200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 201 { 202 if (cfg_flags & UART_CONFIG_TYPE) { 203 uport->type = PORT_MSM; 204 qcom_geni_serial_request_port(uport); 205 } 206 } 207 208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 209 { 210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 211 u32 geni_ios; 212 213 if (uart_console(uport)) { 214 mctrl |= TIOCM_CTS; 215 } else { 216 geni_ios = readl(uport->membase + SE_GENI_IOS); 217 if (!(geni_ios & IO2_DATA_IN)) 218 mctrl |= TIOCM_CTS; 219 } 220 221 return mctrl; 222 } 223 224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 225 unsigned int mctrl) 226 { 227 u32 uart_manual_rfr = 0; 228 struct qcom_geni_serial_port *port = to_dev_port(uport); 229 230 if (uart_console(uport)) 231 return; 232 233 if (mctrl & TIOCM_LOOP) 234 port->loopback = RX_TX_CTS_RTS_SORTED; 235 236 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 239 } 240 241 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 242 { 243 return "MSM"; 244 } 245 246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 247 { 248 struct qcom_geni_serial_port *port; 249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 250 251 if (line < 0 || line >= nr_ports) 252 return ERR_PTR(-ENXIO); 253 254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 255 return port; 256 } 257 258 static bool qcom_geni_serial_main_active(struct uart_port *uport) 259 { 260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 261 } 262 263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 264 { 265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 266 } 267 268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 269 int offset, int field, bool set) 270 { 271 u32 reg; 272 struct qcom_geni_serial_port *port; 273 unsigned int baud; 274 unsigned int fifo_bits; 275 unsigned long timeout_us = 20000; 276 struct qcom_geni_private_data *private_data = uport->private_data; 277 278 if (private_data->drv) { 279 port = to_dev_port(uport); 280 baud = port->baud; 281 if (!baud) 282 baud = 115200; 283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 284 /* 285 * Total polling iterations based on FIFO worth of bytes to be 286 * sent at current baud. Add a little fluff to the wait. 287 */ 288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 289 } 290 291 /* 292 * Use custom implementation instead of readl_poll_atomic since ktimer 293 * is not ready at the time of early console. 294 */ 295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 296 while (timeout_us) { 297 reg = readl(uport->membase + offset); 298 if ((bool)(reg & field) == set) 299 return true; 300 udelay(10); 301 timeout_us -= 10; 302 } 303 return false; 304 } 305 306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 307 { 308 u32 m_cmd; 309 310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 311 m_cmd = UART_START_TX << M_OPCODE_SHFT; 312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 313 } 314 315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 316 { 317 int done; 318 u32 irq_clear = M_CMD_DONE_EN; 319 320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 321 M_CMD_DONE_EN, true); 322 if (!done) { 323 writel(M_GENI_CMD_ABORT, uport->membase + 324 SE_GENI_M_CMD_CTRL_REG); 325 irq_clear |= M_CMD_ABORT_EN; 326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 327 M_CMD_ABORT_EN, true); 328 } 329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 330 } 331 332 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 333 { 334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 335 336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 338 S_GENI_CMD_ABORT, false); 339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 341 } 342 343 #ifdef CONFIG_CONSOLE_POLL 344 static int qcom_geni_serial_get_char(struct uart_port *uport) 345 { 346 struct qcom_geni_private_data *private_data = uport->private_data; 347 u32 status; 348 u32 word_cnt; 349 int ret; 350 351 if (!private_data->poll_cached_bytes_cnt) { 352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 354 355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 357 358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 359 word_cnt = status & RX_FIFO_WC_MSK; 360 if (!word_cnt) 361 return NO_POLL_CHAR; 362 363 if (word_cnt == 1 && (status & RX_LAST)) 364 /* 365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 366 * treated as if it was BYTES_PER_FIFO_WORD. 367 */ 368 private_data->poll_cached_bytes_cnt = 369 (status & RX_LAST_BYTE_VALID_MSK) >> 370 RX_LAST_BYTE_VALID_SHFT; 371 372 if (private_data->poll_cached_bytes_cnt == 0) 373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 374 375 private_data->poll_cached_bytes = 376 readl(uport->membase + SE_GENI_RX_FIFOn); 377 } 378 379 private_data->poll_cached_bytes_cnt--; 380 ret = private_data->poll_cached_bytes & 0xff; 381 private_data->poll_cached_bytes >>= 8; 382 383 return ret; 384 } 385 386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 387 unsigned char c) 388 { 389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 390 qcom_geni_serial_setup_tx(uport, 1); 391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 392 M_TX_FIFO_WATERMARK_EN, true)); 393 writel(c, uport->membase + SE_GENI_TX_FIFOn); 394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 395 qcom_geni_serial_poll_tx_done(uport); 396 } 397 #endif 398 399 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 400 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 401 { 402 struct qcom_geni_private_data *private_data = uport->private_data; 403 404 private_data->write_cached_bytes = 405 (private_data->write_cached_bytes >> 8) | (ch << 24); 406 private_data->write_cached_bytes_cnt++; 407 408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 409 writel(private_data->write_cached_bytes, 410 uport->membase + SE_GENI_TX_FIFOn); 411 private_data->write_cached_bytes_cnt = 0; 412 } 413 } 414 415 static void 416 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 417 unsigned int count) 418 { 419 struct qcom_geni_private_data *private_data = uport->private_data; 420 421 int i; 422 u32 bytes_to_send = count; 423 424 for (i = 0; i < count; i++) { 425 /* 426 * uart_console_write() adds a carriage return for each newline. 427 * Account for additional bytes to be written. 428 */ 429 if (s[i] == '\n') 430 bytes_to_send++; 431 } 432 433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 434 qcom_geni_serial_setup_tx(uport, bytes_to_send); 435 for (i = 0; i < count; ) { 436 size_t chars_to_write = 0; 437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 438 439 /* 440 * If the WM bit never set, then the Tx state machine is not 441 * in a valid state, so break, cancel/abort any existing 442 * command. Unfortunately the current data being written is 443 * lost. 444 */ 445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 446 M_TX_FIFO_WATERMARK_EN, true)) 447 break; 448 chars_to_write = min_t(size_t, count - i, avail / 2); 449 uart_console_write(uport, s + i, chars_to_write, 450 qcom_geni_serial_wr_char); 451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 452 SE_GENI_M_IRQ_CLEAR); 453 i += chars_to_write; 454 } 455 456 if (private_data->write_cached_bytes_cnt) { 457 private_data->write_cached_bytes >>= BITS_PER_BYTE * 458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 459 writel(private_data->write_cached_bytes, 460 uport->membase + SE_GENI_TX_FIFOn); 461 private_data->write_cached_bytes_cnt = 0; 462 } 463 464 qcom_geni_serial_poll_tx_done(uport); 465 } 466 467 static void qcom_geni_serial_console_write(struct console *co, const char *s, 468 unsigned int count) 469 { 470 struct uart_port *uport; 471 struct qcom_geni_serial_port *port; 472 bool locked = true; 473 unsigned long flags; 474 u32 geni_status; 475 u32 irq_en; 476 477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 478 479 port = get_port_from_line(co->index, true); 480 if (IS_ERR(port)) 481 return; 482 483 uport = &port->uport; 484 if (oops_in_progress) 485 locked = spin_trylock_irqsave(&uport->lock, flags); 486 else 487 spin_lock_irqsave(&uport->lock, flags); 488 489 geni_status = readl(uport->membase + SE_GENI_STATUS); 490 491 /* Cancel the current write to log the fault */ 492 if (!locked) { 493 geni_se_cancel_m_cmd(&port->se); 494 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 495 M_CMD_CANCEL_EN, true)) { 496 geni_se_abort_m_cmd(&port->se); 497 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 498 M_CMD_ABORT_EN, true); 499 writel(M_CMD_ABORT_EN, uport->membase + 500 SE_GENI_M_IRQ_CLEAR); 501 } 502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 504 /* 505 * It seems we can't interrupt existing transfers if all data 506 * has been sent, in which case we need to look for done first. 507 */ 508 qcom_geni_serial_poll_tx_done(uport); 509 510 if (!uart_circ_empty(&uport->state->xmit)) { 511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 512 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 513 uport->membase + SE_GENI_M_IRQ_EN); 514 } 515 } 516 517 __qcom_geni_serial_console_write(uport, s, count); 518 519 if (port->tx_remaining) 520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 521 522 if (locked) 523 spin_unlock_irqrestore(&uport->lock, flags); 524 } 525 526 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 527 { 528 u32 i; 529 unsigned char buf[sizeof(u32)]; 530 struct tty_port *tport; 531 struct qcom_geni_serial_port *port = to_dev_port(uport); 532 533 tport = &uport->state->port; 534 for (i = 0; i < bytes; ) { 535 int c; 536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 537 538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 539 i += chunk; 540 if (drop) 541 continue; 542 543 for (c = 0; c < chunk; c++) { 544 int sysrq; 545 546 uport->icount.rx++; 547 if (port->brk && buf[c] == 0) { 548 port->brk = false; 549 if (uart_handle_break(uport)) 550 continue; 551 } 552 553 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 554 555 if (!sysrq) 556 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 557 } 558 } 559 if (!drop) 560 tty_flip_buffer_push(tport); 561 } 562 #else 563 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 564 { 565 566 } 567 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 568 569 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 570 { 571 struct qcom_geni_serial_port *port = to_dev_port(uport); 572 struct tty_port *tport = &uport->state->port; 573 int ret; 574 575 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 576 if (ret != bytes) { 577 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 578 __func__, ret, bytes); 579 WARN_ON_ONCE(1); 580 } 581 uport->icount.rx += ret; 582 tty_flip_buffer_push(tport); 583 } 584 585 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 586 { 587 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 588 } 589 590 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 591 { 592 struct qcom_geni_serial_port *port = to_dev_port(uport); 593 bool done; 594 u32 m_irq_en; 595 596 if (!qcom_geni_serial_main_active(uport)) 597 return; 598 599 if (port->tx_dma_addr) { 600 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 601 port->tx_remaining); 602 port->tx_dma_addr = 0; 603 port->tx_remaining = 0; 604 } 605 606 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 607 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); 608 geni_se_cancel_m_cmd(&port->se); 609 610 done = qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 611 S_CMD_CANCEL_EN, true); 612 if (!done) { 613 geni_se_abort_m_cmd(&port->se); 614 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 615 M_CMD_ABORT_EN, true); 616 if (!done) 617 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 618 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 619 } 620 621 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 622 } 623 624 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 625 { 626 struct qcom_geni_serial_port *port = to_dev_port(uport); 627 struct circ_buf *xmit = &uport->state->xmit; 628 unsigned int xmit_size; 629 int ret; 630 631 if (port->tx_dma_addr) 632 return; 633 634 if (uart_circ_empty(xmit)) 635 return; 636 637 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 638 639 qcom_geni_serial_setup_tx(uport, xmit_size); 640 641 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], 642 xmit_size, &port->tx_dma_addr); 643 if (ret) { 644 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 645 qcom_geni_serial_stop_tx_dma(uport); 646 return; 647 } 648 649 port->tx_remaining = xmit_size; 650 } 651 652 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 653 { 654 u32 irq_en; 655 656 if (qcom_geni_serial_main_active(uport) || 657 !qcom_geni_serial_tx_empty(uport)) 658 return; 659 660 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 661 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 662 663 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 664 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 665 } 666 667 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 668 { 669 u32 irq_en; 670 struct qcom_geni_serial_port *port = to_dev_port(uport); 671 672 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 673 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 674 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 675 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 676 /* Possible stop tx is called multiple times. */ 677 if (!qcom_geni_serial_main_active(uport)) 678 return; 679 680 geni_se_cancel_m_cmd(&port->se); 681 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 682 M_CMD_CANCEL_EN, true)) { 683 geni_se_abort_m_cmd(&port->se); 684 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 685 M_CMD_ABORT_EN, true); 686 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 687 } 688 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 689 } 690 691 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 692 { 693 u32 status; 694 u32 word_cnt; 695 u32 last_word_byte_cnt; 696 u32 last_word_partial; 697 u32 total_bytes; 698 699 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 700 word_cnt = status & RX_FIFO_WC_MSK; 701 last_word_partial = status & RX_LAST; 702 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 703 RX_LAST_BYTE_VALID_SHFT; 704 705 if (!word_cnt) 706 return; 707 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 708 if (last_word_partial && last_word_byte_cnt) 709 total_bytes += last_word_byte_cnt; 710 else 711 total_bytes += BYTES_PER_FIFO_WORD; 712 handle_rx_console(uport, total_bytes, drop); 713 } 714 715 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 716 { 717 u32 irq_en; 718 struct qcom_geni_serial_port *port = to_dev_port(uport); 719 u32 s_irq_status; 720 721 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 722 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 723 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 724 725 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 726 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 727 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 728 729 if (!qcom_geni_serial_secondary_active(uport)) 730 return; 731 732 geni_se_cancel_s_cmd(&port->se); 733 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 734 S_CMD_CANCEL_EN, true); 735 /* 736 * If timeout occurs secondary engine remains active 737 * and Abort sequence is executed. 738 */ 739 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 740 /* Flush the Rx buffer */ 741 if (s_irq_status & S_RX_FIFO_LAST_EN) 742 qcom_geni_serial_handle_rx_fifo(uport, true); 743 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 744 745 if (qcom_geni_serial_secondary_active(uport)) 746 qcom_geni_serial_abort_rx(uport); 747 } 748 749 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 750 { 751 u32 irq_en; 752 struct qcom_geni_serial_port *port = to_dev_port(uport); 753 754 if (qcom_geni_serial_secondary_active(uport)) 755 qcom_geni_serial_stop_rx_fifo(uport); 756 757 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 758 759 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 760 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 761 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 762 763 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 764 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 765 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 766 } 767 768 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 769 { 770 struct qcom_geni_serial_port *port = to_dev_port(uport); 771 772 if (!qcom_geni_serial_secondary_active(uport)) 773 return; 774 775 geni_se_cancel_s_cmd(&port->se); 776 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 777 S_CMD_CANCEL_EN, true); 778 779 if (qcom_geni_serial_secondary_active(uport)) 780 qcom_geni_serial_abort_rx(uport); 781 782 if (port->rx_dma_addr) { 783 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 784 DMA_RX_BUF_SIZE); 785 port->rx_dma_addr = 0; 786 } 787 } 788 789 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 790 { 791 struct qcom_geni_serial_port *port = to_dev_port(uport); 792 int ret; 793 794 if (qcom_geni_serial_secondary_active(uport)) 795 qcom_geni_serial_stop_rx_dma(uport); 796 797 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 798 799 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 800 DMA_RX_BUF_SIZE, 801 &port->rx_dma_addr); 802 if (ret) { 803 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 804 qcom_geni_serial_stop_rx_dma(uport); 805 } 806 } 807 808 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 809 { 810 struct qcom_geni_serial_port *port = to_dev_port(uport); 811 u32 rx_in; 812 int ret; 813 814 if (!qcom_geni_serial_secondary_active(uport)) 815 return; 816 817 if (!port->rx_dma_addr) 818 return; 819 820 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 821 port->rx_dma_addr = 0; 822 823 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 824 if (!rx_in) { 825 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 826 return; 827 } 828 829 if (!drop) 830 handle_rx_uart(uport, rx_in, drop); 831 832 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 833 DMA_RX_BUF_SIZE, 834 &port->rx_dma_addr); 835 if (ret) { 836 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 837 qcom_geni_serial_stop_rx_dma(uport); 838 } 839 } 840 841 static void qcom_geni_serial_start_rx(struct uart_port *uport) 842 { 843 uport->ops->start_rx(uport); 844 } 845 846 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 847 { 848 uport->ops->stop_rx(uport); 849 } 850 851 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 852 { 853 uport->ops->stop_tx(uport); 854 } 855 856 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 857 unsigned int remaining) 858 { 859 struct qcom_geni_serial_port *port = to_dev_port(uport); 860 struct circ_buf *xmit = &uport->state->xmit; 861 unsigned int tx_bytes; 862 u8 buf[BYTES_PER_FIFO_WORD]; 863 864 while (remaining) { 865 memset(buf, 0, sizeof(buf)); 866 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 867 868 memcpy(buf, &xmit->buf[xmit->tail], tx_bytes); 869 uart_xmit_advance(uport, tx_bytes); 870 871 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 872 873 remaining -= tx_bytes; 874 port->tx_remaining -= tx_bytes; 875 } 876 } 877 878 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 879 bool done, bool active) 880 { 881 struct qcom_geni_serial_port *port = to_dev_port(uport); 882 struct circ_buf *xmit = &uport->state->xmit; 883 size_t avail; 884 size_t pending; 885 u32 status; 886 u32 irq_en; 887 unsigned int chunk; 888 889 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 890 891 /* Complete the current tx command before taking newly added data */ 892 if (active) 893 pending = port->tx_remaining; 894 else 895 pending = uart_circ_chars_pending(xmit); 896 897 /* All data has been transmitted and acknowledged as received */ 898 if (!pending && !status && done) { 899 qcom_geni_serial_stop_tx_fifo(uport); 900 goto out_write_wakeup; 901 } 902 903 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 904 avail *= BYTES_PER_FIFO_WORD; 905 906 chunk = min(avail, pending); 907 if (!chunk) 908 goto out_write_wakeup; 909 910 if (!port->tx_remaining) { 911 qcom_geni_serial_setup_tx(uport, pending); 912 port->tx_remaining = pending; 913 914 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 915 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 916 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 917 uport->membase + SE_GENI_M_IRQ_EN); 918 } 919 920 qcom_geni_serial_send_chunk_fifo(uport, chunk); 921 922 /* 923 * The tx fifo watermark is level triggered and latched. Though we had 924 * cleared it in qcom_geni_serial_isr it will have already reasserted 925 * so we must clear it again here after our writes. 926 */ 927 writel(M_TX_FIFO_WATERMARK_EN, 928 uport->membase + SE_GENI_M_IRQ_CLEAR); 929 930 out_write_wakeup: 931 if (!port->tx_remaining) { 932 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 933 if (irq_en & M_TX_FIFO_WATERMARK_EN) 934 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 935 uport->membase + SE_GENI_M_IRQ_EN); 936 } 937 938 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 939 uart_write_wakeup(uport); 940 } 941 942 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 943 { 944 struct qcom_geni_serial_port *port = to_dev_port(uport); 945 struct circ_buf *xmit = &uport->state->xmit; 946 947 uart_xmit_advance(uport, port->tx_remaining); 948 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 949 port->tx_dma_addr = 0; 950 port->tx_remaining = 0; 951 952 if (!uart_circ_empty(xmit)) 953 qcom_geni_serial_start_tx_dma(uport); 954 955 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 956 uart_write_wakeup(uport); 957 } 958 959 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 960 { 961 u32 m_irq_en; 962 u32 m_irq_status; 963 u32 s_irq_status; 964 u32 geni_status; 965 u32 dma; 966 u32 dma_tx_status; 967 u32 dma_rx_status; 968 struct uart_port *uport = dev; 969 bool drop_rx = false; 970 struct tty_port *tport = &uport->state->port; 971 struct qcom_geni_serial_port *port = to_dev_port(uport); 972 973 if (uport->suspended) 974 return IRQ_NONE; 975 976 spin_lock(&uport->lock); 977 978 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 979 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 980 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 981 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 982 geni_status = readl(uport->membase + SE_GENI_STATUS); 983 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 984 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 985 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 986 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 987 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 988 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 989 990 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 991 goto out_unlock; 992 993 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 994 uport->icount.overrun++; 995 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 996 } 997 998 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 999 if (s_irq_status & S_GP_IRQ_0_EN) 1000 uport->icount.parity++; 1001 drop_rx = true; 1002 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1003 uport->icount.brk++; 1004 port->brk = true; 1005 } 1006 1007 if (dma) { 1008 if (dma_tx_status & TX_DMA_DONE) 1009 qcom_geni_serial_handle_tx_dma(uport); 1010 1011 if (dma_rx_status) { 1012 if (dma_rx_status & RX_RESET_DONE) 1013 goto out_unlock; 1014 1015 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1016 uport->icount.parity++; 1017 drop_rx = true; 1018 } 1019 1020 if (dma_rx_status & RX_DMA_BREAK) 1021 uport->icount.brk++; 1022 1023 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1024 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1025 } 1026 } else { 1027 if (m_irq_status & m_irq_en & 1028 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1029 qcom_geni_serial_handle_tx_fifo(uport, 1030 m_irq_status & M_CMD_DONE_EN, 1031 geni_status & M_GENI_CMD_ACTIVE); 1032 1033 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1034 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1035 } 1036 1037 out_unlock: 1038 uart_unlock_and_check_sysrq(uport); 1039 1040 return IRQ_HANDLED; 1041 } 1042 1043 static int setup_fifos(struct qcom_geni_serial_port *port) 1044 { 1045 struct uart_port *uport; 1046 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1047 1048 uport = &port->uport; 1049 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1050 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1051 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1052 uport->fifosize = 1053 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1054 1055 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1056 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1057 port->rx_fifo_depth * sizeof(u32), 1058 GFP_KERNEL); 1059 if (!port->rx_buf) 1060 return -ENOMEM; 1061 } 1062 1063 return 0; 1064 } 1065 1066 1067 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1068 { 1069 disable_irq(uport->irq); 1070 1071 if (uart_console(uport)) 1072 return; 1073 1074 qcom_geni_serial_stop_tx(uport); 1075 qcom_geni_serial_stop_rx(uport); 1076 } 1077 1078 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1079 { 1080 struct qcom_geni_serial_port *port = to_dev_port(uport); 1081 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1082 u32 proto; 1083 u32 pin_swap; 1084 int ret; 1085 1086 proto = geni_se_read_proto(&port->se); 1087 if (proto != GENI_SE_UART) { 1088 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1089 return -ENXIO; 1090 } 1091 1092 qcom_geni_serial_stop_rx(uport); 1093 1094 ret = setup_fifos(port); 1095 if (ret) 1096 return ret; 1097 1098 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1099 1100 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1101 if (port->rx_tx_swap) { 1102 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1103 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1104 } 1105 if (port->cts_rts_swap) { 1106 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1107 pin_swap |= IO_MACRO_IO0_SEL; 1108 } 1109 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1110 if (port->rx_tx_swap || port->cts_rts_swap) 1111 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1112 1113 /* 1114 * Make an unconditional cancel on the main sequencer to reset 1115 * it else we could end up in data loss scenarios. 1116 */ 1117 if (uart_console(uport)) 1118 qcom_geni_serial_poll_tx_done(uport); 1119 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1120 false, true, true); 1121 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1122 geni_se_select_mode(&port->se, port->dev_data->mode); 1123 qcom_geni_serial_start_rx(uport); 1124 port->setup = true; 1125 1126 return 0; 1127 } 1128 1129 static int qcom_geni_serial_startup(struct uart_port *uport) 1130 { 1131 int ret; 1132 struct qcom_geni_serial_port *port = to_dev_port(uport); 1133 1134 if (!port->setup) { 1135 ret = qcom_geni_serial_port_setup(uport); 1136 if (ret) 1137 return ret; 1138 } 1139 enable_irq(uport->irq); 1140 1141 return 0; 1142 } 1143 1144 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1145 unsigned int *clk_div, unsigned int percent_tol) 1146 { 1147 unsigned long freq; 1148 unsigned long div, maxdiv; 1149 u64 mult; 1150 unsigned long offset, abs_tol, achieved; 1151 1152 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1153 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1154 div = 1; 1155 while (div <= maxdiv) { 1156 mult = (u64)div * desired_clk; 1157 if (mult != (unsigned long)mult) 1158 break; 1159 1160 offset = div * abs_tol; 1161 freq = clk_round_rate(clk, mult - offset); 1162 1163 /* Can only get lower if we're done */ 1164 if (freq < mult - offset) 1165 break; 1166 1167 /* 1168 * Re-calculate div in case rounding skipped rates but we 1169 * ended up at a good one, then check for a match. 1170 */ 1171 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1172 achieved = DIV_ROUND_CLOSEST(freq, div); 1173 if (achieved <= desired_clk + abs_tol && 1174 achieved >= desired_clk - abs_tol) { 1175 *clk_div = div; 1176 return freq; 1177 } 1178 1179 div = DIV_ROUND_UP(freq, desired_clk); 1180 } 1181 1182 return 0; 1183 } 1184 1185 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1186 unsigned int sampling_rate, unsigned int *clk_div) 1187 { 1188 unsigned long ser_clk; 1189 unsigned long desired_clk; 1190 1191 desired_clk = baud * sampling_rate; 1192 if (!desired_clk) 1193 return 0; 1194 1195 /* 1196 * try to find a clock rate within 2% tolerance, then within 5% 1197 */ 1198 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1199 if (!ser_clk) 1200 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1201 1202 return ser_clk; 1203 } 1204 1205 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1206 struct ktermios *termios, 1207 const struct ktermios *old) 1208 { 1209 unsigned int baud; 1210 u32 bits_per_char; 1211 u32 tx_trans_cfg; 1212 u32 tx_parity_cfg; 1213 u32 rx_trans_cfg; 1214 u32 rx_parity_cfg; 1215 u32 stop_bit_len; 1216 unsigned int clk_div; 1217 u32 ser_clk_cfg; 1218 struct qcom_geni_serial_port *port = to_dev_port(uport); 1219 unsigned long clk_rate; 1220 u32 ver, sampling_rate; 1221 unsigned int avg_bw_core; 1222 1223 qcom_geni_serial_stop_rx(uport); 1224 /* baud rate */ 1225 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1226 port->baud = baud; 1227 1228 sampling_rate = UART_OVERSAMPLING; 1229 /* Sampling rate is halved for IP versions >= 2.5 */ 1230 ver = geni_se_get_qup_hw_version(&port->se); 1231 if (ver >= QUP_SE_VERSION_2_5) 1232 sampling_rate /= 2; 1233 1234 clk_rate = get_clk_div_rate(port->se.clk, baud, 1235 sampling_rate, &clk_div); 1236 if (!clk_rate) { 1237 dev_err(port->se.dev, 1238 "Couldn't find suitable clock rate for %u\n", 1239 baud * sampling_rate); 1240 goto out_restart_rx; 1241 } 1242 1243 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", 1244 baud * sampling_rate, clk_rate, clk_div); 1245 1246 uport->uartclk = clk_rate; 1247 dev_pm_opp_set_rate(uport->dev, clk_rate); 1248 ser_clk_cfg = SER_CLK_EN; 1249 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1250 1251 /* 1252 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1253 * only. 1254 */ 1255 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1256 : GENI_DEFAULT_BW; 1257 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1258 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1259 geni_icc_set_bw(&port->se); 1260 1261 /* parity */ 1262 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1263 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1264 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1265 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1266 if (termios->c_cflag & PARENB) { 1267 tx_trans_cfg |= UART_TX_PAR_EN; 1268 rx_trans_cfg |= UART_RX_PAR_EN; 1269 tx_parity_cfg |= PAR_CALC_EN; 1270 rx_parity_cfg |= PAR_CALC_EN; 1271 if (termios->c_cflag & PARODD) { 1272 tx_parity_cfg |= PAR_ODD; 1273 rx_parity_cfg |= PAR_ODD; 1274 } else if (termios->c_cflag & CMSPAR) { 1275 tx_parity_cfg |= PAR_SPACE; 1276 rx_parity_cfg |= PAR_SPACE; 1277 } else { 1278 tx_parity_cfg |= PAR_EVEN; 1279 rx_parity_cfg |= PAR_EVEN; 1280 } 1281 } else { 1282 tx_trans_cfg &= ~UART_TX_PAR_EN; 1283 rx_trans_cfg &= ~UART_RX_PAR_EN; 1284 tx_parity_cfg &= ~PAR_CALC_EN; 1285 rx_parity_cfg &= ~PAR_CALC_EN; 1286 } 1287 1288 /* bits per char */ 1289 bits_per_char = tty_get_char_size(termios->c_cflag); 1290 1291 /* stop bits */ 1292 if (termios->c_cflag & CSTOPB) 1293 stop_bit_len = TX_STOP_BIT_LEN_2; 1294 else 1295 stop_bit_len = TX_STOP_BIT_LEN_1; 1296 1297 /* flow control, clear the CTS_MASK bit if using flow control. */ 1298 if (termios->c_cflag & CRTSCTS) 1299 tx_trans_cfg &= ~UART_CTS_MASK; 1300 else 1301 tx_trans_cfg |= UART_CTS_MASK; 1302 1303 if (baud) 1304 uart_update_timeout(uport, termios->c_cflag, baud); 1305 1306 if (!uart_console(uport)) 1307 writel(port->loopback, 1308 uport->membase + SE_UART_LOOPBACK_CFG); 1309 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1310 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1311 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1312 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1313 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1314 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1315 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1316 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1317 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1318 out_restart_rx: 1319 qcom_geni_serial_start_rx(uport); 1320 } 1321 1322 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1323 static int qcom_geni_console_setup(struct console *co, char *options) 1324 { 1325 struct uart_port *uport; 1326 struct qcom_geni_serial_port *port; 1327 int baud = 115200; 1328 int bits = 8; 1329 int parity = 'n'; 1330 int flow = 'n'; 1331 int ret; 1332 1333 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1334 return -ENXIO; 1335 1336 port = get_port_from_line(co->index, true); 1337 if (IS_ERR(port)) { 1338 pr_err("Invalid line %d\n", co->index); 1339 return PTR_ERR(port); 1340 } 1341 1342 uport = &port->uport; 1343 1344 if (unlikely(!uport->membase)) 1345 return -ENXIO; 1346 1347 if (!port->setup) { 1348 ret = qcom_geni_serial_port_setup(uport); 1349 if (ret) 1350 return ret; 1351 } 1352 1353 if (options) 1354 uart_parse_options(options, &baud, &parity, &bits, &flow); 1355 1356 return uart_set_options(uport, co, baud, parity, bits, flow); 1357 } 1358 1359 static void qcom_geni_serial_earlycon_write(struct console *con, 1360 const char *s, unsigned int n) 1361 { 1362 struct earlycon_device *dev = con->data; 1363 1364 __qcom_geni_serial_console_write(&dev->port, s, n); 1365 } 1366 1367 #ifdef CONFIG_CONSOLE_POLL 1368 static int qcom_geni_serial_earlycon_read(struct console *con, 1369 char *s, unsigned int n) 1370 { 1371 struct earlycon_device *dev = con->data; 1372 struct uart_port *uport = &dev->port; 1373 int num_read = 0; 1374 int ch; 1375 1376 while (num_read < n) { 1377 ch = qcom_geni_serial_get_char(uport); 1378 if (ch == NO_POLL_CHAR) 1379 break; 1380 s[num_read++] = ch; 1381 } 1382 1383 return num_read; 1384 } 1385 1386 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1387 struct console *con) 1388 { 1389 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1390 con->read = qcom_geni_serial_earlycon_read; 1391 } 1392 #else 1393 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1394 struct console *con) { } 1395 #endif 1396 1397 static struct qcom_geni_private_data earlycon_private_data; 1398 1399 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1400 const char *opt) 1401 { 1402 struct uart_port *uport = &dev->port; 1403 u32 tx_trans_cfg; 1404 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1405 u32 rx_trans_cfg = 0; 1406 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1407 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1408 u32 bits_per_char; 1409 struct geni_se se; 1410 1411 if (!uport->membase) 1412 return -EINVAL; 1413 1414 uport->private_data = &earlycon_private_data; 1415 1416 memset(&se, 0, sizeof(se)); 1417 se.base = uport->membase; 1418 if (geni_se_read_proto(&se) != GENI_SE_UART) 1419 return -ENXIO; 1420 /* 1421 * Ignore Flow control. 1422 * n = 8. 1423 */ 1424 tx_trans_cfg = UART_CTS_MASK; 1425 bits_per_char = BITS_PER_BYTE; 1426 1427 /* 1428 * Make an unconditional cancel on the main sequencer to reset 1429 * it else we could end up in data loss scenarios. 1430 */ 1431 qcom_geni_serial_poll_tx_done(uport); 1432 qcom_geni_serial_abort_rx(uport); 1433 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1434 false, true, true); 1435 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1436 geni_se_select_mode(&se, GENI_SE_FIFO); 1437 1438 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1439 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1440 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1441 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1442 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1443 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1444 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1445 1446 dev->con->write = qcom_geni_serial_earlycon_write; 1447 dev->con->setup = NULL; 1448 qcom_geni_serial_enable_early_read(&se, dev->con); 1449 1450 return 0; 1451 } 1452 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1453 qcom_geni_serial_earlycon_setup); 1454 1455 static int __init console_register(struct uart_driver *drv) 1456 { 1457 return uart_register_driver(drv); 1458 } 1459 1460 static void console_unregister(struct uart_driver *drv) 1461 { 1462 uart_unregister_driver(drv); 1463 } 1464 1465 static struct console cons_ops = { 1466 .name = "ttyMSM", 1467 .write = qcom_geni_serial_console_write, 1468 .device = uart_console_device, 1469 .setup = qcom_geni_console_setup, 1470 .flags = CON_PRINTBUFFER, 1471 .index = -1, 1472 .data = &qcom_geni_console_driver, 1473 }; 1474 1475 static struct uart_driver qcom_geni_console_driver = { 1476 .owner = THIS_MODULE, 1477 .driver_name = "qcom_geni_console", 1478 .dev_name = "ttyMSM", 1479 .nr = GENI_UART_CONS_PORTS, 1480 .cons = &cons_ops, 1481 }; 1482 #else 1483 static int console_register(struct uart_driver *drv) 1484 { 1485 return 0; 1486 } 1487 1488 static void console_unregister(struct uart_driver *drv) 1489 { 1490 } 1491 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1492 1493 static struct uart_driver qcom_geni_uart_driver = { 1494 .owner = THIS_MODULE, 1495 .driver_name = "qcom_geni_uart", 1496 .dev_name = "ttyHS", 1497 .nr = GENI_UART_PORTS, 1498 }; 1499 1500 static void qcom_geni_serial_pm(struct uart_port *uport, 1501 unsigned int new_state, unsigned int old_state) 1502 { 1503 struct qcom_geni_serial_port *port = to_dev_port(uport); 1504 1505 /* If we've never been called, treat it as off */ 1506 if (old_state == UART_PM_STATE_UNDEFINED) 1507 old_state = UART_PM_STATE_OFF; 1508 1509 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1510 geni_icc_enable(&port->se); 1511 geni_se_resources_on(&port->se); 1512 } else if (new_state == UART_PM_STATE_OFF && 1513 old_state == UART_PM_STATE_ON) { 1514 geni_se_resources_off(&port->se); 1515 geni_icc_disable(&port->se); 1516 } 1517 } 1518 1519 static const struct uart_ops qcom_geni_console_pops = { 1520 .tx_empty = qcom_geni_serial_tx_empty, 1521 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1522 .start_tx = qcom_geni_serial_start_tx_fifo, 1523 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1524 .start_rx = qcom_geni_serial_start_rx_fifo, 1525 .set_termios = qcom_geni_serial_set_termios, 1526 .startup = qcom_geni_serial_startup, 1527 .request_port = qcom_geni_serial_request_port, 1528 .config_port = qcom_geni_serial_config_port, 1529 .shutdown = qcom_geni_serial_shutdown, 1530 .type = qcom_geni_serial_get_type, 1531 .set_mctrl = qcom_geni_serial_set_mctrl, 1532 .get_mctrl = qcom_geni_serial_get_mctrl, 1533 #ifdef CONFIG_CONSOLE_POLL 1534 .poll_get_char = qcom_geni_serial_get_char, 1535 .poll_put_char = qcom_geni_serial_poll_put_char, 1536 .poll_init = qcom_geni_serial_port_setup, 1537 #endif 1538 .pm = qcom_geni_serial_pm, 1539 }; 1540 1541 static const struct uart_ops qcom_geni_uart_pops = { 1542 .tx_empty = qcom_geni_serial_tx_empty, 1543 .stop_tx = qcom_geni_serial_stop_tx_dma, 1544 .start_tx = qcom_geni_serial_start_tx_dma, 1545 .start_rx = qcom_geni_serial_start_rx_dma, 1546 .stop_rx = qcom_geni_serial_stop_rx_dma, 1547 .set_termios = qcom_geni_serial_set_termios, 1548 .startup = qcom_geni_serial_startup, 1549 .request_port = qcom_geni_serial_request_port, 1550 .config_port = qcom_geni_serial_config_port, 1551 .shutdown = qcom_geni_serial_shutdown, 1552 .type = qcom_geni_serial_get_type, 1553 .set_mctrl = qcom_geni_serial_set_mctrl, 1554 .get_mctrl = qcom_geni_serial_get_mctrl, 1555 .pm = qcom_geni_serial_pm, 1556 }; 1557 1558 static int qcom_geni_serial_probe(struct platform_device *pdev) 1559 { 1560 int ret = 0; 1561 int line; 1562 struct qcom_geni_serial_port *port; 1563 struct uart_port *uport; 1564 struct resource *res; 1565 int irq; 1566 struct uart_driver *drv; 1567 const struct qcom_geni_device_data *data; 1568 1569 data = of_device_get_match_data(&pdev->dev); 1570 if (!data) 1571 return -EINVAL; 1572 1573 if (data->console) { 1574 drv = &qcom_geni_console_driver; 1575 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1576 } else { 1577 drv = &qcom_geni_uart_driver; 1578 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1579 if (line == -ENODEV) /* compat with non-standard aliases */ 1580 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1581 } 1582 1583 port = get_port_from_line(line, data->console); 1584 if (IS_ERR(port)) { 1585 dev_err(&pdev->dev, "Invalid line %d\n", line); 1586 return PTR_ERR(port); 1587 } 1588 1589 uport = &port->uport; 1590 /* Don't allow 2 drivers to access the same port */ 1591 if (uport->private_data) 1592 return -ENODEV; 1593 1594 uport->dev = &pdev->dev; 1595 port->dev_data = data; 1596 port->se.dev = &pdev->dev; 1597 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1598 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1599 if (IS_ERR(port->se.clk)) { 1600 ret = PTR_ERR(port->se.clk); 1601 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1602 return ret; 1603 } 1604 1605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1606 if (!res) 1607 return -EINVAL; 1608 uport->mapbase = res->start; 1609 1610 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1611 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1612 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1613 1614 if (!data->console) { 1615 port->rx_buf = devm_kzalloc(uport->dev, 1616 DMA_RX_BUF_SIZE, GFP_KERNEL); 1617 if (!port->rx_buf) 1618 return -ENOMEM; 1619 } 1620 1621 ret = geni_icc_get(&port->se, NULL); 1622 if (ret) 1623 return ret; 1624 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1625 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1626 1627 /* Set BW for register access */ 1628 ret = geni_icc_set_bw(&port->se); 1629 if (ret) 1630 return ret; 1631 1632 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1633 "qcom_geni_serial_%s%d", 1634 uart_console(uport) ? "console" : "uart", uport->line); 1635 if (!port->name) 1636 return -ENOMEM; 1637 1638 irq = platform_get_irq(pdev, 0); 1639 if (irq < 0) 1640 return irq; 1641 uport->irq = irq; 1642 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1643 1644 if (!data->console) 1645 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1646 1647 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1648 port->rx_tx_swap = true; 1649 1650 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1651 port->cts_rts_swap = true; 1652 1653 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1654 if (ret) 1655 return ret; 1656 /* OPP table is optional */ 1657 ret = devm_pm_opp_of_add_table(&pdev->dev); 1658 if (ret && ret != -ENODEV) { 1659 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1660 return ret; 1661 } 1662 1663 port->private_data.drv = drv; 1664 uport->private_data = &port->private_data; 1665 platform_set_drvdata(pdev, port); 1666 1667 ret = uart_add_one_port(drv, uport); 1668 if (ret) 1669 return ret; 1670 1671 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1672 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1673 IRQF_TRIGGER_HIGH, port->name, uport); 1674 if (ret) { 1675 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1676 uart_remove_one_port(drv, uport); 1677 return ret; 1678 } 1679 1680 /* 1681 * Set pm_runtime status as ACTIVE so that wakeup_irq gets 1682 * enabled/disabled from dev_pm_arm_wake_irq during system 1683 * suspend/resume respectively. 1684 */ 1685 pm_runtime_set_active(&pdev->dev); 1686 1687 if (port->wakeup_irq > 0) { 1688 device_init_wakeup(&pdev->dev, true); 1689 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1690 port->wakeup_irq); 1691 if (ret) { 1692 device_init_wakeup(&pdev->dev, false); 1693 uart_remove_one_port(drv, uport); 1694 return ret; 1695 } 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int qcom_geni_serial_remove(struct platform_device *pdev) 1702 { 1703 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1704 struct uart_driver *drv = port->private_data.drv; 1705 1706 dev_pm_clear_wake_irq(&pdev->dev); 1707 device_init_wakeup(&pdev->dev, false); 1708 uart_remove_one_port(drv, &port->uport); 1709 1710 return 0; 1711 } 1712 1713 static int qcom_geni_serial_sys_suspend(struct device *dev) 1714 { 1715 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1716 struct uart_port *uport = &port->uport; 1717 struct qcom_geni_private_data *private_data = uport->private_data; 1718 1719 /* 1720 * This is done so we can hit the lowest possible state in suspend 1721 * even with no_console_suspend 1722 */ 1723 if (uart_console(uport)) { 1724 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1725 geni_icc_set_bw(&port->se); 1726 } 1727 return uart_suspend_port(private_data->drv, uport); 1728 } 1729 1730 static int qcom_geni_serial_sys_resume(struct device *dev) 1731 { 1732 int ret; 1733 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1734 struct uart_port *uport = &port->uport; 1735 struct qcom_geni_private_data *private_data = uport->private_data; 1736 1737 ret = uart_resume_port(private_data->drv, uport); 1738 if (uart_console(uport)) { 1739 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1740 geni_icc_set_bw(&port->se); 1741 } 1742 return ret; 1743 } 1744 1745 static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1746 { 1747 int ret = 0; 1748 struct uart_port *uport; 1749 struct qcom_geni_private_data *private_data; 1750 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1751 1752 uport = &port->uport; 1753 private_data = uport->private_data; 1754 1755 if (uart_console(uport)) { 1756 geni_icc_set_tag(&port->se, 0x7); 1757 geni_icc_set_bw(&port->se); 1758 ret = uart_resume_port(private_data->drv, uport); 1759 /* 1760 * For hibernation usecase clients for 1761 * console UART won't call port setup during restore, 1762 * hence call port setup for console uart. 1763 */ 1764 qcom_geni_serial_port_setup(uport); 1765 } else { 1766 /* 1767 * Peripheral register settings are lost during hibernation. 1768 * Update setup flag such that port setup happens again 1769 * during next session. Clients of HS-UART will close and 1770 * open the port during hibernation. 1771 */ 1772 port->setup = false; 1773 } 1774 return ret; 1775 } 1776 1777 static const struct qcom_geni_device_data qcom_geni_console_data = { 1778 .console = true, 1779 .mode = GENI_SE_FIFO, 1780 }; 1781 1782 static const struct qcom_geni_device_data qcom_geni_uart_data = { 1783 .console = false, 1784 .mode = GENI_SE_DMA, 1785 }; 1786 1787 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1788 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1789 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), 1790 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1791 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1792 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1793 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1794 }; 1795 1796 static const struct of_device_id qcom_geni_serial_match_table[] = { 1797 { 1798 .compatible = "qcom,geni-debug-uart", 1799 .data = &qcom_geni_console_data, 1800 }, 1801 { 1802 .compatible = "qcom,geni-uart", 1803 .data = &qcom_geni_uart_data, 1804 }, 1805 {} 1806 }; 1807 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1808 1809 static struct platform_driver qcom_geni_serial_platform_driver = { 1810 .remove = qcom_geni_serial_remove, 1811 .probe = qcom_geni_serial_probe, 1812 .driver = { 1813 .name = "qcom_geni_serial", 1814 .of_match_table = qcom_geni_serial_match_table, 1815 .pm = &qcom_geni_serial_pm_ops, 1816 }, 1817 }; 1818 1819 static int __init qcom_geni_serial_init(void) 1820 { 1821 int ret; 1822 1823 ret = console_register(&qcom_geni_console_driver); 1824 if (ret) 1825 return ret; 1826 1827 ret = uart_register_driver(&qcom_geni_uart_driver); 1828 if (ret) { 1829 console_unregister(&qcom_geni_console_driver); 1830 return ret; 1831 } 1832 1833 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1834 if (ret) { 1835 console_unregister(&qcom_geni_console_driver); 1836 uart_unregister_driver(&qcom_geni_uart_driver); 1837 } 1838 return ret; 1839 } 1840 module_init(qcom_geni_serial_init); 1841 1842 static void __exit qcom_geni_serial_exit(void) 1843 { 1844 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1845 console_unregister(&qcom_geni_console_driver); 1846 uart_unregister_driver(&qcom_geni_uart_driver); 1847 } 1848 module_exit(qcom_geni_serial_exit); 1849 1850 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1851 MODULE_LICENSE("GPL v2"); 1852