1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/console.h> 6 #include <linux/io.h> 7 #include <linux/iopoll.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/qcom-geni-se.h> 13 #include <linux/serial.h> 14 #include <linux/serial_core.h> 15 #include <linux/slab.h> 16 #include <linux/tty.h> 17 #include <linux/tty_flip.h> 18 19 /* UART specific GENI registers */ 20 #define SE_UART_LOOPBACK_CFG 0x22c 21 #define SE_UART_TX_TRANS_CFG 0x25c 22 #define SE_UART_TX_WORD_LEN 0x268 23 #define SE_UART_TX_STOP_BIT_LEN 0x26c 24 #define SE_UART_TX_TRANS_LEN 0x270 25 #define SE_UART_RX_TRANS_CFG 0x280 26 #define SE_UART_RX_WORD_LEN 0x28c 27 #define SE_UART_RX_STALE_CNT 0x294 28 #define SE_UART_TX_PARITY_CFG 0x2a4 29 #define SE_UART_RX_PARITY_CFG 0x2a8 30 #define SE_UART_MANUAL_RFR 0x2ac 31 32 /* SE_UART_TRANS_CFG */ 33 #define UART_TX_PAR_EN BIT(0) 34 #define UART_CTS_MASK BIT(1) 35 36 /* SE_UART_TX_WORD_LEN */ 37 #define TX_WORD_LEN_MSK GENMASK(9, 0) 38 39 /* SE_UART_TX_STOP_BIT_LEN */ 40 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) 41 #define TX_STOP_BIT_LEN_1 0 42 #define TX_STOP_BIT_LEN_1_5 1 43 #define TX_STOP_BIT_LEN_2 2 44 45 /* SE_UART_TX_TRANS_LEN */ 46 #define TX_TRANS_LEN_MSK GENMASK(23, 0) 47 48 /* SE_UART_RX_TRANS_CFG */ 49 #define UART_RX_INS_STATUS_BIT BIT(2) 50 #define UART_RX_PAR_EN BIT(3) 51 52 /* SE_UART_RX_WORD_LEN */ 53 #define RX_WORD_LEN_MASK GENMASK(9, 0) 54 55 /* SE_UART_RX_STALE_CNT */ 56 #define RX_STALE_CNT GENMASK(23, 0) 57 58 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 59 #define PAR_CALC_EN BIT(0) 60 #define PAR_MODE_MSK GENMASK(2, 1) 61 #define PAR_MODE_SHFT 1 62 #define PAR_EVEN 0x00 63 #define PAR_ODD 0x01 64 #define PAR_SPACE 0x10 65 #define PAR_MARK 0x11 66 67 /* SE_UART_MANUAL_RFR register fields */ 68 #define UART_MANUAL_RFR_EN BIT(31) 69 #define UART_RFR_NOT_READY BIT(1) 70 #define UART_RFR_READY BIT(0) 71 72 /* UART M_CMD OP codes */ 73 #define UART_START_TX 0x1 74 #define UART_START_BREAK 0x4 75 #define UART_STOP_BREAK 0x5 76 /* UART S_CMD OP codes */ 77 #define UART_START_READ 0x1 78 #define UART_PARAM 0x1 79 80 #define UART_OVERSAMPLING 32 81 #define STALE_TIMEOUT 16 82 #define DEFAULT_BITS_PER_CHAR 10 83 #define GENI_UART_CONS_PORTS 1 84 #define GENI_UART_PORTS 3 85 #define DEF_FIFO_DEPTH_WORDS 16 86 #define DEF_TX_WM 2 87 #define DEF_FIFO_WIDTH_BITS 32 88 #define UART_CONSOLE_RX_WM 2 89 #define MAX_LOOPBACK_CFG 3 90 91 #ifdef CONFIG_CONSOLE_POLL 92 #define RX_BYTES_PW 1 93 #else 94 #define RX_BYTES_PW 4 95 #endif 96 97 struct qcom_geni_serial_port { 98 struct uart_port uport; 99 struct geni_se se; 100 char name[20]; 101 u32 tx_fifo_depth; 102 u32 tx_fifo_width; 103 u32 rx_fifo_depth; 104 u32 tx_wm; 105 u32 rx_wm; 106 u32 rx_rfr; 107 enum geni_se_xfer_mode xfer_mode; 108 bool setup; 109 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); 110 unsigned int baud; 111 unsigned int tx_bytes_pw; 112 unsigned int rx_bytes_pw; 113 u32 *rx_fifo; 114 u32 loopback; 115 bool brk; 116 }; 117 118 static const struct uart_ops qcom_geni_console_pops; 119 static const struct uart_ops qcom_geni_uart_pops; 120 static struct uart_driver qcom_geni_console_driver; 121 static struct uart_driver qcom_geni_uart_driver; 122 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); 123 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); 124 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); 125 static void qcom_geni_serial_stop_rx(struct uart_port *uport); 126 127 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 128 32000000, 48000000, 64000000, 80000000, 129 96000000, 100000000, 102400000, 130 112000000, 120000000, 128000000}; 131 132 #define to_dev_port(ptr, member) \ 133 container_of(ptr, struct qcom_geni_serial_port, member) 134 135 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 136 [0] = { 137 .uport = { 138 .iotype = UPIO_MEM, 139 .ops = &qcom_geni_uart_pops, 140 .flags = UPF_BOOT_AUTOCONF, 141 .line = 0, 142 }, 143 }, 144 [1] = { 145 .uport = { 146 .iotype = UPIO_MEM, 147 .ops = &qcom_geni_uart_pops, 148 .flags = UPF_BOOT_AUTOCONF, 149 .line = 1, 150 }, 151 }, 152 [2] = { 153 .uport = { 154 .iotype = UPIO_MEM, 155 .ops = &qcom_geni_uart_pops, 156 .flags = UPF_BOOT_AUTOCONF, 157 .line = 2, 158 }, 159 }, 160 }; 161 162 static ssize_t loopback_show(struct device *dev, 163 struct device_attribute *attr, char *buf) 164 { 165 struct platform_device *pdev = to_platform_device(dev); 166 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 167 168 return snprintf(buf, sizeof(u32), "%d\n", port->loopback); 169 } 170 171 static ssize_t loopback_store(struct device *dev, 172 struct device_attribute *attr, const char *buf, 173 size_t size) 174 { 175 struct platform_device *pdev = to_platform_device(dev); 176 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 177 u32 loopback; 178 179 if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) { 180 dev_err(dev, "Invalid input\n"); 181 return -EINVAL; 182 } 183 port->loopback = loopback; 184 return size; 185 } 186 static DEVICE_ATTR_RW(loopback); 187 188 static struct qcom_geni_serial_port qcom_geni_console_port = { 189 .uport = { 190 .iotype = UPIO_MEM, 191 .ops = &qcom_geni_console_pops, 192 .flags = UPF_BOOT_AUTOCONF, 193 .line = 0, 194 }, 195 }; 196 197 static int qcom_geni_serial_request_port(struct uart_port *uport) 198 { 199 struct platform_device *pdev = to_platform_device(uport->dev); 200 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 201 struct resource *res; 202 203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 204 uport->membase = devm_ioremap_resource(&pdev->dev, res); 205 if (IS_ERR(uport->membase)) 206 return PTR_ERR(uport->membase); 207 port->se.base = uport->membase; 208 return 0; 209 } 210 211 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 212 { 213 if (cfg_flags & UART_CONFIG_TYPE) { 214 uport->type = PORT_MSM; 215 qcom_geni_serial_request_port(uport); 216 } 217 } 218 219 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 220 { 221 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 222 u32 geni_ios; 223 224 if (uart_console(uport) || !uart_cts_enabled(uport)) { 225 mctrl |= TIOCM_CTS; 226 } else { 227 geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS); 228 if (!(geni_ios & IO2_DATA_IN)) 229 mctrl |= TIOCM_CTS; 230 } 231 232 return mctrl; 233 } 234 235 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 236 unsigned int mctrl) 237 { 238 u32 uart_manual_rfr = 0; 239 240 if (uart_console(uport) || !uart_cts_enabled(uport)) 241 return; 242 243 if (!(mctrl & TIOCM_RTS)) 244 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 245 writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 246 } 247 248 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 249 { 250 return "MSM"; 251 } 252 253 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 254 { 255 struct qcom_geni_serial_port *port; 256 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 257 258 if (line < 0 || line >= nr_ports) 259 return ERR_PTR(-ENXIO); 260 261 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 262 return port; 263 } 264 265 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 266 int offset, int field, bool set) 267 { 268 u32 reg; 269 struct qcom_geni_serial_port *port; 270 unsigned int baud; 271 unsigned int fifo_bits; 272 unsigned long timeout_us = 20000; 273 274 /* Ensure polling is not re-ordered before the prior writes/reads */ 275 mb(); 276 277 if (uport->private_data) { 278 port = to_dev_port(uport, uport); 279 baud = port->baud; 280 if (!baud) 281 baud = 115200; 282 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 283 /* 284 * Total polling iterations based on FIFO worth of bytes to be 285 * sent at current baud. Add a little fluff to the wait. 286 */ 287 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 288 } 289 290 /* 291 * Use custom implementation instead of readl_poll_atomic since ktimer 292 * is not ready at the time of early console. 293 */ 294 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 295 while (timeout_us) { 296 reg = readl_relaxed(uport->membase + offset); 297 if ((bool)(reg & field) == set) 298 return true; 299 udelay(10); 300 timeout_us -= 10; 301 } 302 return false; 303 } 304 305 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 306 { 307 u32 m_cmd; 308 309 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 310 m_cmd = UART_START_TX << M_OPCODE_SHFT; 311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 312 } 313 314 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 315 { 316 int done; 317 u32 irq_clear = M_CMD_DONE_EN; 318 319 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 320 M_CMD_DONE_EN, true); 321 if (!done) { 322 writel_relaxed(M_GENI_CMD_ABORT, uport->membase + 323 SE_GENI_M_CMD_CTRL_REG); 324 irq_clear |= M_CMD_ABORT_EN; 325 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 326 M_CMD_ABORT_EN, true); 327 } 328 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 329 } 330 331 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 332 { 333 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 334 335 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 336 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 337 S_GENI_CMD_ABORT, false); 338 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 339 writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 340 } 341 342 #ifdef CONFIG_CONSOLE_POLL 343 static int qcom_geni_serial_get_char(struct uart_port *uport) 344 { 345 u32 rx_fifo; 346 u32 status; 347 348 status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS); 349 writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 350 351 status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS); 352 writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 353 354 /* 355 * Ensure the writes to clear interrupts is not re-ordered after 356 * reading the data. 357 */ 358 mb(); 359 360 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS); 361 if (!(status & RX_FIFO_WC_MSK)) 362 return NO_POLL_CHAR; 363 364 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn); 365 return rx_fifo & 0xff; 366 } 367 368 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 369 unsigned char c) 370 { 371 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 372 373 writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG); 374 qcom_geni_serial_setup_tx(uport, 1); 375 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 376 M_TX_FIFO_WATERMARK_EN, true)); 377 writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn); 378 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase + 379 SE_GENI_M_IRQ_CLEAR); 380 qcom_geni_serial_poll_tx_done(uport); 381 } 382 #endif 383 384 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 385 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch) 386 { 387 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn); 388 } 389 390 static void 391 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 392 unsigned int count) 393 { 394 int i; 395 u32 bytes_to_send = count; 396 397 for (i = 0; i < count; i++) { 398 /* 399 * uart_console_write() adds a carriage return for each newline. 400 * Account for additional bytes to be written. 401 */ 402 if (s[i] == '\n') 403 bytes_to_send++; 404 } 405 406 writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 407 qcom_geni_serial_setup_tx(uport, bytes_to_send); 408 for (i = 0; i < count; ) { 409 size_t chars_to_write = 0; 410 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 411 412 /* 413 * If the WM bit never set, then the Tx state machine is not 414 * in a valid state, so break, cancel/abort any existing 415 * command. Unfortunately the current data being written is 416 * lost. 417 */ 418 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 419 M_TX_FIFO_WATERMARK_EN, true)) 420 break; 421 chars_to_write = min_t(size_t, count - i, avail / 2); 422 uart_console_write(uport, s + i, chars_to_write, 423 qcom_geni_serial_wr_char); 424 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase + 425 SE_GENI_M_IRQ_CLEAR); 426 i += chars_to_write; 427 } 428 qcom_geni_serial_poll_tx_done(uport); 429 } 430 431 static void qcom_geni_serial_console_write(struct console *co, const char *s, 432 unsigned int count) 433 { 434 struct uart_port *uport; 435 struct qcom_geni_serial_port *port; 436 bool locked = true; 437 unsigned long flags; 438 439 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 440 441 port = get_port_from_line(co->index, true); 442 if (IS_ERR(port)) 443 return; 444 445 uport = &port->uport; 446 if (oops_in_progress) 447 locked = spin_trylock_irqsave(&uport->lock, flags); 448 else 449 spin_lock_irqsave(&uport->lock, flags); 450 451 /* Cancel the current write to log the fault */ 452 if (!locked) { 453 geni_se_cancel_m_cmd(&port->se); 454 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 455 M_CMD_CANCEL_EN, true)) { 456 geni_se_abort_m_cmd(&port->se); 457 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 458 M_CMD_ABORT_EN, true); 459 writel_relaxed(M_CMD_ABORT_EN, uport->membase + 460 SE_GENI_M_IRQ_CLEAR); 461 } 462 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + 463 SE_GENI_M_IRQ_CLEAR); 464 } 465 466 __qcom_geni_serial_console_write(uport, s, count); 467 if (locked) 468 spin_unlock_irqrestore(&uport->lock, flags); 469 } 470 471 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 472 { 473 u32 i; 474 unsigned char buf[sizeof(u32)]; 475 struct tty_port *tport; 476 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 477 478 tport = &uport->state->port; 479 for (i = 0; i < bytes; ) { 480 int c; 481 int chunk = min_t(int, bytes - i, port->rx_bytes_pw); 482 483 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 484 i += chunk; 485 if (drop) 486 continue; 487 488 for (c = 0; c < chunk; c++) { 489 int sysrq; 490 491 uport->icount.rx++; 492 if (port->brk && buf[c] == 0) { 493 port->brk = false; 494 if (uart_handle_break(uport)) 495 continue; 496 } 497 498 sysrq = uart_handle_sysrq_char(uport, buf[c]); 499 if (!sysrq) 500 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 501 } 502 } 503 if (!drop) 504 tty_flip_buffer_push(tport); 505 return 0; 506 } 507 #else 508 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 509 { 510 return -EPERM; 511 } 512 513 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 514 515 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 516 { 517 unsigned char *buf; 518 struct tty_port *tport; 519 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 520 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; 521 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; 522 int ret; 523 524 tport = &uport->state->port; 525 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); 526 if (drop) 527 return 0; 528 529 buf = (unsigned char *)port->rx_fifo; 530 ret = tty_insert_flip_string(tport, buf, bytes); 531 if (ret != bytes) { 532 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 533 __func__, ret, bytes); 534 WARN_ON_ONCE(1); 535 } 536 uport->icount.rx += ret; 537 tty_flip_buffer_push(tport); 538 return ret; 539 } 540 541 static void qcom_geni_serial_start_tx(struct uart_port *uport) 542 { 543 u32 irq_en; 544 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 545 u32 status; 546 547 if (port->xfer_mode == GENI_SE_FIFO) { 548 /* 549 * readl ensures reading & writing of IRQ_EN register 550 * is not re-ordered before checking the status of the 551 * Serial Engine. 552 */ 553 status = readl(uport->membase + SE_GENI_STATUS); 554 if (status & M_GENI_CMD_ACTIVE) 555 return; 556 557 if (!qcom_geni_serial_tx_empty(uport)) 558 return; 559 560 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); 561 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 562 563 writel_relaxed(port->tx_wm, uport->membase + 564 SE_GENI_TX_WATERMARK_REG); 565 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 566 } 567 } 568 569 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 570 { 571 u32 irq_en; 572 u32 status; 573 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 574 575 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); 576 irq_en &= ~M_CMD_DONE_EN; 577 if (port->xfer_mode == GENI_SE_FIFO) { 578 irq_en &= ~M_TX_FIFO_WATERMARK_EN; 579 writel_relaxed(0, uport->membase + 580 SE_GENI_TX_WATERMARK_REG); 581 } 582 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 583 status = readl_relaxed(uport->membase + SE_GENI_STATUS); 584 /* Possible stop tx is called multiple times. */ 585 if (!(status & M_GENI_CMD_ACTIVE)) 586 return; 587 588 /* 589 * Ensure cancel command write is not re-ordered before checking 590 * the status of the Primary Sequencer. 591 */ 592 mb(); 593 594 geni_se_cancel_m_cmd(&port->se); 595 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 596 M_CMD_CANCEL_EN, true)) { 597 geni_se_abort_m_cmd(&port->se); 598 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 599 M_CMD_ABORT_EN, true); 600 writel_relaxed(M_CMD_ABORT_EN, uport->membase + 601 SE_GENI_M_IRQ_CLEAR); 602 } 603 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 604 } 605 606 static void qcom_geni_serial_start_rx(struct uart_port *uport) 607 { 608 u32 irq_en; 609 u32 status; 610 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 611 612 status = readl_relaxed(uport->membase + SE_GENI_STATUS); 613 if (status & S_GENI_CMD_ACTIVE) 614 qcom_geni_serial_stop_rx(uport); 615 616 /* 617 * Ensure setup command write is not re-ordered before checking 618 * the status of the Secondary Sequencer. 619 */ 620 mb(); 621 622 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 623 624 if (port->xfer_mode == GENI_SE_FIFO) { 625 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN); 626 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 627 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 628 629 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); 630 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 631 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 632 } 633 } 634 635 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 636 { 637 u32 irq_en; 638 u32 status; 639 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 640 u32 irq_clear = S_CMD_DONE_EN; 641 642 if (port->xfer_mode == GENI_SE_FIFO) { 643 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN); 644 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 645 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 646 647 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); 648 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 649 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 650 } 651 652 status = readl_relaxed(uport->membase + SE_GENI_STATUS); 653 /* Possible stop rx is called multiple times. */ 654 if (!(status & S_GENI_CMD_ACTIVE)) 655 return; 656 657 /* 658 * Ensure cancel command write is not re-ordered before checking 659 * the status of the Secondary Sequencer. 660 */ 661 mb(); 662 663 geni_se_cancel_s_cmd(&port->se); 664 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 665 S_GENI_CMD_CANCEL, false); 666 status = readl_relaxed(uport->membase + SE_GENI_STATUS); 667 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 668 if (status & S_GENI_CMD_ACTIVE) 669 qcom_geni_serial_abort_rx(uport); 670 } 671 672 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) 673 { 674 u32 status; 675 u32 word_cnt; 676 u32 last_word_byte_cnt; 677 u32 last_word_partial; 678 u32 total_bytes; 679 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 680 681 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS); 682 word_cnt = status & RX_FIFO_WC_MSK; 683 last_word_partial = status & RX_LAST; 684 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 685 RX_LAST_BYTE_VALID_SHFT; 686 687 if (!word_cnt) 688 return; 689 total_bytes = port->rx_bytes_pw * (word_cnt - 1); 690 if (last_word_partial && last_word_byte_cnt) 691 total_bytes += last_word_byte_cnt; 692 else 693 total_bytes += port->rx_bytes_pw; 694 port->handle_rx(uport, total_bytes, drop); 695 } 696 697 static void qcom_geni_serial_handle_tx(struct uart_port *uport) 698 { 699 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 700 struct circ_buf *xmit = &uport->state->xmit; 701 size_t avail; 702 size_t remaining; 703 int i; 704 u32 status; 705 unsigned int chunk; 706 int tail; 707 u32 irq_en; 708 709 chunk = uart_circ_chars_pending(xmit); 710 status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS); 711 /* Both FIFO and framework buffer are drained */ 712 if (!chunk && !status) { 713 qcom_geni_serial_stop_tx(uport); 714 goto out_write_wakeup; 715 } 716 717 if (!uart_console(uport)) { 718 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); 719 irq_en &= ~(M_TX_FIFO_WATERMARK_EN); 720 writel_relaxed(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 721 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 722 } 723 724 avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw; 725 tail = xmit->tail; 726 chunk = min3((size_t)chunk, (size_t)(UART_XMIT_SIZE - tail), avail); 727 if (!chunk) 728 goto out_write_wakeup; 729 730 qcom_geni_serial_setup_tx(uport, chunk); 731 732 remaining = chunk; 733 for (i = 0; i < chunk; ) { 734 unsigned int tx_bytes; 735 u8 buf[sizeof(u32)]; 736 int c; 737 738 memset(buf, 0, ARRAY_SIZE(buf)); 739 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw); 740 for (c = 0; c < tx_bytes ; c++) 741 buf[c] = xmit->buf[tail + c]; 742 743 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 744 745 i += tx_bytes; 746 tail += tx_bytes; 747 uport->icount.tx += tx_bytes; 748 remaining -= tx_bytes; 749 } 750 751 xmit->tail = tail & (UART_XMIT_SIZE - 1); 752 if (uart_console(uport)) 753 qcom_geni_serial_poll_tx_done(uport); 754 out_write_wakeup: 755 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 756 uart_write_wakeup(uport); 757 } 758 759 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 760 { 761 unsigned int m_irq_status; 762 unsigned int s_irq_status; 763 struct uart_port *uport = dev; 764 unsigned long flags; 765 unsigned int m_irq_en; 766 bool drop_rx = false; 767 struct tty_port *tport = &uport->state->port; 768 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 769 770 if (uport->suspended) 771 return IRQ_NONE; 772 773 spin_lock_irqsave(&uport->lock, flags); 774 m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS); 775 s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS); 776 m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); 777 writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 778 writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 779 780 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 781 goto out_unlock; 782 783 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 784 uport->icount.overrun++; 785 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 786 } 787 788 if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) && 789 m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 790 qcom_geni_serial_handle_tx(uport); 791 792 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { 793 if (s_irq_status & S_GP_IRQ_0_EN) 794 uport->icount.parity++; 795 drop_rx = true; 796 } else if (s_irq_status & S_GP_IRQ_2_EN || 797 s_irq_status & S_GP_IRQ_3_EN) { 798 uport->icount.brk++; 799 port->brk = true; 800 } 801 802 if (s_irq_status & S_RX_FIFO_WATERMARK_EN || 803 s_irq_status & S_RX_FIFO_LAST_EN) 804 qcom_geni_serial_handle_rx(uport, drop_rx); 805 806 out_unlock: 807 spin_unlock_irqrestore(&uport->lock, flags); 808 return IRQ_HANDLED; 809 } 810 811 static void get_tx_fifo_size(struct qcom_geni_serial_port *port) 812 { 813 struct uart_port *uport; 814 815 uport = &port->uport; 816 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 817 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 818 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 819 uport->fifosize = 820 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 821 } 822 823 static void set_rfr_wm(struct qcom_geni_serial_port *port) 824 { 825 /* 826 * Set RFR (Flow off) to FIFO_DEPTH - 2. 827 * RX WM level at 10% RX_FIFO_DEPTH. 828 * TX WM level at 10% TX_FIFO_DEPTH. 829 */ 830 port->rx_rfr = port->rx_fifo_depth - 2; 831 port->rx_wm = UART_CONSOLE_RX_WM; 832 port->tx_wm = DEF_TX_WM; 833 } 834 835 static void qcom_geni_serial_shutdown(struct uart_port *uport) 836 { 837 unsigned long flags; 838 839 /* Stop the console before stopping the current tx */ 840 if (uart_console(uport)) 841 console_stop(uport->cons); 842 843 free_irq(uport->irq, uport); 844 spin_lock_irqsave(&uport->lock, flags); 845 qcom_geni_serial_stop_tx(uport); 846 qcom_geni_serial_stop_rx(uport); 847 spin_unlock_irqrestore(&uport->lock, flags); 848 } 849 850 static int qcom_geni_serial_port_setup(struct uart_port *uport) 851 { 852 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 853 unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 854 855 set_rfr_wm(port); 856 writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 857 /* 858 * Make an unconditional cancel on the main sequencer to reset 859 * it else we could end up in data loss scenarios. 860 */ 861 port->xfer_mode = GENI_SE_FIFO; 862 if (uart_console(uport)) 863 qcom_geni_serial_poll_tx_done(uport); 864 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw, 865 false, true, false); 866 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw, 867 false, false, true); 868 geni_se_init(&port->se, port->rx_wm, port->rx_rfr); 869 geni_se_select_mode(&port->se, port->xfer_mode); 870 if (!uart_console(uport)) { 871 port->rx_fifo = devm_kzalloc(uport->dev, 872 port->rx_fifo_depth * sizeof(u32), GFP_KERNEL); 873 if (!port->rx_fifo) 874 return -ENOMEM; 875 } 876 port->setup = true; 877 return 0; 878 } 879 880 static int qcom_geni_serial_startup(struct uart_port *uport) 881 { 882 int ret; 883 u32 proto; 884 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 885 886 scnprintf(port->name, sizeof(port->name), 887 "qcom_serial_%s%d", 888 (uart_console(uport) ? "console" : "uart"), uport->line); 889 890 if (!uart_console(uport)) { 891 port->tx_bytes_pw = 4; 892 port->rx_bytes_pw = RX_BYTES_PW; 893 } 894 proto = geni_se_read_proto(&port->se); 895 if (proto != GENI_SE_UART) { 896 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 897 return -ENXIO; 898 } 899 900 get_tx_fifo_size(port); 901 if (!port->setup) { 902 ret = qcom_geni_serial_port_setup(uport); 903 if (ret) 904 return ret; 905 } 906 907 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH, 908 port->name, uport); 909 if (ret) 910 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 911 return ret; 912 } 913 914 static unsigned long get_clk_cfg(unsigned long clk_freq) 915 { 916 int i; 917 918 for (i = 0; i < ARRAY_SIZE(root_freq); i++) { 919 if (!(root_freq[i] % clk_freq)) 920 return root_freq[i]; 921 } 922 return 0; 923 } 924 925 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div) 926 { 927 unsigned long ser_clk; 928 unsigned long desired_clk; 929 930 desired_clk = baud * UART_OVERSAMPLING; 931 ser_clk = get_clk_cfg(desired_clk); 932 if (!ser_clk) { 933 pr_err("%s: Can't find matching DFS entry for baud %d\n", 934 __func__, baud); 935 return ser_clk; 936 } 937 938 *clk_div = ser_clk / desired_clk; 939 return ser_clk; 940 } 941 942 static void qcom_geni_serial_set_termios(struct uart_port *uport, 943 struct ktermios *termios, struct ktermios *old) 944 { 945 unsigned int baud; 946 unsigned int bits_per_char; 947 unsigned int tx_trans_cfg; 948 unsigned int tx_parity_cfg; 949 unsigned int rx_trans_cfg; 950 unsigned int rx_parity_cfg; 951 unsigned int stop_bit_len; 952 unsigned int clk_div; 953 unsigned long ser_clk_cfg; 954 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 955 unsigned long clk_rate; 956 957 qcom_geni_serial_stop_rx(uport); 958 /* baud rate */ 959 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 960 port->baud = baud; 961 clk_rate = get_clk_div_rate(baud, &clk_div); 962 if (!clk_rate) 963 goto out_restart_rx; 964 965 uport->uartclk = clk_rate; 966 clk_set_rate(port->se.clk, clk_rate); 967 ser_clk_cfg = SER_CLK_EN; 968 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 969 970 /* parity */ 971 tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG); 972 tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG); 973 rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG); 974 rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG); 975 if (termios->c_cflag & PARENB) { 976 tx_trans_cfg |= UART_TX_PAR_EN; 977 rx_trans_cfg |= UART_RX_PAR_EN; 978 tx_parity_cfg |= PAR_CALC_EN; 979 rx_parity_cfg |= PAR_CALC_EN; 980 if (termios->c_cflag & PARODD) { 981 tx_parity_cfg |= PAR_ODD; 982 rx_parity_cfg |= PAR_ODD; 983 } else if (termios->c_cflag & CMSPAR) { 984 tx_parity_cfg |= PAR_SPACE; 985 rx_parity_cfg |= PAR_SPACE; 986 } else { 987 tx_parity_cfg |= PAR_EVEN; 988 rx_parity_cfg |= PAR_EVEN; 989 } 990 } else { 991 tx_trans_cfg &= ~UART_TX_PAR_EN; 992 rx_trans_cfg &= ~UART_RX_PAR_EN; 993 tx_parity_cfg &= ~PAR_CALC_EN; 994 rx_parity_cfg &= ~PAR_CALC_EN; 995 } 996 997 /* bits per char */ 998 switch (termios->c_cflag & CSIZE) { 999 case CS5: 1000 bits_per_char = 5; 1001 break; 1002 case CS6: 1003 bits_per_char = 6; 1004 break; 1005 case CS7: 1006 bits_per_char = 7; 1007 break; 1008 case CS8: 1009 default: 1010 bits_per_char = 8; 1011 break; 1012 } 1013 1014 /* stop bits */ 1015 if (termios->c_cflag & CSTOPB) 1016 stop_bit_len = TX_STOP_BIT_LEN_2; 1017 else 1018 stop_bit_len = TX_STOP_BIT_LEN_1; 1019 1020 /* flow control, clear the CTS_MASK bit if using flow control. */ 1021 if (termios->c_cflag & CRTSCTS) 1022 tx_trans_cfg &= ~UART_CTS_MASK; 1023 else 1024 tx_trans_cfg |= UART_CTS_MASK; 1025 1026 if (baud) 1027 uart_update_timeout(uport, termios->c_cflag, baud); 1028 1029 if (!uart_console(uport)) 1030 writel_relaxed(port->loopback, 1031 uport->membase + SE_UART_LOOPBACK_CFG); 1032 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1033 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1034 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1035 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1036 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1037 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1038 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1039 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1040 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1041 out_restart_rx: 1042 qcom_geni_serial_start_rx(uport); 1043 } 1044 1045 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 1046 { 1047 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 1048 } 1049 1050 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1051 static int __init qcom_geni_console_setup(struct console *co, char *options) 1052 { 1053 struct uart_port *uport; 1054 struct qcom_geni_serial_port *port; 1055 int baud; 1056 int bits = 8; 1057 int parity = 'n'; 1058 int flow = 'n'; 1059 1060 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1061 return -ENXIO; 1062 1063 port = get_port_from_line(co->index, true); 1064 if (IS_ERR(port)) { 1065 pr_err("Invalid line %d\n", co->index); 1066 return PTR_ERR(port); 1067 } 1068 1069 uport = &port->uport; 1070 1071 if (unlikely(!uport->membase)) 1072 return -ENXIO; 1073 1074 if (geni_se_resources_on(&port->se)) { 1075 dev_err(port->se.dev, "Error turning on resources\n"); 1076 return -ENXIO; 1077 } 1078 1079 if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) { 1080 geni_se_resources_off(&port->se); 1081 return -ENXIO; 1082 } 1083 1084 if (!port->setup) { 1085 port->tx_bytes_pw = 1; 1086 port->rx_bytes_pw = RX_BYTES_PW; 1087 qcom_geni_serial_stop_rx(uport); 1088 qcom_geni_serial_port_setup(uport); 1089 } 1090 1091 if (options) 1092 uart_parse_options(options, &baud, &parity, &bits, &flow); 1093 1094 return uart_set_options(uport, co, baud, parity, bits, flow); 1095 } 1096 1097 static void qcom_geni_serial_earlycon_write(struct console *con, 1098 const char *s, unsigned int n) 1099 { 1100 struct earlycon_device *dev = con->data; 1101 1102 __qcom_geni_serial_console_write(&dev->port, s, n); 1103 } 1104 1105 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1106 const char *opt) 1107 { 1108 struct uart_port *uport = &dev->port; 1109 u32 tx_trans_cfg; 1110 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1111 u32 rx_trans_cfg = 0; 1112 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1113 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1114 u32 bits_per_char; 1115 struct geni_se se; 1116 1117 if (!uport->membase) 1118 return -EINVAL; 1119 1120 memset(&se, 0, sizeof(se)); 1121 se.base = uport->membase; 1122 if (geni_se_read_proto(&se) != GENI_SE_UART) 1123 return -ENXIO; 1124 /* 1125 * Ignore Flow control. 1126 * n = 8. 1127 */ 1128 tx_trans_cfg = UART_CTS_MASK; 1129 bits_per_char = BITS_PER_BYTE; 1130 1131 /* 1132 * Make an unconditional cancel on the main sequencer to reset 1133 * it else we could end up in data loss scenarios. 1134 */ 1135 qcom_geni_serial_poll_tx_done(uport); 1136 qcom_geni_serial_abort_rx(uport); 1137 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false); 1138 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1139 geni_se_select_mode(&se, GENI_SE_FIFO); 1140 1141 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1142 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1143 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1144 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1145 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1146 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1147 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1148 1149 dev->con->write = qcom_geni_serial_earlycon_write; 1150 dev->con->setup = NULL; 1151 return 0; 1152 } 1153 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1154 qcom_geni_serial_earlycon_setup); 1155 1156 static int __init console_register(struct uart_driver *drv) 1157 { 1158 return uart_register_driver(drv); 1159 } 1160 1161 static void console_unregister(struct uart_driver *drv) 1162 { 1163 uart_unregister_driver(drv); 1164 } 1165 1166 static struct console cons_ops = { 1167 .name = "ttyMSM", 1168 .write = qcom_geni_serial_console_write, 1169 .device = uart_console_device, 1170 .setup = qcom_geni_console_setup, 1171 .flags = CON_PRINTBUFFER, 1172 .index = -1, 1173 .data = &qcom_geni_console_driver, 1174 }; 1175 1176 static struct uart_driver qcom_geni_console_driver = { 1177 .owner = THIS_MODULE, 1178 .driver_name = "qcom_geni_console", 1179 .dev_name = "ttyMSM", 1180 .nr = GENI_UART_CONS_PORTS, 1181 .cons = &cons_ops, 1182 }; 1183 #else 1184 static int console_register(struct uart_driver *drv) 1185 { 1186 return 0; 1187 } 1188 1189 static void console_unregister(struct uart_driver *drv) 1190 { 1191 } 1192 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1193 1194 static struct uart_driver qcom_geni_uart_driver = { 1195 .owner = THIS_MODULE, 1196 .driver_name = "qcom_geni_uart", 1197 .dev_name = "ttyHS", 1198 .nr = GENI_UART_PORTS, 1199 }; 1200 1201 static void qcom_geni_serial_pm(struct uart_port *uport, 1202 unsigned int new_state, unsigned int old_state) 1203 { 1204 struct qcom_geni_serial_port *port = to_dev_port(uport, uport); 1205 1206 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) 1207 geni_se_resources_on(&port->se); 1208 else if (!uart_console(uport) && (new_state == UART_PM_STATE_ON && 1209 old_state == UART_PM_STATE_UNDEFINED)) 1210 geni_se_resources_on(&port->se); 1211 else if (new_state == UART_PM_STATE_OFF && 1212 old_state == UART_PM_STATE_ON) 1213 geni_se_resources_off(&port->se); 1214 } 1215 1216 static const struct uart_ops qcom_geni_console_pops = { 1217 .tx_empty = qcom_geni_serial_tx_empty, 1218 .stop_tx = qcom_geni_serial_stop_tx, 1219 .start_tx = qcom_geni_serial_start_tx, 1220 .stop_rx = qcom_geni_serial_stop_rx, 1221 .set_termios = qcom_geni_serial_set_termios, 1222 .startup = qcom_geni_serial_startup, 1223 .request_port = qcom_geni_serial_request_port, 1224 .config_port = qcom_geni_serial_config_port, 1225 .shutdown = qcom_geni_serial_shutdown, 1226 .type = qcom_geni_serial_get_type, 1227 .set_mctrl = qcom_geni_serial_set_mctrl, 1228 .get_mctrl = qcom_geni_serial_get_mctrl, 1229 #ifdef CONFIG_CONSOLE_POLL 1230 .poll_get_char = qcom_geni_serial_get_char, 1231 .poll_put_char = qcom_geni_serial_poll_put_char, 1232 #endif 1233 .pm = qcom_geni_serial_pm, 1234 }; 1235 1236 static const struct uart_ops qcom_geni_uart_pops = { 1237 .tx_empty = qcom_geni_serial_tx_empty, 1238 .stop_tx = qcom_geni_serial_stop_tx, 1239 .start_tx = qcom_geni_serial_start_tx, 1240 .stop_rx = qcom_geni_serial_stop_rx, 1241 .set_termios = qcom_geni_serial_set_termios, 1242 .startup = qcom_geni_serial_startup, 1243 .request_port = qcom_geni_serial_request_port, 1244 .config_port = qcom_geni_serial_config_port, 1245 .shutdown = qcom_geni_serial_shutdown, 1246 .type = qcom_geni_serial_get_type, 1247 .set_mctrl = qcom_geni_serial_set_mctrl, 1248 .get_mctrl = qcom_geni_serial_get_mctrl, 1249 .pm = qcom_geni_serial_pm, 1250 }; 1251 1252 static int qcom_geni_serial_probe(struct platform_device *pdev) 1253 { 1254 int ret = 0; 1255 int line = -1; 1256 struct qcom_geni_serial_port *port; 1257 struct uart_port *uport; 1258 struct resource *res; 1259 int irq; 1260 bool console = false; 1261 struct uart_driver *drv; 1262 1263 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) 1264 console = true; 1265 1266 if (pdev->dev.of_node) { 1267 if (console) { 1268 drv = &qcom_geni_console_driver; 1269 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1270 } else { 1271 drv = &qcom_geni_uart_driver; 1272 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1273 } 1274 } 1275 1276 port = get_port_from_line(line, console); 1277 if (IS_ERR(port)) { 1278 dev_err(&pdev->dev, "Invalid line %d\n", line); 1279 return PTR_ERR(port); 1280 } 1281 1282 uport = &port->uport; 1283 /* Don't allow 2 drivers to access the same port */ 1284 if (uport->private_data) 1285 return -ENODEV; 1286 1287 uport->dev = &pdev->dev; 1288 port->se.dev = &pdev->dev; 1289 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1290 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1291 if (IS_ERR(port->se.clk)) { 1292 ret = PTR_ERR(port->se.clk); 1293 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1294 return ret; 1295 } 1296 1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1298 if (!res) 1299 return -EINVAL; 1300 uport->mapbase = res->start; 1301 1302 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1303 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1304 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1305 1306 irq = platform_get_irq(pdev, 0); 1307 if (irq < 0) { 1308 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq); 1309 return irq; 1310 } 1311 uport->irq = irq; 1312 1313 uport->private_data = drv; 1314 platform_set_drvdata(pdev, port); 1315 port->handle_rx = console ? handle_rx_console : handle_rx_uart; 1316 if (!console) 1317 device_create_file(uport->dev, &dev_attr_loopback); 1318 return uart_add_one_port(drv, uport); 1319 } 1320 1321 static int qcom_geni_serial_remove(struct platform_device *pdev) 1322 { 1323 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1324 struct uart_driver *drv = port->uport.private_data; 1325 1326 uart_remove_one_port(drv, &port->uport); 1327 return 0; 1328 } 1329 1330 static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev) 1331 { 1332 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1333 struct uart_port *uport = &port->uport; 1334 1335 if (uart_console(uport)) { 1336 uart_suspend_port(uport->private_data, uport); 1337 } else { 1338 struct uart_state *state = uport->state; 1339 /* 1340 * If the port is open, deny system suspend. 1341 */ 1342 if (state->pm_state == UART_PM_STATE_ON) 1343 return -EBUSY; 1344 } 1345 1346 return 0; 1347 } 1348 1349 static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev) 1350 { 1351 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1352 struct uart_port *uport = &port->uport; 1353 1354 if (uart_console(uport) && 1355 console_suspend_enabled && uport->suspended) { 1356 uart_resume_port(uport->private_data, uport); 1357 /* 1358 * uart_suspend_port() invokes port shutdown which in turn 1359 * frees the irq. uart_resume_port invokes port startup which 1360 * performs request_irq. The request_irq auto-enables the IRQ. 1361 * In addition, resume_noirq implicitly enables the IRQ and 1362 * leads to an unbalanced IRQ enable warning. Disable the IRQ 1363 * before returning so that the warning is suppressed. 1364 */ 1365 disable_irq(uport->irq); 1366 } 1367 return 0; 1368 } 1369 1370 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1371 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq, 1372 qcom_geni_serial_sys_resume_noirq) 1373 }; 1374 1375 static const struct of_device_id qcom_geni_serial_match_table[] = { 1376 { .compatible = "qcom,geni-debug-uart", }, 1377 { .compatible = "qcom,geni-uart", }, 1378 {} 1379 }; 1380 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1381 1382 static struct platform_driver qcom_geni_serial_platform_driver = { 1383 .remove = qcom_geni_serial_remove, 1384 .probe = qcom_geni_serial_probe, 1385 .driver = { 1386 .name = "qcom_geni_serial", 1387 .of_match_table = qcom_geni_serial_match_table, 1388 .pm = &qcom_geni_serial_pm_ops, 1389 }, 1390 }; 1391 1392 static int __init qcom_geni_serial_init(void) 1393 { 1394 int ret; 1395 1396 ret = console_register(&qcom_geni_console_driver); 1397 if (ret) 1398 return ret; 1399 1400 ret = uart_register_driver(&qcom_geni_uart_driver); 1401 if (ret) { 1402 console_unregister(&qcom_geni_console_driver); 1403 return ret; 1404 } 1405 1406 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1407 if (ret) { 1408 console_unregister(&qcom_geni_console_driver); 1409 uart_unregister_driver(&qcom_geni_uart_driver); 1410 } 1411 return ret; 1412 } 1413 module_init(qcom_geni_serial_init); 1414 1415 static void __exit qcom_geni_serial_exit(void) 1416 { 1417 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1418 console_unregister(&qcom_geni_console_driver); 1419 uart_unregister_driver(&qcom_geni_uart_driver); 1420 } 1421 module_exit(qcom_geni_serial_exit); 1422 1423 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1424 MODULE_LICENSE("GPL v2"); 1425