1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_opp.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/soc/qcom/geni-se.h> 19 #include <linux/serial.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty.h> 23 #include <linux/tty_flip.h> 24 #include <dt-bindings/interconnect/qcom,icc.h> 25 26 /* UART specific GENI registers */ 27 #define SE_UART_LOOPBACK_CFG 0x22c 28 #define SE_UART_IO_MACRO_CTRL 0x240 29 #define SE_UART_TX_TRANS_CFG 0x25c 30 #define SE_UART_TX_WORD_LEN 0x268 31 #define SE_UART_TX_STOP_BIT_LEN 0x26c 32 #define SE_UART_TX_TRANS_LEN 0x270 33 #define SE_UART_RX_TRANS_CFG 0x280 34 #define SE_UART_RX_WORD_LEN 0x28c 35 #define SE_UART_RX_STALE_CNT 0x294 36 #define SE_UART_TX_PARITY_CFG 0x2a4 37 #define SE_UART_RX_PARITY_CFG 0x2a8 38 #define SE_UART_MANUAL_RFR 0x2ac 39 40 /* SE_UART_TRANS_CFG */ 41 #define UART_TX_PAR_EN BIT(0) 42 #define UART_CTS_MASK BIT(1) 43 44 /* SE_UART_TX_STOP_BIT_LEN */ 45 #define TX_STOP_BIT_LEN_1 0 46 #define TX_STOP_BIT_LEN_2 2 47 48 /* SE_UART_RX_TRANS_CFG */ 49 #define UART_RX_PAR_EN BIT(3) 50 51 /* SE_UART_RX_WORD_LEN */ 52 #define RX_WORD_LEN_MASK GENMASK(9, 0) 53 54 /* SE_UART_RX_STALE_CNT */ 55 #define RX_STALE_CNT GENMASK(23, 0) 56 57 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 58 #define PAR_CALC_EN BIT(0) 59 #define PAR_EVEN 0x00 60 #define PAR_ODD 0x01 61 #define PAR_SPACE 0x10 62 63 /* SE_UART_MANUAL_RFR register fields */ 64 #define UART_MANUAL_RFR_EN BIT(31) 65 #define UART_RFR_NOT_READY BIT(1) 66 #define UART_RFR_READY BIT(0) 67 68 /* UART M_CMD OP codes */ 69 #define UART_START_TX 0x1 70 /* UART S_CMD OP codes */ 71 #define UART_START_READ 0x1 72 #define UART_PARAM 0x1 73 #define UART_PARAM_RFR_OPEN BIT(7) 74 75 #define UART_OVERSAMPLING 32 76 #define STALE_TIMEOUT 16 77 #define DEFAULT_BITS_PER_CHAR 10 78 #define GENI_UART_CONS_PORTS 1 79 #define GENI_UART_PORTS 3 80 #define DEF_FIFO_DEPTH_WORDS 16 81 #define DEF_TX_WM 2 82 #define DEF_FIFO_WIDTH_BITS 32 83 #define UART_RX_WM 2 84 85 /* SE_UART_LOOPBACK_CFG */ 86 #define RX_TX_SORTED BIT(0) 87 #define CTS_RTS_SORTED BIT(1) 88 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 89 90 /* UART pin swap value */ 91 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 92 #define IO_MACRO_IO0_SEL 0x3 93 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 94 #define IO_MACRO_IO2_IO3_SWAP 0x4640 95 96 /* We always configure 4 bytes per FIFO word */ 97 #define BYTES_PER_FIFO_WORD 4U 98 99 #define DMA_RX_BUF_SIZE 2048 100 101 struct qcom_geni_device_data { 102 bool console; 103 enum geni_se_xfer_mode mode; 104 }; 105 106 struct qcom_geni_private_data { 107 /* NOTE: earlycon port will have NULL here */ 108 struct uart_driver *drv; 109 110 u32 poll_cached_bytes; 111 unsigned int poll_cached_bytes_cnt; 112 113 u32 write_cached_bytes; 114 unsigned int write_cached_bytes_cnt; 115 }; 116 117 struct qcom_geni_serial_port { 118 struct uart_port uport; 119 struct geni_se se; 120 const char *name; 121 u32 tx_fifo_depth; 122 u32 tx_fifo_width; 123 u32 rx_fifo_depth; 124 dma_addr_t tx_dma_addr; 125 dma_addr_t rx_dma_addr; 126 bool setup; 127 unsigned long poll_timeout_us; 128 unsigned long clk_rate; 129 void *rx_buf; 130 u32 loopback; 131 bool brk; 132 133 unsigned int tx_remaining; 134 int wakeup_irq; 135 bool rx_tx_swap; 136 bool cts_rts_swap; 137 138 struct qcom_geni_private_data private_data; 139 const struct qcom_geni_device_data *dev_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 148 { 149 return container_of(uport, struct qcom_geni_serial_port, uport); 150 } 151 152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 153 [0] = { 154 .uport = { 155 .iotype = UPIO_MEM, 156 .ops = &qcom_geni_uart_pops, 157 .flags = UPF_BOOT_AUTOCONF, 158 .line = 0, 159 }, 160 }, 161 [1] = { 162 .uport = { 163 .iotype = UPIO_MEM, 164 .ops = &qcom_geni_uart_pops, 165 .flags = UPF_BOOT_AUTOCONF, 166 .line = 1, 167 }, 168 }, 169 [2] = { 170 .uport = { 171 .iotype = UPIO_MEM, 172 .ops = &qcom_geni_uart_pops, 173 .flags = UPF_BOOT_AUTOCONF, 174 .line = 2, 175 }, 176 }, 177 }; 178 179 static struct qcom_geni_serial_port qcom_geni_console_port = { 180 .uport = { 181 .iotype = UPIO_MEM, 182 .ops = &qcom_geni_console_pops, 183 .flags = UPF_BOOT_AUTOCONF, 184 .line = 0, 185 }, 186 }; 187 188 static int qcom_geni_serial_request_port(struct uart_port *uport) 189 { 190 struct platform_device *pdev = to_platform_device(uport->dev); 191 struct qcom_geni_serial_port *port = to_dev_port(uport); 192 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); 194 if (IS_ERR(uport->membase)) 195 return PTR_ERR(uport->membase); 196 port->se.base = uport->membase; 197 return 0; 198 } 199 200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 201 { 202 if (cfg_flags & UART_CONFIG_TYPE) { 203 uport->type = PORT_MSM; 204 qcom_geni_serial_request_port(uport); 205 } 206 } 207 208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 209 { 210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 211 u32 geni_ios; 212 213 if (uart_console(uport)) { 214 mctrl |= TIOCM_CTS; 215 } else { 216 geni_ios = readl(uport->membase + SE_GENI_IOS); 217 if (!(geni_ios & IO2_DATA_IN)) 218 mctrl |= TIOCM_CTS; 219 } 220 221 return mctrl; 222 } 223 224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 225 unsigned int mctrl) 226 { 227 u32 uart_manual_rfr = 0; 228 struct qcom_geni_serial_port *port = to_dev_port(uport); 229 230 if (uart_console(uport)) 231 return; 232 233 if (mctrl & TIOCM_LOOP) 234 port->loopback = RX_TX_CTS_RTS_SORTED; 235 236 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 239 } 240 241 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 242 { 243 return "MSM"; 244 } 245 246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 247 { 248 struct qcom_geni_serial_port *port; 249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 250 251 if (line < 0 || line >= nr_ports) 252 return ERR_PTR(-ENXIO); 253 254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 255 return port; 256 } 257 258 static bool qcom_geni_serial_main_active(struct uart_port *uport) 259 { 260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 261 } 262 263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 264 { 265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 266 } 267 268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 269 int offset, int field, bool set) 270 { 271 u32 reg; 272 struct qcom_geni_serial_port *port; 273 unsigned long timeout_us = 20000; 274 struct qcom_geni_private_data *private_data = uport->private_data; 275 276 if (private_data->drv) { 277 port = to_dev_port(uport); 278 if (port->poll_timeout_us) 279 timeout_us = port->poll_timeout_us; 280 } 281 282 /* 283 * Use custom implementation instead of readl_poll_atomic since ktimer 284 * is not ready at the time of early console. 285 */ 286 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 287 while (timeout_us) { 288 reg = readl(uport->membase + offset); 289 if ((bool)(reg & field) == set) 290 return true; 291 udelay(10); 292 timeout_us -= 10; 293 } 294 return false; 295 } 296 297 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 298 { 299 u32 m_cmd; 300 301 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 302 m_cmd = UART_START_TX << M_OPCODE_SHFT; 303 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 304 } 305 306 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 307 { 308 int done; 309 u32 irq_clear = M_CMD_DONE_EN; 310 311 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 312 M_CMD_DONE_EN, true); 313 if (!done) { 314 writel(M_GENI_CMD_ABORT, uport->membase + 315 SE_GENI_M_CMD_CTRL_REG); 316 irq_clear |= M_CMD_ABORT_EN; 317 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 318 M_CMD_ABORT_EN, true); 319 } 320 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 321 } 322 323 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 324 { 325 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 326 327 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 328 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 329 S_GENI_CMD_ABORT, false); 330 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 331 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 332 } 333 334 #ifdef CONFIG_CONSOLE_POLL 335 static int qcom_geni_serial_get_char(struct uart_port *uport) 336 { 337 struct qcom_geni_private_data *private_data = uport->private_data; 338 u32 status; 339 u32 word_cnt; 340 int ret; 341 342 if (!private_data->poll_cached_bytes_cnt) { 343 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 344 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 345 346 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 347 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 348 349 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 350 word_cnt = status & RX_FIFO_WC_MSK; 351 if (!word_cnt) 352 return NO_POLL_CHAR; 353 354 if (word_cnt == 1 && (status & RX_LAST)) 355 /* 356 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 357 * treated as if it was BYTES_PER_FIFO_WORD. 358 */ 359 private_data->poll_cached_bytes_cnt = 360 (status & RX_LAST_BYTE_VALID_MSK) >> 361 RX_LAST_BYTE_VALID_SHFT; 362 363 if (private_data->poll_cached_bytes_cnt == 0) 364 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 365 366 private_data->poll_cached_bytes = 367 readl(uport->membase + SE_GENI_RX_FIFOn); 368 } 369 370 private_data->poll_cached_bytes_cnt--; 371 ret = private_data->poll_cached_bytes & 0xff; 372 private_data->poll_cached_bytes >>= 8; 373 374 return ret; 375 } 376 377 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 378 unsigned char c) 379 { 380 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 381 qcom_geni_serial_setup_tx(uport, 1); 382 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 383 M_TX_FIFO_WATERMARK_EN, true)); 384 writel(c, uport->membase + SE_GENI_TX_FIFOn); 385 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 386 qcom_geni_serial_poll_tx_done(uport); 387 } 388 #endif 389 390 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 391 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 392 { 393 struct qcom_geni_private_data *private_data = uport->private_data; 394 395 private_data->write_cached_bytes = 396 (private_data->write_cached_bytes >> 8) | (ch << 24); 397 private_data->write_cached_bytes_cnt++; 398 399 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 400 writel(private_data->write_cached_bytes, 401 uport->membase + SE_GENI_TX_FIFOn); 402 private_data->write_cached_bytes_cnt = 0; 403 } 404 } 405 406 static void 407 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 408 unsigned int count) 409 { 410 struct qcom_geni_private_data *private_data = uport->private_data; 411 412 int i; 413 u32 bytes_to_send = count; 414 415 for (i = 0; i < count; i++) { 416 /* 417 * uart_console_write() adds a carriage return for each newline. 418 * Account for additional bytes to be written. 419 */ 420 if (s[i] == '\n') 421 bytes_to_send++; 422 } 423 424 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 425 qcom_geni_serial_setup_tx(uport, bytes_to_send); 426 for (i = 0; i < count; ) { 427 size_t chars_to_write = 0; 428 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 429 430 /* 431 * If the WM bit never set, then the Tx state machine is not 432 * in a valid state, so break, cancel/abort any existing 433 * command. Unfortunately the current data being written is 434 * lost. 435 */ 436 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 437 M_TX_FIFO_WATERMARK_EN, true)) 438 break; 439 chars_to_write = min_t(size_t, count - i, avail / 2); 440 uart_console_write(uport, s + i, chars_to_write, 441 qcom_geni_serial_wr_char); 442 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 443 SE_GENI_M_IRQ_CLEAR); 444 i += chars_to_write; 445 } 446 447 if (private_data->write_cached_bytes_cnt) { 448 private_data->write_cached_bytes >>= BITS_PER_BYTE * 449 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 450 writel(private_data->write_cached_bytes, 451 uport->membase + SE_GENI_TX_FIFOn); 452 private_data->write_cached_bytes_cnt = 0; 453 } 454 455 qcom_geni_serial_poll_tx_done(uport); 456 } 457 458 static void qcom_geni_serial_console_write(struct console *co, const char *s, 459 unsigned int count) 460 { 461 struct uart_port *uport; 462 struct qcom_geni_serial_port *port; 463 bool locked = true; 464 unsigned long flags; 465 u32 geni_status; 466 u32 irq_en; 467 468 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 469 470 port = get_port_from_line(co->index, true); 471 if (IS_ERR(port)) 472 return; 473 474 uport = &port->uport; 475 if (oops_in_progress) 476 locked = spin_trylock_irqsave(&uport->lock, flags); 477 else 478 spin_lock_irqsave(&uport->lock, flags); 479 480 geni_status = readl(uport->membase + SE_GENI_STATUS); 481 482 /* Cancel the current write to log the fault */ 483 if (!locked) { 484 geni_se_cancel_m_cmd(&port->se); 485 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 486 M_CMD_CANCEL_EN, true)) { 487 geni_se_abort_m_cmd(&port->se); 488 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 489 M_CMD_ABORT_EN, true); 490 writel(M_CMD_ABORT_EN, uport->membase + 491 SE_GENI_M_IRQ_CLEAR); 492 } 493 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 494 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 495 /* 496 * It seems we can't interrupt existing transfers if all data 497 * has been sent, in which case we need to look for done first. 498 */ 499 qcom_geni_serial_poll_tx_done(uport); 500 501 if (!uart_circ_empty(&uport->state->xmit)) { 502 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 503 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 504 uport->membase + SE_GENI_M_IRQ_EN); 505 } 506 } 507 508 __qcom_geni_serial_console_write(uport, s, count); 509 510 if (port->tx_remaining) 511 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 512 513 if (locked) 514 spin_unlock_irqrestore(&uport->lock, flags); 515 } 516 517 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 518 { 519 u32 i; 520 unsigned char buf[sizeof(u32)]; 521 struct tty_port *tport; 522 struct qcom_geni_serial_port *port = to_dev_port(uport); 523 524 tport = &uport->state->port; 525 for (i = 0; i < bytes; ) { 526 int c; 527 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 528 529 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 530 i += chunk; 531 if (drop) 532 continue; 533 534 for (c = 0; c < chunk; c++) { 535 int sysrq; 536 537 uport->icount.rx++; 538 if (port->brk && buf[c] == 0) { 539 port->brk = false; 540 if (uart_handle_break(uport)) 541 continue; 542 } 543 544 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 545 546 if (!sysrq) 547 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 548 } 549 } 550 if (!drop) 551 tty_flip_buffer_push(tport); 552 } 553 #else 554 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 555 { 556 557 } 558 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 559 560 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 561 { 562 struct qcom_geni_serial_port *port = to_dev_port(uport); 563 struct tty_port *tport = &uport->state->port; 564 int ret; 565 566 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 567 if (ret != bytes) { 568 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 569 __func__, ret, bytes); 570 WARN_ON_ONCE(1); 571 } 572 uport->icount.rx += ret; 573 tty_flip_buffer_push(tport); 574 } 575 576 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 577 { 578 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 579 } 580 581 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 582 { 583 struct qcom_geni_serial_port *port = to_dev_port(uport); 584 bool done; 585 586 if (!qcom_geni_serial_main_active(uport)) 587 return; 588 589 if (port->tx_dma_addr) { 590 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 591 port->tx_remaining); 592 port->tx_dma_addr = 0; 593 port->tx_remaining = 0; 594 } 595 596 geni_se_cancel_m_cmd(&port->se); 597 598 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 599 M_CMD_CANCEL_EN, true); 600 if (!done) { 601 geni_se_abort_m_cmd(&port->se); 602 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 603 M_CMD_ABORT_EN, true); 604 if (!done) 605 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 606 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 607 } 608 609 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 610 } 611 612 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 613 { 614 struct qcom_geni_serial_port *port = to_dev_port(uport); 615 struct circ_buf *xmit = &uport->state->xmit; 616 unsigned int xmit_size; 617 int ret; 618 619 if (port->tx_dma_addr) 620 return; 621 622 if (uart_circ_empty(xmit)) 623 return; 624 625 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 626 627 qcom_geni_serial_setup_tx(uport, xmit_size); 628 629 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], 630 xmit_size, &port->tx_dma_addr); 631 if (ret) { 632 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 633 qcom_geni_serial_stop_tx_dma(uport); 634 return; 635 } 636 637 port->tx_remaining = xmit_size; 638 } 639 640 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 641 { 642 u32 irq_en; 643 644 if (qcom_geni_serial_main_active(uport) || 645 !qcom_geni_serial_tx_empty(uport)) 646 return; 647 648 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 649 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 650 651 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 652 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 653 } 654 655 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 656 { 657 u32 irq_en; 658 struct qcom_geni_serial_port *port = to_dev_port(uport); 659 660 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 661 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 662 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 663 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 664 /* Possible stop tx is called multiple times. */ 665 if (!qcom_geni_serial_main_active(uport)) 666 return; 667 668 geni_se_cancel_m_cmd(&port->se); 669 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 670 M_CMD_CANCEL_EN, true)) { 671 geni_se_abort_m_cmd(&port->se); 672 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 673 M_CMD_ABORT_EN, true); 674 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 675 } 676 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 677 } 678 679 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 680 { 681 u32 status; 682 u32 word_cnt; 683 u32 last_word_byte_cnt; 684 u32 last_word_partial; 685 u32 total_bytes; 686 687 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 688 word_cnt = status & RX_FIFO_WC_MSK; 689 last_word_partial = status & RX_LAST; 690 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 691 RX_LAST_BYTE_VALID_SHFT; 692 693 if (!word_cnt) 694 return; 695 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 696 if (last_word_partial && last_word_byte_cnt) 697 total_bytes += last_word_byte_cnt; 698 else 699 total_bytes += BYTES_PER_FIFO_WORD; 700 handle_rx_console(uport, total_bytes, drop); 701 } 702 703 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 704 { 705 u32 irq_en; 706 struct qcom_geni_serial_port *port = to_dev_port(uport); 707 u32 s_irq_status; 708 709 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 710 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 711 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 712 713 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 714 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 715 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 716 717 if (!qcom_geni_serial_secondary_active(uport)) 718 return; 719 720 geni_se_cancel_s_cmd(&port->se); 721 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 722 S_CMD_CANCEL_EN, true); 723 /* 724 * If timeout occurs secondary engine remains active 725 * and Abort sequence is executed. 726 */ 727 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 728 /* Flush the Rx buffer */ 729 if (s_irq_status & S_RX_FIFO_LAST_EN) 730 qcom_geni_serial_handle_rx_fifo(uport, true); 731 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 732 733 if (qcom_geni_serial_secondary_active(uport)) 734 qcom_geni_serial_abort_rx(uport); 735 } 736 737 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 738 { 739 u32 irq_en; 740 struct qcom_geni_serial_port *port = to_dev_port(uport); 741 742 if (qcom_geni_serial_secondary_active(uport)) 743 qcom_geni_serial_stop_rx_fifo(uport); 744 745 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 746 747 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 748 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 749 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 750 751 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 752 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 753 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 754 } 755 756 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 757 { 758 struct qcom_geni_serial_port *port = to_dev_port(uport); 759 760 if (!qcom_geni_serial_secondary_active(uport)) 761 return; 762 763 geni_se_cancel_s_cmd(&port->se); 764 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 765 S_CMD_CANCEL_EN, true); 766 767 if (qcom_geni_serial_secondary_active(uport)) 768 qcom_geni_serial_abort_rx(uport); 769 770 if (port->rx_dma_addr) { 771 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 772 DMA_RX_BUF_SIZE); 773 port->rx_dma_addr = 0; 774 } 775 } 776 777 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 778 { 779 struct qcom_geni_serial_port *port = to_dev_port(uport); 780 int ret; 781 782 if (qcom_geni_serial_secondary_active(uport)) 783 qcom_geni_serial_stop_rx_dma(uport); 784 785 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 786 787 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 788 DMA_RX_BUF_SIZE, 789 &port->rx_dma_addr); 790 if (ret) { 791 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 792 qcom_geni_serial_stop_rx_dma(uport); 793 } 794 } 795 796 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 797 { 798 struct qcom_geni_serial_port *port = to_dev_port(uport); 799 u32 rx_in; 800 int ret; 801 802 if (!qcom_geni_serial_secondary_active(uport)) 803 return; 804 805 if (!port->rx_dma_addr) 806 return; 807 808 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 809 port->rx_dma_addr = 0; 810 811 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 812 if (!rx_in) { 813 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 814 return; 815 } 816 817 if (!drop) 818 handle_rx_uart(uport, rx_in, drop); 819 820 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 821 DMA_RX_BUF_SIZE, 822 &port->rx_dma_addr); 823 if (ret) { 824 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 825 qcom_geni_serial_stop_rx_dma(uport); 826 } 827 } 828 829 static void qcom_geni_serial_start_rx(struct uart_port *uport) 830 { 831 uport->ops->start_rx(uport); 832 } 833 834 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 835 { 836 uport->ops->stop_rx(uport); 837 } 838 839 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 840 { 841 uport->ops->stop_tx(uport); 842 } 843 844 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 845 unsigned int chunk) 846 { 847 struct qcom_geni_serial_port *port = to_dev_port(uport); 848 struct circ_buf *xmit = &uport->state->xmit; 849 unsigned int tx_bytes, c, remaining = chunk; 850 u8 buf[BYTES_PER_FIFO_WORD]; 851 852 while (remaining) { 853 memset(buf, 0, sizeof(buf)); 854 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 855 856 for (c = 0; c < tx_bytes ; c++) { 857 buf[c] = xmit->buf[xmit->tail]; 858 uart_xmit_advance(uport, 1); 859 } 860 861 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 862 863 remaining -= tx_bytes; 864 port->tx_remaining -= tx_bytes; 865 } 866 } 867 868 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 869 bool done, bool active) 870 { 871 struct qcom_geni_serial_port *port = to_dev_port(uport); 872 struct circ_buf *xmit = &uport->state->xmit; 873 size_t avail; 874 size_t pending; 875 u32 status; 876 u32 irq_en; 877 unsigned int chunk; 878 879 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 880 881 /* Complete the current tx command before taking newly added data */ 882 if (active) 883 pending = port->tx_remaining; 884 else 885 pending = uart_circ_chars_pending(xmit); 886 887 /* All data has been transmitted and acknowledged as received */ 888 if (!pending && !status && done) { 889 qcom_geni_serial_stop_tx_fifo(uport); 890 goto out_write_wakeup; 891 } 892 893 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 894 avail *= BYTES_PER_FIFO_WORD; 895 896 chunk = min(avail, pending); 897 if (!chunk) 898 goto out_write_wakeup; 899 900 if (!port->tx_remaining) { 901 qcom_geni_serial_setup_tx(uport, pending); 902 port->tx_remaining = pending; 903 904 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 905 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 906 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 907 uport->membase + SE_GENI_M_IRQ_EN); 908 } 909 910 qcom_geni_serial_send_chunk_fifo(uport, chunk); 911 912 /* 913 * The tx fifo watermark is level triggered and latched. Though we had 914 * cleared it in qcom_geni_serial_isr it will have already reasserted 915 * so we must clear it again here after our writes. 916 */ 917 writel(M_TX_FIFO_WATERMARK_EN, 918 uport->membase + SE_GENI_M_IRQ_CLEAR); 919 920 out_write_wakeup: 921 if (!port->tx_remaining) { 922 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 923 if (irq_en & M_TX_FIFO_WATERMARK_EN) 924 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 925 uport->membase + SE_GENI_M_IRQ_EN); 926 } 927 928 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 929 uart_write_wakeup(uport); 930 } 931 932 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 933 { 934 struct qcom_geni_serial_port *port = to_dev_port(uport); 935 struct circ_buf *xmit = &uport->state->xmit; 936 937 uart_xmit_advance(uport, port->tx_remaining); 938 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 939 port->tx_dma_addr = 0; 940 port->tx_remaining = 0; 941 942 if (!uart_circ_empty(xmit)) 943 qcom_geni_serial_start_tx_dma(uport); 944 945 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 946 uart_write_wakeup(uport); 947 } 948 949 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 950 { 951 u32 m_irq_en; 952 u32 m_irq_status; 953 u32 s_irq_status; 954 u32 geni_status; 955 u32 dma; 956 u32 dma_tx_status; 957 u32 dma_rx_status; 958 struct uart_port *uport = dev; 959 bool drop_rx = false; 960 struct tty_port *tport = &uport->state->port; 961 struct qcom_geni_serial_port *port = to_dev_port(uport); 962 963 if (uport->suspended) 964 return IRQ_NONE; 965 966 spin_lock(&uport->lock); 967 968 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 969 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 970 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 971 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 972 geni_status = readl(uport->membase + SE_GENI_STATUS); 973 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 974 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 975 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 976 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 977 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 978 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 979 980 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 981 goto out_unlock; 982 983 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 984 uport->icount.overrun++; 985 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 986 } 987 988 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 989 if (s_irq_status & S_GP_IRQ_0_EN) 990 uport->icount.parity++; 991 drop_rx = true; 992 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 993 uport->icount.brk++; 994 port->brk = true; 995 } 996 997 if (dma) { 998 if (dma_tx_status & TX_DMA_DONE) 999 qcom_geni_serial_handle_tx_dma(uport); 1000 1001 if (dma_rx_status) { 1002 if (dma_rx_status & RX_RESET_DONE) 1003 goto out_unlock; 1004 1005 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1006 uport->icount.parity++; 1007 drop_rx = true; 1008 } 1009 1010 if (dma_rx_status & RX_DMA_BREAK) 1011 uport->icount.brk++; 1012 1013 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1014 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1015 } 1016 } else { 1017 if (m_irq_status & m_irq_en & 1018 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1019 qcom_geni_serial_handle_tx_fifo(uport, 1020 m_irq_status & M_CMD_DONE_EN, 1021 geni_status & M_GENI_CMD_ACTIVE); 1022 1023 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1024 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1025 } 1026 1027 out_unlock: 1028 uart_unlock_and_check_sysrq(uport); 1029 1030 return IRQ_HANDLED; 1031 } 1032 1033 static int setup_fifos(struct qcom_geni_serial_port *port) 1034 { 1035 struct uart_port *uport; 1036 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1037 1038 uport = &port->uport; 1039 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1040 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1041 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1042 uport->fifosize = 1043 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1044 1045 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1046 /* 1047 * Use krealloc rather than krealloc_array because rx_buf is 1048 * accessed as 1 byte entries as well as 4 byte entries so it's 1049 * not necessarily an array. 1050 */ 1051 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1052 port->rx_fifo_depth * sizeof(u32), 1053 GFP_KERNEL); 1054 if (!port->rx_buf) 1055 return -ENOMEM; 1056 } 1057 1058 return 0; 1059 } 1060 1061 1062 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1063 { 1064 disable_irq(uport->irq); 1065 1066 if (uart_console(uport)) 1067 return; 1068 1069 qcom_geni_serial_stop_tx(uport); 1070 qcom_geni_serial_stop_rx(uport); 1071 } 1072 1073 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1074 { 1075 struct qcom_geni_serial_port *port = to_dev_port(uport); 1076 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1077 u32 proto; 1078 u32 pin_swap; 1079 int ret; 1080 1081 proto = geni_se_read_proto(&port->se); 1082 if (proto != GENI_SE_UART) { 1083 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1084 return -ENXIO; 1085 } 1086 1087 qcom_geni_serial_stop_rx(uport); 1088 1089 ret = setup_fifos(port); 1090 if (ret) 1091 return ret; 1092 1093 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1094 1095 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1096 if (port->rx_tx_swap) { 1097 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1098 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1099 } 1100 if (port->cts_rts_swap) { 1101 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1102 pin_swap |= IO_MACRO_IO0_SEL; 1103 } 1104 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1105 if (port->rx_tx_swap || port->cts_rts_swap) 1106 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1107 1108 /* 1109 * Make an unconditional cancel on the main sequencer to reset 1110 * it else we could end up in data loss scenarios. 1111 */ 1112 if (uart_console(uport)) 1113 qcom_geni_serial_poll_tx_done(uport); 1114 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1115 false, true, true); 1116 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1117 geni_se_select_mode(&port->se, port->dev_data->mode); 1118 qcom_geni_serial_start_rx(uport); 1119 port->setup = true; 1120 1121 return 0; 1122 } 1123 1124 static int qcom_geni_serial_startup(struct uart_port *uport) 1125 { 1126 int ret; 1127 struct qcom_geni_serial_port *port = to_dev_port(uport); 1128 1129 if (!port->setup) { 1130 ret = qcom_geni_serial_port_setup(uport); 1131 if (ret) 1132 return ret; 1133 } 1134 enable_irq(uport->irq); 1135 1136 return 0; 1137 } 1138 1139 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1140 unsigned int *clk_div, unsigned int percent_tol) 1141 { 1142 unsigned long freq; 1143 unsigned long div, maxdiv; 1144 u64 mult; 1145 unsigned long offset, abs_tol, achieved; 1146 1147 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1148 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1149 div = 1; 1150 while (div <= maxdiv) { 1151 mult = (u64)div * desired_clk; 1152 if (mult != (unsigned long)mult) 1153 break; 1154 1155 offset = div * abs_tol; 1156 freq = clk_round_rate(clk, mult - offset); 1157 1158 /* Can only get lower if we're done */ 1159 if (freq < mult - offset) 1160 break; 1161 1162 /* 1163 * Re-calculate div in case rounding skipped rates but we 1164 * ended up at a good one, then check for a match. 1165 */ 1166 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1167 achieved = DIV_ROUND_CLOSEST(freq, div); 1168 if (achieved <= desired_clk + abs_tol && 1169 achieved >= desired_clk - abs_tol) { 1170 *clk_div = div; 1171 return freq; 1172 } 1173 1174 div = DIV_ROUND_UP(freq, desired_clk); 1175 } 1176 1177 return 0; 1178 } 1179 1180 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1181 unsigned int sampling_rate, unsigned int *clk_div) 1182 { 1183 unsigned long ser_clk; 1184 unsigned long desired_clk; 1185 1186 desired_clk = baud * sampling_rate; 1187 if (!desired_clk) 1188 return 0; 1189 1190 /* 1191 * try to find a clock rate within 2% tolerance, then within 5% 1192 */ 1193 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1194 if (!ser_clk) 1195 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1196 1197 return ser_clk; 1198 } 1199 1200 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1201 struct ktermios *termios, 1202 const struct ktermios *old) 1203 { 1204 unsigned int baud; 1205 u32 bits_per_char; 1206 u32 tx_trans_cfg; 1207 u32 tx_parity_cfg; 1208 u32 rx_trans_cfg; 1209 u32 rx_parity_cfg; 1210 u32 stop_bit_len; 1211 unsigned int clk_div; 1212 u32 ser_clk_cfg; 1213 struct qcom_geni_serial_port *port = to_dev_port(uport); 1214 unsigned long clk_rate; 1215 u32 ver, sampling_rate; 1216 unsigned int avg_bw_core; 1217 unsigned long timeout; 1218 1219 qcom_geni_serial_stop_rx(uport); 1220 /* baud rate */ 1221 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1222 1223 sampling_rate = UART_OVERSAMPLING; 1224 /* Sampling rate is halved for IP versions >= 2.5 */ 1225 ver = geni_se_get_qup_hw_version(&port->se); 1226 if (ver >= QUP_SE_VERSION_2_5) 1227 sampling_rate /= 2; 1228 1229 clk_rate = get_clk_div_rate(port->se.clk, baud, 1230 sampling_rate, &clk_div); 1231 if (!clk_rate) { 1232 dev_err(port->se.dev, 1233 "Couldn't find suitable clock rate for %u\n", 1234 baud * sampling_rate); 1235 goto out_restart_rx; 1236 } 1237 1238 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", 1239 baud * sampling_rate, clk_rate, clk_div); 1240 1241 uport->uartclk = clk_rate; 1242 port->clk_rate = clk_rate; 1243 dev_pm_opp_set_rate(uport->dev, clk_rate); 1244 ser_clk_cfg = SER_CLK_EN; 1245 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1246 1247 /* 1248 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1249 * only. 1250 */ 1251 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1252 : GENI_DEFAULT_BW; 1253 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1254 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1255 geni_icc_set_bw(&port->se); 1256 1257 /* parity */ 1258 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1259 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1260 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1261 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1262 if (termios->c_cflag & PARENB) { 1263 tx_trans_cfg |= UART_TX_PAR_EN; 1264 rx_trans_cfg |= UART_RX_PAR_EN; 1265 tx_parity_cfg |= PAR_CALC_EN; 1266 rx_parity_cfg |= PAR_CALC_EN; 1267 if (termios->c_cflag & PARODD) { 1268 tx_parity_cfg |= PAR_ODD; 1269 rx_parity_cfg |= PAR_ODD; 1270 } else if (termios->c_cflag & CMSPAR) { 1271 tx_parity_cfg |= PAR_SPACE; 1272 rx_parity_cfg |= PAR_SPACE; 1273 } else { 1274 tx_parity_cfg |= PAR_EVEN; 1275 rx_parity_cfg |= PAR_EVEN; 1276 } 1277 } else { 1278 tx_trans_cfg &= ~UART_TX_PAR_EN; 1279 rx_trans_cfg &= ~UART_RX_PAR_EN; 1280 tx_parity_cfg &= ~PAR_CALC_EN; 1281 rx_parity_cfg &= ~PAR_CALC_EN; 1282 } 1283 1284 /* bits per char */ 1285 bits_per_char = tty_get_char_size(termios->c_cflag); 1286 1287 /* stop bits */ 1288 if (termios->c_cflag & CSTOPB) 1289 stop_bit_len = TX_STOP_BIT_LEN_2; 1290 else 1291 stop_bit_len = TX_STOP_BIT_LEN_1; 1292 1293 /* flow control, clear the CTS_MASK bit if using flow control. */ 1294 if (termios->c_cflag & CRTSCTS) 1295 tx_trans_cfg &= ~UART_CTS_MASK; 1296 else 1297 tx_trans_cfg |= UART_CTS_MASK; 1298 1299 if (baud) { 1300 uart_update_timeout(uport, termios->c_cflag, baud); 1301 1302 /* 1303 * Make sure that qcom_geni_serial_poll_bitfield() waits for 1304 * the FIFO, two-word intermediate transfer register and shift 1305 * register to clear. 1306 * 1307 * Note that uart_fifo_timeout() also adds a 20 ms margin. 1308 */ 1309 timeout = jiffies_to_usecs(uart_fifo_timeout(uport)); 1310 timeout += 3 * timeout / port->tx_fifo_depth; 1311 WRITE_ONCE(port->poll_timeout_us, timeout); 1312 } 1313 1314 if (!uart_console(uport)) 1315 writel(port->loopback, 1316 uport->membase + SE_UART_LOOPBACK_CFG); 1317 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1318 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1319 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1320 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1321 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1322 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1323 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1324 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1325 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1326 out_restart_rx: 1327 qcom_geni_serial_start_rx(uport); 1328 } 1329 1330 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1331 static int qcom_geni_console_setup(struct console *co, char *options) 1332 { 1333 struct uart_port *uport; 1334 struct qcom_geni_serial_port *port; 1335 int baud = 115200; 1336 int bits = 8; 1337 int parity = 'n'; 1338 int flow = 'n'; 1339 int ret; 1340 1341 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1342 return -ENXIO; 1343 1344 port = get_port_from_line(co->index, true); 1345 if (IS_ERR(port)) { 1346 pr_err("Invalid line %d\n", co->index); 1347 return PTR_ERR(port); 1348 } 1349 1350 uport = &port->uport; 1351 1352 if (unlikely(!uport->membase)) 1353 return -ENXIO; 1354 1355 if (!port->setup) { 1356 ret = qcom_geni_serial_port_setup(uport); 1357 if (ret) 1358 return ret; 1359 } 1360 1361 if (options) 1362 uart_parse_options(options, &baud, &parity, &bits, &flow); 1363 1364 return uart_set_options(uport, co, baud, parity, bits, flow); 1365 } 1366 1367 static void qcom_geni_serial_earlycon_write(struct console *con, 1368 const char *s, unsigned int n) 1369 { 1370 struct earlycon_device *dev = con->data; 1371 1372 __qcom_geni_serial_console_write(&dev->port, s, n); 1373 } 1374 1375 #ifdef CONFIG_CONSOLE_POLL 1376 static int qcom_geni_serial_earlycon_read(struct console *con, 1377 char *s, unsigned int n) 1378 { 1379 struct earlycon_device *dev = con->data; 1380 struct uart_port *uport = &dev->port; 1381 int num_read = 0; 1382 int ch; 1383 1384 while (num_read < n) { 1385 ch = qcom_geni_serial_get_char(uport); 1386 if (ch == NO_POLL_CHAR) 1387 break; 1388 s[num_read++] = ch; 1389 } 1390 1391 return num_read; 1392 } 1393 1394 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1395 struct console *con) 1396 { 1397 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1398 con->read = qcom_geni_serial_earlycon_read; 1399 } 1400 #else 1401 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1402 struct console *con) { } 1403 #endif 1404 1405 static struct qcom_geni_private_data earlycon_private_data; 1406 1407 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1408 const char *opt) 1409 { 1410 struct uart_port *uport = &dev->port; 1411 u32 tx_trans_cfg; 1412 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1413 u32 rx_trans_cfg = 0; 1414 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1415 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1416 u32 bits_per_char; 1417 struct geni_se se; 1418 1419 if (!uport->membase) 1420 return -EINVAL; 1421 1422 uport->private_data = &earlycon_private_data; 1423 1424 memset(&se, 0, sizeof(se)); 1425 se.base = uport->membase; 1426 if (geni_se_read_proto(&se) != GENI_SE_UART) 1427 return -ENXIO; 1428 /* 1429 * Ignore Flow control. 1430 * n = 8. 1431 */ 1432 tx_trans_cfg = UART_CTS_MASK; 1433 bits_per_char = BITS_PER_BYTE; 1434 1435 /* 1436 * Make an unconditional cancel on the main sequencer to reset 1437 * it else we could end up in data loss scenarios. 1438 */ 1439 qcom_geni_serial_poll_tx_done(uport); 1440 qcom_geni_serial_abort_rx(uport); 1441 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1442 false, true, true); 1443 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1444 geni_se_select_mode(&se, GENI_SE_FIFO); 1445 1446 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1447 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1448 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1449 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1450 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1451 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1452 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1453 1454 dev->con->write = qcom_geni_serial_earlycon_write; 1455 dev->con->setup = NULL; 1456 qcom_geni_serial_enable_early_read(&se, dev->con); 1457 1458 return 0; 1459 } 1460 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1461 qcom_geni_serial_earlycon_setup); 1462 1463 static int __init console_register(struct uart_driver *drv) 1464 { 1465 return uart_register_driver(drv); 1466 } 1467 1468 static void console_unregister(struct uart_driver *drv) 1469 { 1470 uart_unregister_driver(drv); 1471 } 1472 1473 static struct console cons_ops = { 1474 .name = "ttyMSM", 1475 .write = qcom_geni_serial_console_write, 1476 .device = uart_console_device, 1477 .setup = qcom_geni_console_setup, 1478 .flags = CON_PRINTBUFFER, 1479 .index = -1, 1480 .data = &qcom_geni_console_driver, 1481 }; 1482 1483 static struct uart_driver qcom_geni_console_driver = { 1484 .owner = THIS_MODULE, 1485 .driver_name = "qcom_geni_console", 1486 .dev_name = "ttyMSM", 1487 .nr = GENI_UART_CONS_PORTS, 1488 .cons = &cons_ops, 1489 }; 1490 #else 1491 static int console_register(struct uart_driver *drv) 1492 { 1493 return 0; 1494 } 1495 1496 static void console_unregister(struct uart_driver *drv) 1497 { 1498 } 1499 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1500 1501 static struct uart_driver qcom_geni_uart_driver = { 1502 .owner = THIS_MODULE, 1503 .driver_name = "qcom_geni_uart", 1504 .dev_name = "ttyHS", 1505 .nr = GENI_UART_PORTS, 1506 }; 1507 1508 static void qcom_geni_serial_pm(struct uart_port *uport, 1509 unsigned int new_state, unsigned int old_state) 1510 { 1511 struct qcom_geni_serial_port *port = to_dev_port(uport); 1512 1513 /* If we've never been called, treat it as off */ 1514 if (old_state == UART_PM_STATE_UNDEFINED) 1515 old_state = UART_PM_STATE_OFF; 1516 1517 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1518 geni_icc_enable(&port->se); 1519 if (port->clk_rate) 1520 dev_pm_opp_set_rate(uport->dev, port->clk_rate); 1521 geni_se_resources_on(&port->se); 1522 } else if (new_state == UART_PM_STATE_OFF && 1523 old_state == UART_PM_STATE_ON) { 1524 geni_se_resources_off(&port->se); 1525 dev_pm_opp_set_rate(uport->dev, 0); 1526 geni_icc_disable(&port->se); 1527 } 1528 } 1529 1530 static const struct uart_ops qcom_geni_console_pops = { 1531 .tx_empty = qcom_geni_serial_tx_empty, 1532 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1533 .start_tx = qcom_geni_serial_start_tx_fifo, 1534 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1535 .start_rx = qcom_geni_serial_start_rx_fifo, 1536 .set_termios = qcom_geni_serial_set_termios, 1537 .startup = qcom_geni_serial_startup, 1538 .request_port = qcom_geni_serial_request_port, 1539 .config_port = qcom_geni_serial_config_port, 1540 .shutdown = qcom_geni_serial_shutdown, 1541 .type = qcom_geni_serial_get_type, 1542 .set_mctrl = qcom_geni_serial_set_mctrl, 1543 .get_mctrl = qcom_geni_serial_get_mctrl, 1544 #ifdef CONFIG_CONSOLE_POLL 1545 .poll_get_char = qcom_geni_serial_get_char, 1546 .poll_put_char = qcom_geni_serial_poll_put_char, 1547 .poll_init = qcom_geni_serial_port_setup, 1548 #endif 1549 .pm = qcom_geni_serial_pm, 1550 }; 1551 1552 static const struct uart_ops qcom_geni_uart_pops = { 1553 .tx_empty = qcom_geni_serial_tx_empty, 1554 .stop_tx = qcom_geni_serial_stop_tx_dma, 1555 .start_tx = qcom_geni_serial_start_tx_dma, 1556 .start_rx = qcom_geni_serial_start_rx_dma, 1557 .stop_rx = qcom_geni_serial_stop_rx_dma, 1558 .set_termios = qcom_geni_serial_set_termios, 1559 .startup = qcom_geni_serial_startup, 1560 .request_port = qcom_geni_serial_request_port, 1561 .config_port = qcom_geni_serial_config_port, 1562 .shutdown = qcom_geni_serial_shutdown, 1563 .type = qcom_geni_serial_get_type, 1564 .set_mctrl = qcom_geni_serial_set_mctrl, 1565 .get_mctrl = qcom_geni_serial_get_mctrl, 1566 .pm = qcom_geni_serial_pm, 1567 }; 1568 1569 static int qcom_geni_serial_probe(struct platform_device *pdev) 1570 { 1571 int ret = 0; 1572 int line; 1573 struct qcom_geni_serial_port *port; 1574 struct uart_port *uport; 1575 struct resource *res; 1576 int irq; 1577 struct uart_driver *drv; 1578 const struct qcom_geni_device_data *data; 1579 1580 data = of_device_get_match_data(&pdev->dev); 1581 if (!data) 1582 return -EINVAL; 1583 1584 if (data->console) { 1585 drv = &qcom_geni_console_driver; 1586 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1587 } else { 1588 drv = &qcom_geni_uart_driver; 1589 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1590 if (line == -ENODEV) /* compat with non-standard aliases */ 1591 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1592 } 1593 1594 port = get_port_from_line(line, data->console); 1595 if (IS_ERR(port)) { 1596 dev_err(&pdev->dev, "Invalid line %d\n", line); 1597 return PTR_ERR(port); 1598 } 1599 1600 uport = &port->uport; 1601 /* Don't allow 2 drivers to access the same port */ 1602 if (uport->private_data) 1603 return -ENODEV; 1604 1605 uport->dev = &pdev->dev; 1606 port->dev_data = data; 1607 port->se.dev = &pdev->dev; 1608 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1609 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1610 if (IS_ERR(port->se.clk)) { 1611 ret = PTR_ERR(port->se.clk); 1612 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1613 return ret; 1614 } 1615 1616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1617 if (!res) 1618 return -EINVAL; 1619 uport->mapbase = res->start; 1620 1621 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1622 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1623 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1624 1625 if (!data->console) { 1626 port->rx_buf = devm_kzalloc(uport->dev, 1627 DMA_RX_BUF_SIZE, GFP_KERNEL); 1628 if (!port->rx_buf) 1629 return -ENOMEM; 1630 } 1631 1632 ret = geni_icc_get(&port->se, NULL); 1633 if (ret) 1634 return ret; 1635 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1636 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1637 1638 /* Set BW for register access */ 1639 ret = geni_icc_set_bw(&port->se); 1640 if (ret) 1641 return ret; 1642 1643 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1644 "qcom_geni_serial_%s%d", 1645 uart_console(uport) ? "console" : "uart", uport->line); 1646 if (!port->name) 1647 return -ENOMEM; 1648 1649 irq = platform_get_irq(pdev, 0); 1650 if (irq < 0) 1651 return irq; 1652 uport->irq = irq; 1653 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1654 1655 if (!data->console) 1656 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1657 1658 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1659 port->rx_tx_swap = true; 1660 1661 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1662 port->cts_rts_swap = true; 1663 1664 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1665 if (ret) 1666 return ret; 1667 /* OPP table is optional */ 1668 ret = devm_pm_opp_of_add_table(&pdev->dev); 1669 if (ret && ret != -ENODEV) { 1670 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1671 return ret; 1672 } 1673 1674 port->private_data.drv = drv; 1675 uport->private_data = &port->private_data; 1676 platform_set_drvdata(pdev, port); 1677 1678 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1679 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1680 IRQF_TRIGGER_HIGH, port->name, uport); 1681 if (ret) { 1682 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1683 return ret; 1684 } 1685 1686 ret = uart_add_one_port(drv, uport); 1687 if (ret) 1688 return ret; 1689 1690 if (port->wakeup_irq > 0) { 1691 device_init_wakeup(&pdev->dev, true); 1692 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1693 port->wakeup_irq); 1694 if (ret) { 1695 device_init_wakeup(&pdev->dev, false); 1696 uart_remove_one_port(drv, uport); 1697 return ret; 1698 } 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int qcom_geni_serial_remove(struct platform_device *pdev) 1705 { 1706 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1707 struct uart_driver *drv = port->private_data.drv; 1708 1709 dev_pm_clear_wake_irq(&pdev->dev); 1710 device_init_wakeup(&pdev->dev, false); 1711 uart_remove_one_port(drv, &port->uport); 1712 1713 return 0; 1714 } 1715 1716 static int qcom_geni_serial_sys_suspend(struct device *dev) 1717 { 1718 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1719 struct uart_port *uport = &port->uport; 1720 struct qcom_geni_private_data *private_data = uport->private_data; 1721 1722 /* 1723 * This is done so we can hit the lowest possible state in suspend 1724 * even with no_console_suspend 1725 */ 1726 if (uart_console(uport)) { 1727 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1728 geni_icc_set_bw(&port->se); 1729 } 1730 return uart_suspend_port(private_data->drv, uport); 1731 } 1732 1733 static int qcom_geni_serial_sys_resume(struct device *dev) 1734 { 1735 int ret; 1736 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1737 struct uart_port *uport = &port->uport; 1738 struct qcom_geni_private_data *private_data = uport->private_data; 1739 1740 ret = uart_resume_port(private_data->drv, uport); 1741 if (uart_console(uport)) { 1742 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1743 geni_icc_set_bw(&port->se); 1744 } 1745 return ret; 1746 } 1747 1748 static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1749 { 1750 int ret = 0; 1751 struct uart_port *uport; 1752 struct qcom_geni_private_data *private_data; 1753 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1754 1755 uport = &port->uport; 1756 private_data = uport->private_data; 1757 1758 if (uart_console(uport)) { 1759 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1760 geni_icc_set_bw(&port->se); 1761 ret = uart_resume_port(private_data->drv, uport); 1762 /* 1763 * For hibernation usecase clients for 1764 * console UART won't call port setup during restore, 1765 * hence call port setup for console uart. 1766 */ 1767 qcom_geni_serial_port_setup(uport); 1768 } else { 1769 /* 1770 * Peripheral register settings are lost during hibernation. 1771 * Update setup flag such that port setup happens again 1772 * during next session. Clients of HS-UART will close and 1773 * open the port during hibernation. 1774 */ 1775 port->setup = false; 1776 } 1777 return ret; 1778 } 1779 1780 static const struct qcom_geni_device_data qcom_geni_console_data = { 1781 .console = true, 1782 .mode = GENI_SE_FIFO, 1783 }; 1784 1785 static const struct qcom_geni_device_data qcom_geni_uart_data = { 1786 .console = false, 1787 .mode = GENI_SE_DMA, 1788 }; 1789 1790 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1791 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1792 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), 1793 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1794 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1795 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1796 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1797 }; 1798 1799 static const struct of_device_id qcom_geni_serial_match_table[] = { 1800 { 1801 .compatible = "qcom,geni-debug-uart", 1802 .data = &qcom_geni_console_data, 1803 }, 1804 { 1805 .compatible = "qcom,geni-uart", 1806 .data = &qcom_geni_uart_data, 1807 }, 1808 {} 1809 }; 1810 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1811 1812 static struct platform_driver qcom_geni_serial_platform_driver = { 1813 .remove = qcom_geni_serial_remove, 1814 .probe = qcom_geni_serial_probe, 1815 .driver = { 1816 .name = "qcom_geni_serial", 1817 .of_match_table = qcom_geni_serial_match_table, 1818 .pm = &qcom_geni_serial_pm_ops, 1819 }, 1820 }; 1821 1822 static int __init qcom_geni_serial_init(void) 1823 { 1824 int ret; 1825 1826 ret = console_register(&qcom_geni_console_driver); 1827 if (ret) 1828 return ret; 1829 1830 ret = uart_register_driver(&qcom_geni_uart_driver); 1831 if (ret) { 1832 console_unregister(&qcom_geni_console_driver); 1833 return ret; 1834 } 1835 1836 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1837 if (ret) { 1838 console_unregister(&qcom_geni_console_driver); 1839 uart_unregister_driver(&qcom_geni_uart_driver); 1840 } 1841 return ret; 1842 } 1843 module_init(qcom_geni_serial_init); 1844 1845 static void __exit qcom_geni_serial_exit(void) 1846 { 1847 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1848 console_unregister(&qcom_geni_console_driver); 1849 uart_unregister_driver(&qcom_geni_uart_driver); 1850 } 1851 module_exit(qcom_geni_serial_exit); 1852 1853 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1854 MODULE_LICENSE("GPL v2"); 1855