1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ 5 #define __DISABLE_TRACE_MMIO__ 6 7 #include <linux/clk.h> 8 #include <linux/console.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/soc/qcom/geni-se.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <dt-bindings/interconnect/qcom,icc.h> 26 27 /* UART specific GENI registers */ 28 #define SE_UART_LOOPBACK_CFG 0x22c 29 #define SE_UART_IO_MACRO_CTRL 0x240 30 #define SE_UART_TX_TRANS_CFG 0x25c 31 #define SE_UART_TX_WORD_LEN 0x268 32 #define SE_UART_TX_STOP_BIT_LEN 0x26c 33 #define SE_UART_TX_TRANS_LEN 0x270 34 #define SE_UART_RX_TRANS_CFG 0x280 35 #define SE_UART_RX_WORD_LEN 0x28c 36 #define SE_UART_RX_STALE_CNT 0x294 37 #define SE_UART_TX_PARITY_CFG 0x2a4 38 #define SE_UART_RX_PARITY_CFG 0x2a8 39 #define SE_UART_MANUAL_RFR 0x2ac 40 41 /* SE_UART_TRANS_CFG */ 42 #define UART_TX_PAR_EN BIT(0) 43 #define UART_CTS_MASK BIT(1) 44 45 /* SE_UART_TX_STOP_BIT_LEN */ 46 #define TX_STOP_BIT_LEN_1 0 47 #define TX_STOP_BIT_LEN_2 2 48 49 /* SE_UART_RX_TRANS_CFG */ 50 #define UART_RX_PAR_EN BIT(3) 51 52 /* SE_UART_RX_WORD_LEN */ 53 #define RX_WORD_LEN_MASK GENMASK(9, 0) 54 55 /* SE_UART_RX_STALE_CNT */ 56 #define RX_STALE_CNT GENMASK(23, 0) 57 58 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ 59 #define PAR_CALC_EN BIT(0) 60 #define PAR_EVEN 0x00 61 #define PAR_ODD 0x01 62 #define PAR_SPACE 0x10 63 64 /* SE_UART_MANUAL_RFR register fields */ 65 #define UART_MANUAL_RFR_EN BIT(31) 66 #define UART_RFR_NOT_READY BIT(1) 67 #define UART_RFR_READY BIT(0) 68 69 /* UART M_CMD OP codes */ 70 #define UART_START_TX 0x1 71 /* UART S_CMD OP codes */ 72 #define UART_START_READ 0x1 73 #define UART_PARAM 0x1 74 #define UART_PARAM_RFR_OPEN BIT(7) 75 76 #define UART_OVERSAMPLING 32 77 #define STALE_TIMEOUT 16 78 #define DEFAULT_BITS_PER_CHAR 10 79 #define GENI_UART_CONS_PORTS 1 80 #define GENI_UART_PORTS 3 81 #define DEF_FIFO_DEPTH_WORDS 16 82 #define DEF_TX_WM 2 83 #define DEF_FIFO_WIDTH_BITS 32 84 #define UART_RX_WM 2 85 86 /* SE_UART_LOOPBACK_CFG */ 87 #define RX_TX_SORTED BIT(0) 88 #define CTS_RTS_SORTED BIT(1) 89 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) 90 91 /* UART pin swap value */ 92 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) 93 #define IO_MACRO_IO0_SEL 0x3 94 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) 95 #define IO_MACRO_IO2_IO3_SWAP 0x4640 96 97 /* We always configure 4 bytes per FIFO word */ 98 #define BYTES_PER_FIFO_WORD 4U 99 100 #define DMA_RX_BUF_SIZE 2048 101 102 struct qcom_geni_device_data { 103 bool console; 104 enum geni_se_xfer_mode mode; 105 }; 106 107 struct qcom_geni_private_data { 108 /* NOTE: earlycon port will have NULL here */ 109 struct uart_driver *drv; 110 111 u32 poll_cached_bytes; 112 unsigned int poll_cached_bytes_cnt; 113 114 u32 write_cached_bytes; 115 unsigned int write_cached_bytes_cnt; 116 }; 117 118 struct qcom_geni_serial_port { 119 struct uart_port uport; 120 struct geni_se se; 121 const char *name; 122 u32 tx_fifo_depth; 123 u32 tx_fifo_width; 124 u32 rx_fifo_depth; 125 dma_addr_t tx_dma_addr; 126 dma_addr_t rx_dma_addr; 127 bool setup; 128 unsigned int baud; 129 void *rx_buf; 130 u32 loopback; 131 bool brk; 132 133 unsigned int tx_remaining; 134 int wakeup_irq; 135 bool rx_tx_swap; 136 bool cts_rts_swap; 137 138 struct qcom_geni_private_data private_data; 139 const struct qcom_geni_device_data *dev_data; 140 }; 141 142 static const struct uart_ops qcom_geni_console_pops; 143 static const struct uart_ops qcom_geni_uart_pops; 144 static struct uart_driver qcom_geni_console_driver; 145 static struct uart_driver qcom_geni_uart_driver; 146 147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) 148 { 149 return container_of(uport, struct qcom_geni_serial_port, uport); 150 } 151 152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { 153 [0] = { 154 .uport = { 155 .iotype = UPIO_MEM, 156 .ops = &qcom_geni_uart_pops, 157 .flags = UPF_BOOT_AUTOCONF, 158 .line = 0, 159 }, 160 }, 161 [1] = { 162 .uport = { 163 .iotype = UPIO_MEM, 164 .ops = &qcom_geni_uart_pops, 165 .flags = UPF_BOOT_AUTOCONF, 166 .line = 1, 167 }, 168 }, 169 [2] = { 170 .uport = { 171 .iotype = UPIO_MEM, 172 .ops = &qcom_geni_uart_pops, 173 .flags = UPF_BOOT_AUTOCONF, 174 .line = 2, 175 }, 176 }, 177 }; 178 179 static struct qcom_geni_serial_port qcom_geni_console_port = { 180 .uport = { 181 .iotype = UPIO_MEM, 182 .ops = &qcom_geni_console_pops, 183 .flags = UPF_BOOT_AUTOCONF, 184 .line = 0, 185 }, 186 }; 187 188 static int qcom_geni_serial_request_port(struct uart_port *uport) 189 { 190 struct platform_device *pdev = to_platform_device(uport->dev); 191 struct qcom_geni_serial_port *port = to_dev_port(uport); 192 193 uport->membase = devm_platform_ioremap_resource(pdev, 0); 194 if (IS_ERR(uport->membase)) 195 return PTR_ERR(uport->membase); 196 port->se.base = uport->membase; 197 return 0; 198 } 199 200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) 201 { 202 if (cfg_flags & UART_CONFIG_TYPE) { 203 uport->type = PORT_MSM; 204 qcom_geni_serial_request_port(uport); 205 } 206 } 207 208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) 209 { 210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; 211 u32 geni_ios; 212 213 if (uart_console(uport)) { 214 mctrl |= TIOCM_CTS; 215 } else { 216 geni_ios = readl(uport->membase + SE_GENI_IOS); 217 if (!(geni_ios & IO2_DATA_IN)) 218 mctrl |= TIOCM_CTS; 219 } 220 221 return mctrl; 222 } 223 224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport, 225 unsigned int mctrl) 226 { 227 u32 uart_manual_rfr = 0; 228 struct qcom_geni_serial_port *port = to_dev_port(uport); 229 230 if (uart_console(uport)) 231 return; 232 233 if (mctrl & TIOCM_LOOP) 234 port->loopback = RX_TX_CTS_RTS_SORTED; 235 236 if (!(mctrl & TIOCM_RTS) && !uport->suspended) 237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 239 } 240 241 static const char *qcom_geni_serial_get_type(struct uart_port *uport) 242 { 243 return "MSM"; 244 } 245 246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) 247 { 248 struct qcom_geni_serial_port *port; 249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; 250 251 if (line < 0 || line >= nr_ports) 252 return ERR_PTR(-ENXIO); 253 254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; 255 return port; 256 } 257 258 static bool qcom_geni_serial_main_active(struct uart_port *uport) 259 { 260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; 261 } 262 263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport) 264 { 265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; 266 } 267 268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport, 269 int offset, int field, bool set) 270 { 271 u32 reg; 272 struct qcom_geni_serial_port *port; 273 unsigned int baud; 274 unsigned int fifo_bits; 275 unsigned long timeout_us = 20000; 276 struct qcom_geni_private_data *private_data = uport->private_data; 277 278 if (private_data->drv) { 279 port = to_dev_port(uport); 280 baud = port->baud; 281 if (!baud) 282 baud = 115200; 283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; 284 /* 285 * Total polling iterations based on FIFO worth of bytes to be 286 * sent at current baud. Add a little fluff to the wait. 287 */ 288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; 289 } 290 291 /* 292 * Use custom implementation instead of readl_poll_atomic since ktimer 293 * is not ready at the time of early console. 294 */ 295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; 296 while (timeout_us) { 297 reg = readl(uport->membase + offset); 298 if ((bool)(reg & field) == set) 299 return true; 300 udelay(10); 301 timeout_us -= 10; 302 } 303 return false; 304 } 305 306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) 307 { 308 u32 m_cmd; 309 310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); 311 m_cmd = UART_START_TX << M_OPCODE_SHFT; 312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); 313 } 314 315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) 316 { 317 int done; 318 u32 irq_clear = M_CMD_DONE_EN; 319 320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 321 M_CMD_DONE_EN, true); 322 if (!done) { 323 writel(M_GENI_CMD_ABORT, uport->membase + 324 SE_GENI_M_CMD_CTRL_REG); 325 irq_clear |= M_CMD_ABORT_EN; 326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 327 M_CMD_ABORT_EN, true); 328 } 329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); 330 } 331 332 static void qcom_geni_serial_abort_rx(struct uart_port *uport) 333 { 334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; 335 336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); 337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, 338 S_GENI_CMD_ABORT, false); 339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); 340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); 341 } 342 343 #ifdef CONFIG_CONSOLE_POLL 344 static int qcom_geni_serial_get_char(struct uart_port *uport) 345 { 346 struct qcom_geni_private_data *private_data = uport->private_data; 347 u32 status; 348 u32 word_cnt; 349 int ret; 350 351 if (!private_data->poll_cached_bytes_cnt) { 352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); 354 355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); 357 358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 359 word_cnt = status & RX_FIFO_WC_MSK; 360 if (!word_cnt) 361 return NO_POLL_CHAR; 362 363 if (word_cnt == 1 && (status & RX_LAST)) 364 /* 365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be 366 * treated as if it was BYTES_PER_FIFO_WORD. 367 */ 368 private_data->poll_cached_bytes_cnt = 369 (status & RX_LAST_BYTE_VALID_MSK) >> 370 RX_LAST_BYTE_VALID_SHFT; 371 372 if (private_data->poll_cached_bytes_cnt == 0) 373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; 374 375 private_data->poll_cached_bytes = 376 readl(uport->membase + SE_GENI_RX_FIFOn); 377 } 378 379 private_data->poll_cached_bytes_cnt--; 380 ret = private_data->poll_cached_bytes & 0xff; 381 private_data->poll_cached_bytes >>= 8; 382 383 return ret; 384 } 385 386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport, 387 unsigned char c) 388 { 389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 390 qcom_geni_serial_setup_tx(uport, 1); 391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 392 M_TX_FIFO_WATERMARK_EN, true)); 393 writel(c, uport->membase + SE_GENI_TX_FIFOn); 394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 395 qcom_geni_serial_poll_tx_done(uport); 396 } 397 #endif 398 399 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 400 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) 401 { 402 struct qcom_geni_private_data *private_data = uport->private_data; 403 404 private_data->write_cached_bytes = 405 (private_data->write_cached_bytes >> 8) | (ch << 24); 406 private_data->write_cached_bytes_cnt++; 407 408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { 409 writel(private_data->write_cached_bytes, 410 uport->membase + SE_GENI_TX_FIFOn); 411 private_data->write_cached_bytes_cnt = 0; 412 } 413 } 414 415 static void 416 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, 417 unsigned int count) 418 { 419 struct qcom_geni_private_data *private_data = uport->private_data; 420 421 int i; 422 u32 bytes_to_send = count; 423 424 for (i = 0; i < count; i++) { 425 /* 426 * uart_console_write() adds a carriage return for each newline. 427 * Account for additional bytes to be written. 428 */ 429 if (s[i] == '\n') 430 bytes_to_send++; 431 } 432 433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 434 qcom_geni_serial_setup_tx(uport, bytes_to_send); 435 for (i = 0; i < count; ) { 436 size_t chars_to_write = 0; 437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; 438 439 /* 440 * If the WM bit never set, then the Tx state machine is not 441 * in a valid state, so break, cancel/abort any existing 442 * command. Unfortunately the current data being written is 443 * lost. 444 */ 445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 446 M_TX_FIFO_WATERMARK_EN, true)) 447 break; 448 chars_to_write = min_t(size_t, count - i, avail / 2); 449 uart_console_write(uport, s + i, chars_to_write, 450 qcom_geni_serial_wr_char); 451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + 452 SE_GENI_M_IRQ_CLEAR); 453 i += chars_to_write; 454 } 455 456 if (private_data->write_cached_bytes_cnt) { 457 private_data->write_cached_bytes >>= BITS_PER_BYTE * 458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); 459 writel(private_data->write_cached_bytes, 460 uport->membase + SE_GENI_TX_FIFOn); 461 private_data->write_cached_bytes_cnt = 0; 462 } 463 464 qcom_geni_serial_poll_tx_done(uport); 465 } 466 467 static void qcom_geni_serial_console_write(struct console *co, const char *s, 468 unsigned int count) 469 { 470 struct uart_port *uport; 471 struct qcom_geni_serial_port *port; 472 bool locked = true; 473 unsigned long flags; 474 u32 geni_status; 475 u32 irq_en; 476 477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); 478 479 port = get_port_from_line(co->index, true); 480 if (IS_ERR(port)) 481 return; 482 483 uport = &port->uport; 484 if (oops_in_progress) 485 locked = spin_trylock_irqsave(&uport->lock, flags); 486 else 487 spin_lock_irqsave(&uport->lock, flags); 488 489 geni_status = readl(uport->membase + SE_GENI_STATUS); 490 491 /* Cancel the current write to log the fault */ 492 if (!locked) { 493 geni_se_cancel_m_cmd(&port->se); 494 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 495 M_CMD_CANCEL_EN, true)) { 496 geni_se_abort_m_cmd(&port->se); 497 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 498 M_CMD_ABORT_EN, true); 499 writel(M_CMD_ABORT_EN, uport->membase + 500 SE_GENI_M_IRQ_CLEAR); 501 } 502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { 504 /* 505 * It seems we can't interrupt existing transfers if all data 506 * has been sent, in which case we need to look for done first. 507 */ 508 qcom_geni_serial_poll_tx_done(uport); 509 510 if (!uart_circ_empty(&uport->state->xmit)) { 511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 512 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 513 uport->membase + SE_GENI_M_IRQ_EN); 514 } 515 } 516 517 __qcom_geni_serial_console_write(uport, s, count); 518 519 if (port->tx_remaining) 520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 521 522 if (locked) 523 spin_unlock_irqrestore(&uport->lock, flags); 524 } 525 526 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 527 { 528 u32 i; 529 unsigned char buf[sizeof(u32)]; 530 struct tty_port *tport; 531 struct qcom_geni_serial_port *port = to_dev_port(uport); 532 533 tport = &uport->state->port; 534 for (i = 0; i < bytes; ) { 535 int c; 536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); 537 538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); 539 i += chunk; 540 if (drop) 541 continue; 542 543 for (c = 0; c < chunk; c++) { 544 int sysrq; 545 546 uport->icount.rx++; 547 if (port->brk && buf[c] == 0) { 548 port->brk = false; 549 if (uart_handle_break(uport)) 550 continue; 551 } 552 553 sysrq = uart_prepare_sysrq_char(uport, buf[c]); 554 555 if (!sysrq) 556 tty_insert_flip_char(tport, buf[c], TTY_NORMAL); 557 } 558 } 559 if (!drop) 560 tty_flip_buffer_push(tport); 561 } 562 #else 563 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) 564 { 565 566 } 567 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 568 569 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) 570 { 571 struct qcom_geni_serial_port *port = to_dev_port(uport); 572 struct tty_port *tport = &uport->state->port; 573 int ret; 574 575 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); 576 if (ret != bytes) { 577 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", 578 __func__, ret, bytes); 579 WARN_ON_ONCE(1); 580 } 581 uport->icount.rx += ret; 582 tty_flip_buffer_push(tport); 583 } 584 585 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) 586 { 587 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 588 } 589 590 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) 591 { 592 struct qcom_geni_serial_port *port = to_dev_port(uport); 593 bool done; 594 u32 m_irq_en; 595 596 if (!qcom_geni_serial_main_active(uport)) 597 return; 598 599 if (port->rx_dma_addr) { 600 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, 601 port->tx_remaining); 602 port->tx_dma_addr = 0; 603 port->tx_remaining = 0; 604 } 605 606 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 607 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); 608 geni_se_cancel_m_cmd(&port->se); 609 610 done = qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 611 S_CMD_CANCEL_EN, true); 612 if (!done) { 613 geni_se_abort_m_cmd(&port->se); 614 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 615 M_CMD_ABORT_EN, true); 616 if (!done) 617 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); 618 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 619 } 620 621 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 622 } 623 624 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) 625 { 626 struct qcom_geni_serial_port *port = to_dev_port(uport); 627 struct circ_buf *xmit = &uport->state->xmit; 628 unsigned int xmit_size; 629 int ret; 630 631 if (port->tx_dma_addr) 632 return; 633 634 xmit_size = uart_circ_chars_pending(xmit); 635 if (xmit_size < WAKEUP_CHARS) 636 uart_write_wakeup(uport); 637 638 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 639 640 qcom_geni_serial_setup_tx(uport, xmit_size); 641 642 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], 643 xmit_size, &port->tx_dma_addr); 644 if (ret) { 645 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); 646 qcom_geni_serial_stop_tx_dma(uport); 647 return; 648 } 649 650 port->tx_remaining = xmit_size; 651 } 652 653 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) 654 { 655 u32 irq_en; 656 657 if (qcom_geni_serial_main_active(uport) || 658 !qcom_geni_serial_tx_empty(uport)) 659 return; 660 661 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 662 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; 663 664 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); 665 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 666 } 667 668 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) 669 { 670 u32 irq_en; 671 struct qcom_geni_serial_port *port = to_dev_port(uport); 672 673 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 674 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 675 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); 676 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 677 /* Possible stop tx is called multiple times. */ 678 if (!qcom_geni_serial_main_active(uport)) 679 return; 680 681 geni_se_cancel_m_cmd(&port->se); 682 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 683 M_CMD_CANCEL_EN, true)) { 684 geni_se_abort_m_cmd(&port->se); 685 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, 686 M_CMD_ABORT_EN, true); 687 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 688 } 689 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); 690 } 691 692 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) 693 { 694 u32 status; 695 u32 word_cnt; 696 u32 last_word_byte_cnt; 697 u32 last_word_partial; 698 u32 total_bytes; 699 700 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); 701 word_cnt = status & RX_FIFO_WC_MSK; 702 last_word_partial = status & RX_LAST; 703 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> 704 RX_LAST_BYTE_VALID_SHFT; 705 706 if (!word_cnt) 707 return; 708 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); 709 if (last_word_partial && last_word_byte_cnt) 710 total_bytes += last_word_byte_cnt; 711 else 712 total_bytes += BYTES_PER_FIFO_WORD; 713 handle_rx_console(uport, total_bytes, drop); 714 } 715 716 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) 717 { 718 u32 irq_en; 719 struct qcom_geni_serial_port *port = to_dev_port(uport); 720 u32 s_irq_status; 721 722 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 723 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); 724 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 725 726 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 727 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 728 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 729 730 if (!qcom_geni_serial_secondary_active(uport)) 731 return; 732 733 geni_se_cancel_s_cmd(&port->se); 734 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 735 S_CMD_CANCEL_EN, true); 736 /* 737 * If timeout occurs secondary engine remains active 738 * and Abort sequence is executed. 739 */ 740 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 741 /* Flush the Rx buffer */ 742 if (s_irq_status & S_RX_FIFO_LAST_EN) 743 qcom_geni_serial_handle_rx_fifo(uport, true); 744 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 745 746 if (qcom_geni_serial_secondary_active(uport)) 747 qcom_geni_serial_abort_rx(uport); 748 } 749 750 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) 751 { 752 u32 irq_en; 753 struct qcom_geni_serial_port *port = to_dev_port(uport); 754 755 if (qcom_geni_serial_secondary_active(uport)) 756 qcom_geni_serial_stop_rx_fifo(uport); 757 758 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); 759 760 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); 761 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; 762 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); 763 764 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 765 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 766 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); 767 } 768 769 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) 770 { 771 struct qcom_geni_serial_port *port = to_dev_port(uport); 772 773 if (!qcom_geni_serial_secondary_active(uport)) 774 return; 775 776 geni_se_cancel_s_cmd(&port->se); 777 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, 778 S_CMD_CANCEL_EN, true); 779 780 if (qcom_geni_serial_secondary_active(uport)) 781 qcom_geni_serial_abort_rx(uport); 782 783 if (port->rx_dma_addr) { 784 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, 785 DMA_RX_BUF_SIZE); 786 port->rx_dma_addr = 0; 787 } 788 } 789 790 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) 791 { 792 struct qcom_geni_serial_port *port = to_dev_port(uport); 793 int ret; 794 795 if (qcom_geni_serial_secondary_active(uport)) 796 qcom_geni_serial_stop_rx_dma(uport); 797 798 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); 799 800 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 801 DMA_RX_BUF_SIZE, 802 &port->rx_dma_addr); 803 if (ret) { 804 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 805 qcom_geni_serial_stop_rx_dma(uport); 806 } 807 } 808 809 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) 810 { 811 struct qcom_geni_serial_port *port = to_dev_port(uport); 812 u32 rx_in; 813 int ret; 814 815 if (!qcom_geni_serial_secondary_active(uport)) 816 return; 817 818 if (!port->rx_dma_addr) 819 return; 820 821 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); 822 port->rx_dma_addr = 0; 823 824 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); 825 if (!rx_in) { 826 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); 827 return; 828 } 829 830 if (!drop) 831 handle_rx_uart(uport, rx_in, drop); 832 833 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, 834 DMA_RX_BUF_SIZE, 835 &port->rx_dma_addr); 836 if (ret) { 837 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); 838 qcom_geni_serial_stop_rx_dma(uport); 839 } 840 } 841 842 static void qcom_geni_serial_start_rx(struct uart_port *uport) 843 { 844 uport->ops->start_rx(uport); 845 } 846 847 static void qcom_geni_serial_stop_rx(struct uart_port *uport) 848 { 849 uport->ops->stop_rx(uport); 850 } 851 852 static void qcom_geni_serial_stop_tx(struct uart_port *uport) 853 { 854 uport->ops->stop_tx(uport); 855 } 856 857 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, 858 unsigned int chunk) 859 { 860 struct qcom_geni_serial_port *port = to_dev_port(uport); 861 struct circ_buf *xmit = &uport->state->xmit; 862 unsigned int tx_bytes, c, remaining = chunk; 863 u8 buf[BYTES_PER_FIFO_WORD]; 864 865 while (remaining) { 866 memset(buf, 0, sizeof(buf)); 867 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); 868 869 for (c = 0; c < tx_bytes ; c++) { 870 buf[c] = xmit->buf[xmit->tail]; 871 uart_xmit_advance(uport, 1); 872 } 873 874 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); 875 876 remaining -= tx_bytes; 877 port->tx_remaining -= tx_bytes; 878 } 879 } 880 881 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, 882 bool done, bool active) 883 { 884 struct qcom_geni_serial_port *port = to_dev_port(uport); 885 struct circ_buf *xmit = &uport->state->xmit; 886 size_t avail; 887 size_t pending; 888 u32 status; 889 u32 irq_en; 890 unsigned int chunk; 891 892 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); 893 894 /* Complete the current tx command before taking newly added data */ 895 if (active) 896 pending = port->tx_remaining; 897 else 898 pending = uart_circ_chars_pending(xmit); 899 900 /* All data has been transmitted and acknowledged as received */ 901 if (!pending && !status && done) { 902 qcom_geni_serial_stop_tx_fifo(uport); 903 goto out_write_wakeup; 904 } 905 906 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); 907 avail *= BYTES_PER_FIFO_WORD; 908 909 chunk = min(avail, pending); 910 if (!chunk) 911 goto out_write_wakeup; 912 913 if (!port->tx_remaining) { 914 qcom_geni_serial_setup_tx(uport, pending); 915 port->tx_remaining = pending; 916 917 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 918 if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) 919 writel(irq_en | M_TX_FIFO_WATERMARK_EN, 920 uport->membase + SE_GENI_M_IRQ_EN); 921 } 922 923 qcom_geni_serial_send_chunk_fifo(uport, chunk); 924 925 /* 926 * The tx fifo watermark is level triggered and latched. Though we had 927 * cleared it in qcom_geni_serial_isr it will have already reasserted 928 * so we must clear it again here after our writes. 929 */ 930 writel(M_TX_FIFO_WATERMARK_EN, 931 uport->membase + SE_GENI_M_IRQ_CLEAR); 932 933 out_write_wakeup: 934 if (!port->tx_remaining) { 935 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 936 if (irq_en & M_TX_FIFO_WATERMARK_EN) 937 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, 938 uport->membase + SE_GENI_M_IRQ_EN); 939 } 940 941 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 942 uart_write_wakeup(uport); 943 } 944 945 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) 946 { 947 struct qcom_geni_serial_port *port = to_dev_port(uport); 948 struct circ_buf *xmit = &uport->state->xmit; 949 950 uart_xmit_advance(uport, port->tx_remaining); 951 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); 952 port->tx_dma_addr = 0; 953 port->tx_remaining = 0; 954 955 if (!uart_circ_empty(xmit)) 956 qcom_geni_serial_start_tx_dma(uport); 957 958 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 959 uart_write_wakeup(uport); 960 } 961 962 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) 963 { 964 u32 m_irq_en; 965 u32 m_irq_status; 966 u32 s_irq_status; 967 u32 geni_status; 968 u32 dma; 969 u32 dma_tx_status; 970 u32 dma_rx_status; 971 struct uart_port *uport = dev; 972 bool drop_rx = false; 973 struct tty_port *tport = &uport->state->port; 974 struct qcom_geni_serial_port *port = to_dev_port(uport); 975 976 if (uport->suspended) 977 return IRQ_NONE; 978 979 spin_lock(&uport->lock); 980 981 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 982 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); 983 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); 984 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); 985 geni_status = readl(uport->membase + SE_GENI_STATUS); 986 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); 987 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); 988 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); 989 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); 990 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); 991 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); 992 993 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) 994 goto out_unlock; 995 996 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { 997 uport->icount.overrun++; 998 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 999 } 1000 1001 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { 1002 if (s_irq_status & S_GP_IRQ_0_EN) 1003 uport->icount.parity++; 1004 drop_rx = true; 1005 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { 1006 uport->icount.brk++; 1007 port->brk = true; 1008 } 1009 1010 if (dma) { 1011 if (dma_tx_status & TX_DMA_DONE) 1012 qcom_geni_serial_handle_tx_dma(uport); 1013 1014 if (dma_rx_status) { 1015 if (dma_rx_status & RX_RESET_DONE) 1016 goto out_unlock; 1017 1018 if (dma_rx_status & RX_DMA_PARITY_ERR) { 1019 uport->icount.parity++; 1020 drop_rx = true; 1021 } 1022 1023 if (dma_rx_status & RX_DMA_BREAK) 1024 uport->icount.brk++; 1025 1026 if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) 1027 qcom_geni_serial_handle_rx_dma(uport, drop_rx); 1028 } 1029 } else { 1030 if (m_irq_status & m_irq_en & 1031 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) 1032 qcom_geni_serial_handle_tx_fifo(uport, 1033 m_irq_status & M_CMD_DONE_EN, 1034 geni_status & M_GENI_CMD_ACTIVE); 1035 1036 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) 1037 qcom_geni_serial_handle_rx_fifo(uport, drop_rx); 1038 } 1039 1040 out_unlock: 1041 uart_unlock_and_check_sysrq(uport); 1042 1043 return IRQ_HANDLED; 1044 } 1045 1046 static int setup_fifos(struct qcom_geni_serial_port *port) 1047 { 1048 struct uart_port *uport; 1049 u32 old_rx_fifo_depth = port->rx_fifo_depth; 1050 1051 uport = &port->uport; 1052 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); 1053 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); 1054 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); 1055 uport->fifosize = 1056 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; 1057 1058 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { 1059 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, 1060 port->rx_fifo_depth * sizeof(u32), 1061 GFP_KERNEL); 1062 if (!port->rx_buf) 1063 return -ENOMEM; 1064 } 1065 1066 return 0; 1067 } 1068 1069 1070 static void qcom_geni_serial_shutdown(struct uart_port *uport) 1071 { 1072 disable_irq(uport->irq); 1073 qcom_geni_serial_stop_tx(uport); 1074 qcom_geni_serial_stop_rx(uport); 1075 } 1076 1077 static int qcom_geni_serial_port_setup(struct uart_port *uport) 1078 { 1079 struct qcom_geni_serial_port *port = to_dev_port(uport); 1080 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; 1081 u32 proto; 1082 u32 pin_swap; 1083 int ret; 1084 1085 proto = geni_se_read_proto(&port->se); 1086 if (proto != GENI_SE_UART) { 1087 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); 1088 return -ENXIO; 1089 } 1090 1091 qcom_geni_serial_stop_rx(uport); 1092 1093 ret = setup_fifos(port); 1094 if (ret) 1095 return ret; 1096 1097 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); 1098 1099 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); 1100 if (port->rx_tx_swap) { 1101 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; 1102 pin_swap |= IO_MACRO_IO2_IO3_SWAP; 1103 } 1104 if (port->cts_rts_swap) { 1105 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; 1106 pin_swap |= IO_MACRO_IO0_SEL; 1107 } 1108 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ 1109 if (port->rx_tx_swap || port->cts_rts_swap) 1110 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); 1111 1112 /* 1113 * Make an unconditional cancel on the main sequencer to reset 1114 * it else we could end up in data loss scenarios. 1115 */ 1116 if (uart_console(uport)) 1117 qcom_geni_serial_poll_tx_done(uport); 1118 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1119 false, true, true); 1120 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); 1121 geni_se_select_mode(&port->se, port->dev_data->mode); 1122 qcom_geni_serial_start_rx(uport); 1123 port->setup = true; 1124 1125 return 0; 1126 } 1127 1128 static int qcom_geni_serial_startup(struct uart_port *uport) 1129 { 1130 int ret; 1131 struct qcom_geni_serial_port *port = to_dev_port(uport); 1132 1133 if (!port->setup) { 1134 ret = qcom_geni_serial_port_setup(uport); 1135 if (ret) 1136 return ret; 1137 } 1138 enable_irq(uport->irq); 1139 1140 return 0; 1141 } 1142 1143 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, 1144 unsigned int *clk_div, unsigned int percent_tol) 1145 { 1146 unsigned long freq; 1147 unsigned long div, maxdiv; 1148 u64 mult; 1149 unsigned long offset, abs_tol, achieved; 1150 1151 abs_tol = div_u64((u64)desired_clk * percent_tol, 100); 1152 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; 1153 div = 1; 1154 while (div <= maxdiv) { 1155 mult = (u64)div * desired_clk; 1156 if (mult != (unsigned long)mult) 1157 break; 1158 1159 offset = div * abs_tol; 1160 freq = clk_round_rate(clk, mult - offset); 1161 1162 /* Can only get lower if we're done */ 1163 if (freq < mult - offset) 1164 break; 1165 1166 /* 1167 * Re-calculate div in case rounding skipped rates but we 1168 * ended up at a good one, then check for a match. 1169 */ 1170 div = DIV_ROUND_CLOSEST(freq, desired_clk); 1171 achieved = DIV_ROUND_CLOSEST(freq, div); 1172 if (achieved <= desired_clk + abs_tol && 1173 achieved >= desired_clk - abs_tol) { 1174 *clk_div = div; 1175 return freq; 1176 } 1177 1178 div = DIV_ROUND_UP(freq, desired_clk); 1179 } 1180 1181 return 0; 1182 } 1183 1184 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, 1185 unsigned int sampling_rate, unsigned int *clk_div) 1186 { 1187 unsigned long ser_clk; 1188 unsigned long desired_clk; 1189 1190 desired_clk = baud * sampling_rate; 1191 if (!desired_clk) 1192 return 0; 1193 1194 /* 1195 * try to find a clock rate within 2% tolerance, then within 5% 1196 */ 1197 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); 1198 if (!ser_clk) 1199 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); 1200 1201 return ser_clk; 1202 } 1203 1204 static void qcom_geni_serial_set_termios(struct uart_port *uport, 1205 struct ktermios *termios, 1206 const struct ktermios *old) 1207 { 1208 unsigned int baud; 1209 u32 bits_per_char; 1210 u32 tx_trans_cfg; 1211 u32 tx_parity_cfg; 1212 u32 rx_trans_cfg; 1213 u32 rx_parity_cfg; 1214 u32 stop_bit_len; 1215 unsigned int clk_div; 1216 u32 ser_clk_cfg; 1217 struct qcom_geni_serial_port *port = to_dev_port(uport); 1218 unsigned long clk_rate; 1219 u32 ver, sampling_rate; 1220 unsigned int avg_bw_core; 1221 1222 qcom_geni_serial_stop_rx(uport); 1223 /* baud rate */ 1224 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); 1225 port->baud = baud; 1226 1227 sampling_rate = UART_OVERSAMPLING; 1228 /* Sampling rate is halved for IP versions >= 2.5 */ 1229 ver = geni_se_get_qup_hw_version(&port->se); 1230 if (ver >= QUP_SE_VERSION_2_5) 1231 sampling_rate /= 2; 1232 1233 clk_rate = get_clk_div_rate(port->se.clk, baud, 1234 sampling_rate, &clk_div); 1235 if (!clk_rate) { 1236 dev_err(port->se.dev, 1237 "Couldn't find suitable clock rate for %u\n", 1238 baud * sampling_rate); 1239 goto out_restart_rx; 1240 } 1241 1242 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", 1243 baud * sampling_rate, clk_rate, clk_div); 1244 1245 uport->uartclk = clk_rate; 1246 dev_pm_opp_set_rate(uport->dev, clk_rate); 1247 ser_clk_cfg = SER_CLK_EN; 1248 ser_clk_cfg |= clk_div << CLK_DIV_SHFT; 1249 1250 /* 1251 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode 1252 * only. 1253 */ 1254 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) 1255 : GENI_DEFAULT_BW; 1256 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; 1257 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); 1258 geni_icc_set_bw(&port->se); 1259 1260 /* parity */ 1261 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); 1262 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); 1263 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); 1264 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); 1265 if (termios->c_cflag & PARENB) { 1266 tx_trans_cfg |= UART_TX_PAR_EN; 1267 rx_trans_cfg |= UART_RX_PAR_EN; 1268 tx_parity_cfg |= PAR_CALC_EN; 1269 rx_parity_cfg |= PAR_CALC_EN; 1270 if (termios->c_cflag & PARODD) { 1271 tx_parity_cfg |= PAR_ODD; 1272 rx_parity_cfg |= PAR_ODD; 1273 } else if (termios->c_cflag & CMSPAR) { 1274 tx_parity_cfg |= PAR_SPACE; 1275 rx_parity_cfg |= PAR_SPACE; 1276 } else { 1277 tx_parity_cfg |= PAR_EVEN; 1278 rx_parity_cfg |= PAR_EVEN; 1279 } 1280 } else { 1281 tx_trans_cfg &= ~UART_TX_PAR_EN; 1282 rx_trans_cfg &= ~UART_RX_PAR_EN; 1283 tx_parity_cfg &= ~PAR_CALC_EN; 1284 rx_parity_cfg &= ~PAR_CALC_EN; 1285 } 1286 1287 /* bits per char */ 1288 bits_per_char = tty_get_char_size(termios->c_cflag); 1289 1290 /* stop bits */ 1291 if (termios->c_cflag & CSTOPB) 1292 stop_bit_len = TX_STOP_BIT_LEN_2; 1293 else 1294 stop_bit_len = TX_STOP_BIT_LEN_1; 1295 1296 /* flow control, clear the CTS_MASK bit if using flow control. */ 1297 if (termios->c_cflag & CRTSCTS) 1298 tx_trans_cfg &= ~UART_CTS_MASK; 1299 else 1300 tx_trans_cfg |= UART_CTS_MASK; 1301 1302 if (baud) 1303 uart_update_timeout(uport, termios->c_cflag, baud); 1304 1305 if (!uart_console(uport)) 1306 writel(port->loopback, 1307 uport->membase + SE_UART_LOOPBACK_CFG); 1308 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1309 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1310 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1311 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1312 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1313 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1314 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1315 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); 1316 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); 1317 out_restart_rx: 1318 qcom_geni_serial_start_rx(uport); 1319 } 1320 1321 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE 1322 static int qcom_geni_console_setup(struct console *co, char *options) 1323 { 1324 struct uart_port *uport; 1325 struct qcom_geni_serial_port *port; 1326 int baud = 115200; 1327 int bits = 8; 1328 int parity = 'n'; 1329 int flow = 'n'; 1330 int ret; 1331 1332 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) 1333 return -ENXIO; 1334 1335 port = get_port_from_line(co->index, true); 1336 if (IS_ERR(port)) { 1337 pr_err("Invalid line %d\n", co->index); 1338 return PTR_ERR(port); 1339 } 1340 1341 uport = &port->uport; 1342 1343 if (unlikely(!uport->membase)) 1344 return -ENXIO; 1345 1346 if (!port->setup) { 1347 ret = qcom_geni_serial_port_setup(uport); 1348 if (ret) 1349 return ret; 1350 } 1351 1352 if (options) 1353 uart_parse_options(options, &baud, &parity, &bits, &flow); 1354 1355 return uart_set_options(uport, co, baud, parity, bits, flow); 1356 } 1357 1358 static void qcom_geni_serial_earlycon_write(struct console *con, 1359 const char *s, unsigned int n) 1360 { 1361 struct earlycon_device *dev = con->data; 1362 1363 __qcom_geni_serial_console_write(&dev->port, s, n); 1364 } 1365 1366 #ifdef CONFIG_CONSOLE_POLL 1367 static int qcom_geni_serial_earlycon_read(struct console *con, 1368 char *s, unsigned int n) 1369 { 1370 struct earlycon_device *dev = con->data; 1371 struct uart_port *uport = &dev->port; 1372 int num_read = 0; 1373 int ch; 1374 1375 while (num_read < n) { 1376 ch = qcom_geni_serial_get_char(uport); 1377 if (ch == NO_POLL_CHAR) 1378 break; 1379 s[num_read++] = ch; 1380 } 1381 1382 return num_read; 1383 } 1384 1385 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, 1386 struct console *con) 1387 { 1388 geni_se_setup_s_cmd(se, UART_START_READ, 0); 1389 con->read = qcom_geni_serial_earlycon_read; 1390 } 1391 #else 1392 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, 1393 struct console *con) { } 1394 #endif 1395 1396 static struct qcom_geni_private_data earlycon_private_data; 1397 1398 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, 1399 const char *opt) 1400 { 1401 struct uart_port *uport = &dev->port; 1402 u32 tx_trans_cfg; 1403 u32 tx_parity_cfg = 0; /* Disable Tx Parity */ 1404 u32 rx_trans_cfg = 0; 1405 u32 rx_parity_cfg = 0; /* Disable Rx Parity */ 1406 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ 1407 u32 bits_per_char; 1408 struct geni_se se; 1409 1410 if (!uport->membase) 1411 return -EINVAL; 1412 1413 uport->private_data = &earlycon_private_data; 1414 1415 memset(&se, 0, sizeof(se)); 1416 se.base = uport->membase; 1417 if (geni_se_read_proto(&se) != GENI_SE_UART) 1418 return -ENXIO; 1419 /* 1420 * Ignore Flow control. 1421 * n = 8. 1422 */ 1423 tx_trans_cfg = UART_CTS_MASK; 1424 bits_per_char = BITS_PER_BYTE; 1425 1426 /* 1427 * Make an unconditional cancel on the main sequencer to reset 1428 * it else we could end up in data loss scenarios. 1429 */ 1430 qcom_geni_serial_poll_tx_done(uport); 1431 qcom_geni_serial_abort_rx(uport); 1432 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, 1433 false, true, true); 1434 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); 1435 geni_se_select_mode(&se, GENI_SE_FIFO); 1436 1437 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); 1438 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); 1439 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); 1440 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); 1441 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); 1442 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); 1443 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); 1444 1445 dev->con->write = qcom_geni_serial_earlycon_write; 1446 dev->con->setup = NULL; 1447 qcom_geni_serial_enable_early_read(&se, dev->con); 1448 1449 return 0; 1450 } 1451 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", 1452 qcom_geni_serial_earlycon_setup); 1453 1454 static int __init console_register(struct uart_driver *drv) 1455 { 1456 return uart_register_driver(drv); 1457 } 1458 1459 static void console_unregister(struct uart_driver *drv) 1460 { 1461 uart_unregister_driver(drv); 1462 } 1463 1464 static struct console cons_ops = { 1465 .name = "ttyMSM", 1466 .write = qcom_geni_serial_console_write, 1467 .device = uart_console_device, 1468 .setup = qcom_geni_console_setup, 1469 .flags = CON_PRINTBUFFER, 1470 .index = -1, 1471 .data = &qcom_geni_console_driver, 1472 }; 1473 1474 static struct uart_driver qcom_geni_console_driver = { 1475 .owner = THIS_MODULE, 1476 .driver_name = "qcom_geni_console", 1477 .dev_name = "ttyMSM", 1478 .nr = GENI_UART_CONS_PORTS, 1479 .cons = &cons_ops, 1480 }; 1481 #else 1482 static int console_register(struct uart_driver *drv) 1483 { 1484 return 0; 1485 } 1486 1487 static void console_unregister(struct uart_driver *drv) 1488 { 1489 } 1490 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ 1491 1492 static struct uart_driver qcom_geni_uart_driver = { 1493 .owner = THIS_MODULE, 1494 .driver_name = "qcom_geni_uart", 1495 .dev_name = "ttyHS", 1496 .nr = GENI_UART_PORTS, 1497 }; 1498 1499 static void qcom_geni_serial_pm(struct uart_port *uport, 1500 unsigned int new_state, unsigned int old_state) 1501 { 1502 struct qcom_geni_serial_port *port = to_dev_port(uport); 1503 1504 /* If we've never been called, treat it as off */ 1505 if (old_state == UART_PM_STATE_UNDEFINED) 1506 old_state = UART_PM_STATE_OFF; 1507 1508 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { 1509 geni_icc_enable(&port->se); 1510 geni_se_resources_on(&port->se); 1511 } else if (new_state == UART_PM_STATE_OFF && 1512 old_state == UART_PM_STATE_ON) { 1513 geni_se_resources_off(&port->se); 1514 geni_icc_disable(&port->se); 1515 } 1516 } 1517 1518 static const struct uart_ops qcom_geni_console_pops = { 1519 .tx_empty = qcom_geni_serial_tx_empty, 1520 .stop_tx = qcom_geni_serial_stop_tx_fifo, 1521 .start_tx = qcom_geni_serial_start_tx_fifo, 1522 .stop_rx = qcom_geni_serial_stop_rx_fifo, 1523 .start_rx = qcom_geni_serial_start_rx_fifo, 1524 .set_termios = qcom_geni_serial_set_termios, 1525 .startup = qcom_geni_serial_startup, 1526 .request_port = qcom_geni_serial_request_port, 1527 .config_port = qcom_geni_serial_config_port, 1528 .shutdown = qcom_geni_serial_shutdown, 1529 .type = qcom_geni_serial_get_type, 1530 .set_mctrl = qcom_geni_serial_set_mctrl, 1531 .get_mctrl = qcom_geni_serial_get_mctrl, 1532 #ifdef CONFIG_CONSOLE_POLL 1533 .poll_get_char = qcom_geni_serial_get_char, 1534 .poll_put_char = qcom_geni_serial_poll_put_char, 1535 #endif 1536 .pm = qcom_geni_serial_pm, 1537 }; 1538 1539 static const struct uart_ops qcom_geni_uart_pops = { 1540 .tx_empty = qcom_geni_serial_tx_empty, 1541 .stop_tx = qcom_geni_serial_stop_tx_dma, 1542 .start_tx = qcom_geni_serial_start_tx_dma, 1543 .start_rx = qcom_geni_serial_start_rx_dma, 1544 .stop_rx = qcom_geni_serial_stop_rx_dma, 1545 .set_termios = qcom_geni_serial_set_termios, 1546 .startup = qcom_geni_serial_startup, 1547 .request_port = qcom_geni_serial_request_port, 1548 .config_port = qcom_geni_serial_config_port, 1549 .shutdown = qcom_geni_serial_shutdown, 1550 .type = qcom_geni_serial_get_type, 1551 .set_mctrl = qcom_geni_serial_set_mctrl, 1552 .get_mctrl = qcom_geni_serial_get_mctrl, 1553 .pm = qcom_geni_serial_pm, 1554 }; 1555 1556 static int qcom_geni_serial_probe(struct platform_device *pdev) 1557 { 1558 int ret = 0; 1559 int line; 1560 struct qcom_geni_serial_port *port; 1561 struct uart_port *uport; 1562 struct resource *res; 1563 int irq; 1564 struct uart_driver *drv; 1565 const struct qcom_geni_device_data *data; 1566 1567 data = of_device_get_match_data(&pdev->dev); 1568 if (!data) 1569 return -EINVAL; 1570 1571 if (data->console) { 1572 drv = &qcom_geni_console_driver; 1573 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1574 } else { 1575 drv = &qcom_geni_uart_driver; 1576 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1577 if (line == -ENODEV) /* compat with non-standard aliases */ 1578 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); 1579 } 1580 1581 port = get_port_from_line(line, data->console); 1582 if (IS_ERR(port)) { 1583 dev_err(&pdev->dev, "Invalid line %d\n", line); 1584 return PTR_ERR(port); 1585 } 1586 1587 uport = &port->uport; 1588 /* Don't allow 2 drivers to access the same port */ 1589 if (uport->private_data) 1590 return -ENODEV; 1591 1592 uport->dev = &pdev->dev; 1593 port->dev_data = data; 1594 port->se.dev = &pdev->dev; 1595 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); 1596 port->se.clk = devm_clk_get(&pdev->dev, "se"); 1597 if (IS_ERR(port->se.clk)) { 1598 ret = PTR_ERR(port->se.clk); 1599 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); 1600 return ret; 1601 } 1602 1603 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1604 if (!res) 1605 return -EINVAL; 1606 uport->mapbase = res->start; 1607 1608 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1609 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; 1610 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; 1611 1612 if (!data->console) { 1613 port->rx_buf = devm_kzalloc(uport->dev, 1614 DMA_RX_BUF_SIZE, GFP_KERNEL); 1615 if (!port->rx_buf) 1616 return -ENOMEM; 1617 } 1618 1619 ret = geni_icc_get(&port->se, NULL); 1620 if (ret) 1621 return ret; 1622 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1623 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1624 1625 /* Set BW for register access */ 1626 ret = geni_icc_set_bw(&port->se); 1627 if (ret) 1628 return ret; 1629 1630 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, 1631 "qcom_geni_serial_%s%d", 1632 uart_console(uport) ? "console" : "uart", uport->line); 1633 if (!port->name) 1634 return -ENOMEM; 1635 1636 irq = platform_get_irq(pdev, 0); 1637 if (irq < 0) 1638 return irq; 1639 uport->irq = irq; 1640 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); 1641 1642 if (!data->console) 1643 port->wakeup_irq = platform_get_irq_optional(pdev, 1); 1644 1645 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) 1646 port->rx_tx_swap = true; 1647 1648 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) 1649 port->cts_rts_swap = true; 1650 1651 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1652 if (ret) 1653 return ret; 1654 /* OPP table is optional */ 1655 ret = devm_pm_opp_of_add_table(&pdev->dev); 1656 if (ret && ret != -ENODEV) { 1657 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1658 return ret; 1659 } 1660 1661 port->private_data.drv = drv; 1662 uport->private_data = &port->private_data; 1663 platform_set_drvdata(pdev, port); 1664 1665 ret = uart_add_one_port(drv, uport); 1666 if (ret) 1667 return ret; 1668 1669 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); 1670 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, 1671 IRQF_TRIGGER_HIGH, port->name, uport); 1672 if (ret) { 1673 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); 1674 uart_remove_one_port(drv, uport); 1675 return ret; 1676 } 1677 1678 /* 1679 * Set pm_runtime status as ACTIVE so that wakeup_irq gets 1680 * enabled/disabled from dev_pm_arm_wake_irq during system 1681 * suspend/resume respectively. 1682 */ 1683 pm_runtime_set_active(&pdev->dev); 1684 1685 if (port->wakeup_irq > 0) { 1686 device_init_wakeup(&pdev->dev, true); 1687 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1688 port->wakeup_irq); 1689 if (ret) { 1690 device_init_wakeup(&pdev->dev, false); 1691 uart_remove_one_port(drv, uport); 1692 return ret; 1693 } 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int qcom_geni_serial_remove(struct platform_device *pdev) 1700 { 1701 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); 1702 struct uart_driver *drv = port->private_data.drv; 1703 1704 dev_pm_clear_wake_irq(&pdev->dev); 1705 device_init_wakeup(&pdev->dev, false); 1706 uart_remove_one_port(drv, &port->uport); 1707 1708 return 0; 1709 } 1710 1711 static int qcom_geni_serial_sys_suspend(struct device *dev) 1712 { 1713 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1714 struct uart_port *uport = &port->uport; 1715 struct qcom_geni_private_data *private_data = uport->private_data; 1716 1717 /* 1718 * This is done so we can hit the lowest possible state in suspend 1719 * even with no_console_suspend 1720 */ 1721 if (uart_console(uport)) { 1722 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); 1723 geni_icc_set_bw(&port->se); 1724 } 1725 return uart_suspend_port(private_data->drv, uport); 1726 } 1727 1728 static int qcom_geni_serial_sys_resume(struct device *dev) 1729 { 1730 int ret; 1731 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1732 struct uart_port *uport = &port->uport; 1733 struct qcom_geni_private_data *private_data = uport->private_data; 1734 1735 ret = uart_resume_port(private_data->drv, uport); 1736 if (uart_console(uport)) { 1737 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); 1738 geni_icc_set_bw(&port->se); 1739 } 1740 return ret; 1741 } 1742 1743 static int qcom_geni_serial_sys_hib_resume(struct device *dev) 1744 { 1745 int ret = 0; 1746 struct uart_port *uport; 1747 struct qcom_geni_private_data *private_data; 1748 struct qcom_geni_serial_port *port = dev_get_drvdata(dev); 1749 1750 uport = &port->uport; 1751 private_data = uport->private_data; 1752 1753 if (uart_console(uport)) { 1754 geni_icc_set_tag(&port->se, 0x7); 1755 geni_icc_set_bw(&port->se); 1756 ret = uart_resume_port(private_data->drv, uport); 1757 /* 1758 * For hibernation usecase clients for 1759 * console UART won't call port setup during restore, 1760 * hence call port setup for console uart. 1761 */ 1762 qcom_geni_serial_port_setup(uport); 1763 } else { 1764 /* 1765 * Peripheral register settings are lost during hibernation. 1766 * Update setup flag such that port setup happens again 1767 * during next session. Clients of HS-UART will close and 1768 * open the port during hibernation. 1769 */ 1770 port->setup = false; 1771 } 1772 return ret; 1773 } 1774 1775 static const struct qcom_geni_device_data qcom_geni_console_data = { 1776 .console = true, 1777 .mode = GENI_SE_FIFO, 1778 }; 1779 1780 static const struct qcom_geni_device_data qcom_geni_uart_data = { 1781 .console = false, 1782 .mode = GENI_SE_DMA, 1783 }; 1784 1785 static const struct dev_pm_ops qcom_geni_serial_pm_ops = { 1786 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1787 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), 1788 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1789 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), 1790 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1791 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), 1792 }; 1793 1794 static const struct of_device_id qcom_geni_serial_match_table[] = { 1795 { 1796 .compatible = "qcom,geni-debug-uart", 1797 .data = &qcom_geni_console_data, 1798 }, 1799 { 1800 .compatible = "qcom,geni-uart", 1801 .data = &qcom_geni_uart_data, 1802 }, 1803 {} 1804 }; 1805 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); 1806 1807 static struct platform_driver qcom_geni_serial_platform_driver = { 1808 .remove = qcom_geni_serial_remove, 1809 .probe = qcom_geni_serial_probe, 1810 .driver = { 1811 .name = "qcom_geni_serial", 1812 .of_match_table = qcom_geni_serial_match_table, 1813 .pm = &qcom_geni_serial_pm_ops, 1814 }, 1815 }; 1816 1817 static int __init qcom_geni_serial_init(void) 1818 { 1819 int ret; 1820 1821 ret = console_register(&qcom_geni_console_driver); 1822 if (ret) 1823 return ret; 1824 1825 ret = uart_register_driver(&qcom_geni_uart_driver); 1826 if (ret) { 1827 console_unregister(&qcom_geni_console_driver); 1828 return ret; 1829 } 1830 1831 ret = platform_driver_register(&qcom_geni_serial_platform_driver); 1832 if (ret) { 1833 console_unregister(&qcom_geni_console_driver); 1834 uart_unregister_driver(&qcom_geni_uart_driver); 1835 } 1836 return ret; 1837 } 1838 module_init(qcom_geni_serial_init); 1839 1840 static void __exit qcom_geni_serial_exit(void) 1841 { 1842 platform_driver_unregister(&qcom_geni_serial_platform_driver); 1843 console_unregister(&qcom_geni_console_driver); 1844 uart_unregister_driver(&qcom_geni_uart_driver); 1845 } 1846 module_exit(qcom_geni_serial_exit); 1847 1848 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); 1849 MODULE_LICENSE("GPL v2"); 1850